Pin-Outs

®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
DNU
DNU
RREF_TL
REFCLK3Ln
REFCLK3Lp
GXB_TX_L11n
GXB_TX_L11p
GXB_RX_L11p,GXB_REFCLK_L11p
GXB_RX_L11n,GXB_REFCLK_L11n
GXB_TX_L10n
GXB_TX_L10p
GXB_RX_L10p,GXB_REFCLK_L10p
GXB_RX_L10n,GXB_REFCLK_L10n
GXB_TX_L9n
GXB_TX_L9p
GXB_RX_L9p,GXB_REFCLK_L9p
GXB_RX_L9n,GXB_REFCLK_L9n
GXB_TX_L8n
GXB_TX_L8p
GXB_RX_L8p,GXB_REFCLK_L8p
GXB_RX_L8n,GXB_REFCLK_L8n
GXB_TX_L7n
GXB_TX_L7p
GXB_RX_L7p,GXB_REFCLK_L7p
GXB_RX_L7n,GXB_REFCLK_L7n
GXB_TX_L6n
GXB_TX_L6p
GXB_RX_L6p,GXB_REFCLK_L6p
GXB_RX_L6n,GXB_REFCLK_L6n
REFCLK2Ln
REFCLK2Lp
REFCLK1Ln
REFCLK1Lp
GXB_TX_L5n
GXB_TX_L5p
GXB_RX_L5p,GXB_REFCLK_L5p
GXB_RX_L5n,GXB_REFCLK_L5n
GXB_TX_L4n
GXB_TX_L4p
GXB_RX_L4p,GXB_REFCLK_L4p
GXB_RX_L4n,GXB_REFCLK_L4n
GXB_TX_L3n
GXB_TX_L3p
GXB_RX_L3p,GXB_REFCLK_L3p
GXB_RX_L3n,GXB_REFCLK_L3n
GXB_TX_L2n
GXB_TX_L2p
GXB_RX_L2p,GXB_REFCLK_L2p
GXB_RX_L2n,GXB_REFCLK_L2n
GXB_TX_L1n
GXB_TX_L1p
GXB_RX_L1p,GXB_REFCLK_L1p
GXB_RX_L1n,GXB_REFCLK_L1n
GXB_TX_L0n
GXB_TX_L0p
GXB_RX_L0p,GXB_REFCLK_L0p
GXB_RX_L0n,GXB_REFCLK_L0n
REFCLK0Ln
REFCLK0Lp
DNU
TDO
TMS
TCK
TDI
DCLK
nCSO
AS_DATA3
AS_DATA2
AS_DATA1
AS_DATA0,ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3B
3B
3B
3B
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
TDO
TMS
TCK
TDI
DCLK
DATA4
DATA3
DATA2
DATA1
DATA0
RZQ_0
CLK0n
CLK0p
CLK1n
CLK1p
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB0
FPLL_BL_CLKOUT3,FPLL_BL_FBn
FPLL_BL_CLKOUT2,FPLL_BL_FBp,FPLL_BL_FB1
VREFB3AN0
CLK2n
CLK2p
CLK3n
CLK3p
DIFFIO_TX_B1n
DIFFIO_RX_B2n
DIFFIO_RX_B2p
DIFFIO_RX_B4n
DIFFIO_RX_B4p
DIFFIO_TX_B5n
DIFFIO_TX_B5p
DIFFIO_RX_B6n
DIFFIO_RX_B6p
DIFFOUT_B1n
DIFFOUT_B2n
DIFFOUT_B2p
DIFFOUT_B4n
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B5p
DIFFOUT_B6n
DIFFOUT_B6p
DIFFIO_RX_B7n
DIFFIO_RX_B7p
DIFFIO_TX_B8n
DIFFIO_TX_B8p
DIFFIO_RX_B9n
DIFFIO_RX_B9p
DIFFIO_TX_B10n
DIFFIO_TX_B10p
DIFFIO_RX_B11n
DIFFIO_RX_B11p
DIFFIO_TX_B12n
DIFFIO_TX_B12p
DIFFIO_RX_B13n
DIFFIO_RX_B13p
DIFFIO_TX_B14n
DIFFIO_TX_B14p
DIFFIO_RX_B15n
DIFFIO_RX_B15p
DIFFIO_TX_B16n
DIFFIO_TX_B16p
DIFFIO_RX_B17n
DIFFIO_RX_B17p
DIFFIO_TX_B18n
DIFFIO_TX_B18p
DIFFIO_RX_B19n
DIFFIO_RX_B19p
DIFFIO_TX_B20n
DIFFIO_TX_B20p
DIFFIO_RX_B21n
DIFFIO_RX_B21p
DIFFIO_TX_B22n
DIFFIO_TX_B22p
DIFFIO_RX_B23n
DIFFIO_RX_B23p
DIFFIO_TX_B24n
DIFFIO_TX_B24p
DIFFIO_RX_B25n
DIFFIO_RX_B25p
DIFFOUT_B7n
DIFFOUT_B7p
DIFFOUT_B8n
DIFFOUT_B8p
DIFFOUT_B9n
DIFFOUT_B9p
DIFFOUT_B10n
DIFFOUT_B10p
DIFFOUT_B11n
DIFFOUT_B11p
DIFFOUT_B12n
DIFFOUT_B12p
DIFFOUT_B13n
DIFFOUT_B13p
DIFFOUT_B14n
DIFFOUT_B14p
DIFFOUT_B15n
DIFFOUT_B15p
DIFFOUT_B16n
DIFFOUT_B16p
DIFFOUT_B17n
DIFFOUT_B17p
DIFFOUT_B18n
DIFFOUT_B18p
DIFFOUT_B19n
DIFFOUT_B19p
DIFFOUT_B20n
DIFFOUT_B20p
DIFFOUT_B21n
DIFFOUT_B21p
DIFFOUT_B22n
DIFFOUT_B22p
DIFFOUT_B23n
DIFFOUT_B23p
DIFFOUT_B24n
DIFFOUT_B24p
DIFFOUT_B25n
DIFFOUT_B25p
F1152 (4) DQS for X8/X9
E33
F33
F34
R27
R26
G31
G32
H34
H33
J31
J32
K34
K33
L31
L32
M34
M33
N31
N32
P34
P33
R31
R32
T34
T33
U31
U32
V34
V33
U27
U26
W27
W26
W31
W32
Y34
Y33
AA31
AA32
AB34
AB33
AC31
AC32
AD34
AD33
AE31
AE32
AF34
AF33
AG31
AG32
AH34
AH33
AJ31
AJ32
AK34
AK33
AA28
AA27
AL32
AM33
AD30
AM34
AN34
AP33
AC26
AL31
AM32
AN33
AL30
AM30
AF29
AG29
AH29
AH28
AJ29
AK29
AM31
AN32
AC27
AG27
AH27
AP32
AP31
AG26
AH26
AE26
AF26
AL29
AL28
AN30
AP30
AM28
AM29
AD27
AE27
AJ27
AK27
AP29
AP28
AL27
AM27
AE28
AF28
AJ26
AK26
AN27
AP27
AL26
AM26
AD29
AE29
AN26
AP26
AD26
AE25
AE24
AF24
DQS for X16/ X18
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn1B/QK1B
DQS1B/CQ1B/CQn1B/QKn1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ2B
DQSn2B/QK2B
DQS2B/CQ2B/CQn2B/QKn2B
DQ1B
DQSn1B/QK1B
DQS1B/CQ1B/CQn1B/QKn1B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ3B
DQ3B
DQ3B
DQ2B
DQ2B
DQ2B
Pin List GF35
DQS for X32/ X36
DQ1B
DQ1B
DQ1B
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
CS#_3A_1
CS#_3A_0
CS#_3A_1
CS#_3A_0
ODT_3A_1
ODT_3A_0
WE#_3A
CAS#_3A
RAS#_3A
BA_3A_2
BA_3A_1
BA_3A_0
A_3A_15
A_3A_14
A_3A_13
A_3A_12
A_3A_11
A_3A_10
A_3A_9
A_3A_8
A_3A_7
A_3A_6
A_3A_5
A_3A_4
A_3A_3
A_3A_2
A_3A_1
A_3A_0
CKE_3A_1
CKE_3A_0
CK#_3A
CK_3A
RESET#_3A
DQ1_3B_8
DQ1_3B_7
DQ1_3B_6
ODT_3A_1
ODT_3A_0
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
CA_3A_9
CA_3A_8
CA_3A_7
CA_3A_6
CA_3A_5
CA_3A_4
CA_3A_3
CA_3A_2
CA_3A_1
CA_3A_0
CKE_3A_1
CKE_3A_0
CK#_3A
CK_3A
DQ1_3B_8
DQ1_3B_7
DQ1_3B_6
Page 1 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4C
4C
4C
4C
4C
4C
4C
4C
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VCCD_FPLL
VCCA_FPLL
DNU
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1152 (4) DQS for X8/X9
DIFFIO_TX_B26n
DIFFIO_TX_B26p
DIFFIO_RX_B27n
DIFFIO_RX_B27p
DIFFIO_TX_B28n
DIFFIO_TX_B28p
DIFFIO_RX_B29n
DIFFIO_RX_B29p
DIFFOUT_B26n
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B27p
DIFFOUT_B28n
DIFFOUT_B28p
DIFFOUT_B29n
DIFFOUT_B29p
DIFFIO_RX_B30n
DIFFIO_RX_B30p
DIFFIO_TX_B31p
DIFFIO_RX_B32n
DIFFIO_RX_B32p
DIFFIO_TX_B33p
DIFFIO_RX_B34n
DIFFIO_RX_B34p
DIFFIO_TX_B35p
DIFFIO_RX_B36n
DIFFIO_RX_B36p
DIFFIO_TX_B37p
DIFFIO_RX_B38n
DIFFIO_RX_B38p
DIFFIO_TX_B39p
DIFFIO_RX_B40n
DIFFIO_RX_B40p
DIFFIO_TX_B41p
DIFFIO_RX_B42n
DIFFIO_RX_B42p
DIFFIO_TX_B43p
DIFFIO_RX_B44n
DIFFIO_RX_B44p
DIFFIO_TX_B45p
DIFFIO_RX_B46n
DIFFIO_RX_B46p
DIFFIO_TX_B47n
DIFFIO_TX_B47p
DIFFIO_RX_B48n
DIFFIO_RX_B48p
DIFFIO_TX_B49p
DIFFIO_RX_B50n
DIFFIO_RX_B50p
DIFFIO_TX_B51p
DIFFIO_RX_B52n
DIFFIO_RX_B52p
DIFFOUT_B30n
DIFFOUT_B30p
DIFFOUT_B31p
DIFFOUT_B32n
DIFFOUT_B32p
DIFFOUT_B33p
DIFFOUT_B34n
DIFFOUT_B34p
DIFFOUT_B35p
DIFFOUT_B36n
DIFFOUT_B36p
DIFFOUT_B37p
DIFFOUT_B38n
DIFFOUT_B38p
DIFFOUT_B39p
DIFFOUT_B40n
DIFFOUT_B40p
DIFFOUT_B41p
DIFFOUT_B42n
DIFFOUT_B42p
DIFFOUT_B43p
DIFFOUT_B44n
DIFFOUT_B44p
DIFFOUT_B45p
DIFFOUT_B46n
DIFFOUT_B46p
DIFFOUT_B47n
DIFFOUT_B47p
DIFFOUT_B48n
DIFFOUT_B48p
DIFFOUT_B49p
DIFFOUT_B50n
DIFFOUT_B50p
DIFFOUT_B51p
DIFFOUT_B52n
DIFFOUT_B52p
DIFFIO_RX_B53n
DIFFIO_RX_B53p
DIFFIO_TX_B54p
DIFFIO_RX_B55n
DIFFIO_RX_B55p
DIFFIO_TX_B56p
DIFFIO_RX_B57n
DIFFIO_RX_B57p
DIFFIO_TX_B58p
DIFFIO_RX_B59n
DIFFIO_RX_B59p
DIFFIO_TX_B60p
DIFFIO_RX_B61n
DIFFIO_RX_B61p
DIFFOUT_B53n
DIFFOUT_B53p
DIFFOUT_B54p
DIFFOUT_B55n
DIFFOUT_B55p
DIFFOUT_B56p
DIFFOUT_B57n
DIFFOUT_B57p
DIFFOUT_B58p
DIFFOUT_B59n
DIFFOUT_B59p
DIFFOUT_B60p
DIFFOUT_B61n
DIFFOUT_B61p
DIFFIO_RX_B76n
DIFFIO_RX_B76p
DIFFIO_RX_B78n
DIFFIO_RX_B78p
DIFFIO_TX_B79n
DIFFIO_TX_B79p
DIFFIO_RX_B80n
DIFFIO_RX_B80p
DIFFIO_RX_B82n
DIFFIO_RX_B82p
DIFFIO_RX_B84n
DIFFIO_RX_B84p
DIFFOUT_B76n
DIFFOUT_B76p
DIFFOUT_B78n
DIFFOUT_B78p
DIFFOUT_B79n
DIFFOUT_B79p
DIFFOUT_B80n
DIFFOUT_B80p
DIFFOUT_B82n
DIFFOUT_B82p
DIFFOUT_B84n
DIFFOUT_B84p
DIFFIO_TX_B93n
DIFFIO_TX_B93p
DIFFIO_RX_B94n
DIFFIO_RX_B94p
DIFFIO_TX_B95n
DIFFIO_TX_B95p
DIFFIO_RX_B96n
DIFFIO_RX_B96p
DIFFIO_TX_B97n
DIFFIO_TX_B97p
DIFFIO_RX_B98n
DIFFIO_RX_B98p
DIFFOUT_B93n
DIFFOUT_B93p
DIFFOUT_B94n
DIFFOUT_B94p
DIFFOUT_B95n
DIFFOUT_B95p
DIFFOUT_B96n
DIFFOUT_B96p
DIFFOUT_B97n
DIFFOUT_B97p
DIFFOUT_B98n
DIFFOUT_B98p
DIFFIO_RX_B99n
DIFFIO_RX_B99p
DIFFIO_TX_B100n
DIFFIO_TX_B100p
DIFFIO_RX_B101n
DIFFIO_RX_B101p
DIFFIO_TX_B102n
DIFFIO_TX_B102p
DIFFIO_RX_B103n
DIFFIO_RX_B103p
DIFFIO_TX_B104n
DIFFIO_TX_B104p
DIFFIO_RX_B105n
DIFFIO_RX_B105p
DIFFIO_TX_B106n
DIFFIO_TX_B106p
DIFFIO_RX_B107n
DIFFIO_RX_B107p
DIFFIO_TX_B108n
DIFFIO_TX_B108p
DIFFIO_RX_B109n
DIFFIO_RX_B109p
DIFFIO_TX_B110p
DIFFIO_RX_B111n
DIFFIO_RX_B111p
DIFFIO_TX_B112p
DIFFOUT_B99n
DIFFOUT_B99p
DIFFOUT_B100n
DIFFOUT_B100p
DIFFOUT_B101n
DIFFOUT_B101p
DIFFOUT_B102n
DIFFOUT_B102p
DIFFOUT_B103n
DIFFOUT_B103p
DIFFOUT_B104n
DIFFOUT_B104p
DIFFOUT_B105n
DIFFOUT_B105p
DIFFOUT_B106n
DIFFOUT_B106p
DIFFOUT_B107n
DIFFOUT_B107p
DIFFOUT_B108n
DIFFOUT_B108p
DIFFOUT_B109n
DIFFOUT_B109p
DIFFOUT_B110p
DIFFOUT_B111n
DIFFOUT_B111p
DIFFOUT_B112p
AB24
AB25
AC24
AD24
AH25
AJ25
AG24
AH24
AC25
AC23
AL25
AL24
AJ24
AE23
AF23
AD23
AP25
AP24
AM25
AM23
AM24
AB23
AN23
AP23
AF22
AG23
AH23
AE22
AJ23
AJ22
AH22
AG21
AH21
AC22
AK23
AL23
AL22
AM22
AN21
AP22
AB21
AE21
AE20
AL20
AF20
AG20
AB22
AB20
AK21
AL21
AH20
AJ20
AK20
AC21
AP21
AP20
AM20
AN20
AP19
AC19
AC20
AD20
AD18
AH19
AJ19
AL19
AM19
AE19
AF19
AM18
AN18
AJ18
AK18
AF18
AG18
AA17
AA18
AB19
AD17
AE17
AE16
AF16
AB18
AC18
AF17
AG17
AH17
AH16
AJ16
AJ17
AB17
AC17
AK17
AL16
AL17
AM17
AP17
AP18
AB16
AC16
AP16
AP15
AG15
AH15
AK15
AL15
AD15
AE15
AM16
AN15
AN14
AP14
AL14
AM14
AC15
AJ14
AK14
AH14
VREFB3BN0
VREFB3CN0
VREFB3DN0
CLK4n
CLK4p
CLK5n
CLK5p
FPLL_BC_CLKOUT1,FPLL_BC_CLKOUTn
FPLL_BC_CLKOUT0,FPLL_BC_CLKOUTp,FPLL_BC_FB0
FPLL_BC_CLKOUT3,FPLL_BC_FBn
FPLL_BC_CLKOUT2,FPLL_BC_FBp,FPLL_BC_FB1
CLK6n
CLK6p
CLK7n
CLK7p
VREFB4DN0
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
DQ3B
DQSn3B/QK3B
DQS3B/CQ3B/CQn3B/QKn3B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DM1_3B
DQS#1_3B
DQS1_3B
DM1_3B
DQS#1_3B
DQS1_3B
DQ3B
DQ3B
DQ3B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1_3B_5
DQ1_3B_4
DQ1_3B_3
DQ1_3B_5
DQ1_3B_4
DQ1_3B_3
DQ3B
DQ3B
DQ3B
DQ4B
DQ4B
DQ4B
DQ4B
DQSn4B/QK4B
DQS4B/CQ4B/CQn4B/QKn4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ5B
DQ5B
DQ5B
DQ5B
DQSn5B/QK5B
DQS5B/CQ5B/CQn5B/QKn5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQSn2B/QK2B
DQS2B/CQ2B/CQn2B/QKn2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn1B/QK1B
DQS1B/CQ1B/CQn1B/QKn1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1_3B_2
DQ1_3B_1
DQ1_3B_0
DQ2_3B_8
DQ2_3B_7
DQ2_3B_6
DM2_3B
DQS#2_3B
DQS2_3B
DQ2_3B_5
DQ2_3B_4
DQ2_3B_3
DQ2_3B_2
DQ2_3B_1
DQ2_3B_0
DQ3_3C_8
DQ3_3C_7
DQ3_3C_6
DM3_3C
DQS#3_3C
DQS3_3C
DQ3_3C_5
DQ3_3C_4
DQ3_3C_3
DQ3_3C_2
DQ3_3C_1
DQ3_3C_0
DQ1_3B_2
DQ1_3B_1
DQ1_3B_0
DQ2_3B_8
DQ2_3B_7
DQ2_3B_6
DM2_3B
DQS#2_3B
DQS2_3B
DQ2_3B_5
DQ2_3B_4
DQ2_3B_3
DQ2_3B_2
DQ2_3B_1
DQ2_3B_0
DQ3_3C_8
DQ3_3C_7
DQ3_3C_6
DM3_3C
DQS#3_3C
DQS3_3C
DQ3_3C_5
DQ3_3C_4
DQ3_3C_3
DQ3_3C_2
DQ3_3C_1
DQ3_3C_0
DQ6B
DQ6B
DQ6B
DQ6B
DQSn6B/QK6B
DQS6B/CQ6B/CQn6B/QKn6B
DQ6B
DQ6B
DQ6B
DQ3B
DQ3B
DQ3B
DQ3B
DQSn3B/QK3B
DQS3B/CQ3B/CQn3B/QKn3B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ4_3C_8
DQ4_3C_7
DQ4_3C_6
DM4_3C
DQS#4_3C
DQS4_3C
DQ4_3C_5
DQ4_3C_4
DQ4_3C_3
DQ4_3C_8
DQ4_3C_7
DQ4_3C_6
DM4_3C
DQS#4_3C
DQS4_3C
DQ4_3C_5
DQ4_3C_4
DQ4_3C_3
DQ6B
DQ6B
DQ6B
DQ7B
DQ7B
DQ7B
DQ7B
DQSn7B/QK7B
DQS7B/CQ7B/CQn7B/QKn7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ4_3C_2
DQ4_3C_1
DQ4_3C_0
DQ5_3C_8
DQ5_3C_7
DQ5_3C_6
DM5_3C
DQS#5_3C
DQS5_3C
DQ5_3C_5
DQ5_3C_4
DQ5_3C_3
DQ5_3C_2
DQ5_3C_1
DQ5_3C_0
DQ4_3C_2
DQ4_3C_1
DQ4_3C_0
DQ5_3C_8
DQ5_3C_7
DQ5_3C_6
DM5_3C
DQS#5_3C
DQS5_3C
DQ5_3C_5
DQ5_3C_4
DQ5_3C_3
DQ5_3C_2
DQ5_3C_1
DQ5_3C_0
DQ8B
DQ8B
DQ8B
DQ4B
DQ4B
DQ4B
CS#_4D_1
CS#_4D_0
CS#_4D_1
CS#_4D_0
DQ8B
DQSn8B/QK8B
DQS8B/CQ8B/CQn8B/QKn8B
DQ4B
DQ4B
DQ4B
DQ8B
DQ8B
DQ8B
DQ4B
DQ4B
DQ4B
DQ8B
DQ8B
DQ8B
DQ4B
DQ4B
DQ4B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ9B
DQSn9B/QK9B
DQS9B/CQ9B/CQn9B/QKn9B
DQ4B
DQSn4B/QK4B
DQS4B/CQ4B/CQn4B/QKn4B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ10B
DQ10B
DQ10B
DQ10B
DQSn10B/QK10B
DQS10B/CQ10B/CQn10B/QKn10B
DQ10B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
Pin List GF35
A_4D_15
ODT_4D_1
ODT_4D_0
WE#_4D
CAS#_4D
RAS#_4D
BA_4D_2
BA_4D_1
BA_4D_0
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
A_4D_14
A_4D_13
A_4D_12
A_4D_11
A_4D_10
A_4D_9
A_4D_8
A_4D_7
A_4D_6
A_4D_5
A_4D_4
A_4D_3
A_4D_2
A_4D_1
A_4D_0
CKE_4D_1
CKE_4D_0
CK#_4D
CK_4D
RESET#_4D
DQ1_4C_8
DQ1_4C_7
DQ1_4C_6
DM1_4C
DQS#1_4C
DQS1_4C
DQ1_4C_5
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
ODT_4D_1
ODT_4D_0
CA_4D_9
CA_4D_8
CA_4D_7
CA_4D_6
CA_4D_5
CA_4D_4
CA_4D_3
CA_4D_2
CA_4D_1
CA_4D_0
CKE_4D_1
CKE_4D_0
CK#_4D
CK_4D
DQ1_4C_8
DQ1_4C_7
DQ1_4C_6
DM1_4C
DQS#1_4C
DQS1_4C
DQ1_4C_5
Page 2 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
RREF_BR
DNU
DNU
REFCLK0Rp
REFCLK0Rn
GXB_RX_R0n,GXB_REFCLK_R0n
GXB_RX_R0p,GXB_REFCLK_R0p
GXB_TX_R0p
GXB_TX_R0n
GXB_RX_R1n,GXB_REFCLK_R1n
GXB_RX_R1p,GXB_REFCLK_R1p
GXB_TX_R1p
GXB_TX_R1n
GXB_RX_R2n,GXB_REFCLK_R2n
GXB_RX_R2p,GXB_REFCLK_R2p
GXB_TX_R2p
GXB_TX_R2n
GXB_RX_R3n,GXB_REFCLK_R3n
GXB_RX_R3p,GXB_REFCLK_R3p
GXB_TX_R3p
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1152 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
DIFFIO_RX_B113n
DIFFIO_RX_B113p
DIFFOUT_B113n
DIFFOUT_B113p
DQ10B
DQ10B
DQ5B
DQ5B
DQ2B
DQ2B
HMC pin
assignment for
DDR3 (5)
DQ1_4C_4
DQ1_4C_3
HMC pin
assignment for
LPDDR2
DQ1_4C_4
DQ1_4C_3
DIFFIO_RX_B114n
DIFFIO_RX_B114p
DIFFIO_TX_B115p
DIFFIO_RX_B116n
DIFFIO_RX_B116p
DIFFIO_TX_B117p
DIFFIO_RX_B118n
DIFFIO_RX_B118p
DIFFIO_TX_B119p
DIFFIO_RX_B120n
DIFFIO_RX_B120p
DIFFIO_TX_B121p
DIFFIO_RX_B122n
DIFFIO_RX_B122p
DIFFIO_TX_B123p
DIFFIO_RX_B124n
DIFFIO_RX_B124p
DIFFIO_TX_B125p
DIFFIO_RX_B126n
DIFFIO_RX_B126p
DIFFIO_TX_B127p
DIFFIO_RX_B128n
DIFFIO_RX_B128p
DIFFIO_TX_B129p
DIFFIO_RX_B130n
DIFFIO_RX_B130p
DIFFIO_TX_B131n
DIFFIO_TX_B131p
DIFFIO_RX_B132n
DIFFIO_RX_B132p
DIFFIO_TX_B133p
DIFFIO_RX_B134n
DIFFIO_RX_B134p
DIFFIO_TX_B135p
DIFFIO_RX_B136n
DIFFIO_RX_B136p
DIFFOUT_B114n
DIFFOUT_B114p
DIFFOUT_B115p
DIFFOUT_B116n
DIFFOUT_B116p
DIFFOUT_B117p
DIFFOUT_B118n
DIFFOUT_B118p
DIFFOUT_B119p
DIFFOUT_B120n
DIFFOUT_B120p
DIFFOUT_B121p
DIFFOUT_B122n
DIFFOUT_B122p
DIFFOUT_B123p
DIFFOUT_B124n
DIFFOUT_B124p
DIFFOUT_B125p
DIFFOUT_B126n
DIFFOUT_B126p
DIFFOUT_B127p
DIFFOUT_B128n
DIFFOUT_B128p
DIFFOUT_B129p
DIFFOUT_B130n
DIFFOUT_B130p
DIFFOUT_B131n
DIFFOUT_B131p
DIFFOUT_B132n
DIFFOUT_B132p
DIFFOUT_B133p
DIFFOUT_B134n
DIFFOUT_B134p
DIFFOUT_B135p
DIFFOUT_B136n
DIFFOUT_B136p
DQ10B
DQ10B
DQ10B
DQ11B
DQ11B
DQ11B
DQ11B
DQSn11B/QK11B
DQS11B/CQ11B/CQn11B/QKn11B
DQ11B
DQ11B
DQ11B
DQ11B
DQ11B
DQ11B
DQ12B
DQ12B
DQ12B
DQ12B
DQSn12B/QK12B
DQS12B/CQ12B/CQn12B/QKn12B
DQ12B
DQ12B
DQ12B
DQ12B
DQ12B
DQ12B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQSn5B/QK5B
DQS5B/CQ5B/CQn5B/QKn5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ5B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQSn2B/QK2B
DQS2B/CQ2B/CQn2B/QKn2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ1_4C_2
DQ1_4C_1
DQ1_4C_0
DQ2_4C_8
DQ2_4C_7
DQ2_4C_6
DM2_4C
DQS#2_4C
DQS2_4C
DQ2_4C_5
DQ2_4C_4
DQ2_4C_3
DQ2_4C_2
DQ2_4C_1
DQ2_4C_0
DQ3_4B_8
DQ3_4B_7
DQ3_4B_6
DM3_4B
DQS#3_4B
DQS3_4B
DQ3_4B_5
DQ3_4B_4
DQ3_4B_3
DQ3_4B_2
DQ3_4B_1
DQ3_4B_0
DQ1_4C_2
DQ1_4C_1
DQ1_4C_0
DQ2_4C_8
DQ2_4C_7
DQ2_4C_6
DM2_4C
DQS#2_4C
DQS2_4C
DQ2_4C_5
DQ2_4C_4
DQ2_4C_3
DQ2_4C_2
DQ2_4C_1
DQ2_4C_0
DQ3_4B_8
DQ3_4B_7
DQ3_4B_6
DM3_4B
DQS#3_4B
DQS3_4B
DQ3_4B_5
DQ3_4B_4
DQ3_4B_3
DQ3_4B_2
DQ3_4B_1
DQ3_4B_0
DQ13B
DQ13B
DQ13B
DQ13B
DQSn13B/QK13B
DQS13B/CQ13B/CQn13B/QKn13B
DQ13B
DQ13B
DQ13B
DQ6B
DQ6B
DQ6B
DQ6B
DQSn6B/QK6B
DQS6B/CQ6B/CQn6B/QKn6B
DQ6B
DQ6B
DQ6B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ4_4B_8
DQ4_4B_7
DQ4_4B_6
DM4_4B
DQS#4_4B
DQS4_4B
DQ4_4B_5
DQ4_4B_4
DQ4_4B_3
DQ4_4B_8
DQ4_4B_7
DQ4_4B_6
DM4_4B
DQS#4_4B
DQS4_4B
DQ4_4B_5
DQ4_4B_4
DQ4_4B_3
DIFFIO_RX_B137n
DIFFIO_RX_B137p
DIFFIO_TX_B138p
DIFFIO_RX_B139n
DIFFIO_RX_B139p
DIFFIO_TX_B140p
DIFFIO_RX_B141n
DIFFIO_RX_B141p
DIFFIO_TX_B142p
DIFFIO_RX_B143n
DIFFIO_RX_B143p
DIFFIO_TX_B144p
DIFFIO_RX_B145n
DIFFIO_RX_B145p
DIFFIO_TX_B146p
DIFFIO_RX_B147n
DIFFIO_RX_B147p
DIFFIO_TX_B148p
DIFFIO_RX_B149n
DIFFIO_RX_B149p
DIFFIO_TX_B150n
DIFFIO_TX_B150p
DIFFIO_RX_B151n
DIFFIO_RX_B151p
DIFFIO_TX_B152n
DIFFIO_TX_B152p
DIFFIO_RX_B153n
DIFFIO_RX_B153p
DIFFIO_TX_B154n
DIFFIO_TX_B154p
DIFFIO_RX_B155n
DIFFIO_RX_B155p
DIFFIO_TX_B156n
DIFFIO_TX_B156p
DIFFIO_RX_B157n
DIFFIO_RX_B157p
DIFFIO_TX_B158n
DIFFIO_TX_B158p
DIFFIO_RX_B159n
DIFFIO_RX_B159p
DIFFOUT_B137n
DIFFOUT_B137p
DIFFOUT_B138p
DIFFOUT_B139n
DIFFOUT_B139p
DIFFOUT_B140p
DIFFOUT_B141n
DIFFOUT_B141p
DIFFOUT_B142p
DIFFOUT_B143n
DIFFOUT_B143p
DIFFOUT_B144p
DIFFOUT_B145n
DIFFOUT_B145p
DIFFOUT_B146p
DIFFOUT_B147n
DIFFOUT_B147p
DIFFOUT_B148p
DIFFOUT_B149n
DIFFOUT_B149p
DIFFOUT_B150n
DIFFOUT_B150p
DIFFOUT_B151n
DIFFOUT_B151p
DIFFOUT_B152n
DIFFOUT_B152p
DIFFOUT_B153n
DIFFOUT_B153p
DIFFOUT_B154n
DIFFOUT_B154p
DIFFOUT_B155n
DIFFOUT_B155p
DIFFOUT_B156n
DIFFOUT_B156p
DIFFOUT_B157n
DIFFOUT_B157p
DIFFOUT_B158n
DIFFOUT_B158p
DIFFOUT_B159n
DIFFOUT_B159p
DQ13B
DQ13B
DQ13B
DQ14B
DQ14B
DQ14B
DQ14B
DQSn14B/QK14B
DQS14B/CQ14B/CQn14B/QKn14B
DQ14B
DQ14B
DQ14B
DQ14B
DQ14B
DQ14B
DQ15B
DQ15B
DQ15B
DQ15B
DQSn15B/QK15B
DQS15B/CQ15B/CQn15B/QKn15B
DQ6B
DQ6B
DQ6B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQSn7B/QK7B
DQS7B/CQ7B/CQn7B/QKn7B
DQ2B
DQ2B
DQ2B
DQ4_4B_2
DQ4_4B_1
DQ4_4B_0
DQ5_4B_8
DQ5_4B_7
DQ5_4B_6
DM5_4B
DQS#5_4B
DQS5_4B
DQ5_4B_5
DQ5_4B_4
DQ5_4B_3
DQ5_4B_2
DQ5_4B_1
DQ5_4B_0
DQ4_4B_2
DQ4_4B_1
DQ4_4B_0
DQ5_4B_8
DQ5_4B_7
DQ5_4B_6
DM5_4B
DQS#5_4B
DQS5_4B
DQ5_4B_5
DQ5_4B_4
DQ5_4B_3
DQ5_4B_2
DQ5_4B_1
DQ5_4B_0
DQ15B
DQ15B
DQ15B
DQ7B
DQ7B
DQ7B
DQ15B
DQ15B
DQ15B
DQ7B
DQ7B
DQ7B
DIFFIO_RX_B160n
DIFFIO_RX_B160p
DIFFIO_TX_B161n
DIFFIO_TX_B161p
DIFFIO_RX_B162n
DIFFIO_RX_B162p
DIFFIO_RX_B164n
DIFFIO_RX_B164p
DIFFIO_RX_B166n
DIFFIO_RX_B166p
DIFFIO_TX_B167n
DIFFIO_TX_B167p
DIFFIO_RX_B168n
DIFFIO_RX_B168p
DIFFOUT_B160n
DIFFOUT_B160p
DIFFOUT_B161n
DIFFOUT_B161p
DIFFOUT_B162n
DIFFOUT_B162p
DIFFOUT_B164n
DIFFOUT_B164p
DIFFOUT_B166n
DIFFOUT_B166p
DIFFOUT_B167n
DIFFOUT_B167p
DIFFOUT_B168n
DIFFOUT_B168p
AH13
AJ13
AB15
AC13
AC14
AD14
AF14
AL13
AM13
AB14
AJ12
AK12
AG14
AE14
AF13
AB13
AF12
AG12
AP13
AN12
AP12
AE12
AM12
AN11
AL11
AG11
AH11
AD12
AL10
AM11
AP11
AP10
AJ11
AK11
AB12
AL9
AM10
AF11
AF9
AG9
AA12
AC12
AD9
AE10
AE11
AJ9
AK9
AB11
AH10
AH9
AE9
AC9
AC8
AC11
AB10
AC10
AP9
AN8
AN9
AF8
AL8
AM8
AP8
AP7
AN6
AP6
AE7
AF7
AL7
AM7
AJ8
AK8
AN5
AP5
AD6
AE6
AP4
AP3
AM6
AM5
AK6
AL6
AC7
AD8
AH7
AJ7
AG8
AH8
AN3
AP2
AM4
AM3
AL4
AL5
AF6
AG6
AH6
AJ6
AM1
AM2
AN2
AA8
AA7
AK2
AK1
AJ3
AJ4
AH2
AH1
AG3
AG4
AF2
AF1
AE3
AE4
AD2
AD1
AC3
VREFB4CN0
VREFB4BN0
DATA10
DATA11
DATA5
DATA6
DATA12
DATA13
DATA7
DATA8
DATA14
DATA15
DATA9
CLKUSR
PR_ERROR
PR_READY
PR_DONE
PR_REQUEST
nPERSTR0
nPERSTL0
CvP_CONFDONE
CRC_ERROR
DEV_OE
DEV_CLRn
INIT_DONE
nCEO
VREFB4AN0
CLK11n
CLK11p
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn
FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB0
FPLL_BR_CLKOUT3,FPLL_BR_FBn
FPLL_BR_CLKOUT2,FPLL_BR_FBp,FPLL_BR_FB1
CLK10n
CLK10p
CLK9n
CLK9p
RZQ_1
CLK8n
CLK8p
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
DQ16B
DQ16B
DQ16B
DQ16B
DQSn16B/QK16B
DQS16B/CQ16B/CQn16B/QKn16B
DQ16B
DQ16B
DQ16B
DQ16B
DQ16B
DQ16B
Pin List GF35
Page 3 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
7A
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
VREF
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
PinName/Function (2), (3)
GXB_TX_R3n
GXB_RX_R4n,GXB_REFCLK_R4n
GXB_RX_R4p,GXB_REFCLK_R4p
GXB_TX_R4p
GXB_TX_R4n
GXB_RX_R5n,GXB_REFCLK_R5n
GXB_RX_R5p,GXB_REFCLK_R5p
GXB_TX_R5p
GXB_TX_R5n
REFCLK1Rp
REFCLK1Rn
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI13
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI12
HPS_GPI11
HPS_DDR
HPS_GPI10
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6BN0_HPS
HPS_DDR
HPS_GPI9
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI8
HPS_GPI7
HPS_DDR
HPS_GPI6
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI5
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI4
HPS_GPI3
HPS_DDR
HPS_GPI2
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI1
HPS_GPI0
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_RZQ_0
DNU
GND
GND
HPS_nRST
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1152 (4) DQS for X8/X9
AC4
AB2
AB1
AA3
AA4
Y2
Y1
W3
W4
W8
W7
T7
T8
U2
V1
U3
T3
T1
T4
U1
R1
T5
R2
T6
P1
P2
N1
R3
N4
P7
P4
R7
L1
M3
M2
N3
K1
R4
L2
P5
H2
H1
J2
J1
J3
N5
K3
P6
K4
L3
L5
M4
L6
N6
M6
N7
G3
F1
H3
G1
H4
K5
J4
K6
D1
E1
C1
E2
F3
J6
F4
J7
C2
G4
G5
A2
K7
B1
L7
C3
E3
D4
E4
A4
M8
A3
N9
B4
C4
D5
J8
E5
K8
A6
B5
B7
B6
C7
G7
D6
G6
H6
F6
G8
F7
G9
C8
E7
D7
F8
A8
J9
A7
K9
U4
G10
H10
P11
Pin List GF35
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DM_3
HPS_DM_3
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQS_3
HPS_DQS_3
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DM_2
HPS_DM_2
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DM_1
HPS_DM_1
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_A_0
HPS_A_1
HPS_A_4
HPS_A_2
HPS_A_5
HPS_A_3
HPS_CK
HPS_A_6
HPS_CK#
HPS_A_7
HPS_BA_1
HPS_BA_0
HPS_BA_2
HPS_CAS#
HPS_RAS#
HPS_A_8
HPS_A_10
HPS_A_9
HPS_A_11
HPS_CS#_0
HPS_A_12
HPS_CS#_1
HPS_A_13
HPS_A_14
HPS_WE#
HPS_A_15
HPS_CA_0
HPS_CA_1
HPS_CA_4
HPS_CA_2
HPS_CA_5
HPS_CA_3
HPS_CK
HPS_CA_6
HPS_CK#
HPS_CA_7
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
HPS_CA_8
HPS_CA_9
HPS_CS#_0
HPS_CS#_1
Page 4 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7E
7E
7E
7E
7E
7E
7E
7E
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
PinName/Function (2), (3)
HPS_nPOR
HPS_TDO
VCCRSTCLK_HPS
HPS_TMS
HPS_TCK
HPS_TRST
HPS_TDI
GND
HPS_PORSEL
HPS_CLK1
HPS_CLK2
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0,BOOTSEL0
UART0_RX
UART0_TX,CLKSEL1
I2C0_SDA
I2C0_SCL
UART0_RX*
UART0_TX*,CLKSEL0
SPIS1_CLK
SPIS1_MOSI
SPIS1_MISO
SPIS1_SS0
UART1_RX
UART1_TX
I2C1_SDA
I2C1_SCL
SPIM0_SS0
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE,BOOTSEL2
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0,BOOTSEL1
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TX_CTL
RGMII1_RXD0
RGMII1_RXD1
RGMII1_MDIO
RGMII1_MDC
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RX_CLK
RGMII1_RX_CTL
RGMII1_RXD2
RGMII1_RXD3
VCCA_FPLL
VCCD_FPLL
DNU
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Optional Function(s)
CLK19p
CLK19n
CLK18p
CLK18n
FPLL_TC_CLKOUT2,FPLL_TC_FBp,FPLL_TC_FB1
FPLL_TC_CLKOUT3,FPLL_TC_FBn
FPLL_TC_CLKOUT0,FPLL_TC_CLKOUTp,FPLL_TC_FB0
FPLL_TC_CLKOUT1,FPLL_TC_CLKOUTn
CLK17p
CLK17n
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_T31p
DIFFIO_RX_T31n
DIFFIO_RX_T33p
DIFFIO_RX_T33n
DIFFIO_RX_T35p
DIFFIO_RX_T35n
DIFFIO_TX_T36p
DIFFIO_TX_T36n
DIFFIO_RX_T37p
DIFFIO_RX_T37n
Emulated LVDS
Output Channel
DIFFOUT_T31p
DIFFOUT_T31n
DIFFOUT_T33p
DIFFOUT_T33n
DIFFOUT_T35p
DIFFOUT_T35n
DIFFOUT_T36p
DIFFOUT_T36n
DIFFOUT_T37p
DIFFOUT_T37n
F1152 (4) DQS for X8/X9
F9
P10
E9
A9
C9
B10
D9
N10
C10
L9
D10
A10
K10
A11
J10
A13
B12
A12
C13
C11
L10
C12
L11
E10
E11
F10
F11
H11
M10
J11
M11
D12
E12
D13
F12
J12
L12
K12
M12
F13
G12
G13
H12
A14
M13
B14
N13
B15
C14
C15
D14
G14
N12
H14
P12
K13
J14
L14
K14
M14
P14
N14
R15
F14
D15
E15
J15
F15
K15
E16
G15
F16
G16
H16
M15
J16
L15
A16
A17
A15
B17
C16
L16
C17
M16
D17
E18
D16
F18
F17
P16
G17
N16
J17
G18
K17
H17
L17
N19
M17
N18
M18
J18
N17
K18
T17
T16
P19
C18
D18
D19
E19
A18
B19
G19
H19
C20
D20
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
UART0_RX
UART0_TX
I2C0_SDA
I2C0_SCL
SPIS1_CLK
SPIS1_MOSI
SPIS1_MISO
SPIS1_SS0
UART1_RX
UART1_TX
I2C1_SDA
I2C1_SCL
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TX_CTL
RGMII1_RXD0
RGMII1_RXD1
RGMII1_MDIO
RGMII1_MDC
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RX_CLK
RGMII1_RX_CTL
RGMII1_RXD2
RGMII1_RXD3
Pin List GF35
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
SPIS1_CLK
SPIS1_MOSI
SPIS1_SS0
SPIS1_MISO
I2C1_SDA
I2C1_SCL
UART1_RX
UART1_TX
UART0_RX
UART0_TX
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
SPIM1_SS1
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
SPIM0_SS1
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RXD0
RGMII1_MDIO
RGMII1_MDC
RGMII1_RX_CTL
RGMII1_TX_CTL
RGMII1_RX_CLK
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
QSPI_SS1
UART0_RX
UART0_TX
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
UART0_CTS
UART0_RTS
UART1_CTS
UART1_RTS
SPIM0_SS1
SPIM1_SS1
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
QSPI_SS3
USB1_D0
USB1_D1
USB1_D2
USB1_D3
I2C3_SDA
I2C3_SCL
USB1_D4
USB1_D5
USB1_D6
USB1_D7
QSPI_SS2
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
USB0_D0
USB0_D1
USB0_D2
USB0_D3
USB0_D4
USB0_D5
USB0_D6
USB0_D7
USB0_CLK
USB0_STP
USB0_DIR
USB0_NXT
USB1_D0
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
I2C2_SDA
I2C2_SCL
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
SPIS1_CLK
SPIS1_MOSI
SPIS1_MISO
SPIS1_SS0
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
HPS_GPIO48
HPS_GPIO49
HPS_GPIO50
HPS_GPIO51
HPS_GPIO52
HPS_GPIO53
HPS_GPIO54
HPS_GPIO55
HPS_GPIO56
HPS_GPIO57
HPS_GPIO58
HPS_GPIO59
HPS_GPIO60
HPS_GPIO61
HPS_GPIO62
HPS_GPIO63
HPS_GPIO64
HPS_GPIO65
HPS_GPIO66
HPS_GPIO67
HPS_GPIO68
HPS_GPIO69
HPS_GPIO70
HPS_GPIO62
HPS_GPIO63
HPS_GPIO64
HPS_GPIO65
HPS_GPIO66
HPS_GPIO67
HPS_GPIO68
HPS_GPIO69
HPS_GPIO70
HPS_GPIO14
HPS_GPIO15
HPS_GPIO16
HPS_GPIO17
HPS_GPIO18
HPS_GPIO19
HPS_GPIO20
HPS_GPIO21
HPS_GPIO22
HPS_GPIO23
HPS_GPIO24
HPS_GPIO25
HPS_GPIO26
HPS_GPIO27
HPS_GPIO28
HPS_GPIO29
HPS_GPIO30
HPS_GPIO31
HPS_GPIO32
HPS_GPIO33
HPS_GPIO34
HPS_GPIO35
HPS_GPIO36
HPS_GPIO37
HPS_GPIO38
HPS_GPIO39
HPS_GPIO40
HPS_GPIO41
HPS_GPIO42
HPS_GPIO43
HPS_GPIO44
HPS_GPIO45
HPS_GPIO46
HPS_GPIO47
HPS_GPIO0
HPS_GPIO1
HPS_GPIO2
HPS_GPIO3
HPS_GPIO4
HPS_GPIO5
HPS_GPIO6
HPS_GPIO7
HPS_GPIO8
HPS_GPIO9
HPS_GPIO10
HPS_GPIO11
HPS_GPIO12
HPS_GPIO13
HPS_GPIO48
HPS_GPIO49
HPS_GPIO50
HPS_GPIO51
HPS_GPIO52
HPS_GPIO53
HPS_GPIO54
HPS_GPIO55
HPS_GPIO56
HPS_GPIO57
HPS_GPIO58
HPS_GPIO59
HPS_GPIO60
HPS_GPIO61
Page 5 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
Optional Function(s)
8D
8D
8D
8D
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MSEL0
MSEL1
MSEL2
MSEL3
CLK16p
CLK16n
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1152 (4) DQS for X8/X9
DIFFIO_RX_T39p
DIFFIO_RX_T39n
DIFFOUT_T39p
DIFFOUT_T39n
DIFFIO_RX_T54p
DIFFIO_RX_T54n
DIFFIO_TX_T55p
DIFFIO_RX_T56p
DIFFIO_RX_T56n
DIFFIO_TX_T57p
DIFFIO_RX_T58p
DIFFIO_RX_T58n
DIFFIO_TX_T59p
DIFFIO_RX_T60p
DIFFIO_RX_T60n
DIFFIO_TX_T61p
DIFFIO_RX_T62p
DIFFIO_RX_T62n
DIFFOUT_T54p
DIFFOUT_T54n
DIFFOUT_T55p
DIFFOUT_T56p
DIFFOUT_T56n
DIFFOUT_T57p
DIFFOUT_T58p
DIFFOUT_T58n
DIFFOUT_T59p
DIFFOUT_T60p
DIFFOUT_T60n
DIFFOUT_T61p
DIFFOUT_T62p
DIFFOUT_T62n
DIFFIO_RX_T63p
DIFFIO_RX_T63n
DIFFIO_TX_T64p
DIFFIO_RX_T65p
DIFFIO_RX_T65n
DIFFIO_TX_T66p
DIFFIO_RX_T67p
DIFFIO_RX_T67n
DIFFIO_TX_T68p
DIFFIO_TX_T68n
DIFFIO_RX_T69p
DIFFIO_RX_T69n
DIFFIO_TX_T70p
DIFFIO_RX_T71p
DIFFIO_RX_T71n
DIFFIO_TX_T72p
DIFFIO_RX_T73p
DIFFIO_RX_T73n
DIFFIO_TX_T74p
DIFFIO_RX_T75p
DIFFIO_RX_T75n
DIFFIO_TX_T76p
DIFFIO_RX_T77p
DIFFIO_RX_T77n
DIFFIO_TX_T78p
DIFFIO_RX_T79p
DIFFIO_RX_T79n
DIFFIO_TX_T80p
DIFFIO_RX_T81p
DIFFIO_RX_T81n
DIFFIO_TX_T82p
DIFFIO_RX_T83p
DIFFIO_RX_T83n
DIFFIO_TX_T84p
DIFFIO_RX_T85p
DIFFIO_RX_T85n
DIFFOUT_T63p
DIFFOUT_T63n
DIFFOUT_T64p
DIFFOUT_T65p
DIFFOUT_T65n
DIFFOUT_T66p
DIFFOUT_T67p
DIFFOUT_T67n
DIFFOUT_T68p
DIFFOUT_T68n
DIFFOUT_T69p
DIFFOUT_T69n
DIFFOUT_T70p
DIFFOUT_T71p
DIFFOUT_T71n
DIFFOUT_T72p
DIFFOUT_T73p
DIFFOUT_T73n
DIFFOUT_T74p
DIFFOUT_T75p
DIFFOUT_T75n
DIFFOUT_T76p
DIFFOUT_T77p
DIFFOUT_T77n
DIFFOUT_T78p
DIFFOUT_T79p
DIFFOUT_T79n
DIFFOUT_T80p
DIFFOUT_T81p
DIFFOUT_T81n
DIFFOUT_T82p
DIFFOUT_T83p
DIFFOUT_T83n
DIFFOUT_T84p
DIFFOUT_T85p
DIFFOUT_T85n
DIFFIO_RX_T86p
DIFFIO_RX_T86n
DIFFIO_TX_T87p
DIFFIO_TX_T87n
DIFFIO_RX_T88p
DIFFIO_RX_T88n
DIFFIO_TX_T89p
DIFFIO_TX_T89n
DIFFIO_RX_T90p
DIFFIO_RX_T90n
DIFFIO_TX_T91p
DIFFIO_TX_T91n
DIFFIO_RX_T92p
DIFFIO_RX_T92n
DIFFIO_TX_T93p
DIFFIO_TX_T93n
DIFFIO_RX_T94p
DIFFIO_RX_T94n
DIFFIO_TX_T95p
DIFFIO_TX_T95n
DIFFIO_RX_T96p
DIFFIO_RX_T96n
DIFFIO_TX_T97p
DIFFIO_TX_T97n
DIFFIO_RX_T98p
DIFFIO_RX_T98n
DIFFIO_TX_T99p
DIFFIO_TX_T99n
DIFFIO_RX_T100p
DIFFIO_RX_T100n
DIFFIO_TX_T101p
DIFFIO_TX_T101n
DIFFIO_RX_T102p
DIFFIO_RX_T102n
DIFFIO_TX_T103p
DIFFIO_TX_T103n
DIFFIO_RX_T104p
DIFFIO_RX_T104n
DIFFIO_TX_T105p
DIFFIO_TX_T105n
DIFFIO_RX_T106p
DIFFIO_RX_T106n
DIFFIO_TX_T107p
DIFFIO_TX_T107n
DIFFIO_RX_T108p
DIFFIO_RX_T108n
DIFFOUT_T86p
DIFFOUT_T86n
DIFFOUT_T87p
DIFFOUT_T87n
DIFFOUT_T88p
DIFFOUT_T88n
DIFFOUT_T89p
DIFFOUT_T89n
DIFFOUT_T90p
DIFFOUT_T90n
DIFFOUT_T91p
DIFFOUT_T91n
DIFFOUT_T92p
DIFFOUT_T92n
DIFFOUT_T93p
DIFFOUT_T93n
DIFFOUT_T94p
DIFFOUT_T94n
DIFFOUT_T95p
DIFFOUT_T95n
DIFFOUT_T96p
DIFFOUT_T96n
DIFFOUT_T97p
DIFFOUT_T97n
DIFFOUT_T98p
DIFFOUT_T98n
DIFFOUT_T99p
DIFFOUT_T99n
DIFFOUT_T100p
DIFFOUT_T100n
DIFFOUT_T101p
DIFFOUT_T101n
DIFFOUT_T102p
DIFFOUT_T102n
DIFFOUT_T103p
DIFFOUT_T103n
DIFFOUT_T104p
DIFFOUT_T104n
DIFFOUT_T105p
DIFFOUT_T105n
DIFFOUT_T106p
DIFFOUT_T106n
DIFFOUT_T107p
DIFFOUT_T107n
DIFFOUT_T108p
DIFFOUT_T108n
DIFFIO_RX_T109p
DIFFIO_RX_T109n
DIFFIO_TX_T110p
DIFFIO_TX_T110n
DIFFIO_RX_T111p
DIFFIO_RX_T111n
DIFFIO_RX_T113p
DIFFIO_RX_T113n
DIFFIO_TX_T114n
DIFFOUT_T109p
DIFFOUT_T109n
DIFFOUT_T110p
DIFFOUT_T110n
DIFFOUT_T111p
DIFFOUT_T111n
DIFFOUT_T113p
DIFFOUT_T113n
DIFFOUT_T114n
A20
A21
K19
L19
K20
L20
P20
E20
F20
G20
B21
C21
N20
H21
J20
E21
J21
K21
N21
P21
M21
M20
F21
D22
E22
N22
A24
A23
E23
F23
G23
H23
P22
G22
H22
J23
K22
L22
N23
L23
M23
K23
B23
C24
M24
C23
D23
G24
C25
D24
P24
E24
D25
H24
A25
A26
M25
N25
B26
C26
A27
A28
D26
E26
K24
L24
F26
F25
G26
G25
B27
C28
J25
K25
B29
C29
A29
A30
A31
B30
J26
K26
A33
A32
C33
B32
D27
D28
L26
M26
E27
F27
F28
G28
C32
C31
L27
M28
D31
E31
E30
F29
G29
H29
N26
J29
J28
K29
L29
J27
K28
H26
H27
D29
B34
C34
D34
K30
VREFB8DN0
VREFB8CN0
VREFB8BN0
CLK23p
CLK23n
CLK22p
CLK22n
VREFB8AN0
FPLL_TL_CLKOUT2,FPLL_TL_FBp,FPLL_TL_FB1
FPLL_TL_CLKOUT3,FPLL_TL_FBn
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB0
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn
CLK21p
CLK21n
CLK20p
CLK20n
RZQ_6
MSEL0
MSEL1
MSEL2
MSEL3
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
DQ5_8C_0
DQ5_8C_1
DQ5_8C_2
DQ5_8C_3
DQ5_8C_4
DQ5_8C_5
DQS5_8C
DQS#5_8C
DM5_8C
DQ5_8C_6
DQ5_8C_7
DQ5_8C_8
DQ4_8C_0
DQ4_8C_1
DQ4_8C_2
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQS1T/CQ1T/CQn1T/QKn1T
DQSn1T/QK1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ5_8C_0
DQ5_8C_1
DQ5_8C_2
DQ5_8C_3
DQ5_8C_4
DQ5_8C_5
DQS5_8C
DQS#5_8C
DM5_8C
DQ5_8C_6
DQ5_8C_7
DQ5_8C_8
DQ4_8C_0
DQ4_8C_1
DQ4_8C_2
DQ2T
DQ2T
DQ2T
DQS2T/CQ2T/CQn2T/QKn2T
DQSn2T/QK2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQS1T/CQ1T/CQn1T/QKn1T
DQSn1T/QK1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ4_8C_3
DQ4_8C_4
DQ4_8C_5
DQS4_8C
DQS#4_8C
DM4_8C
DQ4_8C_6
DQ4_8C_7
DQ4_8C_8
DQ4_8C_3
DQ4_8C_4
DQ4_8C_5
DQS4_8C
DQS#4_8C
DM4_8C
DQ4_8C_6
DQ4_8C_7
DQ4_8C_8
DQ3T
DQ3T
DQ3T
DQ3T
DQ3T
DQ3T
DQS3T/CQ3T/CQn3T/QKn3T
DQSn3T/QK3T
DQ3T
DQ3T
DQ3T
DQ3T
DQ4T
DQ4T
DQ4T
DQ4T
DQ4T
DQ4T
DQS4T/CQ4T/CQn4T/QKn4T
DQSn4T/QK4T
DQ4T
DQ4T
DQ4T
DQ4T
DQ5T
DQ5T
DQ5T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQS2T/CQ2T/CQn2T/QKn2T
DQSn2T/QK2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQS1T/CQ1T/CQn1T/QKn1T
DQSn1T/QK1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ3_8C_0
DQ3_8C_1
DQ3_8C_2
DQ3_8C_3
DQ3_8C_4
DQ3_8C_5
DQS3_8C
DQS#3_8C
DM3_8C
DQ3_8C_6
DQ3_8C_7
DQ3_8C_8
DQ2_8B_0
DQ2_8B_1
DQ2_8B_2
DQ2_8B_3
DQ2_8B_4
DQ2_8B_5
DQS2_8B
DQS#2_8B
DM2_8B
DQ2_8B_6
DQ2_8B_7
DQ2_8B_8
DQ1_8B_0
DQ1_8B_1
DQ1_8B_2
DQ3_8C_0
DQ3_8C_1
DQ3_8C_2
DQ3_8C_3
DQ3_8C_4
DQ3_8C_5
DQS3_8C
DQS#3_8C
DM3_8C
DQ3_8C_6
DQ3_8C_7
DQ3_8C_8
DQ2_8B_0
DQ2_8B_1
DQ2_8B_2
DQ2_8B_3
DQ2_8B_4
DQ2_8B_5
DQS2_8B
DQS#2_8B
DM2_8B
DQ2_8B_6
DQ2_8B_7
DQ2_8B_8
DQ1_8B_0
DQ1_8B_1
DQ1_8B_2
DQ5T
DQ5T
DQ5T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1_8B_3
DQ1_8B_4
DQ1_8B_5
DQ1_8B_3
DQ1_8B_4
DQ1_8B_5
DQS5T/CQ5T/CQn5T/QKn5T
DQSn5T/QK5T
DQ5T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQS1_8B
DQS#1_8B
DM1_8B
DQS1_8B
DQS#1_8B
DM1_8B
DQ5T
DQ5T
DQ5T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1_8B_6
DQ1_8B_7
DQ1_8B_8
DQ6T
DQ6T
DQ6T
DQ3T
DQ3T
DQ3T
DQ6T
DQ6T
DQ6T
DQ3T
DQ3T
DQ3T
DQS6T/CQ6T/CQn6T/QKn6T
DQSn6T/QK6T
DQ6T
DQS3T/CQ3T/CQn3T/QKn3T
DQSn3T/QK3T
DQ3T
DQ6T
DQ6T
DQ6T
DQ3T
DQ3T
DQ3T
DQ7T
DQ7T
DQ7T
DQ3T
DQ3T
DQ3T
DQ7T
DQ7T
DQ7T
DQ3T
DQ3T
DQ3T
DQS7T/CQ7T/CQn7T/QKn7T
DQSn7T/QK7T
DQ7T
DQ3T
DQ3T
DQ3T
DQ1_8B_6
DQ1_8B_7
DQ1_8B_8
RESET#_8A
CK_8A
CK#_8A
CKE_8A_0
CKE_8A_1
A_8A_0
A_8A_1
A_8A_2
A_8A_3
A_8A_4
A_8A_5
A_8A_6
A_8A_7
A_8A_8
A_8A_9
A_8A_10
A_8A_11
A_8A_12
A_8A_13
A_8A_14
A_8A_15
BA_8A_0
BA_8A_1
BA_8A_2
RAS#_8A
CAS#_8A
WE#_8A
ODT_8A_0
ODT_8A_1
DQ7T
DQ7T
DQ7T
DQ3T
DQ3T
DQ3T
CS#_8A_0
CS#_8A_1
CS#_8A_0
CS#_8A_1
Pin List GF35
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
CK_8A
CK#_8A
CKE_8A_0
CKE_8A_1
CA_8A_0
CA_8A_1
CA_8A_2
CA_8A_3
CA_8A_4
CA_8A_5
CA_8A_6
CA_8A_7
CA_8A_8
CA_8A_9
ODT_8A_0
ODT_8A_1
Page 6 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
8A
8A
8A
8A
8A
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
VREF
PinName/Function (2), (3)
MSEL4
CONF_DONE
nSTATUS
nCE
nCONFIG
GND
VCC_HPS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
MSEL4
CONF_DONE
nSTATUS
nCE
nCONFIG
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1152 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
D32
D33
N27
H30
M29
F30
U16
U15
AA26
AA29
AA33
AA34
AB27
AB28
AB30
AB31
AB32
AC30
AC33
AC34
AD31
AD32
AE30
AE33
AE34
AF31
AF32
AG30
AG33
AG34
AH31
AH32
AJ30
AJ33
AJ34
AK31
AK32
AL33
AL34
E34
F31
F32
G30
G33
G34
H31
H32
J30
J33
J34
K31
K32
L30
L33
L34
M30
M31
M32
N28
N29
N33
N34
P27
P31
P32
R28
R30
R33
R34
T27
T29
T31
T32
U28
U33
U34
V27
V31
V32
W28
W30
W33
W34
Y27
Y29
Y31
Y32
AA1
AA2
AB3
AB4
AC1
AC2
AC5
AD3
AD4
AE1
AE2
AE5
AF3
AF4
AG1
AG2
AG5
AH3
AH4
AJ1
AJ2
AJ5
AK3
AK4
AL1
AL2
AL3
AN1
V3
V4
V7
Pin List GF35
Page 7 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
GND
GND
GND
GND
GND
GND
GND
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCPLL_HPS
VCCBAT
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX_SHARED
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCA_GXBL0
VCCA_GXBR0
VCCA_GXBL1
VCCH_GXBL0
VCCH_GXBR0
VCCH_GXBL1
VCCL_GXBL0
VCCL_GXBL0
VCCL_GXBR0
VCCL_GXBR0
VCCL_GXBL1
VCCL_GXBL1
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCT_GXBL0
VCCT_GXBL0
VCCT_GXBL0
VCCT_GXBR0
VCCT_GXBR0
VCCT_GXBL1
VCCT_GXBL1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4C
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1152 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
W1
W2
W5
Y3
Y4
Y6
Y8
R18
T21
V25
W10
Y10
Y12
Y22
Y24
Y25
V26
V9
T26
M9
M27
AA24
Y11
R24
R12
Y26
Y9
P26
Y28
Y7
T28
V28
V6
P28
V29
V30
V5
Y5
P29
P30
AA30
AB29
N30
R29
AA5
AB6
AB5
T30
U29
U30
W6
AA6
W29
Y30
AA20
T19
T23
T25
V24
U18
U20
U22
U24
V15
V17
V19
V20
V21
V22
V23
W16
W14
W20
W22
W24
Y13
Y14
Y15
Y16
Y17
Y19
Y21
Y23
W18
T11
U10
U12
U14
V11
V12
V13
W12
AF27
AF30
AH30
AJ28
AK30
AN29
AF25
AK24
AN24
AD21
AF21
AJ21
AM21
AE18
AH18
AL18
AD5
AE8
AF5
AH5
AK5
AD11
AF10
AJ10
AM9
AE13
Pin List GF35
Page 8 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
VREFB7A7B7C7D7EN0_HPS
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
PinName/Function (2), (3)
VCCIO4C
VCCIO4C
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7B_HPS
VCCIO7B_HPS
VCCIO7C_HPS
VCCIO7D_HPS
VCCIO7D_HPS
VCCIO7E_HPS
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8B
VCCIO8B
VCCIO8B
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8D
VCCIO8D
VCCIO8D
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD4A
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD7A_HPS
VCCPD7B_HPS
VCCPD7C_HPS
VCCPD7D_HPS
VCCPD7E_HPS
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPGM
VCCPGM
VCCRSTCLK_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VREFB7A7B7C7D7EN0_HPS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1152 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
AH12
AL12
AF15
AJ15
AM15
AN17
B3
C6
D3
D8
E6
F2
H5
H7
M7
L4
M1
N8
P3
R6
U5
V2
B9
D11
E13
K11
B13
L13
H15
E17
H18
L18
C27
C30
E29
E32
G27
K27
B24
F24
J24
B22
D21
G21
L21
B18
B20
H20
AA21
AA23
AB26
AC28
AB8
AA11
AA14
AA15
AB9
P9
R8
U7
U8
R11
R13
T15
R16
P17
P23
P25
R20
R22
H13
AC29
H9
R10
R14
T13
T9
P15
A19
A22
A5
AA10
AA13
AA16
AA19
AA22
AA25
AA9
AB7
AC6
AD10
AD13
AD16
AD19
AD22
AD25
AD28
AD7
AG10
AG13
AG16
AG19
AG22
AG25
AG28
AG7
AK10
AK13
AK16
AK19
AK22
AK25
AK28
AK7
AN10
AN13
AN16
AN19
Pin List GF35
Page 9 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1152 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select HPS Pin Mux Select HPS Pin Mux Select
2
1
0
AN22
AN25
AN28
AN31
AN4
AN7
B11
B16
B2
B25
B28
B31
B33
B8
C19
C22
C5
D2
D30
E14
E25
E28
E8
F19
F22
F5
G11
G2
H25
H28
H8
J13
J19
J22
J5
K16
K2
L25
L28
L8
M19
M22
M5
N11
N15
N2
N24
P13
P18
P8
V18
V14
V16
V8
W11
W13
W15
W17
W19
W21
W23
W25
W9
Y18
Y20
R17
R19
R21
R23
R25
R5
R9
T10
T12
T14
T18
T2
T20
T22
T24
U11
U13
U17
U19
U21
U23
U25
U6
U9
V10
Notes:
(1) For more information about pin definitions and pin connection guidelines, refer to the
Arria V Device Family Pin Connection Guidelines.
(2) GXB_REFCLK pin is not supported in current Quartus II version, but will be supported in future Quartus II release version.
(3) Pins with * contains similar name with other pins in the same column. For the selection of the HPS pins, refer to the "HPS Pin Mux Select x" columns.
(4) Pins with * are the 10 Gbps transceiver channels. For more information about the 10 Gbps transceiver channels clocking recommendation, refer to the
Transceiver Clocking in Arria V Devices chapter.
(5) RESET pin is only applicable for DDR3 device.
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Pin List GF35
Page 10 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
DNU
DNU
RREF_TL
REFCLK5Ln
REFCLK5Lp
GXB_TX_L17n
GXB_TX_L17p
GXB_RX_L17p,GXB_REFCLK_L17p
GXB_RX_L17n,GXB_REFCLK_L17n
GXB_TX_L16n
GXB_TX_L16p
GXB_RX_L16p,GXB_REFCLK_L16p
GXB_RX_L16n,GXB_REFCLK_L16n
GXB_TX_L15n
GXB_TX_L15p
GXB_RX_L15p,GXB_REFCLK_L15p
GXB_RX_L15n,GXB_REFCLK_L15n
GXB_TX_L14n
GXB_TX_L14p
GXB_RX_L14p,GXB_REFCLK_L14p
GXB_RX_L14n,GXB_REFCLK_L14n
GXB_TX_L13n
GXB_TX_L13p
GXB_RX_L13p,GXB_REFCLK_L13p
GXB_RX_L13n,GXB_REFCLK_L13n
GXB_TX_L12n
GXB_TX_L12p
GXB_RX_L12p,GXB_REFCLK_L12p
GXB_RX_L12n,GXB_REFCLK_L12n
REFCLK4Ln
REFCLK4Lp
REFCLK3Ln
REFCLK3Lp
GXB_TX_L11n
GXB_TX_L11p
GXB_RX_L11p,GXB_REFCLK_L11p
GXB_RX_L11n,GXB_REFCLK_L11n
GXB_TX_L10n
GXB_TX_L10p
GXB_RX_L10p,GXB_REFCLK_L10p
GXB_RX_L10n,GXB_REFCLK_L10n
GXB_TX_L9n
GXB_TX_L9p
GXB_RX_L9p,GXB_REFCLK_L9p
GXB_RX_L9n,GXB_REFCLK_L9n
GXB_TX_L8n
GXB_TX_L8p
GXB_RX_L8p,GXB_REFCLK_L8p
GXB_RX_L8n,GXB_REFCLK_L8n
GXB_TX_L7n
GXB_TX_L7p
GXB_RX_L7p,GXB_REFCLK_L7p
GXB_RX_L7n,GXB_REFCLK_L7n
GXB_TX_L6n
GXB_TX_L6p
GXB_RX_L6p,GXB_REFCLK_L6p
GXB_RX_L6n,GXB_REFCLK_L6n
REFCLK2Ln
REFCLK2Lp
REFCLK1Ln
REFCLK1Lp
GXB_TX_L5n
GXB_TX_L5p
GXB_RX_L5p,GXB_REFCLK_L5p
GXB_RX_L5n,GXB_REFCLK_L5n
GXB_TX_L4n
GXB_TX_L4p
GXB_RX_L4p,GXB_REFCLK_L4p
GXB_RX_L4n,GXB_REFCLK_L4n
GXB_TX_L3n
GXB_TX_L3p
GXB_RX_L3p,GXB_REFCLK_L3p
GXB_RX_L3n,GXB_REFCLK_L3n
GXB_TX_L2n
GXB_TX_L2p
GXB_RX_L2p,GXB_REFCLK_L2p
GXB_RX_L2n,GXB_REFCLK_L2n
GXB_TX_L1n
GXB_TX_L1p
GXB_RX_L1p,GXB_REFCLK_L1p
GXB_RX_L1n,GXB_REFCLK_L1n
GXB_TX_L0n
GXB_TX_L0p
GXB_RX_L0p,GXB_REFCLK_L0p
GXB_RX_L0n,GXB_REFCLK_L0n
REFCLK0Ln
REFCLK0Lp
DNU
TDO
TMS
TCK
TDI
DCLK
nCSO
AS_DATA3
AS_DATA2
AS_DATA1
AS_DATA0,ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L2
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L1
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
GXB_L0
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
TDO
TMS
TCK
TDI
DCLK
DATA4
DATA3
DATA2
DATA1
DATA0
RZQ_0
CLK0n
CLK0p
CLK1n
CLK1p
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB0
FPLL_BL_CLKOUT3,FPLL_BL_FBn
FPLL_BL_CLKOUT2,FPLL_BL_FBp,FPLL_BL_FB1
VREFB3AN0
CLK2n
CLK2p
CLK3n
CLK3p
DIFFIO_TX_B1n
DIFFIO_TX_B1p
DIFFIO_RX_B2n
DIFFIO_RX_B2p
DIFFIO_TX_B3n
DIFFIO_TX_B3p
DIFFIO_RX_B4n
DIFFIO_RX_B4p
DIFFIO_TX_B5n
DIFFIO_TX_B5p
DIFFIO_RX_B6n
DIFFIO_RX_B6p
DIFFOUT_B1n
DIFFOUT_B1p
DIFFOUT_B2n
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B3p
DIFFOUT_B4n
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B5p
DIFFOUT_B6n
DIFFOUT_B6p
DIFFIO_RX_B7n
DIFFIO_RX_B7p
DIFFIO_TX_B8n
DIFFIO_TX_B8p
DIFFIO_RX_B9n
DIFFIO_RX_B9p
DIFFOUT_B7n
DIFFOUT_B7p
DIFFOUT_B8n
DIFFOUT_B8p
DIFFOUT_B9n
DIFFOUT_B9p
F1517 (4) DQS for X8/X9
DQS for X16/ X18
A38
B38
B39
U32
U31
C36
C37
D39
D38
E36
E37
F39
F38
G36
G37
H39
H38
J36
J37
K39
K38
L36
L37
M39
M38
N36
N37
P39
P38
W32
W31
AA32
AA31
R36
R37
T39
T38
U36
U37
V39
V38
W36
W37
Y39
Y38
AA36
AA37
AB39
AB38
AC36
AC37
AD39
AD38
AE36
AE37
AF39
AF38
AC32
AC31
AE32
AE31
AG36
AG37
AH39
AH38
AJ36
AJ37
AK39
AK38
AL36
AL37
AM39
AM38
AN36
AN37
AP39
AP38
AR36
AR37
AT39
AT38
AU36
AU37
AW37
AW36
AG33
AG32
AH31
AT34
AM35
AV34
AT33
AW34
AR34
AU34
AR33
AU33
AV33
AN33
AP33
AN34
AP34
AK32
AL32
AJ34
AK34
AL34
AM34
AJ33
AK33
AJ31
AK31
AL33
AM33
AN32
AP32
AT32
AU32
DQ1B
DQ1B
DQ1B
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
CS#_3A_1
CS#_3A_0
CS#_3A_1
CS#_3A_0
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
DQ1B
DQ1B
DQ1B
DQ1B
DQSn1B/QK1B
DQS1B/CQ1B/CQn1B/QKn1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
Pin List HF40
Page 11 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3C
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3CN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DIFFIO_TX_B10n
DIFFIO_TX_B10p
DIFFIO_RX_B11n
DIFFIO_RX_B11p
DIFFIO_TX_B12n
DIFFIO_TX_B12p
DIFFIO_RX_B13n
DIFFIO_RX_B13p
DIFFIO_TX_B14n
DIFFIO_TX_B14p
DIFFIO_RX_B15n
DIFFIO_RX_B15p
DIFFIO_TX_B16n
DIFFIO_TX_B16p
DIFFIO_RX_B17n
DIFFIO_RX_B17p
DIFFIO_TX_B18n
DIFFIO_TX_B18p
DIFFIO_RX_B19n
DIFFIO_RX_B19p
DIFFIO_TX_B20n
DIFFIO_TX_B20p
DIFFIO_RX_B21n
DIFFIO_RX_B21p
DIFFIO_TX_B22n
DIFFIO_TX_B22p
DIFFIO_RX_B23n
DIFFIO_RX_B23p
DIFFIO_TX_B24n
DIFFIO_TX_B24p
DIFFIO_RX_B25n
DIFFIO_RX_B25p
DIFFIO_TX_B26n
DIFFIO_TX_B26p
DIFFIO_RX_B27n
DIFFIO_RX_B27p
DIFFIO_TX_B28n
DIFFIO_TX_B28p
DIFFIO_RX_B29n
DIFFIO_RX_B29p
DIFFOUT_B10n
DIFFOUT_B10p
DIFFOUT_B11n
DIFFOUT_B11p
DIFFOUT_B12n
DIFFOUT_B12p
DIFFOUT_B13n
DIFFOUT_B13p
DIFFOUT_B14n
DIFFOUT_B14p
DIFFOUT_B15n
DIFFOUT_B15p
DIFFOUT_B16n
DIFFOUT_B16p
DIFFOUT_B17n
DIFFOUT_B17p
DIFFOUT_B18n
DIFFOUT_B18p
DIFFOUT_B19n
DIFFOUT_B19p
DIFFOUT_B20n
DIFFOUT_B20p
DIFFOUT_B21n
DIFFOUT_B21p
DIFFOUT_B22n
DIFFOUT_B22p
DIFFOUT_B23n
DIFFOUT_B23p
DIFFOUT_B24n
DIFFOUT_B24p
DIFFOUT_B25n
DIFFOUT_B25p
DIFFOUT_B26n
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B27p
DIFFOUT_B28n
DIFFOUT_B28p
DIFFOUT_B29n
DIFFOUT_B29p
DIFFIO_RX_B30n
DIFFIO_RX_B30p
DIFFIO_TX_B31n
DIFFIO_TX_B31p
DIFFIO_RX_B32n
DIFFIO_RX_B32p
DIFFIO_TX_B33n
DIFFIO_TX_B33p
DIFFIO_RX_B34n
DIFFIO_RX_B34p
DIFFIO_TX_B35n
DIFFIO_TX_B35p
DIFFIO_RX_B36n
DIFFIO_RX_B36p
DIFFIO_TX_B37n
DIFFIO_TX_B37p
DIFFIO_RX_B38n
DIFFIO_RX_B38p
DIFFIO_TX_B39n
DIFFIO_TX_B39p
DIFFIO_RX_B40n
DIFFIO_RX_B40p
DIFFIO_TX_B41n
DIFFIO_TX_B41p
DIFFIO_RX_B42n
DIFFIO_RX_B42p
DIFFIO_TX_B43n
DIFFIO_TX_B43p
DIFFIO_RX_B44n
DIFFIO_RX_B44p
DIFFIO_TX_B45n
DIFFIO_TX_B45p
DIFFIO_RX_B46n
DIFFIO_RX_B46p
DIFFIO_TX_B47n
DIFFIO_TX_B47p
DIFFIO_RX_B48n
DIFFIO_RX_B48p
DIFFIO_TX_B49n
DIFFIO_TX_B49p
DIFFIO_RX_B50n
DIFFIO_RX_B50p
DIFFIO_TX_B51n
DIFFIO_TX_B51p
DIFFIO_RX_B52n
DIFFIO_RX_B52p
DIFFOUT_B30n
DIFFOUT_B30p
DIFFOUT_B31n
DIFFOUT_B31p
DIFFOUT_B32n
DIFFOUT_B32p
DIFFOUT_B33n
DIFFOUT_B33p
DIFFOUT_B34n
DIFFOUT_B34p
DIFFOUT_B35n
DIFFOUT_B35p
DIFFOUT_B36n
DIFFOUT_B36p
DIFFOUT_B37n
DIFFOUT_B37p
DIFFOUT_B38n
DIFFOUT_B38p
DIFFOUT_B39n
DIFFOUT_B39p
DIFFOUT_B40n
DIFFOUT_B40p
DIFFOUT_B41n
DIFFOUT_B41p
DIFFOUT_B42n
DIFFOUT_B42p
DIFFOUT_B43n
DIFFOUT_B43p
DIFFOUT_B44n
DIFFOUT_B44p
DIFFOUT_B45n
DIFFOUT_B45p
DIFFOUT_B46n
DIFFOUT_B46p
DIFFOUT_B47n
DIFFOUT_B47p
DIFFOUT_B48n
DIFFOUT_B48p
DIFFOUT_B49n
DIFFOUT_B49p
DIFFOUT_B50n
DIFFOUT_B50p
DIFFOUT_B51n
DIFFOUT_B51p
DIFFOUT_B52n
DIFFOUT_B52p
DIFFIO_RX_B53n
DIFFIO_RX_B53p
DIFFIO_TX_B54n
DIFFIO_TX_B54p
DIFFIO_RX_B55n
DIFFIO_RX_B55p
DIFFIO_TX_B56n
DIFFIO_TX_B56p
DIFFIO_RX_B57n
DIFFIO_RX_B57p
DIFFIO_TX_B58n
DIFFIO_TX_B58p
DIFFIO_RX_B59n
DIFFIO_RX_B59p
DIFFIO_TX_B60n
DIFFIO_TX_B60p
DIFFIO_RX_B61n
DIFFIO_RX_B61p
DIFFIO_TX_B62n
DIFFIO_TX_B62p
DIFFIO_RX_B63n
DIFFIO_RX_B63p
DIFFIO_TX_B64n
DIFFIO_TX_B64p
DIFFIO_RX_B65n
DIFFIO_RX_B65p
DIFFIO_TX_B66n
DIFFIO_TX_B66p
DIFFOUT_B53n
DIFFOUT_B53p
DIFFOUT_B54n
DIFFOUT_B54p
DIFFOUT_B55n
DIFFOUT_B55p
DIFFOUT_B56n
DIFFOUT_B56p
DIFFOUT_B57n
DIFFOUT_B57p
DIFFOUT_B58n
DIFFOUT_B58p
DIFFOUT_B59n
DIFFOUT_B59p
DIFFOUT_B60n
DIFFOUT_B60p
DIFFOUT_B61n
DIFFOUT_B61p
DIFFOUT_B62n
DIFFOUT_B62p
DIFFOUT_B63n
DIFFOUT_B63p
DIFFOUT_B64n
DIFFOUT_B64p
DIFFOUT_B65n
DIFFOUT_B65p
DIFFOUT_B66n
DIFFOUT_B66p
AL31
AM31
AW33
AW32
AN31
AP31
AR31
AT31
AD29
AE29
AG30
AH30
AU31
AV31
AW30
AW31
AK30
AL30
AR30
AT30
AU30
AV30
AT29
AU29
AN30
AP30
AN29
AP29
AB29
AC29
AF28
AG28
AK29
AL29
AH28
AJ28
AD28
AE28
AB27
AB28
AL28
AM28
AC27
AD27
AP28
AR28
AU28
AV28
AJ27
AK27
AW29
AW28
AP27
AR27
AT27
AU27
AM27
AN27
AV27
AW27
AG27
AH27
AB25
AC25
AE27
AF27
AE25
AF25
AC24
AD25
AG26
AH26
AD26
AE26
AG25
AH25
AN26
AP26
AM25
AN25
AJ25
AK25
AT26
AU26
AR25
AT25
AW25
AW26
AK26
AL26
AV25
AV24
AD23
AD24
AT24
AU24
AK24
AL24
AE24
AF24
AG24
AH24
AW23
AW24
AN24
AP24
AT23
AU23
AN23
AP23
AD22
AE23
AK23
AL23
AT22
AU22
AV22
AW22
VREFB3BN0
VREFB3CN0
DQS for X16/ X18
HMC pin
assignment for
LPDDR2
ODT_3A_1
ODT_3A_0
DQ1B
DQ1B
DQ1B
HMC pin
assignment for
DDR3 (5)
ODT_3A_1
ODT_3A_0
WE#_3A
CAS#_3A
RAS#_3A
BA_3A_2
BA_3A_1
BA_3A_0
A_3A_15
A_3A_14
A_3A_13
A_3A_12
A_3A_11
A_3A_10
A_3A_9
A_3A_8
A_3A_7
A_3A_6
A_3A_5
A_3A_4
A_3A_3
A_3A_2
A_3A_1
A_3A_0
CKE_3A_1
CKE_3A_0
CK#_3A
CK_3A
RESET#_3A
DQ1_3B_8
DQ1_3B_7
DQ1_3B_6
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DM1_3B
DQS#1_3B
DQS1_3B
DM1_3B
DQS#1_3B
DQS1_3B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1_3B_5
DQ1_3B_4
DQ1_3B_3
DQ1_3B_5
DQ1_3B_4
DQ1_3B_3
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ1_3B_2
DQ1_3B_1
DQ1_3B_0
DQ1_3B_2
DQ1_3B_1
DQ1_3B_0
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ2_3B_8
DQ2_3B_7
DQ2_3B_6
DQ2_3B_8
DQ2_3B_7
DQ2_3B_6
DQ5B
DQSn5B/QK5B
DQS5B/CQ5B/CQn5B/QKn5B
DQ2B
DQSn2B/QK2B
DQS2B/CQ2B/CQn2B/QKn2B
DQ1B
DQ1B
DQ1B
DM2_3B
DQS#2_3B
DQS2_3B
DM2_3B
DQS#2_3B
DQS2_3B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ2_3B_5
DQ2_3B_4
DQ2_3B_3
DQ2_3B_5
DQ2_3B_4
DQ2_3B_3
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ2_3B_2
DQ2_3B_1
DQ2_3B_0
DQ2_3B_2
DQ2_3B_1
DQ2_3B_0
DQ6B
DQ6B
DQ6B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ3_3C_8
DQ3_3C_7
DQ3_3C_6
DQ3_3C_8
DQ3_3C_7
DQ3_3C_6
DQ6B
DQSn6B/QK6B
DQS6B/CQ6B/CQn6B/QKn6B
DQ3B
DQ3B
DQ3B
DQ1B
DQSn1B/QK1B
DQS1B/CQ1B/CQn1B/QKn1B
DM3_3C
DQS#3_3C
DQS3_3C
DM3_3C
DQS#3_3C
DQS3_3C
DQ6B
DQ6B
DQ6B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ3_3C_5
DQ3_3C_4
DQ3_3C_3
DQ3_3C_5
DQ3_3C_4
DQ3_3C_3
DQ6B
DQ6B
DQ6B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ3_3C_2
DQ3_3C_1
DQ3_3C_0
DQ3_3C_2
DQ3_3C_1
DQ3_3C_0
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ4_3C_8
DQ4_3C_7
DQ4_3C_6
DQ4_3C_8
DQ4_3C_7
DQ4_3C_6
DQ7B
DQSn7B/QK7B
DQS7B/CQ7B/CQn7B/QKn7B
DQ3B
DQSn3B/QK3B
DQS3B/CQ3B/CQn3B/QKn3B
DQ1B
DQ1B
DQ1B
DM4_3C
DQS#4_3C
DQS4_3C
DM4_3C
DQS#4_3C
DQS4_3C
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ4_3C_5
DQ4_3C_4
DQ4_3C_3
DQ4_3C_5
DQ4_3C_4
DQ4_3C_3
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ4_3C_2
DQ4_3C_1
DQ4_3C_0
DQ4_3C_2
DQ4_3C_1
DQ4_3C_0
DQ8B
DQ8B
DQ8B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ5_3C_8
DQ5_3C_7
DQ5_3C_6
DQ5_3C_8
DQ5_3C_7
DQ5_3C_6
DQ8B
DQSn8B/QK8B
DQS8B/CQ8B/CQn8B/QKn8B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DM5_3C
DQS#5_3C
DQS5_3C
DM5_3C
DQS#5_3C
DQS5_3C
DQ8B
DQ8B
DQ8B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ5_3C_5
DQ5_3C_4
DQ5_3C_3
DQ5_3C_5
DQ5_3C_4
DQ5_3C_3
DQ8B
DQ8B
DQ8B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ5_3C_2
DQ5_3C_1
DQ5_3C_0
DQ5_3C_2
DQ5_3C_1
DQ5_3C_0
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ9B
DQSn9B/QK9B
DQS9B/CQ9B/CQn9B/QKn9B
DQ4B
DQSn4B/QK4B
DQS4B/CQ4B/CQn4B/QKn4B
DQ2B
DQ2B
DQ2B
DQ9B
DQ4B
DQ2B
DQ2B
DQSn2B/QK2B
DQS2B/CQ2B/CQn2B/QKn2B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ1B
DQ1B
DQ1B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ3B
DQSn3B/QK3B
DQS3B/CQ3B/CQn3B/QKn3B
DQ1B
DQSn1B/QK1B
DQS1B/CQ1B/CQn1B/QKn1B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ4B
DQSn4B/QK4B
DQS4B/CQ4B/CQn4B/QKn4B
Pin List HF40
DQS for X32/ X36
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
CA_3A_9
CA_3A_8
CA_3A_7
CA_3A_6
CA_3A_5
CA_3A_4
CA_3A_3
CA_3A_2
CA_3A_1
CA_3A_0
CKE_3A_1
CKE_3A_0
CK#_3A
CK_3A
DQ1_3B_8
DQ1_3B_7
DQ1_3B_6
Page 12 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
3D
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
VREFB3DN0
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4D
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
4C
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4DN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4CN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VCCD_FPLL
VCCA_FPLL
DNU
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
DIFFIO_RX_B67n
DIFFIO_RX_B67p
DIFFIO_TX_B68n
DIFFIO_TX_B68p
DIFFIO_RX_B69n
DIFFIO_RX_B69p
DIFFIO_TX_B70n
DIFFIO_TX_B70p
DIFFIO_RX_B71n
DIFFIO_RX_B71p
DIFFIO_TX_B72n
DIFFIO_TX_B72p
DIFFIO_RX_B73n
DIFFIO_RX_B73p
DIFFIO_TX_B74n
DIFFIO_TX_B74p
DIFFIO_RX_B75n
DIFFIO_RX_B75p
DIFFOUT_B67n
DIFFOUT_B67p
DIFFOUT_B68n
DIFFOUT_B68p
DIFFOUT_B69n
DIFFOUT_B69p
DIFFOUT_B70n
DIFFOUT_B70p
DIFFOUT_B71n
DIFFOUT_B71p
DIFFOUT_B72n
DIFFOUT_B72p
DIFFOUT_B73n
DIFFOUT_B73p
DIFFOUT_B74n
DIFFOUT_B74p
DIFFOUT_B75n
DIFFOUT_B75p
DQ9B
DQ9B
DQ4B
DQ4B
DQ2B
DQ2B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ2B
DQ2B
DQ2B
DQ10B
DQ10B
DQ10B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ10B
DQSn10B/QK10B
DQS10B/CQ10B/CQn10B/QKn10B
DQ5B
DQ5B
DQ5B
DQ2B
DQSn2B/QK2B
DQS2B/CQ2B/CQn2B/QKn2B
DQ10B
DQ10B
DQ10B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DIFFIO_RX_B76n
DIFFIO_RX_B76p
DIFFIO_TX_B77n
DIFFIO_TX_B77p
DIFFIO_RX_B78n
DIFFIO_RX_B78p
DIFFIO_TX_B79n
DIFFIO_TX_B79p
DIFFIO_RX_B80n
DIFFIO_RX_B80p
DIFFIO_TX_B81n
DIFFIO_TX_B81p
DIFFIO_RX_B82n
DIFFIO_RX_B82p
DIFFIO_TX_B83n
DIFFIO_TX_B83p
DIFFIO_RX_B84n
DIFFIO_RX_B84p
DIFFOUT_B76n
DIFFOUT_B76p
DIFFOUT_B77n
DIFFOUT_B77p
DIFFOUT_B78n
DIFFOUT_B78p
DIFFOUT_B79n
DIFFOUT_B79p
DIFFOUT_B80n
DIFFOUT_B80p
DIFFOUT_B81n
DIFFOUT_B81p
DIFFOUT_B82n
DIFFOUT_B82p
DIFFOUT_B83n
DIFFOUT_B83p
DIFFOUT_B84n
DIFFOUT_B84p
DQ10B
DQ10B
DQ10B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ11B
DQ11B
DQ11B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ11B
DQSn11B/QK11B
DQS11B/CQ11B/CQn11B/QKn11B
DQ5B
DQSn5B/QK5B
DQS5B/CQ5B/CQn5B/QKn5B
DQ2B
DQ2B
DQ2B
DQ11B
DQ11B
DQ11B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DQ11B
DQ11B
DQ11B
DQ5B
DQ5B
DQ5B
DQ2B
DQ2B
DQ2B
DIFFIO_TX_B85n
DIFFIO_TX_B85p
DIFFIO_RX_B86n
DIFFIO_RX_B86p
DIFFIO_TX_B87n
DIFFIO_TX_B87p
DIFFIO_RX_B88n
DIFFIO_RX_B88p
DIFFIO_TX_B89n
DIFFIO_TX_B89p
DIFFIO_RX_B90n
DIFFIO_RX_B90p
DIFFIO_TX_B91n
DIFFIO_TX_B91p
DIFFIO_RX_B92n
DIFFIO_RX_B92p
DIFFIO_TX_B93n
DIFFIO_TX_B93p
DIFFIO_RX_B94n
DIFFIO_RX_B94p
DIFFIO_TX_B95n
DIFFIO_TX_B95p
DIFFIO_RX_B96n
DIFFIO_RX_B96p
DIFFIO_TX_B97n
DIFFIO_TX_B97p
DIFFIO_RX_B98n
DIFFIO_RX_B98p
DIFFOUT_B85n
DIFFOUT_B85p
DIFFOUT_B86n
DIFFOUT_B86p
DIFFOUT_B87n
DIFFOUT_B87p
DIFFOUT_B88n
DIFFOUT_B88p
DIFFOUT_B89n
DIFFOUT_B89p
DIFFOUT_B90n
DIFFOUT_B90p
DIFFOUT_B91n
DIFFOUT_B91p
DIFFOUT_B92n
DIFFOUT_B92p
DIFFOUT_B93n
DIFFOUT_B93p
DIFFOUT_B94n
DIFFOUT_B94p
DIFFOUT_B95n
DIFFOUT_B95p
DIFFOUT_B96n
DIFFOUT_B96p
DIFFOUT_B97n
DIFFOUT_B97p
DIFFOUT_B98n
DIFFOUT_B98p
DIFFIO_RX_B99n
DIFFIO_RX_B99p
DIFFIO_TX_B100n
DIFFIO_TX_B100p
DIFFIO_RX_B101n
DIFFIO_RX_B101p
DIFFIO_TX_B102n
DIFFIO_TX_B102p
DIFFIO_RX_B103n
DIFFIO_RX_B103p
DIFFIO_TX_B104n
DIFFIO_TX_B104p
DIFFIO_RX_B105n
DIFFIO_RX_B105p
DIFFIO_TX_B106n
DIFFIO_TX_B106p
DIFFIO_RX_B107n
DIFFIO_RX_B107p
DIFFIO_TX_B108n
DIFFIO_TX_B108p
DIFFIO_RX_B109n
DIFFIO_RX_B109p
DIFFIO_TX_B110n
DIFFIO_TX_B110p
DIFFIO_RX_B111n
DIFFIO_RX_B111p
DIFFIO_TX_B112n
DIFFIO_TX_B112p
DIFFIO_RX_B113n
DIFFIO_RX_B113p
DIFFOUT_B99n
DIFFOUT_B99p
DIFFOUT_B100n
DIFFOUT_B100p
DIFFOUT_B101n
DIFFOUT_B101p
DIFFOUT_B102n
DIFFOUT_B102p
DIFFOUT_B103n
DIFFOUT_B103p
DIFFOUT_B104n
DIFFOUT_B104p
DIFFOUT_B105n
DIFFOUT_B105p
DIFFOUT_B106n
DIFFOUT_B106p
DIFFOUT_B107n
DIFFOUT_B107p
DIFFOUT_B108n
DIFFOUT_B108p
DIFFOUT_B109n
DIFFOUT_B109p
DIFFOUT_B110n
DIFFOUT_B110p
DIFFOUT_B111n
DIFFOUT_B111p
DIFFOUT_B112n
DIFFOUT_B112p
DIFFOUT_B113n
DIFFOUT_B113p
DIFFIO_RX_B114n
DIFFIO_RX_B114p
DIFFIO_TX_B115n
DIFFIO_TX_B115p
DIFFIO_RX_B116n
DIFFIO_RX_B116p
DIFFIO_TX_B117n
DIFFIO_TX_B117p
DIFFIO_RX_B118n
DIFFIO_RX_B118p
DIFFIO_TX_B119n
DIFFIO_TX_B119p
DIFFIO_RX_B120n
DIFFIO_RX_B120p
DIFFIO_TX_B121n
DIFFOUT_B114n
DIFFOUT_B114p
DIFFOUT_B115n
DIFFOUT_B115p
DIFFOUT_B116n
DIFFOUT_B116p
DIFFOUT_B117n
DIFFOUT_B117p
DIFFOUT_B118n
DIFFOUT_B118p
DIFFOUT_B119n
DIFFOUT_B119p
DIFFOUT_B120n
DIFFOUT_B120p
DIFFOUT_B121n
AV21
AW21
AG23
AH23
AE22
AF22
AN22
AP22
AW19
AW20
AK22
AL22
AR21
AT21
AG22
AH22
AT20
AU20
AJ21
AK21
AU19
AV19
AM21
AN21
AE21
AF21
AD21
AC22
AG21
AH21
AN20
AP20
AC21
AD20
AG20
AH20
AK20
AL20
AB20
AB21
AE20
AV18
AW18
AG19
AH19
AN19
AP19
AK19
AL19
AH18
AJ18
AU18
AT19
AE19
AF19
AW17
AW16
AK17
AL17
AT17
AU17
AC19
AD19
AP18
AR18
AD17
AC18
AD18
AE18
AF18
AG18
AL18
AM18
AG17
AH17
AN17
AP17
AR16
AT16
AU16
AV16
AJ16
AK16
AN16
AP16
AL16
AM16
AE17
AF16
AN15
AP15
AW14
AW15
AC16
AD16
AG16
AH16
AK15
AL15
AV13
AW13
AG15
AH15
AT15
AU15
AC15
AD14
AT14
AU14
AT13
AU13
AE16
AF15
AK14
AL14
AN14
AP14
AG14
VREFB3DN0
CLK4n
CLK4p
CLK5n
CLK5p
FPLL_BC_CLKOUT1,FPLL_BC_CLKOUTn
FPLL_BC_CLKOUT0,FPLL_BC_CLKOUTp,FPLL_BC_FB0
FPLL_BC_CLKOUT3,FPLL_BC_FBn
FPLL_BC_CLKOUT2,FPLL_BC_FBp,FPLL_BC_FB1
CLK6n
CLK6p
CLK7n
CLK7p
VREFB4DN0
VREFB4CN0
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
CS#_4D_1
CS#_4D_0
CS#_4D_1
CS#_4D_0
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
DQ12B
DQ12B
DQ12B
DQ12B
DQSn12B/QK12B
DQS12B/CQ12B/CQn12B/QKn12B
DQ12B
DQ12B
DQ12B
DQ12B
DQ12B
DQ12B
DQ13B
DQ13B
DQ13B
DQ6B
DQ6B
DQ6B
DQ13B
DQSn13B/QK13B
DQS13B/CQ13B/CQn13B/QKn13B
DQ6B
DQ6B
DQ6B
DQ13B
DQ13B
DQ13B
DQ6B
DQ6B
DQ6B
DQ13B
DQ13B
DQ13B
DQ6B
DQ6B
DQ6B
DQ14B
DQ14B
DQ14B
DQ6B
DQ6B
DQ6B
DQ14B
DQSn14B/QK14B
DQS14B/CQ14B/CQn14B/QKn14B
DQ6B
DQSn6B/QK6B
DQS6B/CQ6B/CQn6B/QKn6B
DQ14B
DQ14B
DQ14B
DQ6B
DQ6B
DQ6B
DQ14B
DQ14B
DQ14B
DQ6B
DQ6B
DQ6B
DQ15B
DQ15B
DQ15B
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
A_4D_14
A_4D_13
A_4D_12
A_4D_11
A_4D_10
A_4D_9
A_4D_8
A_4D_7
A_4D_6
A_4D_5
A_4D_4
A_4D_3
A_4D_2
A_4D_1
A_4D_0
CKE_4D_1
CKE_4D_0
CK#_4D
CK_4D
RESET#_4D
DQ1_4C_8
DQ1_4C_7
DQ1_4C_6
DQ15B
DQSn15B/QK15B
DQS15B/CQ15B/CQn15B/QKn15B
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DM1_4C
DQS#1_4C
DQS1_4C
DM1_4C
DQS#1_4C
DQS1_4C
DQ15B
DQ15B
DQ15B
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DQ1_4C_5
DQ1_4C_4
DQ1_4C_3
DQ1_4C_5
DQ1_4C_4
DQ1_4C_3
DQ15B
DQ15B
DQ15B
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DQ1_4C_2
DQ1_4C_1
DQ1_4C_0
DQ1_4C_2
DQ1_4C_1
DQ1_4C_0
DQ16B
DQ16B
DQ16B
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DQ2_4C_8
DQ2_4C_7
DQ2_4C_6
DQ2_4C_8
DQ2_4C_7
DQ2_4C_6
DQ16B
DQSn16B/QK16B
DQS16B/CQ16B/CQn16B/QKn16B
DQ7B
DQSn7B/QK7B
DQS7B/CQ7B/CQn7B/QKn7B
DQ3B
DQ3B
DQ3B
DM2_4C
DQS#2_4C
DQS2_4C
DM2_4C
DQS#2_4C
DQS2_4C
DQ16B
DQ16B
DQ16B
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
DQ2_4C_5
DQ2_4C_4
DQ2_4C_3
DQ2_4C_5
DQ2_4C_4
DQ2_4C_3
Pin List HF40
A_4D_15
ODT_4D_1
ODT_4D_0
WE#_4D
CAS#_4D
RAS#_4D
BA_4D_2
BA_4D_1
BA_4D_0
ODT_4D_1
ODT_4D_0
CA_4D_9
CA_4D_8
CA_4D_7
CA_4D_6
CA_4D_5
CA_4D_4
CA_4D_3
CA_4D_2
CA_4D_1
CA_4D_0
CKE_4D_1
CKE_4D_0
CK#_4D
CK_4D
DQ1_4C_8
DQ1_4C_7
DQ1_4C_6
Page 13 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
4C
4C
4C
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
VREFB4CN0
VREFB4CN0
VREFB4CN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4BN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
RREF_BR
DNU
DNU
REFCLK0Rp
REFCLK0Rn
GXB_RX_R0n,GXB_REFCLK_R0n
GXB_RX_R0p,GXB_REFCLK_R0p
GXB_TX_R0p
GXB_TX_R0n
GXB_RX_R1n,GXB_REFCLK_R1n
GXB_RX_R1p,GXB_REFCLK_R1p
GXB_TX_R1p
GXB_TX_R1n
GXB_RX_R2n,GXB_REFCLK_R2n
GXB_RX_R2p,GXB_REFCLK_R2p
GXB_TX_R2p
GXB_TX_R2n
GXB_RX_R3n,GXB_REFCLK_R3n
GXB_RX_R3p,GXB_REFCLK_R3p
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
DIFFIO_TX_B121p
DIFFIO_RX_B122n
DIFFIO_RX_B122p
DIFFIO_TX_B123n
DIFFIO_TX_B123p
DIFFIO_RX_B124n
DIFFIO_RX_B124p
DIFFIO_TX_B125n
DIFFIO_TX_B125p
DIFFIO_RX_B126n
DIFFIO_RX_B126p
DIFFIO_TX_B127n
DIFFIO_TX_B127p
DIFFIO_RX_B128n
DIFFIO_RX_B128p
DIFFIO_TX_B129n
DIFFIO_TX_B129p
DIFFIO_RX_B130n
DIFFIO_RX_B130p
DIFFIO_TX_B131n
DIFFIO_TX_B131p
DIFFIO_RX_B132n
DIFFIO_RX_B132p
DIFFIO_TX_B133n
DIFFIO_TX_B133p
DIFFIO_RX_B134n
DIFFIO_RX_B134p
DIFFIO_TX_B135n
DIFFIO_TX_B135p
DIFFIO_RX_B136n
DIFFIO_RX_B136p
DIFFOUT_B121p
DIFFOUT_B122n
DIFFOUT_B122p
DIFFOUT_B123n
DIFFOUT_B123p
DIFFOUT_B124n
DIFFOUT_B124p
DIFFOUT_B125n
DIFFOUT_B125p
DIFFOUT_B126n
DIFFOUT_B126p
DIFFOUT_B127n
DIFFOUT_B127p
DIFFOUT_B128n
DIFFOUT_B128p
DIFFOUT_B129n
DIFFOUT_B129p
DIFFOUT_B130n
DIFFOUT_B130p
DIFFOUT_B131n
DIFFOUT_B131p
DIFFOUT_B132n
DIFFOUT_B132p
DIFFOUT_B133n
DIFFOUT_B133p
DIFFOUT_B134n
DIFFOUT_B134p
DIFFOUT_B135n
DIFFOUT_B135p
DIFFOUT_B136n
DIFFOUT_B136p
DQ16B
DQ16B
DQ16B
DQ7B
DQ7B
DQ7B
DQ3B
DQ3B
DQ3B
HMC pin
assignment for
DDR3 (5)
DQ2_4C_2
DQ2_4C_1
DQ2_4C_0
HMC pin
assignment for
LPDDR2
DQ2_4C_2
DQ2_4C_1
DQ2_4C_0
DQ17B
DQ17B
DQ17B
DQ8B
DQ8B
DQ8B
DQ3B
DQ3B
DQ3B
DQ3_4B_8
DQ3_4B_7
DQ3_4B_6
DQ3_4B_8
DQ3_4B_7
DQ3_4B_6
DQ17B
DQSn17B/QK17B
DQS17B/CQ17B/CQn17B/QKn17B
DQ8B
DQ8B
DQ8B
DQ3B
DQSn3B/QK3B
DQS3B/CQ3B/CQn3B/QKn3B
DM3_4B
DQS#3_4B
DQS3_4B
DM3_4B
DQS#3_4B
DQS3_4B
DQ17B
DQ17B
DQ17B
DQ8B
DQ8B
DQ8B
DQ3B
DQ3B
DQ3B
DQ3_4B_5
DQ3_4B_4
DQ3_4B_3
DQ3_4B_5
DQ3_4B_4
DQ3_4B_3
DQ17B
DQ17B
DQ17B
DQ8B
DQ8B
DQ8B
DQ3B
DQ3B
DQ3B
DQ3_4B_2
DQ3_4B_1
DQ3_4B_0
DQ3_4B_2
DQ3_4B_1
DQ3_4B_0
DQ18B
DQ18B
DQ18B
DQ8B
DQ8B
DQ8B
DQ3B
DQ3B
DQ3B
DQ4_4B_8
DQ4_4B_7
DQ4_4B_6
DQ4_4B_8
DQ4_4B_7
DQ4_4B_6
DQ18B
DQSn18B/QK18B
DQS18B/CQ18B/CQn18B/QKn18B
DQ8B
DQSn8B/QK8B
DQS8B/CQ8B/CQn8B/QKn8B
DQ3B
DQ3B
DQ3B
DM4_4B
DQS#4_4B
DQS4_4B
DM4_4B
DQS#4_4B
DQS4_4B
DQ18B
DQ18B
DQ18B
DQ8B
DQ8B
DQ8B
DQ3B
DQ3B
DQ3B
DQ4_4B_5
DQ4_4B_4
DQ4_4B_3
DQ4_4B_5
DQ4_4B_4
DQ4_4B_3
DIFFIO_RX_B137n
DIFFIO_RX_B137p
DIFFIO_TX_B138n
DIFFIO_TX_B138p
DIFFIO_RX_B139n
DIFFIO_RX_B139p
DIFFIO_TX_B140n
DIFFIO_TX_B140p
DIFFIO_RX_B141n
DIFFIO_RX_B141p
DIFFIO_TX_B142n
DIFFIO_TX_B142p
DIFFIO_RX_B143n
DIFFIO_RX_B143p
DIFFIO_TX_B144n
DIFFIO_TX_B144p
DIFFIO_RX_B145n
DIFFIO_RX_B145p
DIFFIO_TX_B146n
DIFFIO_TX_B146p
DIFFIO_RX_B147n
DIFFIO_RX_B147p
DIFFIO_TX_B148n
DIFFIO_TX_B148p
DIFFIO_RX_B149n
DIFFIO_RX_B149p
DIFFIO_TX_B150n
DIFFIO_TX_B150p
DIFFIO_RX_B151n
DIFFIO_RX_B151p
DIFFIO_TX_B152n
DIFFIO_TX_B152p
DIFFIO_RX_B153n
DIFFIO_RX_B153p
DIFFIO_TX_B154n
DIFFIO_TX_B154p
DIFFIO_RX_B155n
DIFFIO_RX_B155p
DIFFIO_TX_B156n
DIFFIO_TX_B156p
DIFFIO_RX_B157n
DIFFIO_RX_B157p
DIFFIO_TX_B158n
DIFFIO_TX_B158p
DIFFIO_RX_B159n
DIFFIO_RX_B159p
DIFFOUT_B137n
DIFFOUT_B137p
DIFFOUT_B138n
DIFFOUT_B138p
DIFFOUT_B139n
DIFFOUT_B139p
DIFFOUT_B140n
DIFFOUT_B140p
DIFFOUT_B141n
DIFFOUT_B141p
DIFFOUT_B142n
DIFFOUT_B142p
DIFFOUT_B143n
DIFFOUT_B143p
DIFFOUT_B144n
DIFFOUT_B144p
DIFFOUT_B145n
DIFFOUT_B145p
DIFFOUT_B146n
DIFFOUT_B146p
DIFFOUT_B147n
DIFFOUT_B147p
DIFFOUT_B148n
DIFFOUT_B148p
DIFFOUT_B149n
DIFFOUT_B149p
DIFFOUT_B150n
DIFFOUT_B150p
DIFFOUT_B151n
DIFFOUT_B151p
DIFFOUT_B152n
DIFFOUT_B152p
DIFFOUT_B153n
DIFFOUT_B153p
DIFFOUT_B154n
DIFFOUT_B154p
DIFFOUT_B155n
DIFFOUT_B155p
DIFFOUT_B156n
DIFFOUT_B156p
DIFFOUT_B157n
DIFFOUT_B157p
DIFFOUT_B158n
DIFFOUT_B158p
DIFFOUT_B159n
DIFFOUT_B159p
DQ18B
DQ18B
DQ18B
DQ8B
DQ8B
DQ8B
DQ3B
DQ3B
DQ3B
DQ4_4B_2
DQ4_4B_1
DQ4_4B_0
DQ4_4B_2
DQ4_4B_1
DQ4_4B_0
DQ19B
DQ19B
DQ19B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ5_4B_8
DQ5_4B_7
DQ5_4B_6
DQ5_4B_8
DQ5_4B_7
DQ5_4B_6
DQ19B
DQSn19B/QK19B
DQS19B/CQ19B/CQn19B/QKn19B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DM5_4B
DQS#5_4B
DQS5_4B
DM5_4B
DQS#5_4B
DQS5_4B
DQ19B
DQ19B
DQ19B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ5_4B_5
DQ5_4B_4
DQ5_4B_3
DQ5_4B_5
DQ5_4B_4
DQ5_4B_3
DQ19B
DQ19B
DQ19B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ5_4B_2
DQ5_4B_1
DQ5_4B_0
DQ5_4B_2
DQ5_4B_1
DQ5_4B_0
DQ20B
DQ20B
DQ20B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ20B
DQSn20B/QK20B
DQS20B/CQ20B/CQn20B/QKn20B
DQ9B
DQSn9B/QK9B
DQS9B/CQ9B/CQn9B/QKn9B
DQ4B
DQ4B
DQ4B
DQ20B
DQ20B
DQ20B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ20B
DQ20B
DQ20B
DQ9B
DQ9B
DQ9B
DQ4B
DQ4B
DQ4B
DQ21B
DQ21B
DQ21B
DQ10B
DQ10B
DQ10B
DQ4B
DQ4B
DQ4B
DQ21B
DQSn21B/QK21B
DQS21B/CQ21B/CQn21B/QKn21B
DQ10B
DQ10B
DQ10B
DQ4B
DQSn4B/QK4B
DQS4B/CQ4B/CQn4B/QKn4B
DQ21B
DQ21B
DQ21B
DQ10B
DQ10B
DQ10B
DQ4B
DQ4B
DQ4B
DIFFIO_RX_B160n
DIFFIO_RX_B160p
DIFFIO_TX_B161n
DIFFIO_TX_B161p
DIFFIO_RX_B162n
DIFFIO_RX_B162p
DIFFIO_TX_B163n
DIFFIO_TX_B163p
DIFFIO_RX_B164n
DIFFIO_RX_B164p
DIFFIO_TX_B165n
DIFFIO_TX_B165p
DIFFIO_RX_B166n
DIFFIO_RX_B166p
DIFFIO_TX_B167n
DIFFIO_TX_B167p
DIFFIO_RX_B168n
DIFFIO_RX_B168p
DIFFOUT_B160n
DIFFOUT_B160p
DIFFOUT_B161n
DIFFOUT_B161p
DIFFOUT_B162n
DIFFOUT_B162p
DIFFOUT_B163n
DIFFOUT_B163p
DIFFOUT_B164n
DIFFOUT_B164p
DIFFOUT_B165n
DIFFOUT_B165p
DIFFOUT_B166n
DIFFOUT_B166p
DIFFOUT_B167n
DIFFOUT_B167p
DIFFOUT_B168n
DIFFOUT_B168p
AH14
AD15
AE15
AP13
AR13
AE14
AE13
AT12
AU12
AV12
AW12
AL13
AM13
AW10
AW11
AN12
AP12
AH13
AJ13
AH12
AJ12
AF13
AG13
AU10
AV10
AT11
AU11
AK12
AL12
AC13
AD13
AN11
AP11
AV9
AW9
AC12
AD11
AF12
AG12
AT9
AU9
AG11
AH11
AD12
AE12
AP10
AR10
AK11
AL11
AL10
AM10
AL9
AM9
AW7
AW8
AV7
AV6
AW6
AW5
AK9
AK10
AU7
AU8
AN9
AP9
AT8
AR9
AH10
AJ10
AF10
AE11
AK6
AL6
AH6
AJ6
AH9
AJ9
AM6
AN6
AH7
AH8
AJ7
AK7
AL7
AM7
AN8
AP8
AT6
AU6
AR7
AT7
AK8
AL8
AV4
AW4
AN7
AP7
AP6
AR6
AW2
AV3
AW3
AF8
AF7
AU2
AU1
AT3
AT4
AR2
AR1
AP3
AP4
AN2
AN1
AM3
AM4
AL2
AL1
DQ21B
DQ21B
DQ21B
DQ10B
DQ10B
DQ10B
DQ4B
DQ4B
DQ4B
DQ22B
DQ22B
DQ22B
DQ10B
DQ10B
DQ10B
DQ4B
DQ4B
DQ4B
DQ22B
DQSn22B/QK22B
DQS22B/CQ22B/CQn22B/QKn22B
DQ10B
DQSn10B/QK10B
DQS10B/CQ10B/CQn10B/QKn10B
DQ4B
DQ4B
DQ4B
DQ22B
DQ22B
DQ22B
DQ10B
DQ10B
DQ10B
DQ4B
DQ4B
DQ4B
DQ22B
DQ22B
DQ22B
DQ10B
DQ10B
DQ10B
DQ4B
DQ4B
DQ4B
VREFB4BN0
DATA10
DATA11
DATA5
DATA6
DATA12
DATA13
DATA7
DATA8
DATA14
DATA15
DATA9
CLKUSR
PR_ERROR
PR_READY
PR_DONE
PR_REQUEST
nPERSTR0
nPERSTL0
CvP_CONFDONE
CRC_ERROR
DEV_OE
DEV_CLRn
INIT_DONE
nCEO
VREFB4AN0
CLK11n
CLK11p
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn
FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB0
FPLL_BR_CLKOUT3,FPLL_BR_FBn
FPLL_BR_CLKOUT2,FPLL_BR_FBp,FPLL_BR_FB1
CLK10n
CLK10p
CLK9n
CLK9p
RZQ_1
CLK8n
CLK8p
Pin List HF40
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
Page 14 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R0
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
GXB_R1
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
VREF
PinName/Function (2), (3)
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
GXB_TX_R3p
GXB_TX_R3n
GXB_RX_R4n,GXB_REFCLK_R4n
GXB_RX_R4p,GXB_REFCLK_R4p
GXB_TX_R4p
GXB_TX_R4n
GXB_RX_R5n,GXB_REFCLK_R5n
GXB_RX_R5p,GXB_REFCLK_R5p
GXB_TX_R5p
GXB_TX_R5n
REFCLK1Rp
REFCLK1Rn
REFCLK2Rp
REFCLK2Rn
GXB_RX_R6n,GXB_REFCLK_R6n
GXB_RX_R6p,GXB_REFCLK_R6p
GXB_TX_R6p
GXB_TX_R6n
GXB_RX_R7n,GXB_REFCLK_R7n
GXB_RX_R7p,GXB_REFCLK_R7p
GXB_TX_R7p
GXB_TX_R7n
GXB_RX_R8n,GXB_REFCLK_R8n
GXB_RX_R8p,GXB_REFCLK_R8p
GXB_TX_R8p
GXB_TX_R8n
GXB_RX_R9n,GXB_REFCLK_R9n
GXB_RX_R9p,GXB_REFCLK_R9p
GXB_TX_R9p
GXB_TX_R9n
GXB_RX_R10n,GXB_REFCLK_R10n
GXB_RX_R10p,GXB_REFCLK_R10p
GXB_TX_R10p
GXB_TX_R10n
GXB_RX_R11n,GXB_REFCLK_R11n
GXB_RX_R11p,GXB_REFCLK_R11p
GXB_TX_R11p
GXB_TX_R11n
REFCLK3Rp
REFCLK3Rn
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI13
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI12
HPS_GPI11
HPS_DDR
HPS_GPI10
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6BN0_HPS
HPS_DDR
HPS_GPI9
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI8
HPS_GPI7
HPS_DDR
HPS_GPI6
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI5
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI4
HPS_GPI3
HPS_DDR
HPS_GPI2
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI1
HPS_GPI0
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
AK3
AK4
AJ2
AJ1
AH3
AH4
AG2
AG1
AF3
AF4
AD9
AD8
AB9
AB8
AE2
AE1
AD3
AD4
AC2
AC1
AB3
AB4
AA2
AA1
Y3
Y4
W2
W1
V3
V4
U2
U1
T3
T4
R2
R1
P3
P4
Y9
Y8
T7
R6
M1
N1
M2
J1
K1
H1
L1
F1
P6
G1
R7
J2
D1
K2
E1
F2
M3
G2
M4
C2
B1
D2
C1
A3
P7
A2
N6
K3
D3
K4
C3
J4
M5
H3
L4
G4
E3
H4
F3
K5
N7
J5
M6
C4
E4
B4
F4
A5
R9
A4
R8
D5
F5
E6
G5
G6
N8
H6
M7
B6
C6
D6
A7
L6
A6
K6
F7
H7
E7
G7
C7
R10
D7
P10
N9
M9
Pin List HF40
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DM_3
HPS_DM_3
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQS_3
HPS_DQS_3
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DM_2
HPS_DM_2
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DM_1
HPS_DM_1
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_A_0
HPS_A_1
HPS_CA_0
HPS_CA_1
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
Page 15 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_RZQ_0
DNU
GND
GND
HPS_nRST
HPS_nPOR
HPS_TDO
VCCRSTCLK_HPS
HPS_TMS
HPS_TCK
HPS_TRST
HPS_TDI
GND
HPS_PORSEL
HPS_CLK1
HPS_CLK2
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0,BOOTSEL0
UART0_RX
UART0_TX,CLKSEL1
I2C0_SDA
I2C0_SCL
UART0_RX*
UART0_TX*,CLKSEL0
SPIS1_CLK
SPIS1_MOSI
SPIS1_MISO
SPIS1_SS0
UART1_RX
UART1_TX
I2C1_SDA
I2C1_SCL
SPIM0_SS0
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE,BOOTSEL2
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0,BOOTSEL1
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
A8
N10
B7
M10
A11
B9
B10
A9
C9
L7
D8
G9
G8
D9
K7
C10
J7
H9
F9
J9
E9
D11
J8
D10
K9
B12
C11
A12
R11
K10
T11
J10
F10
G10
F11
H10
M11
C12
N11
D12
J11
K12
K11
J12
H12
E12
G11
F12
A13
P12
A14
N12
B15
B14
A15
C13
L13
M12
M13
L12
E13
F13
D13
G13
N13
R13
M14
P13
H13
C14
J13
D14
A16
P15
A17
R15
C16
G14
B17
H14
L15
P14
K15
R14
K14
C15
L14
D15
G15
M15
H15
N15
F15
E15
D16
P16
C17
N16
F16
G16
E16
H16
K16
L16
J16
M16
R17
F17
P17
F18
E18
J17
D18
K17
B19
A18
C18
A19
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HPS_A_4
HPS_A_2
HPS_A_5
HPS_A_3
HPS_CK
HPS_A_6
HPS_CK#
HPS_A_7
HPS_BA_1
HPS_BA_0
HPS_BA_2
HPS_CAS#
HPS_RAS#
HPS_A_8
HPS_A_10
HPS_A_9
HPS_A_11
HPS_CS#_0
HPS_A_12
HPS_CS#_1
HPS_A_13
HPS_A_14
HPS_WE#
HPS_A_15
HMC pin
assignment for
LPDDR2
HPS_CA_4
HPS_CA_2
HPS_CA_5
HPS_CA_3
HPS_CK
HPS_CA_6
HPS_CK#
HPS_CA_7
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 0
HPS_CA_8
HPS_CA_9
HPS_CS#_0
HPS_CS#_1
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
UART0_RX
UART0_TX
I2C0_SDA
I2C0_SCL
SPIS1_CLK
SPIS1_MOSI
SPIS1_MISO
SPIS1_SS0
UART1_RX
UART1_TX
I2C1_SDA
I2C1_SCL
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
Pin List HF40
HPS Pin Mux
Select 1
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
SPIS1_CLK
SPIS1_MOSI
SPIS1_SS0
SPIS1_MISO
I2C1_SDA
I2C1_SCL
UART1_RX
UART1_TX
UART0_RX
UART0_TX
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
SPIM1_SS1
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
SPIM0_SS1
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RXD0
RGMII1_MDIO
RGMII1_MDC
RGMII1_RX_CTL
RGMII1_TX_CTL
RGMII1_RX_CLK
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
QSPI_SS1
UART0_RX
UART0_TX
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
UART0_CTS
UART0_RTS
UART1_CTS
UART1_RTS
SPIM0_SS1
SPIM1_SS1
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
QSPI_SS3
USB1_D0
USB1_D1
USB1_D2
USB1_D3
I2C3_SDA
I2C3_SCL
USB1_D4
USB1_D5
USB1_D6
USB1_D7
QSPI_SS2
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
USB0_D0
USB0_D1
USB0_D2
USB0_D3
USB0_D4
USB0_D5
USB0_D6
USB0_D7
USB0_CLK
USB0_STP
USB0_DIR
USB0_NXT
USB1_D0
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
USB1_CLK
USB1_STP
I2C2_SDA
I2C2_SCL
HPS_GPIO48
HPS_GPIO49
HPS_GPIO50
HPS_GPIO51
HPS_GPIO52
HPS_GPIO53
HPS_GPIO54
HPS_GPIO55
HPS_GPIO56
HPS_GPIO57
HPS_GPIO58
HPS_GPIO59
HPS_GPIO60
HPS_GPIO61
HPS_GPIO62
HPS_GPIO63
HPS_GPIO64
HPS_GPIO65
HPS_GPIO66
HPS_GPIO67
HPS_GPIO68
HPS_GPIO69
HPS_GPIO70
HPS_GPIO62
HPS_GPIO63
HPS_GPIO64
HPS_GPIO65
HPS_GPIO66
HPS_GPIO67
HPS_GPIO68
HPS_GPIO69
HPS_GPIO70
HPS_GPIO14
HPS_GPIO15
HPS_GPIO16
HPS_GPIO17
HPS_GPIO18
HPS_GPIO19
HPS_GPIO20
HPS_GPIO21
HPS_GPIO22
HPS_GPIO23
HPS_GPIO24
HPS_GPIO25
HPS_GPIO26
HPS_GPIO27
HPS_GPIO28
HPS_GPIO29
HPS_GPIO30
HPS_GPIO31
HPS_GPIO32
HPS_GPIO33
HPS_GPIO34
HPS_GPIO35
HPS_GPIO36
HPS_GPIO37
HPS_GPIO38
HPS_GPIO39
HPS_GPIO40
HPS_GPIO41
HPS_GPIO42
HPS_GPIO43
HPS_GPIO44
HPS_GPIO45
HPS_GPIO46
HPS_GPIO47
HPS_GPIO0
HPS_GPIO1
HPS_GPIO2
HPS_GPIO3
HPS_GPIO4
HPS_GPIO5
HPS_GPIO6
HPS_GPIO7
HPS_GPIO8
HPS_GPIO9
HPS_GPIO10
HPS_GPIO11
Page 16 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
7D
7D
7D
7D
7D
7D
7D
7D
7E
7E
7E
7E
7E
7E
7E
7E
7G
7G
7G
7G
7G
7G
7G
7G
7G
7G
7G
7G
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7A7B7C7D7EN0_HPS
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
VREFB7GN0
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8D
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
8C
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8DN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
RGMII0_RXD2
RGMII0_RXD3
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TX_CTL
RGMII1_RXD0
RGMII1_RXD1
RGMII1_MDIO
RGMII1_MDC
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RX_CLK
RGMII1_RX_CTL
RGMII1_RXD2
RGMII1_RXD3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VCCA_FPLL
VCCD_FPLL
DNU
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
DIFFIO_RX_T16p
DIFFIO_RX_T16n
DIFFOUT_T16p
DIFFOUT_T16n
DIFFIO_RX_T17p
DIFFIO_RX_T17n
DIFFIO_TX_T18p
DIFFIO_RX_T19p
DIFFIO_RX_T19n
DIFFIO_TX_T20p
DIFFIO_RX_T21p
DIFFIO_RX_T21n
DIFFOUT_T17p
DIFFOUT_T17n
DIFFOUT_T18p
DIFFOUT_T19p
DIFFOUT_T19n
DIFFOUT_T20p
DIFFOUT_T21p
DIFFOUT_T21n
DIFFIO_RX_T31p
DIFFIO_RX_T31n
DIFFIO_TX_T32p
DIFFIO_TX_T32n
DIFFIO_RX_T33p
DIFFIO_RX_T33n
DIFFIO_TX_T34p
DIFFIO_TX_T34n
DIFFIO_RX_T35p
DIFFIO_RX_T35n
DIFFIO_TX_T36p
DIFFIO_TX_T36n
DIFFIO_RX_T37p
DIFFIO_RX_T37n
DIFFIO_TX_T38p
DIFFIO_TX_T38n
DIFFIO_RX_T39p
DIFFIO_RX_T39n
DIFFOUT_T31p
DIFFOUT_T31n
DIFFOUT_T32p
DIFFOUT_T32n
DIFFOUT_T33p
DIFFOUT_T33n
DIFFOUT_T34p
DIFFOUT_T34n
DIFFOUT_T35p
DIFFOUT_T35n
DIFFOUT_T36p
DIFFOUT_T36n
DIFFOUT_T37p
DIFFOUT_T37n
DIFFOUT_T38p
DIFFOUT_T38n
DIFFOUT_T39p
DIFFOUT_T39n
DIFFIO_RX_T40p
DIFFIO_RX_T40n
DIFFIO_TX_T41p
DIFFIO_TX_T41n
DIFFIO_RX_T42p
DIFFIO_RX_T42n
DIFFIO_TX_T43p
DIFFIO_TX_T43n
DIFFIO_RX_T44p
DIFFIO_RX_T44n
DIFFIO_TX_T45p
DIFFIO_TX_T45n
DIFFIO_RX_T46p
DIFFIO_RX_T46n
DIFFIO_TX_T47p
DIFFIO_TX_T47n
DIFFIO_RX_T48p
DIFFIO_RX_T48n
DIFFIO_TX_T49p
DIFFIO_TX_T49n
DIFFIO_RX_T50p
DIFFIO_RX_T50n
DIFFIO_TX_T51p
DIFFIO_TX_T51n
DIFFIO_RX_T52p
DIFFIO_RX_T52n
DIFFIO_TX_T53p
DIFFIO_TX_T53n
DIFFIO_RX_T54p
DIFFIO_RX_T54n
DIFFIO_TX_T55p
DIFFIO_TX_T55n
DIFFIO_RX_T56p
DIFFIO_RX_T56n
DIFFIO_TX_T57p
DIFFIO_TX_T57n
DIFFIO_RX_T58p
DIFFIO_RX_T58n
DIFFIO_TX_T59p
DIFFIO_TX_T59n
DIFFIO_RX_T60p
DIFFIO_RX_T60n
DIFFIO_TX_T61p
DIFFIO_TX_T61n
DIFFIO_RX_T62p
DIFFIO_RX_T62n
DIFFOUT_T40p
DIFFOUT_T40n
DIFFOUT_T41p
DIFFOUT_T41n
DIFFOUT_T42p
DIFFOUT_T42n
DIFFOUT_T43p
DIFFOUT_T43n
DIFFOUT_T44p
DIFFOUT_T44n
DIFFOUT_T45p
DIFFOUT_T45n
DIFFOUT_T46p
DIFFOUT_T46n
DIFFOUT_T47p
DIFFOUT_T47n
DIFFOUT_T48p
DIFFOUT_T48n
DIFFOUT_T49p
DIFFOUT_T49n
DIFFOUT_T50p
DIFFOUT_T50n
DIFFOUT_T51p
DIFFOUT_T51n
DIFFOUT_T52p
DIFFOUT_T52n
DIFFOUT_T53p
DIFFOUT_T53n
DIFFOUT_T54p
DIFFOUT_T54n
DIFFOUT_T55p
DIFFOUT_T55n
DIFFOUT_T56p
DIFFOUT_T56n
DIFFOUT_T57p
DIFFOUT_T57n
DIFFOUT_T58p
DIFFOUT_T58n
DIFFOUT_T59p
DIFFOUT_T59n
DIFFOUT_T60p
DIFFOUT_T60n
DIFFOUT_T61p
DIFFOUT_T61n
DIFFOUT_T62p
DIFFOUT_T62n
DIFFIO_RX_T63p
DIFFIO_RX_T63n
DIFFIO_TX_T64p
DIFFIO_TX_T64n
DIFFIO_RX_T65p
DIFFIO_RX_T65n
DIFFIO_TX_T66p
DIFFIO_TX_T66n
DIFFIO_RX_T67p
DIFFIO_RX_T67n
DIFFIO_TX_T68p
DIFFIO_TX_T68n
DIFFIO_RX_T69p
DIFFIO_RX_T69n
DIFFIO_TX_T70p
DIFFIO_TX_T70n
DIFFIO_RX_T71p
DIFFIO_RX_T71n
DIFFIO_TX_T72p
DIFFOUT_T63p
DIFFOUT_T63n
DIFFOUT_T64p
DIFFOUT_T64n
DIFFOUT_T65p
DIFFOUT_T65n
DIFFOUT_T66p
DIFFOUT_T66n
DIFFOUT_T67p
DIFFOUT_T67n
DIFFOUT_T68p
DIFFOUT_T68n
DIFFOUT_T69p
DIFFOUT_T69n
DIFFOUT_T70p
DIFFOUT_T70n
DIFFOUT_T71p
DIFFOUT_T71n
DIFFOUT_T72p
VREFB7GN0
CLK19p
CLK19n
CLK18p
CLK18n
FPLL_TC_CLKOUT2,FPLL_TC_FBp,FPLL_TC_FB1
FPLL_TC_CLKOUT3,FPLL_TC_FBn
FPLL_TC_CLKOUT0,FPLL_TC_CLKOUTp,FPLL_TC_FB0
FPLL_TC_CLKOUT1,FPLL_TC_CLKOUTn
CLK17p
CLK17n
CLK16p
CLK16n
VREFB8DN0
VREFB8CN0
F1517 (4) DQS for X8/X9
C19
G18
D19
H18
F19
N18
E19
M17
J18
L18
K18
M18
G21
H19
G20
G19
R19
T19
N19
P19
U19
U20
L19
P20
R20
M19
L20
M20
V20
V19
F20
C20
D20
N21
P21
H21
J21
D21
E21
A20
B21
K21
L21
A22
A21
R21
T21
B22
C22
J22
H22
E22
F22
A23
A24
C23
D23
L22
M22
N22
P22
R22
T22
F23
G23
R23
T23
B24
C24
M23
N23
D24
E24
J23
K23
F24
G24
H24
J24
T26
T25
G25
H25
N24
P24
R24
T24
A25
B25
K24
L24
D25
E25
P25
R25
C26
D26
K25
L25
R26
T27
A26
A27
M26
N26
J26
K26
F26
G26
M25
N25
P27
R27
H27
J27
B27
C27
E27
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
RGMII0_RXD2
RGMII0_RXD3
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TX_CTL
RGMII1_RXD0
RGMII1_RXD1
RGMII1_MDIO
RGMII1_MDC
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RX_CLK
RGMII1_RX_CTL
RGMII1_RXD2
RGMII1_RXD3
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQS1T/CQ1T/CQn1T/QKn1T
DQSn1T/QK1T
DQ1T
DQS1T/CQ1T/CQn1T/QKn1T
DQSn1T/QK1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQS2T/CQ2T/CQn2T/QKn2T
DQSn2T/QK2T
DQ2T
DQ1T
DQ1T
DQ1T
DQS1T/CQ1T/CQn1T/QKn1T
DQSn1T/QK1T
DQ1T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQS3T/CQ3T/CQn3T/QKn3T
DQSn3T/QK3T
DQ3T
DQS2T/CQ2T/CQn2T/QKn2T
DQSn2T/QK2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ5_8C_0
DQ5_8C_1
DQ5_8C_2
DQ5_8C_0
DQ5_8C_1
DQ5_8C_2
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ5_8C_3
DQ5_8C_4
DQ5_8C_5
DQ5_8C_3
DQ5_8C_4
DQ5_8C_5
DQS4T/CQ4T/CQn4T/QKn4T
DQSn4T/QK4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQS5_8C
DQS#5_8C
DM5_8C
DQS5_8C
DQS#5_8C
DM5_8C
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ1T
DQ1T
DQ1T
DQ5_8C_6
DQ5_8C_7
DQ5_8C_8
DQ5_8C_6
DQ5_8C_7
DQ5_8C_8
DQ5T
DQ5T
DQ5T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ4_8C_0
DQ4_8C_1
DQ4_8C_2
DQ4_8C_0
DQ4_8C_1
DQ4_8C_2
DQ5T
DQ5T
DQ5T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ4_8C_3
DQ4_8C_4
DQ4_8C_5
DQ4_8C_3
DQ4_8C_4
DQ4_8C_5
DQS5T/CQ5T/CQn5T/QKn5T
DQSn5T/QK5T
DQ5T
DQS3T/CQ3T/CQn3T/QKn3T
DQSn3T/QK3T
DQ3T
DQ2T
DQ2T
DQ2T
DQS4_8C
DQS#4_8C
DM4_8C
DQS4_8C
DQS#4_8C
DM4_8C
DQ5T
DQ5T
DQ5T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ4_8C_6
DQ4_8C_7
DQ4_8C_8
DQ4_8C_6
DQ4_8C_7
DQ4_8C_8
DQ6T
DQ6T
DQ6T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ3_8C_0
DQ3_8C_1
DQ3_8C_2
DQ3_8C_0
DQ3_8C_1
DQ3_8C_2
DQ6T
DQ6T
DQ6T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ3_8C_3
DQ3_8C_4
DQ3_8C_5
DQ3_8C_3
DQ3_8C_4
DQ3_8C_5
Pin List HF40
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
HPS_GPIO12
HPS_GPIO13
HPS_GPIO48
HPS_GPIO49
HPS_GPIO50
HPS_GPIO51
HPS_GPIO52
HPS_GPIO53
HPS_GPIO54
HPS_GPIO55
HPS_GPIO56
HPS_GPIO57
HPS_GPIO58
HPS_GPIO59
HPS_GPIO60
HPS_GPIO61
USB1_DIR
USB1_NXT
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
SPIS1_CLK
SPIS1_MOSI
SPIS1_MISO
SPIS1_SS0
Page 17 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
8C
8C
8C
8C
8C
8C
8C
8C
8C
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8B
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8CN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8BN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
CONF_DONE
nSTATUS
nCE
nCONFIG
GND
VCC_HPS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DIFFIO_TX_T72n
DIFFIO_RX_T73p
DIFFIO_RX_T73n
DIFFIO_TX_T74p
DIFFIO_TX_T74n
DIFFIO_RX_T75p
DIFFIO_RX_T75n
DIFFIO_TX_T76p
DIFFIO_TX_T76n
DIFFIO_RX_T77p
DIFFIO_RX_T77n
DIFFIO_TX_T78p
DIFFIO_TX_T78n
DIFFIO_RX_T79p
DIFFIO_RX_T79n
DIFFIO_TX_T80p
DIFFIO_TX_T80n
DIFFIO_RX_T81p
DIFFIO_RX_T81n
DIFFIO_TX_T82p
DIFFIO_TX_T82n
DIFFIO_RX_T83p
DIFFIO_RX_T83n
DIFFIO_TX_T84p
DIFFIO_TX_T84n
DIFFIO_RX_T85p
DIFFIO_RX_T85n
DIFFOUT_T72n
DIFFOUT_T73p
DIFFOUT_T73n
DIFFOUT_T74p
DIFFOUT_T74n
DIFFOUT_T75p
DIFFOUT_T75n
DIFFOUT_T76p
DIFFOUT_T76n
DIFFOUT_T77p
DIFFOUT_T77n
DIFFOUT_T78p
DIFFOUT_T78n
DIFFOUT_T79p
DIFFOUT_T79n
DIFFOUT_T80p
DIFFOUT_T80n
DIFFOUT_T81p
DIFFOUT_T81n
DIFFOUT_T82p
DIFFOUT_T82n
DIFFOUT_T83p
DIFFOUT_T83n
DIFFOUT_T84p
DIFFOUT_T84n
DIFFOUT_T85p
DIFFOUT_T85n
DIFFIO_RX_T86p
DIFFIO_RX_T86n
DIFFIO_TX_T87p
DIFFIO_TX_T87n
DIFFIO_RX_T88p
DIFFIO_RX_T88n
DIFFIO_TX_T89p
DIFFIO_TX_T89n
DIFFIO_RX_T90p
DIFFIO_RX_T90n
DIFFIO_TX_T91p
DIFFIO_TX_T91n
DIFFIO_RX_T92p
DIFFIO_RX_T92n
DIFFIO_TX_T93p
DIFFIO_TX_T93n
DIFFIO_RX_T94p
DIFFIO_RX_T94n
DIFFIO_TX_T95p
DIFFIO_TX_T95n
DIFFIO_RX_T96p
DIFFIO_RX_T96n
DIFFIO_TX_T97p
DIFFIO_TX_T97n
DIFFIO_RX_T98p
DIFFIO_RX_T98n
DIFFIO_TX_T99p
DIFFIO_TX_T99n
DIFFIO_RX_T100p
DIFFIO_RX_T100n
DIFFIO_TX_T101p
DIFFIO_TX_T101n
DIFFIO_RX_T102p
DIFFIO_RX_T102n
DIFFIO_TX_T103p
DIFFIO_TX_T103n
DIFFIO_RX_T104p
DIFFIO_RX_T104n
DIFFIO_TX_T105p
DIFFIO_TX_T105n
DIFFIO_RX_T106p
DIFFIO_RX_T106n
DIFFIO_TX_T107p
DIFFIO_TX_T107n
DIFFIO_RX_T108p
DIFFIO_RX_T108n
DIFFOUT_T86p
DIFFOUT_T86n
DIFFOUT_T87p
DIFFOUT_T87n
DIFFOUT_T88p
DIFFOUT_T88n
DIFFOUT_T89p
DIFFOUT_T89n
DIFFOUT_T90p
DIFFOUT_T90n
DIFFOUT_T91p
DIFFOUT_T91n
DIFFOUT_T92p
DIFFOUT_T92n
DIFFOUT_T93p
DIFFOUT_T93n
DIFFOUT_T94p
DIFFOUT_T94n
DIFFOUT_T95p
DIFFOUT_T95n
DIFFOUT_T96p
DIFFOUT_T96n
DIFFOUT_T97p
DIFFOUT_T97n
DIFFOUT_T98p
DIFFOUT_T98n
DIFFOUT_T99p
DIFFOUT_T99n
DIFFOUT_T100p
DIFFOUT_T100n
DIFFOUT_T101p
DIFFOUT_T101n
DIFFOUT_T102p
DIFFOUT_T102n
DIFFOUT_T103p
DIFFOUT_T103n
DIFFOUT_T104p
DIFFOUT_T104n
DIFFOUT_T105p
DIFFOUT_T105n
DIFFOUT_T106p
DIFFOUT_T106n
DIFFOUT_T107p
DIFFOUT_T107n
DIFFOUT_T108p
DIFFOUT_T108n
DIFFIO_RX_T109p
DIFFIO_RX_T109n
DIFFIO_TX_T110p
DIFFIO_TX_T110n
DIFFIO_RX_T111p
DIFFIO_RX_T111n
DIFFIO_TX_T112p
DIFFIO_TX_T112n
DIFFIO_RX_T113p
DIFFIO_RX_T113n
DIFFIO_TX_T114p
DIFFIO_TX_T114n
DIFFOUT_T109p
DIFFOUT_T109n
DIFFOUT_T110p
DIFFOUT_T110n
DIFFOUT_T111p
DIFFOUT_T111n
DIFFOUT_T112p
DIFFOUT_T112n
DIFFOUT_T113p
DIFFOUT_T113n
DIFFOUT_T114p
DIFFOUT_T114n
F27
R28
T28
K27
L27
M27
N27
N28
P28
L28
M28
H28
J28
C28
D28
F28
G28
R29
T29
J29
K29
M29
N29
F29
G29
B28
C29
R30
R31
A29
A28
L30
M30
N30
P30
J30
K30
D30
D29
F30
G30
B30
C30
E31
F31
B31
A30
A31
A32
A33
B33
H31
J31
C31
D31
C32
D32
N31
P31
J32
K32
M32
N32
J34
K34
L33
M33
L31
M31
N34
N33
L34
M34
E34
F34
J33
H33
B34
A35
C33
D33
G34
H34
F32
G32
C34
D34
E33
F33
H35
A34
D35
A37
P34
K35
F35
M35
A36
P35
V16
W16
AA33
AA35
AA38
AA39
AB31
AB32
AB34
AB36
AB37
AC33
AC38
AC39
AD32
AD36
AD37
AE33
AE35
VREFB8BN0
CLK23p
CLK23n
CLK22p
CLK22n
VREFB8AN0
FPLL_TL_CLKOUT2,FPLL_TL_FBp,FPLL_TL_FB1
FPLL_TL_CLKOUT3,FPLL_TL_FBn
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB0
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn
CLK21p
CLK21n
CLK20p
CLK20n
RZQ_6
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
CONF_DONE
nSTATUS
nCE
nCONFIG
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
DQS6T/CQ6T/CQn6T/QKn6T
DQSn6T/QK6T
DQ6T
DQ3T
DQ3T
DQ3T
DQS2T/CQ2T/CQn2T/QKn2T
DQSn2T/QK2T
DQ2T
DQS3_8C
DQS#3_8C
DM3_8C
DQS3_8C
DQS#3_8C
DM3_8C
DQ6T
DQ6T
DQ6T
DQ3T
DQ3T
DQ3T
DQ2T
DQ2T
DQ2T
DQ3_8C_6
DQ3_8C_7
DQ3_8C_8
DQ3_8C_6
DQ3_8C_7
DQ3_8C_8
DQ7T
DQ7T
DQ7T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ2_8B_0
DQ2_8B_1
DQ2_8B_2
DQ2_8B_0
DQ2_8B_1
DQ2_8B_2
DQ7T
DQ7T
DQ7T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ2_8B_3
DQ2_8B_4
DQ2_8B_5
DQ2_8B_3
DQ2_8B_4
DQ2_8B_5
DQS7T/CQ7T/CQn7T/QKn7T
DQSn7T/QK7T
DQ7T
DQS4T/CQ4T/CQn4T/QKn4T
DQSn4T/QK4T
DQ4T
DQ2T
DQ2T
DQ2T
DQS2_8B
DQS#2_8B
DM2_8B
DQS2_8B
DQS#2_8B
DM2_8B
DQ7T
DQ7T
DQ7T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ2_8B_6
DQ2_8B_7
DQ2_8B_8
DQ2_8B_6
DQ2_8B_7
DQ2_8B_8
DQ8T
DQ8T
DQ8T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ1_8B_0
DQ1_8B_1
DQ1_8B_2
DQ1_8B_0
DQ1_8B_1
DQ1_8B_2
DQ8T
DQ8T
DQ8T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ1_8B_3
DQ1_8B_4
DQ1_8B_5
DQ1_8B_3
DQ1_8B_4
DQ1_8B_5
DQS8T/CQ8T/CQn8T/QKn8T
DQSn8T/QK8T
DQ8T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQS1_8B
DQS#1_8B
DM1_8B
DQS1_8B
DQS#1_8B
DM1_8B
DQ8T
DQ8T
DQ8T
DQ4T
DQ4T
DQ4T
DQ2T
DQ2T
DQ2T
DQ1_8B_6
DQ1_8B_7
DQ1_8B_8
DQ9T
DQ9T
DQ9T
DQ5T
DQ5T
DQ5T
DQ9T
DQ9T
DQ9T
DQ5T
DQ5T
DQ5T
DQS9T/CQ9T/CQn9T/QKn9T
DQSn9T/QK9T
DQ9T
DQS5T/CQ5T/CQn5T/QKn5T
DQSn5T/QK5T
DQ5T
DQ9T
DQ9T
DQ9T
DQ5T
DQ5T
DQ5T
DQ10T
DQ10T
DQ10T
DQ5T
DQ5T
DQ5T
DQ10T
DQ10T
DQ10T
DQ5T
DQ5T
DQ5T
DQS10T/CQ10T/CQn10T/QKn10T
DQSn10T/QK10T
DQ10T
DQ5T
DQ5T
DQ5T
DQ1_8B_6
DQ1_8B_7
DQ1_8B_8
RESET#_8A
CK_8A
CK#_8A
CKE_8A_0
CKE_8A_1
A_8A_0
A_8A_1
A_8A_2
A_8A_3
A_8A_4
A_8A_5
A_8A_6
A_8A_7
A_8A_8
A_8A_9
A_8A_10
A_8A_11
A_8A_12
A_8A_13
A_8A_14
A_8A_15
BA_8A_0
BA_8A_1
BA_8A_2
RAS#_8A
CAS#_8A
WE#_8A
ODT_8A_0
ODT_8A_1
DQ10T
DQ10T
DQ10T
DQ5T
DQ5T
DQ5T
CS#_8A_0
CS#_8A_1
CS#_8A_0
CS#_8A_1
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
CK_8A
CK#_8A
CKE_8A_0
CKE_8A_1
CA_8A_0
CA_8A_1
CA_8A_2
CA_8A_3
CA_8A_4
CA_8A_5
CA_8A_6
CA_8A_7
CA_8A_8
CA_8A_9
ODT_8A_0
ODT_8A_1
DQ11T
DQ11T
DQ11T
DQ11T
DQ11T
DQ11T
DQS11T/CQ11T/CQn11T/QKn11T
DQSn11T/QK11T
DQ11T
DQ11T
DQ11T
DQ11T
Pin List HF40
Page 18 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
AE38
AE39
AF31
AF32
AF34
AF36
AF37
AG38
AG39
AH32
AH33
AH34
AH35
AH36
AH37
AJ35
AJ38
AJ39
AK36
AK37
AL35
AL38
AL39
AM36
AM37
AN35
AN38
AN39
AP36
AP37
AR35
AR38
AR39
AT36
AT37
AU35
AU38
AU39
AV35
AV36
AV37
AV38
AV39
AW35
AW38
B36
B37
C35
C38
C39
D36
D37
E35
E38
E39
F36
F37
G35
G38
G39
H36
H37
J35
J38
J39
K36
K37
L35
L38
L39
M36
M37
N35
N38
N39
P36
P37
R34
R38
R39
T32
T36
T37
U33
U35
U38
U39
V32
V34
V36
V37
W33
W38
W39
Y31
Y32
Y36
Y37
AA3
AA4
AA6
AA8
AB1
AB2
AB7
AC3
AC4
AC8
AD1
AD2
AD5
AD7
AE3
AE4
AE6
AE8
AF1
AF2
Pin List HF40
Page 19 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCPLL_HPS
VCCBAT
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX_SHARED
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCA_GXBL0
VCCA_GXBR0
VCCA_GXBL1
VCCA_GXBR1
VCCA_GXBL2
VCCH_GXBL0
VCCH_GXBR0
VCCH_GXBL1
VCCH_GXBR1
VCCH_GXBL2
VCCL_GXBL0
VCCL_GXBL0
VCCL_GXBR0
VCCL_GXBR0
VCCL_GXBL1
VCCL_GXBL1
VCCL_GXBR1
VCCL_GXBR1
VCCL_GXBL2
VCCL_GXBL2
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCT_GXBL0
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
AF9
AG3
AG4
AG5
AG6
AG7
AG8
AH1
AH2
AH5
AJ3
AJ4
AK1
AK2
AK5
AL3
AL4
AM1
AM2
AM5
AN3
AN4
AP1
AP2
AP5
AR3
AR4
AT1
AT2
AT5
AU3
AU4
AV1
AV2
N3
N4
P1
P2
P5
R3
R4
R5
T1
T2
T5
U3
U4
U5
U6
V1
V2
V7
W3
W4
W8
Y1
Y2
Y5
Y7
AA21
AA25
AB15
U10
U16
V25
V27
W10
Y27
AC30
AC9
Y30
AA9
V31
U8
R33
AB14
AB26
U28
U15
AD31
AE9
W30
W9
T31
AF33
AE7
AB33
AA7
V33
AD33
AC7
Y33
W7
T33
AD34
AD35
AC5
AC6
Y34
Y35
W5
W6
T34
T35
U34
W34
AA34
AB35
AC35
AE34
AF35
V5
V6
Y6
AA5
AB5
AB6
AG35
Pin List HF40
Page 20 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
VCCT_GXBL0
VCCT_GXBR0
VCCT_GXBR0
VCCT_GXBL1
VCCT_GXBL1
VCCT_GXBR1
VCCT_GXBR1
VCCT_GXBL2
VCCT_GXBL2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4C
VCCIO4C
VCCIO4C
VCCIO4C
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7B_HPS
VCCIO7B_HPS
VCCIO7C_HPS
VCCIO7D_HPS
VCCIO7D_HPS
VCCIO7E_HPS
VCCIO7G
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
AG34
AD6
AE5
W35
V35
AF5
AF6
R35
AC34
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA24
AA26
AB11
AB17
U18
V17
V22
V23
V29
W20
W18
W22
W24
W26
W28
Y11
Y15
Y17
Y19
Y23
Y25
Y29
Y21
U12
V11
V12
V13
V15
W12
W14
Y13
AH29
AJ30
AK35
AM30
AP35
AT35
AK28
AL27
AN28
AT28
AJ24
AL25
AM24
AP25
AR24
AU25
AJ22
AL21
AM22
AP21
AR22
AU21
AG10
AJ5
AL5
AN5
AR5
AU5
AK13
AM12
AN10
AN13
AR12
AT10
AJ15
AM15
AR15
AV15
AJ19
AK18
AM19
AN18
AR19
AT18
A10
C5
C8
F6
F8
J6
K8
M8
P9
B3
D4
G3
J3
L3
N2
N5
B13
E10
G12
K13
E14
J15
D17
B18
G17
J20
K19
Pin List HF40
Page 21 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
VREFB7A7B7C7D7EN0_HPS
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
PinName/Function (2), (3)
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8B
VCCIO8B
VCCIO8B
VCCIO8B
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD4A
VCCPD4A
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD7A_HPS
VCCPD7B_HPS
VCCPD7C_HPS
VCCPD7D_HPS
VCCPD7E_HPS
VCCPD7FG
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPGM
VCCPGM
VCCRSTCLK_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VREFB7A7B7C7D7EN0_HPS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
B35
G31
G33
K31
K33
P33
E28
E30
H30
K28
C25
D27
F25
G27
J25
M24
C21
D22
F21
G22
K22
M21
AA27
AA28
AA29
AB22
AB23
AB24
AB30
AC10
AE10
AB12
AB13
AB16
AB18
AB19
L9
T10
T6
T8
R12
T14
R16
T17
R18
U21
R32
T30
U22
U24
U26
U29
J19
AG29
L10
T13
U14
U9
V10
P18
AA11
AA13
AA15
AA17
AA19
AA23
AA30
AB10
AC11
AC14
AC17
AC20
AC23
AC26
AC28
AD10
AD30
AE30
AF11
AF14
AF17
AF20
AF23
AF26
AF29
AF30
AG31
AG9
AJ11
AJ14
AJ17
AJ20
AJ23
AJ26
AJ29
AJ32
AJ8
AM11
AM14
AM17
AM20
AM23
AM26
AM29
AM32
AM8
AR11
AR14
AR17
AR20
AR23
AR26
AR29
AR32
AR8
AV11
AV14
AV17
Pin List HF40
Page 22 of 24
®
Pin Information for the Arria V 5ASXFB3 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2), (3)
Optional Function(s)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F1517 (4) DQS for X8/X9
DQS for X16/ X18
DQS for X32/ X36
HMC pin
assignment for
DDR3 (5)
HMC pin
assignment for
LPDDR2
HPS Pin Mux Select 3 HPS Pin Mux
Select 2
HPS Pin Mux
Select 1
HPS Pin Mux
Select 0
AV20
AV23
AV26
AV29
AV32
AV5
AV8
B11
B16
B2
B20
B23
B26
B29
B32
B5
B8
E11
E17
E2
E20
E23
E26
E29
E32
E5
E8
F14
H11
H17
H2
H20
H23
H26
H29
H32
H5
H8
J14
K20
L11
L17
L2
L23
L26
L29
L32
L5
L8
N14
N17
N20
P11
P23
P26
P29
P32
P8
W21
T12
T15
T16
T18
T20
T9
U11
U13
U17
U23
U25
U27
U30
U7
V14
V9
V18
V21
V24
V26
V28
V30
V8
W27
W11
W13
W15
W17
W19
W23
W25
W29
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
Y26
Y28
Notes:
(1) For more information about pin definitions and pin connection guidelines, refer to the
Arria V Device Family Pin Connection Guidelines.
(2) GXB_REFCLK pin is not supported in current Quartus II version, but will be supported in future Quartus II release version.
(3) Pins with * contains similar name with other pins in the same column. For the selection of the HPS pins, refer to the "HPS Pin Mux Select x" columns.
(4) Pins with * are the 10 Gbps transceiver channels. For more information about the 10 Gbps transceiver channels clocking recommendation, refer to the
Transceiver Clocking in Arria V Devices chapter.
(5) RESET pin is only applicable for DDR3 device.
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Pin List HF40
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Pin Information for the Arria® V 5ASXFB3 Device
Version 1.2
Version Number
1.0
1.1
1.2
PT-5ASXFB3-1.2
Copyright © 2015 Altera Corp.
Date
4/19/2013
9/30/2014
7/31/2015
Changes Made
Initial release.
Remove corresponding bank number from VCCRSTCLK_HPS pin.
Renamed the following columns:
- Renamed "DDR3/DDR2 hard memory PHY" to "HMC pin assignment for DDR3".
- Renamed "LPDDR2 hard memory PHY" to "HMC pin assignment for LPDDR2".
Revision History
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