Pin-Outs

Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3B
3B
3B
3B
3B
3B
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF
PinName/Function (2)
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
TDO
nCSO
TMS
AS_DATA3
TCK
AS_DATA2
TDI
AS_DATA1
DCLK
AS_DATA0,ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6BN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
TDO
DATA4
TMS
DATA3
TCK
DATA2
TDI
DATA1
DCLK
DATA0
DATA6
DATA5
DATA8
DATA7
DATA10
DATA9
DATA12
DATA11
DATA14
DATA13
CLKUSR
DATA15
PR_DONE
PR_READY
PR_ERROR
CLK0n,FPLL_BL_FBn
CLK0p,FPLL_BL_FBp
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB
CLK1n
CLK1p
RZQ_0
CLK2n
CLK2p
CLK3n
CLK3p
RZQ_1
INIT_DONE
PR_REQUEST
CRC_ERROR
nCEO
CvP_CONFDONE
DEV_OE
DEV_CLRn
Dedicated Tx/Rx
Channel
DIFFIO_RX_B1n
DIFFIO_TX_B2n
DIFFIO_RX_B1p
DIFFIO_TX_B2p
DIFFIO_RX_B3n
DIFFIO_TX_B4n
DIFFIO_RX_B3p
DIFFIO_TX_B4p
DIFFIO_RX_B5n
DIFFIO_TX_B6n
DIFFIO_RX_B5p
DIFFIO_TX_B6p
DIFFIO_RX_B7n
DIFFIO_TX_B8n
DIFFIO_RX_B7p
DIFFIO_TX_B8p
DIFFIO_RX_B31n
DIFFIO_RX_B31p
DIFFIO_TX_B37n
DIFFIO_TX_B37p
DIFFIO_RX_B39n
DIFFIO_RX_B39p
DIFFIO_TX_B41n
DIFFIO_RX_B42n
DIFFIO_TX_B41p
DIFFIO_RX_B42p
DIFFIO_RX_B43n
DIFFIO_TX_B44n
DIFFIO_RX_B43p
DIFFIO_TX_B44p
DIFFIO_TX_B45n
DIFFIO_RX_B46n
DIFFIO_TX_B45p
DIFFIO_RX_B46p
DIFFIO_RX_B47n
DIFFIO_TX_B48n
DIFFIO_RX_B47p
DIFFIO_TX_B48p
DIFFIO_RX_B55n
DIFFIO_RX_B55p
DIFFIO_TX_B69n
DIFFIO_RX_B70n
DIFFIO_TX_B69p
DIFFIO_RX_B70p
DIFFIO_TX_R1p
DIFFIO_RX_R2p
DIFFIO_TX_R1n
DIFFIO_RX_R2n
DIFFIO_TX_R3p
DIFFIO_RX_R4p
DIFFIO_TX_R3n
DIFFIO_RX_R4n
DIFFIO_TX_R5p
DIFFIO_RX_R6p
DIFFIO_TX_R5n
DIFFIO_RX_R6n
DIFFIO_TX_R7p
DIFFIO_RX_R8p
DIFFIO_TX_R7n
DIFFIO_RX_R8n
Emulated LVDS
Output Channel
DIFFOUT_B1n
DIFFOUT_B2n
DIFFOUT_B1p
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B4n
DIFFOUT_B3p
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B6n
DIFFOUT_B5p
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT_B8n
DIFFOUT_B7p
DIFFOUT_B8p
DIFFOUT_B31n
DIFFOUT_B31p
DIFFOUT_B37n
DIFFOUT_B37p
DIFFOUT_B39n
DIFFOUT_B39p
DIFFOUT_B41n
DIFFOUT_B42n
DIFFOUT_B41p
DIFFOUT_B42p
DIFFOUT_B43n
DIFFOUT_B44n
DIFFOUT_B43p
DIFFOUT_B44p
DIFFOUT_B45n
DIFFOUT_B46n
DIFFOUT_B45p
DIFFOUT_B46p
DIFFOUT_B47n
DIFFOUT_B48n
DIFFOUT_B47p
DIFFOUT_B48p
DIFFOUT_B55n
DIFFOUT_B55p
DIFFOUT_B69n
DIFFOUT_B70n
DIFFOUT_B69p
DIFFOUT_B70p
DIFFOUT_R1p
DIFFOUT_R2p
DIFFOUT_R1n
DIFFOUT_R2n
DIFFOUT_R3p
DIFFOUT_R4p
DIFFOUT_R3n
DIFFOUT_R4n
DIFFOUT_R5p
DIFFOUT_R6p
DIFFOUT_R5n
DIFFOUT_R6n
DIFFOUT_R7p
DIFFOUT_R8p
DIFFOUT_R7n
DIFFOUT_R8n
U484
U4
AA1
V2
AB2
W3
Y3
W4
AA2
V4
AB3
Y5
AB5
W6
AA5
V5
AB7
U6
AA6
V7
AA7
U7
Y8
W7
W8
V6
V9
V10
U10
AB10
AB9
AB8
AA8
AA11
AB13
Y11
AB12
W11
AB14
V11
AA13
AB17
AB15
AA16
AA15
Y14
AB20
W14
AB19
Y13
W12
AB18
Y16
AA18
Y15
Y19
V17
Y20
W18
AA21
U18
Y21
V19
AB22
V16
AA22
U17
V20
V15
W21
W16
R18
T17
P18
T18
P19
U20
M15
N15
V22
R15
T20
N17
U19
R20
N16
V21
P16
N14
W22
P14
U22
M19
R19
M17
T22
P21
L18
P22
L16
T21
M14
R21
M13
N20
K19
N21
DQS for X8
HMC Pin Assignment for DDR3 HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQSn2B
DQ2B
DQS2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQS1R
DQ1R
DQSn1R
DQ1R
DQ1R
DQ1R
Pin List U19
HPS_DM_3
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DM_3
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQS_3
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DM_2
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DM_1
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQS_3
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DM_2
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DM_1
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
Page 1 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF
PinName/Function (2)
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_RZQ_0
GND
GND
HPS_nRST
HPS_nPOR
HPS_TDO
VCCRSTCLK_HPS
HPS_TMS
HPS_TCK
HPS_TRST
HPS_TDI
GND
HPS_PORSEL
HPS_CLK1
HPS_CLK2
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0,BOOTSEL0
UART0_RX
UART0_TX,CLKSEL1
I2C0_SDA
I2C0_SCL
CAN0_RX
CAN0_TX,CLKSEL0
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE,BOOTSEL2
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0,BOOTSEL1
QSPI_CLK
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7C
7C
7C
7C
7C
7C
7C
7C
7D
7D
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U484
DQS for X8
K20
M22
N22
K16
L22
K18
N19
L15
L20
K14
K21
J19
M20
J18
H19
L21
J22
H17
J21
G19
H20
K15
H22
J14
H21
G20
G22
G18
F20
F21
C22
F22
B22
E19
H15
E20
J16
E21
C21
D22
E18
D21
G17
F17
D18
E15
B18
G15
D17
J13
H14
F16
F15
G14
C16
E14
B15
D19
C15
C20
F13
C19
C14
B19
B20
A21
A22
A20
D14
A16
E13
A15
A18
B14
A17
J11
J12
J9
D13
H12
B13
H10
C12
H11
A13
G12
G10
E11
A12
B12
D11
D12
F10
F11
A11
C11
G9
E8
B10
A10
C10
E9
F8
B9
H7
F7
Pin List U19
HMC Pin Assignment for DDR3 HMC Pin Assignment for
LPDDR2
HPS_DQ_8
HPS_DQ_8
HPS_DM_0
HPS_DM_0
HPS_DQ_7
HPS_DQ_7
HPS_DQ_5
HPS_DQ_5
HPS_DQ_6
HPS_DQ_6
HPS_DQ_4
HPS_DQ_4
HPS_ODT_1
HPS_ODT_1
HPS_DQS_0
HPS_DQS_0
HPS_ODT_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_3
HPS_DQ_1
HPS_DQ_1
HPS_DQ_2
HPS_DQ_2
HPS_DQ_0
HPS_DQ_0
HPS_A_0
HPS_A_1
HPS_A_4
HPS_A_2
HPS_A_5
HPS_A_3
HPS_CK
HPS_A_6
HPS_CK#
HPS_A_7
HPS_BA_1
HPS_BA_0
HPS_BA_2
HPS_CAS#
HPS_RAS#
HPS_A_8
HPS_A_10
HPS_A_9
HPS_A_11
HPS_CS#_0
HPS_A_12
HPS_CS#_1
HPS_A_13
HPS_A_14
HPS_WE#
HPS_A_15
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
SPIS1_CLK
SPIS1_MOSI
SPIS1_SS0
SPIS1_MISO
I2C1_SDA
I2C1_SCL
CAN1_RX
CAN1_TX
CAN0_RX
CAN0_TX
UART1_RX
UART1_TX
UART0_RX
UART0_TX
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RXD0
RGMII1_MDIO
RGMII1_MDC
RGMII1_RX_CTL
RGMII1_TX_CTL
RGMII1_RX_CLK
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
QSPI_SS1
UART0_RX
UART0_TX
I2C1_SDA
I2C1_SCL
CAN1_RX
CAN1_TX
I2C0_SDA
I2C0_SCL
UART0_CTS
UART0_RTS
UART1_CTS
UART1_RTS
SPIM0_SS1
SPIM1_SS1
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
QSPI_SS3
USB1_D0
USB1_D1
USB1_D2
USB1_D3
HPS Pin Mux Select 0
HPS_CA_0
HPS_CA_1
HPS_CA_4
HPS_CA_2
HPS_CA_5
HPS_CA_3
HPS_CK
HPS_CA_6
HPS_CK#
HPS_CA_7
HPS_CA_8
HPS_CA_9
HPS_CS#_0
HPS_CS#_1
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
UART0_RX
UART0_TX
I2C0_SDA
I2C0_SCL
CAN0_RX
CAN0_TX
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0
QSPI_CLK
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
I2C3_SDA
I2C3_SCL
USB1_D4
USB1_D5
USB1_D6
USB1_D7
QSPI_SS2
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
USB0_D0
USB0_D1
USB0_D2
USB0_D3
USB0_CLK
USB0_STP
USB0_DIR
USB0_NXT
USB1_D0
HPS_GPIO48
HPS_GPIO49
HPS_GPIO50
HPS_GPIO51
HPS_GPIO52
HPS_GPIO53
HPS_GPIO54
HPS_GPIO55
HPS_GPIO56
HPS_GPIO57
HPS_GPIO58
HPS_GPIO59
HPS_GPIO60
HPS_GPIO61
HPS_GPIO62
HPS_GPIO63
HPS_GPIO64
HPS_GPIO65
HPS_GPIO66
HPS_GPIO14
HPS_GPIO15
HPS_GPIO16
HPS_GPIO17
HPS_GPIO18
HPS_GPIO19
HPS_GPIO20
HPS_GPIO21
HPS_GPIO22
HPS_GPIO23
HPS_GPIO24
HPS_GPIO25
HPS_GPIO26
HPS_GPIO27
HPS_GPIO28
HPS_GPIO29
HPS_GPIO30
HPS_GPIO31
HPS_GPIO32
HPS_GPIO33
HPS_GPIO34
HPS_GPIO36
HPS_GPIO37
HPS_GPIO38
HPS_GPIO39
HPS_GPIO44
HPS_GPIO45
HPS_GPIO46
HPS_GPIO47
HPS_GPIO0
HPS_GPIO1
Page 2 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
8A
8A
8A
8A
8A
8A
9A
9A
9A
9A
9A
9A
9A
9A
9A
VREF
PinName/Function (2)
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
IO
IO
IO
IO
IO
IO
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
MSEL2
MSEL3
nCONFIG
MSEL4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
CLK7p
CLK7n
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn
CLK6p,FPLL_TL_FBp
CLK6n,FPLL_TL_FBn
Dedicated Tx/Rx
Channel
DIFFIO_RX_T1p
DIFFIO_RX_T1n
DIFFIO_TX_T4p
DIFFIO_TX_T4n
DIFFIO_RX_T9p
DIFFIO_RX_T9n
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
MSEL2
MSEL3
nCONFIG
MSEL4
Emulated LVDS
Output Channel
DIFFOUT_T1p
DIFFOUT_T1n
DIFFOUT_T4p
DIFFOUT_T4n
DIFFOUT_T9p
DIFFOUT_T9n
U484
DQS for X8
G7
A8
D8
F6
A7
C7
H6
D7
H9
B7
B8
E6
F5
E5
A6
A5
C6
C5
B4
A3
E4
B3
A2
A1
C4
B2
C2
C1
A14
A4
AA14
AA4
AB1
AB11
AB21
B1
B11
B21
B6
C18
C3
C8
D1
D15
E1
E12
E2
E22
E3
F14
F19
F2
F3
F4
F9
G1
G16
G2
G4
G5
G6
H13
H2
H4
H5
J10
J20
J3
J5
J7
K1
K11
K13
K17
K2
K4
K6
K8
K9
L10
L12
L14
L2
L3
L5
L7
L8
M1
M11
M2
M21
M4
M6
M9
N1
N10
N12
N18
N2
N3
N5
N7
N8
P11
P15
P2
Pin List U19
HMC Pin Assignment for DDR3 HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
HPS Pin Mux Select 1
I2C2_SDA
I2C2_SCL
HPS Pin Mux Select 0
HPS_GPIO2
HPS_GPIO3
HPS_GPIO4
HPS_GPIO5
HPS_GPIO6
HPS_GPIO7
HPS_GPIO8
HPS_GPIO9
HPS_GPIO10
HPS_GPIO11
HPS_GPIO12
HPS_GPIO13
Page 3 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DNU
DNU
DNU
DNU
DNU
DNU
VCCPGM
VCCPGM
VCCPGM
VCCBAT
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO5A
VCCIO5A
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7B_HPS
VCCIO7B_HPS
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U484
DQS for X8
HMC Pin Assignment for DDR3 HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
P4
P6
P9
R1
R12
R14
R2
R22
R3
R5
R7
R9
T1
T13
T15
T19
T2
T4
T6
T8
U11
U12
U13
U14
U15
U16
U2
U3
U5
U8
U9
V1
V13
V3
V8
W10
W15
W20
Y1
Y17
Y2
Y7
R16
P13
H8
J4
J6
J8
K3
K5
K7
L4
L6
M3
M5
M7
M8
N4
N6
P3
P5
P7
P8
R4
R6
R8
T3
T5
T7
P17
J2
H1
W2
Y9
C17
G8
Y4
Y18
D4
D2
AB6
W5
AA9
AA19
AB16
Y12
V18
Y22
D20
E17
G21
H18
J15
K22
L13
L19
M16
N13
P20
R17
T14
U21
A19
B16
C13
G11
Pin List U19
Page 4 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
3A
3B
4A
5A
8A
VREF
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB5AN0
VREFB7A7B7C7DN0_HPS
VREFB8AN0
PinName/Function (2)
Optional Function(s)
VCCIO7C_HPS
VCCIO7D_HPS
VCCIO7D_HPS
VCCIO8A
VCCPD3A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD5A
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD7A_HPS
VCCPD7B_HPS
VCCPD7C_HPS
VCCPD7D_HPS
VCCPD8A
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB5AN0
VREFB7A7B7C7DN0_HPS
VREFB8AN0
NC
NC
NC
NC
NC
NC
NC
NC
VCCRSTCLK_HPS
RREF_TL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX_SHARED
VCCPLL_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U484
DQS for X8
HMC Pin Assignment for DDR3 HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
D10
A9
E7
D5
Y6
AA12
V12
V14
W13
W9
T16
H16
J17
L17
M18
G13
F12
E10
C9
D6
AB4
AA10
AA20
W19
B17
B5
G3
H3
R10
R11
T10
T11
T12
T9
D16
J1
L1
P1
U1
W1
F1
W17
AA17
AA3
D3
D9
Y10
E16
F18
R13
K10
K12
L11
L9
M10
M12
N11
N9
P10
P12
Notes:
(1) For more information about pin definitions and pin connection guidelines, refer to the
Cyclone V Device Family Pin Connection Guidelines.
(2) HPS_DDR pins are for memory interface only. For the dedicated pin function corresponding with the respective memory interfaces, refer to the HMC columns.
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Pin List U19
Page 5 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
VREF
PinName/Function (2)
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
TDO
nCSO
TMS
AS_DATA3
TCK
AS_DATA2
TDI
AS_DATA1
DCLK
AS_DATA0,ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
CLK0n,FPLL_BL_FBn
CLK0p,FPLL_BL_FBp
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB
CLK1n
CLK1p
RZQ_0
CLK2n
CLK2p
CLK3n
CLK3p
Configuration
Function
TDO
DATA4
TMS
DATA3
TCK
DATA2
TDI
DATA1
DCLK
DATA0
DATA6
DATA5
DATA8
DATA7
DATA10
DATA9
DATA12
DATA11
DATA14
DATA13
CLKUSR
DATA15
PR_DONE
PR_READY
PR_ERROR
Dedicated Tx/Rx
Channel
DIFFIO_RX_B1n
DIFFIO_TX_B2n
DIFFIO_RX_B1p
DIFFIO_TX_B2p
DIFFIO_RX_B3n
DIFFIO_TX_B4n
DIFFIO_RX_B3p
DIFFIO_TX_B4p
DIFFIO_RX_B5n
DIFFIO_TX_B6n
DIFFIO_RX_B5p
DIFFIO_TX_B6p
DIFFIO_RX_B7n
DIFFIO_TX_B8n
DIFFIO_RX_B7p
DIFFIO_TX_B8p
DIFFIO_TX_B25n
DIFFIO_RX_B26n
DIFFIO_TX_B25p
DIFFIO_RX_B26p
DIFFIO_RX_B27n
DIFFIO_TX_B28n
DIFFIO_RX_B27p
DIFFIO_TX_B28p
DIFFIO_TX_B29n
DIFFIO_RX_B30n
DIFFIO_TX_B29p
DIFFIO_RX_B30p
DIFFIO_RX_B31n
DIFFIO_TX_B32n
DIFFIO_RX_B31p
DIFFIO_TX_B32p
DIFFIO_TX_B33n
DIFFIO_RX_B34n
DIFFIO_TX_B33p
DIFFIO_RX_B34p
DIFFIO_RX_B35n
DIFFIO_TX_B36n
DIFFIO_RX_B35p
DIFFIO_TX_B36p
DIFFIO_TX_B37n
DIFFIO_RX_B38n
DIFFIO_TX_B37p
DIFFIO_RX_B38p
DIFFIO_RX_B39n
DIFFIO_TX_B40n
DIFFIO_RX_B39p
DIFFIO_TX_B40p
DIFFIO_TX_B41n
DIFFIO_RX_B42n
DIFFIO_TX_B41p
DIFFIO_RX_B42p
DIFFIO_RX_B43n
DIFFIO_TX_B44n
DIFFIO_RX_B43p
DIFFIO_TX_B44p
DIFFIO_TX_B45n
DIFFIO_RX_B46n
DIFFIO_TX_B45p
DIFFIO_RX_B46p
DIFFIO_RX_B47n
DIFFIO_TX_B48n
DIFFIO_RX_B47p
DIFFIO_TX_B48p
DIFFIO_RX_B50n
DIFFIO_TX_B49p
DIFFIO_RX_B50p
DIFFIO_RX_B51n
DIFFIO_TX_B52n
DIFFIO_RX_B51p
DIFFIO_TX_B52p
DIFFIO_TX_B53n
DIFFIO_RX_B54n
DIFFIO_TX_B53p
DIFFIO_RX_B54p
DIFFIO_RX_B55n
DIFFIO_TX_B56n
DIFFIO_RX_B55p
DIFFIO_TX_B56p
DIFFIO_RX_B58n
DIFFIO_TX_B57p
DIFFIO_RX_B58p
DIFFIO_RX_B59n
DIFFIO_TX_B60n
DIFFIO_RX_B59p
DIFFIO_TX_B60p
DIFFIO_TX_B61n
DIFFIO_RX_B62n
DIFFIO_TX_B61p
DIFFIO_RX_B62p
DIFFIO_TX_B64n
DIFFIO_TX_B64p
DIFFIO_RX_B66n
DIFFIO_TX_B65p
DIFFIO_RX_B66p
DIFFIO_RX_B67n
DIFFIO_TX_B68n
DIFFIO_RX_B67p
DIFFIO_TX_B69n
DIFFIO_RX_B70n
DIFFIO_TX_B69p
DIFFIO_RX_B70p
DIFFIO_TX_B72n
DIFFIO_TX_B72p
DIFFIO_RX_B74n
Emulated LVDS
Output Channel
DIFFOUT_B1n
DIFFOUT_B2n
DIFFOUT_B1p
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B4n
DIFFOUT_B3p
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B6n
DIFFOUT_B5p
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT_B8n
DIFFOUT_B7p
DIFFOUT_B8p
DIFFOUT_B25n
DIFFOUT_B26n
DIFFOUT_B25p
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B28n
DIFFOUT_B27p
DIFFOUT_B28p
DIFFOUT_B29n
DIFFOUT_B30n
DIFFOUT_B29p
DIFFOUT_B30p
DIFFOUT_B31n
DIFFOUT_B32n
DIFFOUT_B31p
DIFFOUT_B32p
DIFFOUT_B33n
DIFFOUT_B34n
DIFFOUT_B33p
DIFFOUT_B34p
DIFFOUT_B35n
DIFFOUT_B36n
DIFFOUT_B35p
DIFFOUT_B36p
DIFFOUT_B37n
DIFFOUT_B38n
DIFFOUT_B37p
DIFFOUT_B38p
DIFFOUT_B39n
DIFFOUT_B40n
DIFFOUT_B39p
DIFFOUT_B40p
DIFFOUT_B41n
DIFFOUT_B42n
DIFFOUT_B41p
DIFFOUT_B42p
DIFFOUT_B43n
DIFFOUT_B44n
DIFFOUT_B43p
DIFFOUT_B44p
DIFFOUT_B45n
DIFFOUT_B46n
DIFFOUT_B45p
DIFFOUT_B46p
DIFFOUT_B47n
DIFFOUT_B48n
DIFFOUT_B47p
DIFFOUT_B48p
DIFFOUT_B50n
DIFFOUT_B49p
DIFFOUT_B50p
DIFFOUT_B51n
DIFFOUT_B52n
DIFFOUT_B51p
DIFFOUT_B52p
DIFFOUT_B53n
DIFFOUT_B54n
DIFFOUT_B53p
DIFFOUT_B54p
DIFFOUT_B55n
DIFFOUT_B56n
DIFFOUT_B55p
DIFFOUT_B56p
DIFFOUT_B58n
DIFFOUT_B57p
DIFFOUT_B58p
DIFFOUT_B59n
DIFFOUT_B60n
DIFFOUT_B59p
DIFFOUT_B60p
DIFFOUT_B61n
DIFFOUT_B62n
DIFFOUT_B61p
DIFFOUT_B62p
DIFFOUT_B64n
DIFFOUT_B64p
DIFFOUT_B66n
DIFFOUT_B65p
DIFFOUT_B66p
DIFFOUT_B67n
DIFFOUT_B68n
DIFFOUT_B67p
DIFFOUT_B69n
DIFFOUT_B70n
DIFFOUT_B69p
DIFFOUT_B70p
DIFFOUT_B72n
DIFFOUT_B72p
DIFFOUT_B74n
U672
Y9
AA6
AC7
AB6
AB5
AC5
W10
AC6
AA8
AD7
Y8
Y4
W8
Y5
T8
AB4
U9
AA4
V10
AD4
U10
AC4
AA11
AE6
Y11
AD5
AF4
AE9
AE4
AD10
U11
AF8
T11
AE7
AF9
AE11
AE8
AD11
W11
AF6
V11
AF5
AG6
AF10
AF7
AF11
T12
AH2
T13
AH3
AH4
AD12
AG5
AE12
W12
AH5
V12
AH6
AH7
AF13
AG8
AG13
U13
AH8
U14
AG9
AH9
AE15
AG10
AF15
AA13
AH11
Y13
AG11
AG16
AH12
AF17
V13
AH13
W14
AG14
AH14
AE17
AG15
AD17
AA15
AH16
Y15
AH17
AD19
AF18
AE19
AA18
AH18
AA19
AG18
AH19
AD20
AG19
AE20
AG20
AF20
AF21
AG21
AF22
AE22
AH21
AD23
AH22
AF23
AH23
AG23
AH24
AG24
AE23
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQSn2B
DQ2B
DQS2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQ3B
DQSn3B
DQ3B
DQS3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ4B
DQ4B
DQ4B
DQSn4B
DQ4B
DQS4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ4B
DQ5B
DQ5B
DQ5B
DQSn5B
DQ5B
DQS5B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ5B
DQ5B
DQ5B
DQ5B
DQ1B
DQ1B
DQ1B
DQ1B
DQ5B
DQ1B
DQ5B
DQ6B
DQ6B
DQ6B
DQSn6B
DQ6B
DQS6B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ7B
DQ7B
DQ7B
DQSn7B
DQ7B
DQS7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ8B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
Pin List U23
Page 6 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5B
5B
5B
5B
5B
5B
5B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF
PinName/Function (2)
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI13
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI12
HPS_GPI11
HPS_DDR
HPS_GPI10
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6BN0_HPS
HPS_DDR
HPS_GPI9
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI8
HPS_GPI7
HPS_DDR
HPS_GPI6
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI5
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI4
HPS_GPI3
HPS_DDR
HPS_GPI2
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI1
HPS_GPI0
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
RZQ_1
INIT_DONE
PR_REQUEST
CRC_ERROR
nCEO
CvP_CONFDONE
DEV_OE
DEV_CLRn
CLK5p
FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB
CLK5n
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn
CLK4p,FPLL_BR_FBp
CLK4n,FPLL_BR_FBn
RZQ_2
Dedicated Tx/Rx
Channel
DIFFIO_TX_B73p
DIFFIO_RX_B74p
DIFFIO_RX_B75n
DIFFIO_TX_B76n
DIFFIO_RX_B75p
DIFFIO_TX_B77n
DIFFIO_RX_B78n
DIFFIO_TX_B77p
DIFFIO_RX_B78p
DIFFIO_TX_B80n
DIFFIO_TX_B80p
DIFFIO_TX_R1p
DIFFIO_RX_R2p
DIFFIO_TX_R1n
DIFFIO_RX_R2n
DIFFIO_TX_R3p
DIFFIO_RX_R4p
DIFFIO_TX_R3n
DIFFIO_RX_R4n
DIFFIO_TX_R5p
DIFFIO_RX_R6p
DIFFIO_TX_R5n
DIFFIO_RX_R6n
DIFFIO_TX_R7p
DIFFIO_RX_R8p
DIFFIO_TX_R7n
DIFFIO_RX_R8n
DIFFIO_RX_R21p
DIFFIO_TX_R22p
DIFFIO_RX_R21n
DIFFIO_TX_R22n
DIFFIO_RX_R23p
DIFFIO_RX_R23n
DIFFIO_TX_R24n
Emulated LVDS
Output Channel
DIFFOUT_B73p
DIFFOUT_B74p
DIFFOUT_B75n
DIFFOUT_B76n
DIFFOUT_B75p
DIFFOUT_B77n
DIFFOUT_B78n
DIFFOUT_B77p
DIFFOUT_B78p
DIFFOUT_B80n
DIFFOUT_B80p
DIFFOUT_R1p
DIFFOUT_R2p
DIFFOUT_R1n
DIFFOUT_R2n
DIFFOUT_R3p
DIFFOUT_R4p
DIFFOUT_R3n
DIFFOUT_R4n
DIFFOUT_R5p
DIFFOUT_R6p
DIFFOUT_R5n
DIFFOUT_R6n
DIFFOUT_R7p
DIFFOUT_R8p
DIFFOUT_R7n
DIFFOUT_R8n
DIFFOUT_R21p
DIFFOUT_R22p
DIFFOUT_R21n
DIFFOUT_R22n
DIFFOUT_R23p
DIFFOUT_R23n
DIFFOUT_R24n
U672
DQS for X8
DQS for X16
AG26
AE24
AC23
AH26
AC22
AH27
AG25
AG28
AF25
AF28
AF27
AF26
AA20
AE26
Y19
AE25
Y17
AD26
Y18
AC24
Y16
AB23
W15
AA24
V16
AA23
V15
W21
AB26
W20
AA26
Y24
W24
AB25
AE28
AD28
V20
AE27
V19
V18
V24
V17
V25
U25
AC28
T26
AC27
U16
AB28
U15
AA27
T24
Y27
R24
T27
U19
Y26
T20
W26
R25
AA28
R26
Y28
T16
W28
T17
V27
N27
R27
N26
P26
T19
V28
T18
U28
N25
T28
N24
R28
R21
P28
R20
N28
M26
M28
M27
L28
R19
K28
R18
J28
L25
J27
K25
K27
M25
G28
F28
K26
G27
J26
G26
R17
D28
R16
D27
J24
E28
J25
H28
C28
B28
J21
E26
J20
DQ8B
DQ8B
DQSn8B
DQ8B
DQS8B
DQ8B
DQ8B
DQ8B
DQ8B
DQ8B
DQ8B
DQ1R
DQ2B
DQ2B
DQSn2B
DQ2B
DQS2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DM_3
HPS_DM_3
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQS_3
HPS_DQS_3
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DM_2
HPS_DM_2
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DM_1
HPS_DM_1
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_A_0
HPS_A_1
HPS_A_4
HPS_A_2
HPS_A_5
HPS_CA_0
HPS_CA_1
HPS_CA_4
HPS_CA_2
HPS_CA_5
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQS1R
DQ1R
DQSn1R
DQ1R
DQ1R
DQ1R
Pin List U23
Page 7 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF
PinName/Function (2)
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_RZQ_0
GND
GND
HPS_nRST
HPS_nPOR
HPS_TDO
VCCRSTCLK_HPS
HPS_TMS
HPS_TCK
HPS_TRST
HPS_TDI
GND
HPS_PORSEL
HPS_CLK1
HPS_CLK2
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0,BOOTSEL0
UART0_RX
UART0_TX,CLKSEL1
I2C0_SDA
I2C0_SCL
CAN0_RX
CAN0_TX,CLKSEL0
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE,BOOTSEL2
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0,BOOTSEL1
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
IO
IO
IO
IO
IO
IO
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
MSEL2
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
8A
8A
8A
8A
8A
8A
9A
9A
9A
9A
9A
9A
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
CLK7p
CLK7n
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn
CLK6p,FPLL_TL_FBp
CLK6n,FPLL_TL_FBn
Dedicated Tx/Rx
Channel
DIFFIO_RX_T1p
DIFFIO_RX_T1n
DIFFIO_TX_T4p
DIFFIO_TX_T4n
DIFFIO_RX_T9p
DIFFIO_RX_T9n
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
MSEL2
Emulated LVDS
Output Channel
DIFFOUT_T1p
DIFFOUT_T1n
DIFFOUT_T4p
DIFFOUT_T4n
DIFFOUT_T9p
DIFFOUT_T9n
U672
DQS for X8
D26
N21
C26
N20
B26
H25
A27
G25
A26
A25
F26
A24
F25
B24
L21
D24
L20
C24
G23
E25
F24
D25
F23
E23
A23
H19
B23
J19
C23
K19
C22
D22
D21
E18
E20
D20
C21
A22
B21
A21
K18
A20
J18
A19
C18
A18
C17
B18
J17
A17
H17
C19
B16
B19
C16
J15
A16
J14
A15
D17
A14
E16
A13
J13
A12
J12
A11
C15
A9
D15
A8
H16
A7
J16
A6
C14
B14
D14
A5
C13
B6
H13
A4
H12
B4
B12
B8
B11
B9
E4
C10
F5
C9
C4
C8
D4
C7
F4
C6
G4
C5
E5
D5
D12
C12
E8
D8
E11
D11
J10
J8
H9
H8
E6
G6
DQS for X16
HMC Pin Assignment for DDR3
HPS_A_3
HPS_CK
HPS_A_6
HPS_CK#
HPS_A_7
HPS_BA_1
HPS_BA_0
HPS_BA_2
HPS_CAS#
HPS_RAS#
HPS_A_8
HPS_A_10
HPS_A_9
HPS_A_11
HPS_CS#_0
HPS_A_12
HPS_CS#_1
HPS_A_13
HPS_A_14
HPS_WE#
HPS_A_15
HMC Pin Assignment for
LPDDR2
HPS_CA_3
HPS_CK
HPS_CA_6
HPS_CK#
HPS_CA_7
HPS Pin Mux Select 3
HPS Pin Mux Select 1
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
SPIS1_CLK
SPIS1_MOSI
SPIS1_SS0
SPIS1_MISO
I2C1_SDA
I2C1_SCL
CAN1_RX
CAN1_TX
CAN0_RX
CAN0_TX
UART1_RX
UART1_TX
UART0_RX
UART0_TX
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RXD0
RGMII1_MDIO
RGMII1_MDC
RGMII1_RX_CTL
RGMII1_TX_CTL
RGMII1_RX_CLK
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
QSPI_SS1
UART0_RX
UART0_TX
I2C1_SDA
I2C1_SCL
CAN1_RX
CAN1_TX
I2C0_SDA
I2C0_SCL
UART0_CTS
UART0_RTS
UART1_CTS
UART1_RTS
SPIM0_SS1
SPIM1_SS1
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
QSPI_SS3
USB1_D0
USB1_D1
USB1_D2
USB1_D3
HPS Pin Mux Select 0
HPS_CA_8
HPS_CA_9
HPS_CS#_0
HPS_CS#_1
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
UART0_RX
UART0_TX
I2C0_SDA
I2C0_SCL
CAN0_RX
CAN0_TX
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
Pin List U23
HPS Pin Mux Select 2
I2C3_SDA
I2C3_SCL
USB1_D4
USB1_D5
USB1_D6
USB1_D7
QSPI_SS2
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
USB0_D0
USB0_D1
USB0_D2
USB0_D3
USB0_D4
USB0_D5
USB0_D6
USB0_D7
USB0_CLK
USB0_STP
USB0_DIR
USB0_NXT
USB1_D0
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
I2C2_SDA
I2C2_SCL
HPS_GPIO48
HPS_GPIO49
HPS_GPIO50
HPS_GPIO51
HPS_GPIO52
HPS_GPIO53
HPS_GPIO54
HPS_GPIO55
HPS_GPIO56
HPS_GPIO57
HPS_GPIO58
HPS_GPIO59
HPS_GPIO60
HPS_GPIO61
HPS_GPIO62
HPS_GPIO63
HPS_GPIO64
HPS_GPIO65
HPS_GPIO66
HPS_GPIO14
HPS_GPIO15
HPS_GPIO16
HPS_GPIO17
HPS_GPIO18
HPS_GPIO19
HPS_GPIO20
HPS_GPIO21
HPS_GPIO22
HPS_GPIO23
HPS_GPIO24
HPS_GPIO25
HPS_GPIO26
HPS_GPIO27
HPS_GPIO28
HPS_GPIO29
HPS_GPIO30
HPS_GPIO31
HPS_GPIO32
HPS_GPIO33
HPS_GPIO34
HPS_GPIO35
HPS_GPIO36
HPS_GPIO37
HPS_GPIO38
HPS_GPIO39
HPS_GPIO40
HPS_GPIO41
HPS_GPIO42
HPS_GPIO43
HPS_GPIO44
HPS_GPIO45
HPS_GPIO46
HPS_GPIO47
HPS_GPIO0
HPS_GPIO1
HPS_GPIO2
HPS_GPIO3
HPS_GPIO4
HPS_GPIO5
HPS_GPIO6
HPS_GPIO7
HPS_GPIO8
HPS_GPIO9
HPS_GPIO10
HPS_GPIO11
HPS_GPIO12
HPS_GPIO13
Page 8 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
9A
9A
9A
VREF
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
PinName/Function (2)
MSEL3
nCONFIG
MSEL4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
MSEL3
nCONFIG
MSEL4
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U672
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
K10
F7
K9
F6
N8
P8
F2
F1
K2
K1
P2
P1
V2
V1
AB2
AB1
AF2
AF1
V5
V4
A10
A3
AA1
AA17
AA2
AA3
AA9
AB24
AB27
AB3
AC1
AC2
AC3
AD14
AD22
AD25
AD3
AD6
AD8
AE1
AE16
AE18
AE2
AE3
AF24
AF3
AG1
AG17
AG2
AG27
AG3
AG7
AH10
AH20
B15
B17
B20
B22
B25
B27
B3
B5
B7
C1
C11
C2
C3
D10
D13
D16
D3
E1
E19
E2
E22
E24
E27
E3
E9
F3
G1
G2
G3
H11
H15
H18
H20
H24
H27
H3
H4
H5
H6
J1
J2
J3
J5
J9
K11
K12
K14
K16
K20
K3
K4
K8
L1
L10
L13
L15
L17
L19
L2
L24
L27
Pin List U23
Page 9 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VCCPGM
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U672
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
L3
L5
L8
L9
M10
M11
M14
M16
M20
M3
M8
N1
N13
N15
N17
N19
N2
N3
N4
P10
P12
P16
P18
P20
P25
P3
P5
P9
R1
R11
R13
R15
R2
R3
R8
T10
T14
T3
U1
U12
U17
U2
U20
U24
U27
U3
U5
V14
V3
V8
V9
W1
W16
W18
W2
W3
W4
Y12
Y14
Y20
Y25
Y3
V26
V21
J11
K13
K15
L11
L12
L14
M12
M13
M15
M9
N10
N11
N12
N14
N9
P11
P13
P14
P15
R10
R12
R14
R9
T15
T9
L4
T4
M5
N5
R5
T5
U26
A2
B2
D1
D2
H1
H2
M1
M2
T1
T2
Y1
Y2
AD1
AD2
U8
AE14
D23
E12
Y10
Pin List U23
Page 10 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Note (1)
Bank
Number
3A
3B
4A
5A
5B
8A
VREF
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB5AN0
VREFB5BN0
VREFB7A7B7C7DN0_HPS
VREFB8AN0
PinName/Function (2)
Optional Function(s)
VCCPGM
VCCPGM
VCCBAT
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO5A
VCCIO5A
VCCIO5B
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7B_HPS
VCCIO7B_HPS
VCCIO7C_HPS
VCCIO7D_HPS
VCCIO7D_HPS
VCCIO8A
VCCPD3A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD5A
VCCPD5B
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD7A_HPS
VCCPD7B_HPS
VCCPD7C_HPS
VCCPD7D_HPS
VCCPD8A
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB5AN0
VREFB5BN0
VREFB7A7B7C7DN0_HPS
VREFB8AN0
VCCRSTCLK_HPS
RREF_TL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX_SHARED
VCCPLL_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U672
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
AD24
H10
D7
AA5
W9
AA12
AE10
AE13
AG4
AA16
AE21
AF14
AF19
AG12
AG22
AH15
AH25
W13
AC25
W17
W25
C25
C27
F27
G24
H21
H26
L26
M21
AD27
P27
T21
T25
U18
W27
C20
D18
B13
H14
B10
D6
G5
E7
AA10
AA14
AD13
AD16
AD18
AD21
AD9
Y21
W19
K21
K24
M24
P21
P24
E21
E17
E14
E13
E10
AE5
AF12
AF16
AC26
AA25
D19
D9
F22
B1
K5
P4
U4
W5
J4
AA21
M4
R4
AC21
AC8
AD15
E15
F8
F21
H23
U21
K17
L16
L18
M17
M18
M19
N16
N18
P17
P19
Notes:
(1) For more information about pin definitions and pin connection guidelines, refer to the
Cyclone V Device Family Pin Connection Guidelines.
(2) HPS_DDR pins are for memory interface only. For the dedicated pin function corresponding with the respective memory interfaces, refer to the HMC columns.
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Pin List U23
Page 11 of 12
Pin Information for the Cyclone® V 5CSEBA5S Device
Version 1.2
Version Number
1.0
1.1
1.2
PT-5CSEBA5S-1.2
Copyright © 2013 Altera Corp.
Date
10/18/2012
1/17/2013
3/25/2013
Changes Made
Initial release.
A pin that was marked as VCC_HPS has been corrected to VCCRSTCLK_HPS
Updated the following pin names:
- Changed SDMMC_CLK_IN to SDMMC_FB_CLK_IN
- Changed SDMMC_CLK to SDMMC_CCLK_OUT
Revision History
Page 12 of 12