Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO VREF0B2 INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO VREF1B2 INPUT INPUT IO IO INPUT INPUT IO IO CLK0n CLK0p IO CLK1p VCCA_PLL1 DIFFIO_RX21p DIFFIO_RX21n DIFFIO_TX21p DIFFIO_TX21n DIFFIO_RX20p/RUP2 DIFFIO_RX20n/RDN2 DIFFIO_TX20p DIFFIO_TX20n DIFFIO_RX19p DIFFIO_RX19n DIFFIO_TX19p DIFFIO_TX19n Copyright © 2006 Altera Corp. DIFFIO_RX18p DIFFIO_RX18n DIFFIO_TX18p DIFFIO_TX18n DIFFIO_RX17p DIFFIO_RX17n DIFFIO_TX17p DIFFIO_TX17n DIFFIO_RX16p DIFFIO_RX16n DIFFIO_TX16p DIFFIO_TX16n DIFFIO_RX15p DIFFIO_RX15n DIFFIO_TX15p DIFFIO_TX15n DIFFIO_RX14p DIFFIO_RX14n DIFFIO_TX14p DIFFIO_TX14n DIFFIO_RX13p DIFFIO_RX13n DIFFIO_TX13p DIFFIO_TX13n DIFFIO_RX12p DIFFIO_RX12n DIFFIO_TX12p DIFFIO_TX12n DIFFIO_RX11p DIFFIO_RX11n DIFFIO_TX11p DIFFIO_TX11n CLK1n Pin List (EP1SGX10D) Configuration Function F672 DQS for x32 F25 F26 H19 H20 G25 G26 J21 J22 H25 H26 K21 K22 L17 J23 J24 J19 J20 H23 H24 K19 K20 J25 J26 L21 L22 K25 K26 K17 K18 K23 K24 L19 L20 L23 L24 M21 M22 L18 M23 M24 M19 M20 L25 M25 M17 M18 N26 N25 N24 N23 N20 Page 1 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank Pin Name/Function VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 GND GNDA_PLL1 VCCG_PLL1 GNDG_PLL1 VCCA_PLL2 GND GNDA_PLL2 VCCG_PLL2 GNDG_PLL2 CLK2p CLK2n CLK3p IO INPUT INPUT IO IO INPUT INPUT IO IO VREF0B1 INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO VREF1B1 INPUT INPUT IO IO Copyright © 2006 Altera Corp. Optionn Function(s) Configuration Function F672 DQS for x32 N22 N21 N19 P21 CLK3n DIFFIO_RX10p DIFFIO_RX10n DIFFIO_TX10p DIFFIO_TX10n DIFFIO_RX9p DIFFIO_RX9n DIFFIO_TX9p DIFFIO_TX9n DIFFIO_RX8p DIFFIO_RX8n DIFFIO_TX8p DIFFIO_TX8n DIFFIO_RX7p DIFFIO_RX7n DIFFIO_TX7p DIFFIO_TX7n DIFFIO_RX6p DIFFIO_RX6n DIFFIO_TX6p DIFFIO_TX6n DIFFIO_RX5p DIFFIO_RX5n DIFFIO_TX5p DIFFIO_TX5n DIFFIO_RX4p DIFFIO_RX4n DIFFIO_TX4p DIFFIO_TX4n DIFFIO_RX3p DIFFIO_RX3n DIFFIO_TX3p DIFFIO_TX3n DIFFIO_RX2p DIFFIO_RX2n DIFFIO_TX2p DIFFIO_TX2n Pin List (EP1SGX10D) P22 P20 P19 P25 P26 P23 P24 R25 T25 R17 R18 U25 U26 R19 R20 R16 R23 R24 R21 R22 V25 V26 T19 T20 T23 T24 T21 T22 W25 W26 U17 U18 U23 U24 U19 U20 W23 W24 V19 V20 T18 V23 V24 U21 U22 Page 2 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) B1 B1 B1 B1 B1 B1 B1 B1 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 INPUT INPUT IO IO INPUT INPUT IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF0B8 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DIFFIO_RX1p/RUP1 DIFFIO_RX1n/RDN1 DIFFIO_TX1p DIFFIO_TX1n DIFFIO_RX0p DIFFIO_RX0n DIFFIO_TX0p DIFFIO_TX0n DQ9B7 DQ9B6 DQ9B5 DQ9B4 DQ9B3 DQS9B DQ9B2 DQ8B7 DQ9B1 DQ8B6 DQ9B0 DQ8B5 Copyright © 2006 Altera Corp. Configuration Function DQ8B4 DQ8B3 DQS8B DQ8B2 DQ8B1 DQ8B0 DQ7B2 DQ7B7 DQ7B6 DQ7B5 DQ7B4 DQ7B3 DQS7B DQ7B1 DQ7B0 DQ6B7 DQ6B6 DQ6B5 DQ6B4 PGM2 FCLK3 FCLK2 DQ6B3 DQS6B DQ6B2 CRC_ERROR DQ6B1 DQ6B0 Pin List (EP1SGX10D) F672 DQS for x32 Y25 Y26 V21 V22 Y23 Y24 W19 W20 AF23 AE22 AD22 AF22 AF21 AE21 AD21 AF20 AD20 AE19 AE20 AD18 V18 AD19 AF19 AE18 AF17 AC18 AF18 AB17 Y18 AA18 AB18 W18 AB16 AA17 Y16 W17 AA16 Y17 AE17 AD17 AD15 AE16 T15 T16 U16 AC17 AD16 AC15 U15 AC16 AE15 DQ1B31 DQ1B30 DQ1B29 DQ1B28 DQ1B27 DQ1B26 DQ1B23 DQ1B25 DQ1B22 DQ1B24 DQ1B21 DQ1B20 DQ1B19 DQ1B18 DQ1B17 DQ1B16 DQ1B10 DQ1B15 DQ1B14 DQ1B13 DQ1B12 DQ1B11 DQS1B DQ1B9 DQ1B8 DQ1B7 DQ1B6 DQ1B5 DQ1B4 DQ1B3 DQ1B2 DQ1B1 DQ1B0 Page 3 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B12 B12 B12 B12 B11 B11 B11 B11 B11 B11 B12 B11 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 IO IO IO IO IO IO VREF1B8 IO CLK5p IO CLK4p PLL_ENA MSEL0 MSEL1 MSEL2 IO IO IO IO IO IO IO IO IO IO VCC_PLL6_OUTB VCC_PLL6_OUTA VCCA_PLL6 GND GNDA_PLL6 VCCG_PLL6 GNDG_PLL6 CLK7p IO CLK6p IO nCE nCEO IO IO IO nIO_PULLUP VCCSEL PORSEL IO IO IO IO IO IO VREF0B7 RDN8 RUP8 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 Copyright © 2006 Altera Corp. Configuration Function RDYnBSY nCS CS CLK5n CLK4n PLL_ENA MSEL0 MSEL1 MSEL2 PLL6_OUT3n PLL6_OUT3p PLL6_OUT2n PLL6_OUT2p PLL6_FBn PLL6_FBp PLL6_OUT1n PLL6_OUT1p PLL6_OUT0n PLL6_OUT0p CLK7n CLK6n nCE nCEO PGM0 nIO_PULLUP VCCSEL PORSEL INIT_DONE nRS RUnLU PGM1 RDN7 RUP7 Pin List (EP1SGX10D) F672 DQS for x32 R15 V16 Y15 W16 R13 U14 V17 AD14 AC14 AF14 AE14 W15 U13 T13 V14 AF13 AE13 AB14 AA14 AE12 AD12 AB13 AA13 AD13 AC13 R11 V13 T11 W12 V12 U12 Y12 AA12 AB12 AC12 P9 T9 Y11 AA11 R10 T10 R9 U10 U11 U9 W11 U8 V8 Y10 V11 Page 4 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B15 B15 B15 B15 B15 B15 B15 B15 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF1B7 IO IO IO IO IO IO IO IO IO IO IO IO GXB_RX11n GXB_RX11p GXB_TX11n GXB_TX11p GXB_RX10n GXB_RX10p GXB_TX10n GXB_TX10p DQ3B7 DQ3B6 DQ3B5 DEV_CLRn DQ3B4 DQ3B3 DQS3B DQ3B2 DQ3B1 DQ3B0 FCLK5 FCLK4 DQ2B7 DQ2B6 DQ2B5 DQ2B4 DQ2B3 DQS2B DQ2B2 DQ1B7 DQ2B1 DQ1B6 DQ2B0 DQ1B5 DQ1B4 DQ1B3 DQS1B DQ1B2 DQ1B1 DQ1B0 Copyright © 2006 Altera Corp. DQ0B7 DQ0B6 DQ0B5 DQ0B4 DQ0B3 DQS0B DQ0B2 DQ0B1 DQ0B0 Pin List (EP1SGX10D) Configuration Function F672 DQS for x32 AF8 AE11 AE10 W10 AF10 AE8 AE9 AF9 AD9 AD8 W9 Y9 AC9 Y7 AA7 AC8 AB9 AB7 Y8 AF5 AA8 AD7 AB8 AF7 AE7 AD6 AE6 AF6 AC7 AC6 V10 W7 V7 AF4 AE5 AC4 AD4 AD5 AE4 AE2 AE3 AC5 W8 AC2 AC1 AA5 AA4 AA2 AA1 W5 W4 DQ0B31 DQ0B30 DQ0B29 DQ0B28 DQ0B27 DQ0B26 DQ0B25 DQ0B24 DQ0B23 DQ0B22 DQ0B21 DQ0B20 DQ0B19 DQS0B DQ0B18 DQ0B15 DQ0B17 DQ0B14 DQ0B16 DQ0B13 DQ0B12 DQ0B11 DQ0B10 DQ0B9 DQ0B8 DQ0B7 DQ0B6 DQ0B5 DQ0B4 DQ0B3 DQ0B2 DQ0B1 DQ0B0 Page 5 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VCCA_B15 REFCLKB15n REFCLKB15p VCCG_B15 GND RREFB15 GXB_RX8n GXB_RX8p GXB_TX8n GXB_TX8p GXB_RX9n GXB_RX9p GXB_TX9n GXB_TX9p GXB_RX7n GXB_RX7p GXB_TX7n GXB_TX7p GXB_RX6n GXB_RX6p GXB_TX6n GXB_TX6p VCCA_B14 REFCLKB14n REFCLKB14p VCCG_B14 GND RREFB14 GXB_RX4n GXB_RX4p GXB_TX4n GXB_TX4p GXB_RX5n GXB_RX5p GXB_TX5n GXB_TX5p IO IO IO IO IO IO IO IO IO IO IO IO VREF0B4 IO IO B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 Copyright © 2006 Altera Corp. Optionn Function(s) DQ0T0 DQ0T1 DQ0T2 DQS0T DQ0T3 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ1T0 DQ1T1 Pin List (EP1SGX10D) Configuration Function F672 DQS for x32 P8 W2 W1 P7 P6 U7 U2 U1 U5 U4 R2 R1 R5 R4 N2 N1 N5 N4 L2 L1 L5 L4 N7 J2 J1 N8 N6 K7 G2 G1 J5 J4 E2 E1 G5 G4 G9 B2 C2 C1 C3 B3 D4 E4 B4 C4 H7 H8 K9 E5 C6 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ0T8 DQ0T9 Page 6 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF1B4 IO IO IO IO IO IO TMS TRST TCK IO IO IO TDI TDO IO CLK12p IO CLK13p TEMPDIODEp TEMPDIODEn VCCA_PLL5 GND DQ1T2 DQS1T DQ1T3 DQ1T4 DQ1T5 DQ2T0 DQ1T6 DQ2T1 DQ1T7 DQ2T2 DQS2T DQ2T3 DQ2T4 DQ2T5 DQ2T6 DQ2T7 FCLK6 FCLK7 DQ3T0 DQ3T1 DQ3T2 DQS3T DQ3T3 DQ3T4 DQ3T5 DEV_OE DQ3T6 DQ3T7 Copyright © 2006 Altera Corp. Configuration Function RUP4 RDN4 nWS DATA0 DATA1 DATA2 TMS TRST TCK DATA3 TDI TDO CLK12n CLK13n Pin List (EP1SGX10D) F672 DQS for x32 B5 C5 D5 A5 A4 B6 E6 E8 D6 F7 C7 A6 B7 D7 E7 A7 G10 G7 D8 A8 C9 B8 C8 A10 A9 J7 B9 D9 K10 G11 G8 H11 H10 F8 K8 F9 H9 J8 J9 E10 E11 F10 F11 D12 E12 F12 G12 J11 J10 H13 DQ0T10 DQ0T11 DQ0T12 DQ0T13 DQ0T16 DQ0T14 DQ0T17 DQ0T15 DQ0T18 DQS0T DQ0T19 DQ0T20 DQ0T21 DQ0T22 DQ0T23 DQ0T24 DQ0T25 DQ0T26 DQ0T27 DQ0T28 DQ0T29 DQ0T30 DQ0T31 Page 7 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number B9 B10 B9 B9 B9 B9 B9 B9 B10 B10 B10 B10 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF Bank VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 Pin Name/Function GNDA_PLL5 VCCG_PLL5 GNDG_PLL5 VCC_PLL5_OUTA VCC_PLL5_OUTB IO IO IO IO IO IO IO IO IO IO nSTATUS nCONFIG DCLK CONF_DONE CLK14p IO CLK15p IO VREF0B3 IO IO IO IO IO IO IO IO IO IO IO IO GND GND IO IO IO IO IO IO IO IO IO IO IO IO IO Copyright © 2006 Altera Corp. Optionn Function(s) Configuration Function PLL5_OUT0p PLL5_OUT0n PLL5_OUT1p PLL5_OUT1n PLL5_FBp PLL5_FBn PLL5_OUT2p PLL5_OUT2n PLL5_OUT3p PLL5_OUT3n nSTATUS nCONFIG DCLK CONF_DONE CLK14n CLK15n DATA4 DATA5 DATA6 RUP3 RDN3 DQ6T0 DQ6T1 DATA7 DQ6T2 DQS6T DQ6T3 CLKUSR FCLK0 FCLK1 DQ6T4 DQ6T5 DQ6T6 DQ6T7 DQ7T0 DQ7T1 DQ7T2 DQS7T DQ7T3 DQ7T4 DQ7T5 Pin List (EP1SGX10D) F672 DQS for x32 G13 H12 J12 J13 K12 D13 C13 C12 B12 F13 E13 F14 E14 B13 A13 K14 L14 K13 K15 B14 A14 D14 C14 J16 L15 M15 K16 L16 M16 E16 B15 G17 E15 D15 C16 F17 H17 F18 G18 D16 F15 C15 B16 E17 B17 A17 C17 D17 C18 B18 DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T4 DQ1T5 DQ1T6 DQ1T7 DQ1T8 DQ1T9 DQ1T10 DQS1T DQ1T11 DQ1T12 DQ1T13 Page 8 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 IO IO IO IO IO IO IO IO IO IO IO VREF1B3 IO IO IO IO IO IO IO IO IO IO IO IO GXB_GND GND VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCP_B14 VCCP_B14 VCCP_B15 VCCP_B15 VCCR_B14 VCCR_B14 VCCR_B15 DQ8T0 DQ7T6 DQ8T1 DQ7T7 DQ8T2 DQS8T DQ8T3 DQ8T4 DQ8T5 DQ8T6 DQ8T7 Copyright © 2006 Altera Corp. DQ9T0 DQ9T1 DQ9T2 DQS9T DQ9T3 DQ9T4 DQ9T5 DQ9T6 DQ9T7 Configuration Function F672 DQS for x32 C19 D18 D19 E18 A18 B19 B20 A20 A19 C20 D20 J17 G16 H18 A21 B21 C21 B22 C22 A22 B23 A23 B24 H16 DQ1T16 DQ1T14 DQ1T17 DQ1T15 DQ1T18 DQ1T19 DQ1T20 DQ1T21 DQ1T22 DQ1T23 DQ1T24 DQ1T25 DQ1T26 DQ1T27 DQ1T28 DQ1T29 DQ1T30 DQ1T31 C26 M26 N18 AD26 P18 R26 AF15 AF24 T14 AF3 AF12 T12 A3 A12 L12 A15 A24 L13 L8 M8 R8 T8 L7 M7 R7 Pin List (EP1SGX10D) Page 9 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) VCCR_B15 VCCT_B14 VCCT_B14 VCCT_B15 VCCT_B15 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND Copyright © 2006 Altera Corp. Configuration Function F672 DQS for x32 T7 L6 M6 R6 T6 AB6 N9 Y6 F6 N11 H6 N13 L11 P12 L9 N16 M10 P16 K6 N15 M9 P14 L10 P10 M14 V6 AA3 D2 H4 M3 T2 Y1 AB2 F1 J3 M5 T4 Y3 AB4 F3 K2 P1 U3 Y5 AD1 F5 K4 P3 V2 D1 H1 Pin List (EP1SGX10D) Page 10 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Copyright © 2006 Altera Corp. Configuration Function F672 DQS for x32 L3 P5 V4 H3 M2 T1 W3 AB1 E3 H5 M4 T3 Y2 AB3 F2 K1 N3 T5 Y4 AB5 F4 K3 P2 V1 AD2 G3 K5 P4 V3 H2 M1 R3 V5 A2 AF2 L26 P13 AA6 B1 N10 R14 A16 AF16 M12 P17 AD3 D3 N14 U6 A11 AF11 Pin List (EP1SGX10D) Page 11 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Copyright © 2006 Altera Corp. Configuration Function F672 DQS for x32 M11 P15 AC3 B26 N12 T26 A25 AF25 M13 R12 AE1 G6 N17 W6 AE26 J6 P11 AA9 AA25 AB22 AC20 AD11 B11 D21 E21 F21 G22 J18 Y13 AA15 AB10 AB24 AC22 AD24 C10 D23 E23 F23 G24 T17 Y19 AA20 AB15 AB26 AC24 AE23 C23 D25 E25 G14 H15 Pin List (EP1SGX10D) Page 12 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Copyright © 2006 Altera Corp. Configuration Function F672 DQS for x32 V15 Y21 AA22 AB20 AC11 AC26 AE25 C25 E9 F16 G19 H22 W14 AA10 AA26 AB23 AC21 AD23 B25 D22 E22 F22 G23 K11 Y14 AA19 AB11 AB25 AC23 AD25 C11 D24 E24 F24 H14 V9 Y20 AA21 AB19 AC10 AC25 AE24 C24 D26 E26 G15 H21 W13 Y22 AA23 AB21 Pin List (EP1SGX10D) Page 13 of 25 Pin Information For The Stratix™ GX EP1SGX10D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optionn Function(s) NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Copyright © 2006 Altera Corp. Configuration Function F672 DQS for x32 AC19 AD10 B10 D10 E19 F19 G20 J14 W21 AA24 D11 E20 F20 G21 J15 W22 Pin List (EP1SGX10D) Page 14 of 25 Pin Definitions For The Stratix™ GX EP1SGX Device, ver 1.7 Pin Name Pin Type (1st, 2nd, & 3rd Function) VREF[1..4]B[1..4,7,8] Input VCCIO[1..4]B[1..4,7,8] Power VCCINT Power VCC_PLL5_OUTA Power VCC_PLL5_OUTB Power VCC_PLL6_OUTA Power VCC_PLL6_OUTB Power VCCA_PLL[1,2,5,..,8,11,12] Power GNDA_PLL[1,2,5,..,8,11,12] Ground VCCG_PLL[1,2,5,..,8,11,12] Power GNDG_PLL[1,2,5,..,8,11,12] Ground GXB_GND Ground GND NC Ground No Connect nSTATUS Bidirectional (opendrain) Bidirectional (opendrain) nCONFIG Input DCLK Input nIO_PULLUP Input PORSEL Input VCCSEL Input nCE Input nCEO Output TMS TDI TCK TDO Input Input Input Output TRST MSEL[2..0] Input Input CONF_DONE Copyright © 2006 Altera Corp. Pin Description Supply and Reference Pins Input reference voltage for banks. If a bank is used for a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If VREF pins are not used, they should be connected to Gnd. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, 3.3-V PCI, and 3.3-V PCI-X I/O standards. These power pins are supplied with a 1.5V source. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, LVPECL, 3.3-V PCML, HyperTransport™ technology, differential HSTL, GTL, GTL+, HSTL, SSTL, CTT, and 3.3-V AGP I/O standards. External clock output buffer power for PLL5 clock outputs PLL5_OUT[1..0]. The designer must connect this pin to the VCCIO of bank 9. External clock output buffer power for PLL5 clock outputs PLL5_OUT[3..2]. The designer must connect this pin to the VCCIO of bank 10. External clock output buffer power for PLL6 clock outputs PLL6_OUT[1..0]. The designer must connect this pin to the VCCIO of bank 11. External clock output buffer power for PLL6 clock outputs PLL6_OUT[3..2]. The designer must connect this pin to the VCCIO of bank 12. Analog power for PLLs[1,2,5,..,8,11,12]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1,2,5,..,8,11,12]. The designer can connect this pin to the GND plane on the board. Guard ring power for PLLs[1,2,5,..,8,11,12]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Guard ring ground for PLLs[1,2,5,..,8,11,12]. The designer can connect this pin to the GND plane on the board. Transceiver Power Ground. These ground pins need to be connected to a ground island plane isolated from noisy digital ground. These ground pins need to be connected to digital ground. The digital ground is used for VCCINT and VCCIO return current. These pins should be left unconnected. Dedicated & Configuration/JTAG Pins This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. Clock input used to clock configuration data from an external source into the Stratix device. This is a dedicated pin used for configuration. IF nIO_PULLUP is driven high during configuration, the weak pull-ups on all user I/O pins are disabled. If driven low, the weak pull-ups are enabled during configuration. nIO_PULLUP can be pulled up to either 1.5, 1.8, 2.5, or 3.3 V. Dedicated input pin used to select POR delay times of 2 ms or 100 ms during powerup. When PORSEL is connected to ground, the POR time is 100 ms. When PORSEL is connected to 3.3 V, the POR time is 2 ms. VCCSEL is used to select which input buffer is used on all configuration pins. VCCSEL will control whether the 3.3-/2.5-V input buffer or the 1.8-/1.5-V input buffer is used. A "0" means 3.3/2.5 V and a "1" means 1.8/1.5 V. At powerup, VCCSEL accepts 3.3 Active-low chip enables. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device’s nCE pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. Active low input, used to asynchronously reset the JTAG boundary scan circuit. Dedicated mode select control pins that set the configuration mode for the device. Pin Definitions (EP1SGX) Page 15 of 25 Pin Definitions For The Stratix™ GX EP1SGX Device, ver 1.7 Pin Name Pin Type (1st, 2nd, & 3rd Function) TEMPDIODEp Input TEMPDIODEn Input Pin Description Pin used in conjunction with the temperature sensing diode (bias-high input) inside the Stratix device. If the temperature sensing diode is not used then connect this pin to GND. Pin used in conjunction with the temperature sensing diode (bias-low input) inside the Stratix device. If the temperature sensing diode is not used then connect this pin to GND. PLL_ENA Input Clock and PLL Pins Dedicated input pin that drives the optional pllena port of all or a set of PLLs. If a PLL uses the pllena port, drive the PLL_ENA pin low to reset all PLLs including the counters to their default state. If VCCSEL = 0, then you must drive the PLL_ENA with a 3.3/2.5 V signal to enable the PLLs. If VCCSEL = 1, connect PLL_ENA to 1.8/1.5 V to enable the PLLs. FCLK[7..0] CLK[15..12]p CLK[15..12]n CLK[7..0]p CLK[7, 6, 5, 4, 3, 1]n CLK[2, 0]n Bidirectional Input I/O, Input Input I/O, Input Input PLL6_OUT[3..0]p I/O, Output PLL6_OUT[3..0]n I/O, Output PLL5_OUT[3..0]p I/O, Output PLL5_OUT[3..0]n I/O, Output DIFFIO_RX[44..0]p Input High speed source synchronous differential I/O receiver channels 0 to 44. Pins with an p suffix carry the positive signal for the differential channel If not used, these pins are dedicated input pins. DIFFIO_RX[44..0]n Input This pin is the complementary signal of the differential inputs. If not used for the differential pair, these pins are dedicated input pins. Pins with an n suffix carry the negative signal for the differential channel. DIFFIO_TX[44..0]p I/O, Output Dual-purpose source synchronous high speed differential I/O transmitter channels 0 to 44. Pins with an p suffix carry the positive signal for the differential channel. If not used, these pins are regular I/O pins. DIFFIO_TX[44..0]n I/O, Output PLL5_FBp PLL5_FBn PLL6_FBp PLL6_FBn I/O, Input I/O, Input I/O, Input I/O, Input INIT_DONE I/O, Output DATA[7..0] nRS I/O, Input I/O, Input DEV_CLRn I/O, Input DEV_OE I/O, Input CLKUSR I/O, Input RDYnBSY I/O, Output Copyright © 2006 Altera Corp. Dedicated fast regional clock pins. FCLK pins can also be used as input, output, or bidirectional pins. Dedicated global clock inputs 12 to 15. Negative terminal input for differential global clock input. May also be used as regular I/O Dedicated global clock inputs 0 to 7. Negative terminal input for differential global clock input. Or may be used as a regular I/O pin. Dedicated negative terminal input for differential global clock input. External clock outputs [3..0] from enhanced PLL 6. These pins can be differential (four output pin pairs) or single ended (eight clock outputs from PLL6). May also be used as regular I/O Negative terminal for external clock outputs [3..0] from PLL6. If the clock outputs are single ended, then each pair of pins (i.e., PLL6_OUT0p and PLL6_OUT0n are considered one pair) can be either in phase or 180 degrees out of phase. May also be used as regular I/O External clock outputs [3..0] from enhanced PLL 5. These pins can be differential (four output pin pairs) or single ended (eight clock outputs from PLL5). May also be used as regular I/O Negative terminal for external clock outputs [3..0] from PLL 5. If the clock outputs are single ended, then each pair of pins (i.e., PLL5_OUT0p and PLL5_OUT0n are considered one pair) can be either in phase or 180 degrees out of phase. May also be used as regular I/O Optional/Dual-Purpose Pins This pin is the complementary signal of the differential inputs and outputs. If not used for the differential pair, these pins are regular I/O pins. Pins with an n suffix carry the negative signal for the differential channel. External feedback input pin for PLL5. This pin can be used as a user I/O pin if external feedback mode is not used. Negative terminal input for external feedback input PLL5_FBp External feedback input pin for PLL6 Negative terminal p pinputpfor external feedback input PLL6_FBp p _ the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after configuration. Dual-purpose configuration input data pins. These pins can be used for configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration. Read strobe input pin. This pin can be used as a user I/O pin after configuration. Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the users design. Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Ready not busy output. A high output indicates that the target device is ready to accept another data byte. A low output indicates that the target device is not ready to receive another data byte. This pin can be used as a user I/O pin after configuration Pin Definitions (EP1SGX) Page 16 of 25 Pin Definitions For The Stratix™ GX EP1SGX Device, ver 1.7 Pin Name Pin Type (1st, 2nd, & 3rd Function) nCS,CS I/O, Input nWS I/O, Input PGM[2..0] I/O, Output RUP[8..7],RUP[4..1] I/O, Input RDN[8..7],RDN[4..1] I/O, Input RUnLU I/O, Input VCCP_B[17..13] VCCR_B[17..13] VCCT_B[17..13] VCCG_B[17..13] VCCA_B[17..13] VCC VCC VCC VCC VCC GXB_RX[19..0]n I, Input GXB_RX[19..0]p I, Input GXB_TX[19..0]n O,Output GXB_TX[19..0]p O,Output REFCLKB[17..13]n I, Input REFCLKB[17..13]p I, Input High speed differential I/O reference clock negative. Connect any of these unused pins to ground through a 10K ohm resistor. High speed differential I/O reference clock positive. Connect any of these unused pins to 1.5V through a 10K ohm resistor. RREFB[17..13] I, Input Reference resistor for Gx side banks. Should be connected to a 2K of a tolerance of 1% to ground. In the PCB layout the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals. RREFB[15,14]A I, Input Reference resistor for Gx side banks. Should be connected to a 2K of a tolerance of 1% to ground. In the PCB layout the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals. Copyright © 2006 Altera Corp. Pin Description These are chip-select inputs that enable the Stratix device in the passive parallel asynchronous configuration mode. Drive nCS low and CS high to target a device for configuration. If a design requires an active high enable, use the CS pin and drive the nCS pin low. Active-low write strobe input to latch a byte of data on the DATA pins. This pin can be used as a user I/O pin after configuration. These output pins control one of eight pages in the EPC16 configuration device when using remote update or local update configuration modes. When not using remote update or local update configuration modes, these pins are user I/O pins. Reference pins for banks 8,7,4,3,2,1 The external precision resistors R UP must be connected to the designated RUP pin on that I/O bank. If not required, these pins are regular I/O pins. Reference pins for banks 8,7,4,3,2,1. The external precision resistors R DN must be connected to the designated RDN pin on that I/O bank. If not required, these pins are regular I/O pins. Pin Definitions Input control pin to select remote update or local update modes. If MSEL2 = 1, this is a input control pin to select remote update (RUnLU =1) or local update (RUnLU =0) modes. If MSEL2 = 0, the RUnLU pin is a user I/ O pin. GX ( I/O banks 13 to 17 ) Pins GX bank [17..13] digital power. This power is connected to 1.5V. GX bank [17..13] receiver power. This power is connected to 1.5V. GX bank [17..13] transmitter power. This power is connected to 1.5V. GX bank[17..13] guard ring power. This power is connected to 1.5V. GX bank [17..13] analog power. This power is connected to 3.3V. High speed differential I/O receiver channels negative. Connect any of these unused pins to ground through a 10K ohm resistor. High speed differential I/O receiver channels positive. Connect any of these unused pins to 1.5V through a 10K ohm resistor. High speed differential I/O transmitter channels negative. Connect any of these unused pins to ground through a 10K ohm resistor. High speed differential I/O transmitter channels positive. Connect any of these unused pins to 1.5V through a 10K ohm resistor. Pin Definitions (EP1SGX) Page 17 of 25 PLL & Bank Diagram For The Stratix GX™ EP1S10 Device, ver 1.7 Notes: 1.This is a top view of the silicon die. 2.This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and the Quartus II for exact locations. PLL Numbering, PowerBank & Vref Arrangement DQST5 DQST3 DQST2 DQST1 VREF4B4 VREF3B4 DQST4 VREF2B4 VREF1B4 DQST0 VREF0B4 B4 Q1D B9 B10 B2 VREF3B2 VREF2B2 VREF1B2 VREF0B2 B3 PLL5 B14 DQST6 VREF1B3 VREF0B3 Q1T DQST7 Q1R DQST8 VREF3B3 VREF2B3 Q1A DQST9 VREF4B3 Device Name PLL1 B8 VREF0B8 DQSB9 Copyright © 2006 Altera Corp. VREF1B8 VREF2B8 DQSB8 DQSB7 DQSB6 DQSB5 PLL6 14 & 15 B15 Q2T Q2R 15 EP1SGX10D B7 B11 B12 VERF3B8 VREF4B8 Q2A Q2D B1 VREF3B1 VREF2B1 VREF1B1 VREF0B1 PLL2 GX Bank # Utilized EP1SGX10C VREF0B7 VREF1B7 DQSB4 DQSB3 VREF2B7 VREF3B7 DQSB2 DQSB1 VREF4B7 DQSB0 PLL & Bank Diagram (EP1SGX10) Page 18 of 25 Power Flip Chip Global Power on Die Pkg route Left, Top, and Bottom Power and Ground are the same as Stratix Devices EPLL clock output power VCC_CLKOUT[0:7] isolated EPLL clock output power EPLL clock output ground VSSN VSSN plane EPLL clock output ground VCCN[4,7] VCCN[4,7]plane EPLL clock output ground VSSN VSSN plane PLL analog power VCCA[1:2, 5:8, 11:12] isolated PLL analog ground VSSA[1:2, 5:8, 11:12] isolated PLL digital power VCC[1:2, 5:8, 11:12] VCC plane PLL digital ground VSS[1:2, 5:8, 11:12] VSS plane PLL guard ring power VCCG[1:2, 5:8, 11:12] isolated PLL guard ring ground VSSG[1:2, 5:8, 11:12] isolated Noisy power VCCN[1:4,7:8] VCCN[1:4,7:8] plane Noisy ground VSSN VSS plane Quiet power VCC VCC plane Quiet ground VSS VSS plane Power Description Notes VSSN VCCA[3:4,9:10] VSSA[3:4,9:10] It is shorted to VCC in the package of the flip chip. It is shorted to VSS in the package of the flip chip. HSSI Global Power: Power and Ground are grouped in QUAD. Quad Order is 0,1,4,2,3 HSSI digital power (1.5 v ) HSSI RX power (1.5 v ) HSSI TX power (1.5 v ) HSSI CMU power (1.5 v ) HSSI Analog power (3.3 v ) HSSI VCCG (1.5 v ) HSSI substrate ground HSSI digital ground HSSI TX/RX ground HSSI CMU ground Marketing VCCP0 VCCP1 VCCP4 VCCP2 VCCP3 VCCR[0:3] VCCR[4:7] VCCR[16:19] VCCR[8:11] VCCR[12:15] VCCT[0:3] VCCT[4:7] VCCT[16:19] VCCT[8:11] VCCT[12:15] VCCM0 VCCM1 VCCM4 VCCM2 VCCM3 VCCAQ0 VCCAQ1 VCCAQ4 VCCAQ2 VCCAQ3 VCCGQ0 VCCGQ1 VCCGQ4 VCCGQ2 VCCGQ3 VSSASUB0 VSSASUB1 VSSASUB4 VSSASUB2 VSSASUB3 DGND DGND DGND DGND DGND HGND HGND HGND HGND HGND CGND Copyright © 2006 Altera Corp. Each Quad has 5 bumps connected to 2 isolated digital power balls Each Quad has 4 bumps connected to 1 isolated RX power ball Each Quad has 4 bumps connected to 1 isolated TX power ball VCCM# bump shares power with VCCT# of the same QUAD There are no pin associated with this pin name since they share the same bump power with VCCT# of the same Quad Each Quad has its own analog power. One bump--> one ball Provides power to Tx PLL and some biasing circuit Each Quad has its own VCCG power. One bump--> one ball Guard ring for TX PLL should be used to isolate noise to TX pll Each Quad has its own substrate ground. One bump--> one ball All digital grounds are connected to the HSSI ground plane at package level All TX/RX grounds are connected to the HSSI ground plane at package level All CMU grounds are connected to the HSSI ground plane at package level Global Power Page 19 of 25 CGND CGND CGND CGND Global Power on Die is the signal name that the schematics and layout use for this power or ground Pkg Route: 1) plane = indicates the power plane the bump/pad routes to in the pkg; 2) isolated = indicates the bump/pad is routed to the pkg ball without connect to any other pkg route or plane. Plane: A plane has multiple bump/pads connected to it which in turn connect to multiple balls. It does not necessarily imply a complete sheet of conductor; it may look be more like Swiss cheese. Net: Multiple bumps/balls can share the same net bus Copyright © 2006 Altera Corp. Global Power Page 20 of 25 Non-Migratable IO Pins Non-Migratable IO Pins 1020FBGA ( EP1SGX40 <--> EP1SGX25 ) 672FBGA ( EP1SGX25 <-->EP1SGX10) AA23 AB23 AC23 AD23 AG25 AG26 AH27 AH28 AH29 AH30 AJ29 AJ30 D29 D30 E29 E30 F27 F28 F29 F30 J23 K23 L23 M23 Copyright © 2006 Altera Corp. Non-Migratable IO Pins Page 21 of 25 Device Part Numbers Name EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G Number of Fast PLL 2 2 2 2 2 4 4 Device Pin Count 672 672 672 672 / 1020 1020 1020 1020 # of Receiver Chs 22 22 39 39 39 45 45 # of Transmitter Chs 22 22 39 39 39 45 45 Speed (Mbps ) 1000 1000 1000 1000 1000 1000 1000 Receiver channels operate at 1,000 Mbps with DPA. Without DPA, the receiver channels operate at 840 Mpbs Device Part Numbers Name EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G I/O Count (1) 672-Pin FineLine BGA 1,020 Pin FineLine BGA 330 330 426 426 542 542 548 548 Note 1 : The total number of I/O pins for each package described above include dedicated clock pins, and dedicated fast I/O pins. However it does not include High-Speed or the Clock Referance pins for High Speed I/O. Copyright © 2006 Altera Corp. Device Names_Device IO Count Page 22 of 25 What Added voltage value to power pins Added information to the VCCM , they share the same bump with VCCT. Added Non-Migrateble pins Added I/O pin count Added info regarding RREF pin Sent to Product Marketing Connected NC pins to RREF pins( NOTE 1) Connected NC pins to VCCx_Bxx ( NOTE 1 ) Connected unused NC pins on the HSSI side to GND. These pins are listed as NC/GND in this document and are listed as GND* in Quartus II software ( NOTE 1 and 2 ) Added pin status change information from rev 1.3 to rev 1.4. Pin changes are for EP1SGX10C, EP1SGX25C,EP1SGX25D,EP1SGX40 D only. Added section for 1SGX25C missing from 1.4. Changed DATA0 to be an IO after configuration. Note 1: Modifications in Rev 1.4 are recommendations for noise reduction. Do NOT make modifications to the board already laid out based on pin table Rev 1.3 . It is recommended that the pin table Rev 1.4 be implemented for new designs or re-designed boards only. NOTE 2 : GND/NC is shown as GND* in Quartus II software Add HSSI_GND to the pin list Wrong Bank was referenced in the GX25C device Update non-migration table change all references of GX_TX, GX_RX to GXB_TX, GXB_RX Change all references of HSSI_GND to GXB_GND Change pin description data[7..1] to include data0 Changed false references of RUP/RDN to different banks Updated pin description so only CLK0n and CLK2n were dedicated clock inputs. While the rest were also I/Os Updated pin description of VCCINT to expliciltly say it needs a 1.5V supply Updated the pin description for PLLENA Update pin description to explain what to do with unused pins for the transceivers and REFCLKB. Definition for RUnLU needed to be updated to correctly indicate poarity of signal for remote and local update. Also the pin definitions for GND and NC were added to the pin definition. Updated pin descriptions for items 74 though 78 of the pin descriptions. These describe the VCC voltages and the pin description was updated with more specific information as to what voltage to connect them to. Item 42 in the pin desription was updated to specify that the CLK[15..12]p pins are dedicated input clock pins Item 43 in the pin desription was updated to specify that the CLK[15..12]n pins are either clock inputs or regular I/O Item 47 through 50 which describe the PLL_OUT pins are updated to specify that they can be used as either I/O or Output Comment rev 1.2 Date 10/15/2002 rev 1.3 rev 1.3 rev 1.3 rev 1.3 rev 1.3 rev 1.4 12/17/2002 12/17/2002 12/17/200 1/10/2003 2/19/2003 5/30/2003 rev 1.4 5/30/2003 rev 1.4 5/30/2003 rev 1.4 5/30/2003 rev 1.42 7/30/2003 rev 1.43 rev 1.44 rev 1.45 9/10/2003 9/11/2003 9/17/2003 rev 1.46 9/19/2003 rev 1.47 10/21/2003 rev 1.48 12/11/2003 Items 80 through 83 was updated to describe the termination of the unused pins for GX_RX and GX_TX. Copyright © 2006 Altera Corp. Revision Notes Page 23 of 25 Items 85 and 86 was updated to describe the termination of the unused pins for REFCLK. Updated description for unused VREF pins so the it reads the same description as Quartus II Updated description for RREFB. Layout guidelines were added. Updated RREFB pins to address new Quartus change (please refer to the "RREFB pin change in 1.6" worksheet) Deleted DQS for x16 column in EP1SGX10C & EP1SGX10D pin-list Created pin definition for RREFB[15,14]A Added CRC_ERROR pins in pin list Copyright © 2006 Altera Corp. Revision Notes rev 1.49 rev 1.50 3/17/2004 6/2/2004 rev 1.60 4/27/2005 rev 1.70 2/22/2006 Page 24 of 25 RREFB pin change in 1.6 Device EP1SGX10CF672 Status in Rev 1.5 RREFB15 RREFB15 Pin name Status in Rev 1.6 U7 RREFB15A K7 RREFB15 EP1SGX25CF672 RREFB15 RREFB15 U7 K7 RREFB15 RREFB15A EP1SGX25DF1020 RREFB14 RREFB14 RREFB15 RREFB15 L7 J7 AC7 T8 RREFB14 RREFB14A RREFB15A RREFB15 EP1SGX40DF1020 RREFB14 RREFB15 RREFB15 RREFB15 RREFB14 J7 AC7 T7 T8 L7 RREFB13 RREFB16 GND/NC RREFB15 RREFB14 Copyright © 2006 Altera Corp. RREFB pin change in 1.6 Page 25 of 25