ACT8894 - Active-Semi

ACT8894
Rev 2, 06-Sep-13
Advanced PMU for Samsung S3C2416/S3C2450
FEATURES
GENERAL DESCRIPTION
• Optimized for Samsung S3C2416/S3C2450
The ACT8894 is a complete, cost effective, highlyefficient ActivePMUTM power management solution,
optimized for the unique power, voltagesequencing, and control requirements of the
Samsung S3C2416/S3C2450 processors.
Processors
•
•
•
•
•
•
Three Step-Down DC/DC Converters
Four Low-Dropout Linear Regulators
I2CTM Serial Interface
Advanced Enable/Disable Sequencing Controller
Minimal External Components
Tiny 4×4mm TQFN44-32 Package
− 0.75mm Package Height
− Pb-Free and RoHS Compliant
This device features three step-down DC/DC
converters and four low-noise, low-dropout linear
regulators.
The three DC/DC converters utilize a highefficiency, fixed-frequency (2MHz), current-mode
PWM control architecture that requires a minimum
number of external components. Two DC/DCs are
capable of supplying up to 900mA of output current,
while the third supports up to 700mA. All four lowdropout linear regulators are high-performance,
low-noise regulators that supply up to 150mA,
150mA, 250mA, and 250mA, respectively.
The ACT8894 is available in a compact, Pb-Free
and RoHS-compliant TQFN44-32 package.
TYPICAL APPLICATION DIAGRAM
Innovative PowerTM
-1Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
TABLE OF CONTENTS
General Information ..................................................................................................................................... p. 01
Functional Block Diagram ............................................................................................................................ p. 03
Ordering Information .................................................................................................................................... p. 04
Pin Configuration ......................................................................................................................................... p. 04
Pin Descriptions ........................................................................................................................................... p. 05
Absolute Maximum Ratings ......................................................................................................................... p. 07
I2C Interface Electrical Characteristics ........................................................................................................ p. 08
Global Register Map .................................................................................................................................... p. 09
Register and Bit Descriptions ...................................................................................................................... p. 10
System Control Electrical Characteristics.................................................................................................... p. 13
Step-Down DC/DC Electrical Characteristics .............................................................................................. p. 14
Low-Noise LDO Electrical Characteristics ................................................................................................... p. 15
Typical Performance Characteristics ........................................................................................................... p. 16
System control information .......................................................................................................................... p. 21
Interfacing with the Samsung S3C2416/S3C2450........................................................................... p. 21
Control Signals ................................................................................................................................. p. 22
Push-Button Control ......................................................................................................................... p. 23
Control Sequences ........................................................................................................................... p. 23
Functional Description ................................................................................................................................. p. 25
I2C Interface ..................................................................................................................................... p. 25
Voltage Monitor and Interrupt........................................................................................................... p. 25
Thermal Shutdown ........................................................................................................................... p. 25
Step-Down DC/DC Regulators .................................................................................................................... p. 26
General Description.......................................................................................................................... p. 26
100% Duty Cycle Operation ............................................................................................................. p. 26
Synchronous Rectification ................................................................................................................ p. 26
Soft-Start .......................................................................................................................................... p. 26
Compensation .................................................................................................................................. p. 26
Configuration Options....................................................................................................................... p. 26
OK[ ] and Output Fault Interrupt ....................................................................................................... p. 27
PCB Layout Considerations ............................................................................................................. p. 27
Low-Noise, Low-Dropout Linear Regulators................................................................................................ p. 28
General Description.......................................................................................................................... p. 28
Output Current Limit ......................................................................................................................... p. 28
Compensation .................................................................................................................................. p. 28
Configuration Options....................................................................................................................... p. 28
OK[ ] and Output Fault Interrupt ....................................................................................................... p. 28
PCB Layout Considerations ............................................................................................................. p. 28
TQFN44-32 Package Outline and Dimensions ........................................................................................... p. 30
Innovative PowerTM
-2Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
FUNCTIONAL BLOCK DIAGRAM
VP1
To Battery
ACT8894
SW1
OUT1
VDDREF
OUT1
nPBIN
PUSH BUTTON
GP1
OUT1
VP2
nRSTO
To Battery
SW2
OUT2
OUT2
OUT1
GP2
nPBSTAT
VP3
OUT1
To Battery
SW3
nIRQ
OUT3
OUT3
System
Control
GP3
PWRHLD
INL45
PWREN
REG4
LDO
VSEL
SCL
SDA
Serial
Interface
REG5
LDO
OUT4
OUT4
OUT5
OUT5
INL67
VDDREF
To Battery
REFBP
Reference
GA
REG6
LDO
REG7
LDO
To Battery
To Battery
OUT6
OUT6
OUT7
OUT7
EP
Innovative PowerTM
-3Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
ORDERING INFORMATION
PART NUMBER VOUT1/VSTBY1 VOUT2/VSTBY2 VOUT3/VSTBY3 VOUT4 VOUT5 VOUT6 VOUT7 PACKAGE PINS
ACT8894Q4I133-T 3.3V/3.3V
1.8V/1.8V
1.3V/1.3V 1.2V 1.2V 1.2V 3.3V TQFN44-32 32
TEMPERATURE
RANGE
-40°C to +85°C
: All Active-Semi components are RoHS Compliant and with Pb-free plating unless otherwise specified.
: Standard product options are listed in this table. Contact factory for custom options, minimum order quantity is 12,000 units.
: To select VSTBYx as the output regulation voltage for REGx, drive VSEL to a logic high. VSTBYx can be set by software via I2C
interface. Refer to appropriate sections of this datasheet for VSTBYx setting.
PIN CONFIGURATION
GP1
GP2
SW2
VP2
NC2
nIRQ
GP3
SW3
VP3
nRSTO
nPBSTAT
VP1
SW1
PWRHLD
nPBIN
REFBP
TOP VIEW
Thin - QFN (TQFN44-32)
Innovative PowerTM
-4Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
OUT1
2
GA
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1,GP2 and GP3
together at a single point as close to the IC as possible.
3
OUT4
REG4 output. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic
capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
4
OUT5
REG5 output. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic
capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
5
INL45
Power Input for REG4 and REG5. Bypass to GA with a high quality ceramic capacitor placed as
close to the IC as possible.
6
INL67
Power Input for REG6 and REG7. Bypass to GA with a high quality ceramic capacitor placed as
close to the IC as possible.
7
OUT6
REG6 output. Capable of delivering up to 250mA of output current. Connect a 2.2µF ceramic
capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
8
OUT7
REG7 output. Capable of delivering up to 250mA of output current. Connect a 2.2µF ceramic
capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
9
nPBIN
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive nPBIN
directly to GA to assert a manual reset condition. Refer to the nPBIN Multi-Function Input section
for more information. nPBIN is internally pulled up to VVDDREF through a 35kΩ resistor.
10
PWRHLD
Power Hold Input. Refer to the Control Sequences section for more information.
11
nRSTO
Active Low Reset Output. See the nRSTO Output section for more information.
12
nIRQ
13
nPBSTAT
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the
nPBIN is pushed, and is high-Z otherwise. See the nPBSTAT Output section for more information.
14
GP3
Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to
the IC as possible.
15
SW3
Switching Node Output for REG3.
16
VP3
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the
IC as possible.
17
PWREN
18
NC1
19
OUT3
Output Feedback Sense for REG3.
20
VSEL
Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage. See the Output Voltage Programming
section for more information.
21
SCL
Clock Input for I2C Serial Interface.
22
SDA
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
Output Feedback Sense for REG1.
Open-Drain Interrupt Output. nIRQ is asserted any time an unmasked fault condition exists or an
interrupt occurs. See the nIRQ Output section for more information.
Power Enable Input. Refer to the Control Sequences section for more information.
Not Connected. Not internally connected.
Innovative PowerTM
-5Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
PIN DESCRIPTIONS CONT’D
PIN
23
NAME
DESCRIPTION
Power supply for the internal reference. Connect this pin directly to the system power supply.
VDDREF Bypass VDDREF to GA with a 1µF capacitor placed as close to the IC as possible. Star
connection with VP1, VP2 and VP3 preferred.
24
OUT2
25
NC2
Not Connected. Not internally connected.
26
VP2
Power Input for REG2 and System Control. Bypass to GP2 with a high quality ceramic capacitor
placed as close to the IC as possible.
27
SW2
Switching Node Output for REG2.
28
GP2
Power Ground for REG2. Connect GA, GP1,GP2 and GP3 together at a single point as close to
the IC as possible.
29
GP1
Power Ground for REG1. Connect GA, GP1,GP2 and GP3 together at a single point as close to
the IC as possible.
30
SW1
Switching Node Output for REG1.
31
VP1
Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close to
the IC as possible.
32
REFBP
EP
EP
Output Feedback Sense for REG2.
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
Exposed Pad. Must be soldered to ground on PCB.
Innovative PowerTM
-6Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
UNIT
VP1 to GP1, VP2 to GP2, VP3 to GP3
-0.3 to + 6
V
INL, VDDREF to GA
-0.3 to + 6
V
-0.3 to (VVDDREF + 0.3)
V
-0.3 to + 6
V
SW1, OUT1 to GP1
-0.3 to (VVP1 + 0.3)
V
SW2, OUT2 to GP2
-0.3 to (VVP2 + 0.3)
V
SW3, OUT3 to GP3
-0.3 to (VVP3 + 0.3)
V
OUT4, OUT5, OUT6, OUT7 to GA
-0.3 to (VINL + 0.3)
V
-0.3 to + 0.3
V
27.5
°C/W
Operating Ambient Temperature
-40 to 85
°C
Maximum Junction Temperature
125
°C
-65 to 150
°C
300
°C
nPBIN, SCL, SDA, REFBP, PWRHLD, PWREN, VSEL to GA
nRSTO, nIRQ, nPBSTAT to GA
GP1, GP2, GP3 to GA
Junction to Ambient Thermal Resistance (θJA)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
Innovative PowerTM
-7Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
MIN
SCL, SDA Input Low
VVDDREF = 3.1V to 5.5V, TA = -40ºC to 85ºC
SCL, SDA Input High
VVDDREF = 3.1V to 5.5V, TA = -40ºC to 85ºC
TYP
UNIT
0.35
V
1.55
V
SDA Leakage Current
SCL Leakage Current
1
SDA Output Low
MAX
IOL = 5mA
1
µA
2
µA
0.35
V
SCL Clock Period, tSCL
1.5
µs
SDA Data Setup Time, tSU
100
ns
SDA Data Hold Time, tHD
300
ns
Start Setup Time, tST
For Start Condition
100
ns
Stop Setup Time, tSP
For Stop Condition
100
ns
Figure 1:
I2C Compatible Serial Bus Timing
tSCL
SCL
tST
tHD
tSU
tSP
SDA
Start
condition
Innovative PowerTM
-8Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
Stop
condition
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
GLOBAL REGISTER MAP
BITS
OUTPUT ADDRESS
SYS
SYS
0x00
0x01
REG1
0x20
REG1
0x21
REG1
REG2
0x22
0x30
REG2
0x31
REG2
0x32
REG3
REG3
0x40
0x41
REG3
0x42
REG4
0x50
REG4
REG5
0x51
0x54
REG5
0x55
REG6
0x60
REG6
REG7
REG7
0x61
0x64
0x65
D7
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
NAME
DEFAULT
TRST
D6
D5
D4
nSYSMODE nSYSLEVMSK nSYSSTAT
0
1
0
R
Reserved
Reserved
Reserved
Reserved
D3
D2
D1
D0
SYSLEV[3] SYSLEV[2] SYSLEV[1] SYSLEV[0]
0
1
1
1
SCRATCH SCRATCH SCRATCH SCRATCH
0
0
0
0
0
0
0
0
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
0
0
1
0
0
1
0
0
Reserved
Reserved
VSET2[5]
VSET2[4]
VSET2[3]
VSET2[2]
VSET2[1]
VSET2[0]
0
0
1
1
1
0
0
1
ON
PHASE
MODE
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
0
0
0
0
0
0
R
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
0
0
0
1
1
0
0
0
Reserved
Reserved
VSET2[5]
VSET2[4]
VSET2[3]
VSET2[2]
VSET2[1]
VSET2[0]
0
0
0
1
1
0
0
0
ON
PHASE
MODE
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
0
0
0
1
1
0
R
Reserved
Reserved
VSET1[5]
VSET1[4]
VSET1[3]
VSET1[2]
VSET1[1]
VSET1[0]
0
0
0
1
1
0
0
0
Reserved
Reserved
VSET2[5]
VSET2[4]
VSET2[3]
VSET2[2]
VSET2[1]
VSET2[0]
0
0
0
1
1
0
0
0
ON
PWRSTAT
MODE
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
0
0
0
1
1
0
R
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
0
1
1
0
0
0
ON
DIS
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
1
0
0
1
1
0
R
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
0
1
1
0
0
0
ON
DIS
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
1
0
0
0
0
0
R
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
1
1
1
0
0
1
ON
DIS
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
1
0
0
0
0
0
R
Reserved
Reserved
VSET[5]
VSET[4]
VSET[3]
VSET[2]
VSET[1]
VSET[0]
0
0
1
1
1
0
0
1
ON
DIS
LOWIQ
DELAY[2]
DELAY[1]
DELAY[0]
nFLTMSK
OK
0
1
0
0
0
0
0
R
: Default values of ACT8894Q4I133-T.
2: All bits are automatically cleared to default values when the input power is removed or falls below the system UVLO.
Innovative PowerTM
-9Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
OUTPUT ADDRESS BIT
SYS
SYS
0x00
0x00
[7]
[6]
NAME
ACCESS
DESCRIPTION
TRST
R/W
Reset Timer Setting. Defines the reset time-out threshold. Reset
time-out is 65ms when value is 1, reset time-out is 260ms when
value is 0. See nRSTO Output section for more information.
R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Generate an interrupt when VVDDREF falls
below the programmed SYSLEV threshold, 0: automatic
shutdown when VVDDREF falls below the programmed SYSLEV
threshold.
R/W
System Voltage Level Interrupt Mask. SYSLEV interrupt is
masked by default, set to 1 to unmask this interrupt. See the
Programmable System Voltage Monitor section for more
information
nSYSMODE
SYS
0x00
[5] nSYSLEVMSK
SYS
0x00
[4]
nSYSSTAT
R
SYS
0x00
[3:0]
SYSLEV
R/W
System Voltage Detect Threshold. Defines the SYSLEV voltage
threshold. See the Programmable System Voltage Monitor
section for more information.
SYS
0x01
[7:4]
-
R/W
Reserved.
SYS
0x01
[3:0]
SCRATCH
R/W
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
when system voltage falls below UVLO threshold.
REG1
0x20
[7:6]
-
R
REG1
0x20
[5:0]
VSET1
R/W
REG1
0x21
[7:6]
-
R
System Voltage Status. Value is 1 when VVDDREF is lower than the
SYSLEV voltage threshold, value is 0 when VVDDREF is higher
than the system voltage detection threshold.
Reserved.
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information.
Reserved.
REG1
0x21
[5:0]
VSET2
R/W
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
REG1
0x22
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1
0x22
[6]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG1
0x22
[5]
MODE
R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-savings
mode under light-load conditions.
REG1
0x22
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG1, REG2, REG3
Turn-on Delay section for more information.
REG1
0x22
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
REG1
0x22
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG2
0x30
[7:6]
-
R
Reserved.
REG2
0x30
[5:0]
VSET1
R/W
REG2
0x31
[7:6]
-
R
REG2
0x31
[5:0]
VSET2
R/W
Primary Output Voltage Selection. Valid when VSEL is driven low.
See the Output Voltage Programming section for more
information.
Reserved.
Secondary Output Voltage Selection. Valid when VSEL is driven
high. See the Output Voltage Programming section for more
information.
Innovative PowerTM
- 10 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT
ADDRESS
BIT
NAME
ACCESS
DESCRIPTION
REG2
0x32
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG2
0x32
[6]
PHASE
R/W
Regulator Phase Control. Set bit to 1 for the regulator to
operate 180° out of phase with the oscillator, clear bit to 0 for
the regulator to operate in phase with the oscillator.
REG2
0x32
[5]
MODE
R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to powersavings mode under light-load conditions.
REG2
0x32
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG1, REG2,
REG3 Turn-on Delay section for more information.
REG2
0x32
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG2
0x32
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG3
0x40
[7:6]
-
R
Reserved.
REG3
0x40
[5:0]
VSET1
R/W
REG3
0x41
[7:6]
-
R
REG3
0x41
[5:0]
VSET2
R/W
Secondary Output Voltage Selection. Valid when VSEL is
driven high. See the Output Voltage Programming section for
more information.
REG3
0x42
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG3
0x42
[6]
PWRSTAT
R/W
Configures regulator behavior with respect to the nPBIN input.
Set bit to 0 to enable regulator when nPBIN is asserted.
REG3
0x42
[5]
MODE
R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to powersavings mode under light-load conditions.
REG3
0x42
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG1, REG2,
REG3 Turn-on Delay section for more information.
REG3
0x42
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG3
0x42
[0]
OK
R
REG4
0x50
[7:6]
-
R
Primary Output Voltage Selection. Valid when VSEL is driven
low. See the Output Voltage Programming section for more
information.
Reserved.
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Reserved.
REG4
0x50
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG4
0x51
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
REG4
0x51
[6]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
REG4
0x51
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG4
0x51
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG4
0x51
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG4
0x51
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
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ACT8894
Rev 2, 06-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT
ADDRESS
BIT
NAME
ACCESS
DESCRIPTION
REG5
0x54
[7:6]
-
R
REG5
0x54
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG5
0x55
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
Reserved.
REG5
0x55
[6]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
REG5
0x55
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG5
0x55
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG5
0x55
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG5
0x55
[0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG6
0x60
[7:6]
-
R
Reserved.
REG6
0x60
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG6
0x61
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG6
0x61
[6]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
REG6
0x61
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG6
0x61
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG6
0x61
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG6
0x61
[0]
OK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG7
0x64
[7:6]
-
R
Reserved.
REG7
0x64
[5:0]
VSET
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
REG7
0x65
[7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
REG7
0x65
[6]
DIS
R/W
Output Discharge Control. When activated, LDO output is
discharged to GA through 1.5kΩ resistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
REG7
0x65
[5]
LOWIQ
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
REG7
0x65
[4:2]
DELAY
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
REG7
0x65
[1]
nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable faultinterrupts, clear bit to 0 to disable fault-interrupts.
REG7
0x65
[0]
OK
R/W
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
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ACT8894
Rev 2, 06-Sep-13
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Input Voltage Range
MIN
TYP
2.7
MAX
UNIT
5.5
V
2.65
V
UVLO Threshold Voltage
VVDDREF Rising
UVLO Hysteresis
VVDDREF Falling
200
REG1, REG2 and REG5 Enabled. REG3,
REG4, REG6 and REG7 Disabled
250
REG1, REG2, REG3, REG4 and REG5
Enabled. REG6 and REG7 Disabled
350
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 Enabled
420
All Regulators Disabled
1.5
3.0
µA
2
2.2
MHz
Supply Current
Shutdown Supply Current
Oscillator Frequency
Logic High Input Voltage
2.2
1.8
2.45
µA
1.4
1
V
Logic Low Input Voltage
Leakage Current
VnIRQ = VnRSTO = 4.2V
Low Level Output Voltage2
ISINK = 5mA
nRSTO Delay
Thermal Shutdown Temperature
mV
Temperature rising
Thermal Shutdown Hysteresis
0.4
V
1
µA
0.35
V
260
ms
160
°C
20
°C
: PWRHLD, PWREN, VSEL are logic inputs.
2: nPBSTAT, nIRQ, nRSTO are open drain outputs.
3: Typical value shown. Actual value may vary from 227.9ms to 291.2ms.
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ACT8894
Rev 2, 06-Sep-13
STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
PARAMETER
CONDITIONS
Operating Voltage Range
MIN
TYP
2.7
5.5
V
2.7
V
Input Voltage Rising
UVLO Hysteresis
Input Voltage Falling
100
Quiescent Supply Current
Regulator Enabled
65
90
µA
Shutdown Current
VVP = 5.5V, Regulator Disabled
0
1
µA
mV
VOUT ≥ 1.2V, IOUT = 10mA
-1%
VNOM
1%
VOUT < 1.2V, IOUT = 10mA
-2%
VNOM
2%
Line Regulation
VVP = Max(VNOM1 +1, 3.2V) to 5.5V
Load Regulation
IOUT = 10mA to IMAX
Power Good Threshold
Power Good Hysteresis
Oscillator Frequency
2.6
UNIT
UVLO Threshold
Output Voltage Accuracy
2.5
MAX
V
0.15
%/V
0.0017
%/mA
VOUT Rising
93
%VNOM
VOUT Falling
2
%VNOM
2
VOUT ≥ 20% of VNOM
1.8
VOUT = 0V
2
2.2
MHz
500
kHz
Soft-Start Period
400
µs
Minimum On-Time
75
ns
REG1
Maximum Output Current
0.9
Current Limit
1.2
A
1.4
1.7
A
PMOS On-Resistance
ISW1 = -100mA
0.18
Ω
NMOS On-Resistance
ISW1 = 100mA
0.16
Ω
SW1 Leakage Current
VVP1 = 5.5V, VSW1 = 0 or 5.5V
0
1
µA
REG2
Maximum Output Current
0.7
Current Limit
0.9
PMOS On-Resistance
A
1.1
ISW2 = -100mA
0.21
NMOS On-Resistance
ISW2 = 100mA
0.16
SW2 Leakage Current
VVP2 = 5.5V, VSW2 = 0 or 5.5V
0
1.3
A
Ω
Ω
1
µA
REG3
Maximum Output Current
0.9
Current Limit
1.2
A
1.4
1.7
A
PMOS On-Resistance
ISW3 = -100mA
0.18
Ω
NMOS On-Resistance
ISW3 = 100mA
0.16
Ω
SW3 Leakage Current
VVP3 = 5.5V, VSW3 = 0 or 5.5V
0
1
µA
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
Innovative PowerTM
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ACT8894
Rev 2, 06-Sep-13
LOW-NOISE LDO ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, COUT4 = COUT5 = 1.5µF, COUT6 = COUT7 = 2.2µF, LOWIQ[ ] = [0], TA = 25°C, unless otherwise specified.)
PARAMETER
TEST CONDITIONS
Operating Voltage Range
Output Voltage Accuracy
Line Regulation
Load Regulation
Power Supply Rejection Ratio
Supply Current per Output
MIN
MAX
UNIT
5.5
V
2.5
VOUT ≥ 1.2V, TA = 25°C, IOUT = 10mA
-1%
VNOM
2%
VOUT < 1.2V, TA = 25°C, IOUT = 10mA
-2%
VNOM
4%
V
VINL = Max(VOUT + 0.5V, 3.6V) to 5.5V
LOWIQ[ ] = [0]
0.05
mV/V
VINL = Max(VOUT + 0.5V, 3.6V) to 5.5V
LOWIQ[ ] = [1]
0.5
mV/V
IOUT = 1mA to IMAX2
0.08
V/A
f = 1kHz, IOUT = 20mA, VOUT =1.2V
75
f = 10kHz, IOUT = 20mA, VOUT =1.2V
65
dB
Regulator Enabled, LOWIQ[ ] = [0]
37
60
Regulator Enabled, LOWIQ[ ] = [1]
31
52
0
1
Regulator Disabled
Soft-Start Period
TYP
µA
VOUT = 2.9V
140
µs
Power Good Threshold
VOUT Rising
89
%
Power Good Hysteresis
VOUT Falling
3
%
Output Noise
IOUT = 20mA, f = 10Hz to 100kHz, VOUT =
1.2V
50
µVRMS
Discharge Resistance
LDO Disabled, DIS[ ] = 1
1.5
kΩ
REG4
Dropout Voltage
IOUT = 80mA, VOUT > 3.1V
Maximum Output Current
Current Limit
90
180
150
VOUT = 95% of regulation voltage
Stable COUT4 Range
mV
mA
200
mA
1.5
20
µF
280
mV
REG5
Dropout Voltage
IOUT = 80mA, VOUT > 3.1V
Maximum Output Current
Current Limit
VOUT = 95% of regulation voltage
Stable COUT5 Range
140
150
mA
200
mA
1.5
20
µF
180
mV
REG6
Dropout Voltage
IOUT = 120mA, VOUT > 3.1V
Maximum Output Current
Current Limit
90
250
VOUT = 95% of regulation voltage
Stable COUT6 Range
mA
300
mA
2.2
20
µF
280
mV
REG7
Dropout Voltage
IOUT = 120mA, VOUT > 3.1V
Maximum Output Current
Current Limit
VOUT = 95% of regulation voltage
Stable COUT7 Range
140
250
mA
300
mA
2.2
20
µF
: VNOM refers to the nominal output voltage level for VOUT as defined by the Ordering Information section.
2: IMAX Maximum Output Current.
3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the
regulation voltage (for 3.1V output voltage or higher)
: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage.
Under heavy overload conditions the output current limit folds back by 30% (typ)
Innovative PowerTM
- 15 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
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Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS
(VVP1 = VVP2 = VVP3 = 3.6V, TA = 25°C, unless otherwise specified.)
Frequency vs. Temperature
VREF vs. Temperature
0
-0.42
2
Frequency (%)
VREF (%)
0.42
2.5
-20
0
20
40
60
80
100
1.5
1
0.5
0
-0.5
Typical VREF=1.2V
-0.84
-40
ACT8894-002
ACT8894-001
0.84
Typical Oscillator Frequency=2MHz
-1
-40
120
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
nPBIN Startup Sequence
PWRHLD Startup Sequence
ACT8894-004
ACT8894-003
CH4
80 85
CH4
CH1
CH1
CH2
CH2
CH3
CH3
CH1: VOUT1, 2V/div
CH2: VOUT2, 1V/div
CH3: VOUT5, 1V/div
CH4: VnPBIN, 2V/div
TIME: 1ms/div
CH1: VOUT1, 2V/div
CH2: VOUT2, 2V/div
CH3: VOUT5, 1V/div
CH4: VPWRHLD, 2V/div
TIME: 2ms/div
PWREN Sequence
ACT8894-005
CH1
CH3
CH4
CH1: VPWREN, 2V/div
CH3: VOUT3, 1V/div
CH4: VOUT4, 1V/div
TIME: 1ms/div
Innovative PowerTM
- 16 Active-Semi Proprietary―For Authorized Recipients and Customers
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I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Push-Button Response (First Power-Up)
Manual Reset Response
ACT8894-007
ACT8894-006
CH1
CH1
CH2
CH2
CH3
CH3
CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
CH3: VnRSTO, 2V/div
TIME: 100ms/div
CH1: VnPBIN, 2V/div
CH2: VnPBSTAT, 2V/div
CH3:VnRSTO , 2V/div
TIME: 100ms/div
nPBIN Resistor = 50kΩ
REG1 Efficiency vs. Output Current
VIN = 4.2V
VIN = 3.6V
VOUT = 1.8V
80
Efficiency (%)
VIN = 5.0V
100
60
40
ACT8894-009
VOUT = 3.3V
80
Efficiency (%)
REG2 Efficiency vs. Output Current
ACT8894-008
100
nPBIN Resistor = 0Ω
VIN = 5.0V
VIN = 3.6V
VIN = 4.2V
60
40
20
20
0
0
1
10
100
10
1
1000
100
1000
Output Current (mA)
Output Current (mA)
REG3 Efficiency vs. Output Current
VOUT3 = 1.3V
80
Efficiency (%)
ACT8894-010
100
VIN = 5.0V
VIN = 3.6V
60
VIN = 4.2V
40
20
0
1
10
100
1000
Output Current (mA)
Innovative PowerTM
- 17 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
REG1 Output Voltage vs. Temperature
REG2 Output Voltage vs. Temperature
Output Voltage (V)
3.306
3.302
3.298
3.294
3.290
-40
-20
0
20
40
60
80
100
VOUT2 = 1.8V
ILOAD = 100mA
1.809
Output Voltage (V)
VOUT1 = 3.3V
ILOAD = 100mA
1.803
1.797
1.791
1.785
-40
120
-20
0
40
60
80
100
120
REG2 MOSFET Resistance
REG3 Output Voltage vs. Temperature
ACT8894-014
350
ACT8894-013
VOUT2 = 1.3V
ILOAD = 100mA
ILOAD = 100mA
300
250
RDSON (mΩ)
1.306
Output Voltage (V)
20
Temperature (°C)
Temperature (°C)
1.310
ACT8894-012
1.815
ACT8894-011
3.310
1.302
1.298
PMOS
200
NMOS
150
100
1.294
1.290
-40
50
0
-20
0
20
40
60
80
100
120
3.0
3.5
Temperature (°C)
4.0
4.5
5.0
5.5
Input Voltage (V)
REG1, 3 MOSFET Resistance
ACT8894-015
350
ILOAD = 100mA
300
RDSON (mΩ)
250
PMOS
200
150
NMOS
100
50
0
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Innovative PowerTM
- 18 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
REG4, REG5
1.220
1.180
1.140
4.00
Output Voltage (V)
Output Voltage (V)
1.260
4.50
ACT8894-017
ACT8894-016
1.300
REG7
3.50
3.00
2.50
2.00
REG6
1.50
1.00
0.50
1.100
0
20
40
60
80
100
120
140
0
160
50
Dropout Voltage vs. Output Current
REG4
80
60
40
20
60
80
100
120
140
200
REG5
150
100
50
VIN = 3.3V
0
VIN = 3.3V
40
0
160
20
Dropout Voltage vs. Output Current
120
100
80
60
40
VIN = 3.3V
150
200
250
300
Output Current (mA)
Innovative PowerTM
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ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
120
140
160
250
REG7
200
150
100
50
VIN = 3.3V
0
100
100
300
Dropout Voltage (mV)
Dropout Voltage (mV)
REG6
50
80
ACT8894-021
160
0
60
Dropout Voltage vs. Output Current
ACT8894-020
180
20
40
Output Current (mA)
Output Current (mA)
140
300
250
Dropout Voltage (mV)
Dropout Voltage (mV)
120
20
250
ACT8894-019
140
0
200
Dropout Voltage vs. Output Current
ACT8894-018
160
0
150
Output Current (mA)
Output Current (mA)
100
100
0
0
50
100
150
200
250
300
Output Current (mA)
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Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
TYPICAL PERFORMANCE CHARACTERISTICS CONT’D
(TA = 25°C, unless otherwise specified.)
Output Voltage vs. Temperature
2.50
ESR (Ω)
Output Voltage (V)
3.00
2.00
REG4, REG5, REG6
1.50
1
ACT8894-023
REG7
3.50
Region of Stable COUT ESR vs. Output Current
ACT8894-022
4.00
0.1
Stable ESR
1.00
0.50
0.01
0
-40
-20
0
20
40
60
80
100
0
120
50
100
150
200
250
Output Current (mA)
Temperature (°C)
LDO Output Voltage Noise
ACT8894-024
CH1
CH1: VOUTx, 200µV/div (AC COUPLED)
TIME: 200ms/div
Innovative PowerTM
- 20 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
SYSTEM CONTROL INFORMATION
Interfacing with the Samsung S3C2416/S3C2450
The ACT8894 is optimized for use in applications
using the S3C2416/S3C2450 processor, supporting
both the power domains as well as the signal
interface for these processors.
While the ACT8894 supports many possible
configurations for powering these processors, one
of the most common configurations is detailed in
this datasheet. In general, this document refers to
the ACT8894 pin names and functions. However, in
cases where the description of interconnections
between these devices benefits by doing so, both
the ACT8894 pin names and the Samsung
processor pin names are provided. When this is
done, the S3C2416/S3C2450 pin names are
located after the ACT8894 pin names, and are
italicized and located inside parentheses. For
example, PWREN (PWR_EN) refers to the logic
signal applied to the ACT8894's PWREN input,
identifying that it is driven from the
S3C2416/S3C2450's PWR_EN output. Likewise,
OUT1 (VDD_IO) refers to ACT8894's OUT1 pin,
identifying that it is connected to the
S3C2416/S3C2450's VDD_IO power domain.
Table 2:
ACT8894 and Samsung S3C2416/S3C2450 Power Domains
POWER DOMAIN
ACT8894 CHANNEL
TYPE
DEFAULT VOLTAGE
CURRENT CAPABILITY
VDD_IO
REG1
DC/DC
3.3V/3.3V
900mA
REG2
DC/DC
1.8V/1.8V
700mA
REG3
DC/DC
1.3V/1.3V
900mA
VDDA_xPLL
REG4
LDO
1.2V
150mA
VDD_Alive
REG5
LDO
1.2V
150mA
VDDI_UDEV
REG6
LDO
1.2V
250mA
VDDA33x
REG7
LDO
3.3V
250mA
VDD_MEM
VDD_SRAM
VDDiarm
VDDi
Table 3:
ACT8894 and Samsung S3C2416/S3C2450 Power Modes
POWER
MODE
CONTROL STATE
POWER DOMAIN STATE
QUIESCENT
CURRENT
ALL ON
PWRHLD is asserted, PWREN is asserted,
REG6 and REG7 are enabled by I2C
REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are all on
420µA
NORMAL
PWRHLD is asserted, PWREN is asserted,
REG6 and REG7 are disabled by I2C
REG1, REG2, REG3, REG4 and REG5
are on. REG6 and REG7 are off
350µA
PWRHLD is asserted, PWREN is de-asserted, REG1, REG2 and REG5 are on. REG3,
REG6 and REG7 are disabled by I2C
REG4, REG6 and REG7 are off
250µA
PWRHLD is de-asserted, PWREN is deasserted, REG6 and REG7 are disabled by I2C
<18µA
SLEEP
ALL OFF
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REG1, REG2, REG3, REG4, REG5,
REG6 and REG7 are all off
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Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
Table 4:
ACT8894 and Samsung S3C2416/S3C2450 Signal Interface
ACT8894
DIRECTION
SAMSUNG S3C2416/S3C2450
PWREN
PWR_EN
SCL
IICSCL
SDA
IICSDA
VSEL
DVS_GPIO
nRSTO
nRESET
nIRQ
EINT0
nPBSTAT
EINT1
PWRHLD
Power hold GPIO
1: Optional connection for DVS control.
2, : Typical connections shown, actual connections may vary.
: Optional connection for power hold control.
Table 5:
Control Pins
PIN NAME
OUTPUT
nPBIN
REG1, REG2, REG5
PWRHLD
REG1, REG2, REG5
PWREN
REG3, REG4
Control Signals
nPBSTAT Output
Enable Inputs
The ACT8894 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWREN, PWRHLD are logic inputs, while nPBIN is
a unique, multi-function input. Refer to Table 5 for a
description of which channels are controlled by
each input.
nPBIN Multi-Function Input
ACT8894 features the nPBIN multi-function pin,
which combines system enable/disable control with
a hardware reset function. Select either of the two
pin functions by asserting this pin, either through a
direct connection to GA, or through a 50kΩ resistor
to GA, as shown in Figure 2.
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage
(typically OUT1) through a 10kΩ or greater resistor.
Figure 2:
nPBIN Input
Manual Reset Function
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kΩ).
When this occurs, nRSTO immediately asserts low,
then remains asserted low until the nPBIN input is
de-asserted and the reset time-out period expires.
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ACT8894
Rev 2, 06-Sep-13
nRSTO Output
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires after
OUT1 reaches its power-OK threshold. When
asserted due to manual-reset, nRSTO immediately
asserts low, then remains asserted low until the
nPBIN input is de-asserted and the reset time-out
period expires.
Connect a 10kΩ or greater pull-up resistor from
nRSTO to an appropriate voltage supply (typically
OUT1).
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kΩ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
Many of the ACT8894's functions support interruptgeneration as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
Push-Button Control
The ACT8894 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWREN or PWRHLD) before nPBIN is de-asserted.
If the microprocessor is unable to complete its
power-up routine successfully before the user
releases the push button, the ACT8894
automatically shuts the system down. This provides
protection against accidental or momentary
assertions of the push-button. If desired, longer
“push-and-hold” times can be implemented by
simply adding an additional time delay before
asserting PWREN or PWRHLD.
Control Sequences
The
ACT8894
features
a
variety
of
control
sequences that are optimized for supporting system
enable and disable, as well as SLEEP mode of the
Samsung S3C2416/S3C2450 processor.
Enabling/Disabling Sequence
A typical enable sequence initiates as a result of
asserting nPBIN, and begins by enabling REG1.
When REG1 reaches its power-OK threshold,
REG2 and REG5 are enabled and nRSTO is
asserted low, resetting the microprocessor. If REG1
is above its power-OK threshold when the reset
timer expires, nRSTO is de-asserted, allowing the
microprocessor to begin its boot sequence.
During the boot sequence, the microprocessor must
assert PWRHLD, holding REG1, REG2, and REG5,
and assert PWREN (PWR_EN), enabling REG3
and REG4 to ensure that the system remains
powered after nPBIN is released. REG6 and REG7
should be enabled/disabled via I2C after
microprocessor completes its boot sequence.
Once the power-up routine is completed, the
system remains enabled after the push-button is
released as long as either PWRHLD or PWREN are
asserted high. If the processor does not assert
PWRHLD or PWREN before the user releases the
push-button, the boot-up sequence is terminated
and all regulators are disabled. This provides
protection against "false-enable", when the pushbutton is accidentally depressed, and also ensures
that the system remains enabled only if the
processor successfully completes the boot-up
sequence.
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes then
finally de-assert PWRHLD and PWREN, disabling
all regulators and shutting the system down.
SLEEP Mode Sequence
The
ACT8894
supports
Samsung
S3C2416/S3C2450 Processor SLEEP mode
operation. Once a successful power-up routine has
been completed, SLEEP mode may be initiated
through a variety of software-controlled
mechanisms.
SLEEP mode is typically initiated when the user
presses the push-button during normal operation.
Pressing the push-button asserts the nPBIN input,
which asserts the nPBSTAT output, which
interrupts the processor. In response to this
interrupt the processor should de-assert PWREN,
disabling REG3 and REG4. PWRHLD should
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ACT8894
Rev 2, 06-Sep-13
remain asserted during SLEEP mode so that
REG1, REG2, and REG5 remain enabled.
Waking from SLEEP mode is initiated when the
user presses the push-button again, which asserts
nPBSTAT. Processors should respond by asserting
PWREN, which enables REG3 and REG4 so that
normal operation may resume.
Figure 3:
Enable/Disable Sequence
Figure 4:
Sleep Mode Sequence
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ACT8894
Rev 2, 06-Sep-13
FUNCTIONAL DESCRIPTION
I2C Interface
below the SYSLEV[-] voltage threshold:
The ACT8894 features an I2C interface that allows
advanced programming capability to enhance overall
system performance. To ensure compatibility with a
wide range of system processors, the I2C interface
supports clock speeds of up to 400kHz (“Fast-Mode”
operation) and uses standard I2C commands. I2C
write-byte commands are used to program the
ACT8894, and I2C read-byte commands are used to
read the ACT8894’s internal registers. The ACT8894
always operates as a slave device, and is addressed
using a 7-bit slave address followed by an eighth bit,
which indicates whether the transaction is a readoperation or a write-operation, [1011011x].
1) If nSYSMODE[-] = 1 (default case), when system
vo l ta g e
l e ve l
i n te r r u p t
is
unmasked
(nSYSLEVMSK[ ]=1) and VVDDREF falls below the
programmable threshold, the ACT8894 asserts
nIRQ, providing a software “under-voltage alarm”.
The response to this interrupt is controlled by the
CPU, but will typically initiate a controlled shutdown
sequence either or alert the user that the battery is
low. In this case the interrupt is cleared when
VVDDREF rises up again above the SYSLEV rising
threshold and nSYSSTAT[-] is read via I2C.
SDA is a bi-directional data line and SCL is a clock
input. The master device initiates a transaction by
issuing a START condition, defined by SDA
transitioning from high to low while SCL is high. Data
is transferred in 8-bit packets, beginning with the
MSB, and is clocked-in on the rising edge of SCL.
Each packet of data is followed by an “Acknowledge”
(ACK) bit, used to confirm that the data was
transmitted successfully.
For more information regarding the I2C 2-wire serial
interface, go to the NXP website: http://www.nxp.com.
2) If nSYSMODE[-] = 0, when VVDDREF falls below the
programmable threshold the ACT8894 shuts down,
immediately disabling all regulators. This option is
useful for implementing a programmable “undervoltage lockout” function that forces the system off
when the battery voltage falls below the SYSLEV
threshold voltage. Since this option does not support
a controlled shutdown sequence, it is generally used
as a "fail-safe" to shut the system down when the
battery voltage is too low.
Table 6:
SYSLEV Threshold
SYSLEV[3:0]
Voltage Monitor and Interrupt
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Programmable System Voltage Monitor
The ACT8894 features a programmable systemvoltage monitor, which monitors the voltage at
VDDREF and compares it to a programmable
threshold voltage. The programmable voltage
threshold is programmed by SYSLEV[3:0], as shown
in Table 6.
SYSLEV[ ] is set to 3.0V by default. There is a
200mV rising hysteresis on SYSLEV[ ] threshold
such that VVDDREF needs to be 3.2V(typ) or higher in
order to power up the IC.
The nSYSSTAT[-] bit reflects the output of an
internal voltage comparator that monitors VDDREF
relative to the SYSLEV[-] voltage threshold, the
value of nSYSTAT[-] = 1 when VVDDREF is lower than
the SYSLEV[-] voltage threshold, and nSYSTAT[-] =
0 when VVDDREF is higher than the SYSLEV[-]
voltage threshold. Note that the SYSLEV[-] voltage
threshold is defined for falling voltages, and that the
comparator produces about 200mV of hysteresis at
VDDREF. As a result, once VVDDREF falls below the
SYSLEV threshold, its voltage must increase by
more than about 200mV to clear that condition.
After the IC is powered up, the ACT8894 responds in
one of two ways when the voltage at VDDREF falls
Thermal Shutdown
The ACT8894 integrates thermal shutdown
protection circuitry to prevent damage resulting from
excessive thermal stress, as may be encountered
under fault conditions. This circuitry disables all
regulators if the ACT8894 die temperature exceeds
160°C, and prevents the regulators from being
enabled until the IC temperature drops by 20°C (typ).
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SYSLEV Threshold
(Hysteresis = 200mV)
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
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Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
STEP-DOWN DC/DC REGULATORS
General Description
The ACT8894 features three synchronous, fixedfrequency, current-mode PWM step down converters
that achieve peak efficiencies of up to 97%. REG1
and REG3 are capable of supplying up to 900mA of
output current, while REG2 supports up to 700mA.
These regulators operate with a fixed frequency of
2MHz, minimizing noise in sensitive applications and
allowing the use of small external components.
100% Duty Cycle Operation
Each regulator is capable of operating at up to 100%
duty cycle. During 100% duty-cycle operation, the
high-side power MOSFET is held on continuously,
providing a direct connection from the input to the
output (through the inductor), ensuring the lowest
possible dropout voltage in battery powered
applications.
Synchronous Rectification
REG1, REG2, and REG3 each feature integrated nchannel synchronous rectifiers, maximizing efficiency
and minimizing the total solution size and cost by
eliminating the need for external rectifiers.
Soft-Start
When enabled, each output voltages tracks an
internal 400μs soft-start ramp, minimizing input
current during startup and allowing each regulator to
power up in a smooth, monotonic manner that is
independent of output load conditions.
Compensation
Each buck regulator utilizes current-mode control and
a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over its full
operating range. No compensation design is
required; simply follow a few simple guidelines
described below when choosing external
components.
Input Capacitor Selection
The input capacitor reduces peak currents and noise
induced upon the voltage source. A 4.7μF ceramic
capacitor is recommended for each regulator in most
applications.
Output Capacitor Selection
For most applications, 22μF ceramic output
capacitors are recommended for REG1 and REG3,
while 15μF ceramic output capacitor is recommended
for REG2.
Despite the advantages of ceramic capacitors, care
must be taken during the design process to ensure
stable operation over the full operating voltage and
temperature range. Ceramic capacitors are available
in a variety of dielectrics, each of which exhibits
different characteristics that can greatly affect
performance over their temperature and voltage
ranges.
Two of the most common dielectrics are Y5V and
X5R. Whereas Y5V dielectrics are inexpensive and
can provide high capacitance in small packages, their
capacitance varies greatly over their voltage and
temperature ranges and are not recommended for
DC/DC applications. X5R and X7R dielectrics are
more suitable for output capacitor applications, as
their characteristics are more stable over their
operating ranges, and are highly recommended.
Inductor Selection
REG1, REG2, and REG3 utilize current-mode control
and a proprietary internal compensation scheme to
simultaneously simplify external component selection
and optimize transient performance over their full
operating range. These devices were optimized for
operation with 2.2μH inductors, although inductors in
the 1.5μH to 3.3μH range can be used. Choose an
inductor with a low DC-resistance, and avoid inductor
saturation by choosing inductors with DC ratings that
exceed the maximum output current by at least 30%.
Configuration Options
Output Voltage Programming
By default, each regulator powers up and regulates to
its default output voltage. Output voltage is selectable
by setting VSEL pin that when VSEL is low, output
voltage is programmed by VSET1[-] bits, and when
VSEL is high, output voltage is programmed by
VSET2[-] bits. However, once the system is enabled,
each regulator's output voltage may be independently
programmed to a different value, typically in order to
minimize the power consumption of the
microprocessor during some operating modes.
Program the output voltages via the I2C serial
interface by writing to the regulator's VSET1[-]
register if VSEL is low or VSET2[-] register if VSEL is
high as shown in Table 8.
Enable / Disable Control
During normal operation, each buck may be enabled
or disabled via the I2C interface by writing to that
regulator's ON[ ] bit. The regulator accept rising or
falling edge of ON[ ] bit as on/off signal. To enable
the regulator, clear ON[ ] to 0 first then set to 1. To
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ACT8894
Rev 2, 06-Sep-13
disable the regulator, set ON[ ] to 1 first then clear it
to 0.
REG1, REG2, REG3 Turn-on Delay
Each of REG1, REG2 and REG3 features a
programmable Turn-on Delay which help ensure a
reliable qualification. This delay is programmed by
DELAY[2:0], as shown in Table 7.
regulation voltage, that regulator's OK[ ] bit will be 0.
If a DC/DC's nFLTMSK[-] bit is set to 1, the ACT8894
will interrupt the processor if that DC/DC's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in regulation,
and the OK[ ] bit has been read via I2C.
PCB Layout Considerations
Table 7:
REGx/DELAY[ ] Turn-On Delay
DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY
0
0
0
0 ms
0
0
1
2 ms
0
1
0
4 ms
0
1
1
8 ms
1
0
0
16 ms
1
0
1
32 ms
1
1
0
64 ms
1
1
1
128 ms
Operating Mode
By default, REG1, REG2, and REG3 each operate in
fixed-frequency PWM mode at medium to heavy
loads, while automatically transitioning to a
proprietary power-saving mode at light loads in order
to maximize standby battery life. In applications
where low noise is critical, force fixed-frequency
PWM operation across the entire load current range,
at the expense of light-load efficiency, by setting the
MODE[ ] bit to 1.
High switching frequencies and large peak currents
make PC board layout an important part of step-down
DC/DC converter design. A good design minimizes
excessive EMI on the feedback paths and voltage
gradients in the ground plane, both of which can
result in instability or regulation errors.
Step-down DC/DCs exhibit discontinuous input
current, so the input capacitors should be placed as
close as possible to the IC, and avoiding the use of
via if possible. The inductor, input filter capacitor, and
output filter capacitor should be connected as close
together as possible, with short, direct, and wide
traces. The ground nodes for each regulator's power
loop should be connected at a single point in a starground configuration, and this point should be
connected to the backside ground plane with multiple
via. The output node for each regulator should be
connected to its corresponding OUTx pin through the
shortest possible route, while keeping sufficient
distance from switching nodes to prevent noise
injection. Finally, the exposed pad should be directly
connected to the backside ground plane using
multiple via to achieve low electrical and thermal
resistance.
OK[ ] and Output Fault Interrupt
Each DC/DC features a power-OK status bit that can
be read by the system microprocessor via the I2C
interface. If an output voltage is lower than the powerOK threshold, typically 7% below the programmed
Table 8:
REGx/VSET[ ] Output Voltage Setting
REGx/VSET[2:0]
REGx/VSET[5:3]
000
001
010
011
100
101
110
111
000
0.600
0.800
1.000
1.200
1.600
2.000
2.400
3.200
001
0.625
0.825
1.025
1.250
1.650
2.050
2.500
3.300
010
0.650
0.850
1.050
1.300
1.700
2.100
2.600
3.400
011
0.675
0.875
1.075
1.350
1.750
2.150
2.700
3.500
100
0.700
0.900
1.100
1.400
1.800
2.200
2.800
3.600
101
0.725
0.925
1.125
1.450
1.850
2.250
2.900
3.700
110
0.750
0.950
1.150
1.500
1.900
2.300
3.000
3.800
111
0.775
0.975
1.175
1.550
1.950
2.350
3.100
3.900
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ACT8894
Rev 2, 06-Sep-13
LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS
General Description
REG4, REG5, REG6, and REG7 are low-noise,
low-dropout linear regulators (LDOs) that supply up
to 150mA, 150mA, 250mA, and 250mA,
respectively. Each LDO has been optimized to
achieve low noise and high-PSRR, achieving more
than 65dB PSRR at frequencies up to 10kHz.
Output Current Limit
Each LDO contains current-limit circuitry featuring a
current-limit fold-back function. During normal and
moderate overload conditions, the regulators can
support more than their rated output currents.
During extreme overload conditions, however, the
current limit is reduced by approximately 30%,
reducing power dissipation within the IC.
Compensation
The LDOs are internally compensated and require
very little design effort, simply select input and
output capacitors according to the guidelines below.
Input Capacitor Selection
Each LDO requires a small ceramic input capacitor
to supply current to support fast transients at the
input of the LDO. Bypassing each INL pin to GA
with 1μF. High quality ceramic capacitors such as
X7R and X5R dielectric types are strongly
recommended.
Output Capacitor Selection
Each LDO requires a small ceramic output
capacitor for stability. Capacitance value is 1.5μF
for REG4 and REG5, 2.2μF for REG6 and REG7.
For best performance, each output capacitor should
be connected directly between the output and GA
pins, as close to the output as possible, and with a
short, direct connection. High quality ceramic
capacitors such as X7R and X5R dielectric types
are strongly recommended.
Configuration Options
Output Voltage Programming
By default, each LDO powers up and regulates to
its default output voltage. Once the system is
enabled, each output voltage may be independently
programmed to a different value by writing to the
regulator's VSET[-] register via the I2C serial
interface as shown in Table 8.
Enable / Disable Control
During normal operation, each LDO may be
enabled or disabled via the I2C interface by writing
to that LDO's ON[ ] bit. The regulator accept rising
or falling edge of ON[ ] bit as on/off signal. To
enable the regulator, clear ON[ ] to 0 first then set to
1. To disable the regulator, set ON[ ] to 1 first then
clear it to 0.
REG4, REG5, REG6, REG7 Turn-on Delay
Each of REG4, REG5, REG6 and REG7 features a
programmable Turn-on Delay which help ensure a
reliable qualification. This delay is programmed by
DELAY[2:0], as shown in Table 7.
Output Discharge
Each of the ACT8894’s LDOs features an optional
output discharge function, which discharges the
output to ground through a 1.5kΩ resistance when
the LDO is disabled. This feature may be enabled
or disabled by setting DIS[-]; set DIS[-] to 1 to
enable this function, clear DIS[-] to 0 to disable it.
Low-Power Mode
Each of ACT8894's LDOs features a LOWIQ[-] bit
which, when set to 1, reduces the LDO's quiescent
current by about 16%, saving power and extending
battery lifetime.
OK[ ] and Output Fault Interrupt
Each LDO features a power-OK status bit that
be read by the system microprocessor via
interface. If an output voltage is lower than
power-OK threshold, typically 11% below
programmed regulation voltage, the value of
regulator's OK[-] bit will be 0.
If a LDO's nFLTMSK[-] bit is set to 1, the ACT8894
will interrupt the processor if that LDO's output
voltage falls below the power-OK threshold. In this
case, nIRQ will assert low and remain asserted until
either the regulator is turned off or back in
regulation, and the OK[-] bit has been read via I2C.
PCB Layout Considerations
PCB Layout Considerations The ACT8894’s LDOs
provide good DC, AC, and noise performance over
a wide range of operating conditions, and are
relatively insensitive to layout considerations. When
designing a PCB, however, careful layout is
necessary to prevent other circuitry from degrading
LDO performance.
A good design places input and output capacitors
as close to the LDO inputs and output as possible,
and utilizes a star-ground configuration for all
regulators to prevent noise-coupling through
ground. Output traces should be routed to avoid
Innovative PowerTM
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can
the
the
the
that
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ACT8894
Rev 2, 06-Sep-13
close proximity to noisy nodes, particularly the SW
nodes of the DC/DCs.
REFBP is a filtered reference noise, and internally
has a direct connection to the linear regulator
controller. Any noise injected onto REFBP will
directly affect the outputs of the linear regulators,
and therefore special care should be taken to
ensure that no noise is injected to the outputs via
REFBP. As with the LDO output capacitors, the
REFBP bypass capacitor should be placed as close
to the IC as possible, with short, direct connections
to the star-ground. Avoid the use of via whenever
possible. Noisy nodes, such as from the DC/DCs,
should be routed as far away from REFBP as
possible.
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- 29 Active-Semi Proprietary―For Authorized Recipients and Customers
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Copyright © 2013 Active-Semi, Inc.
ACT8894
Rev 2, 06-Sep-13
TQFN44-32 PACKAGE OUTLINE AND DIMENSIONS
D
D/ 2
SYMBOL
E/ 2
E
A3
MAX
MIN
MAX
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
D2
L
0.150
0.250
0.008
0.006
0.010
4.000 TYP
0.158 TYP
E
4.000 TYP
0.158 TYP
D2
2.550
2.800
0.100
0.110
E2
2.550
2.800
0.100
0.110
L
b
0.200
D
e
A1
DIMENSION IN
INCHES
MIN
b
A
DIMENSION IN
MILLIMETERS
R
0.400 TYP
0.250
0.450
0.250
0.016 TYP
0.010
0.018
0.010
e
E2
R
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each
product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
sales@active-semi.com or visit http://www.active-semi.com.
is a registered trademark of Active-Semi.
Innovative PowerTM
- 30 Active-Semi Proprietary―For Authorized Recipients and Customers
ActivePMUTM is trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.