AND8396 - Implementing Power Factor Correction with the NCP1608

AND8396/D
Implementing Power Factor
Correction with the
NCP1608
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APPLICATION NOTE
Introduction
The NCP1608 is a voltage mode power factor correction
(PFC) controller designed to implement converters to
comply with line current harmonic regulations. The device
operates in critical conduction mode (CrM) for optimal
performance in applications up to 350 W. Its voltage mode
scheme enables it to obtain near unity power factor (PF)
without the need for a line-sensing network. The output
voltage is accurately controlled with an integrated high
precision transconductance error amplifier. The controller
also implements a comprehensive set of safety features that
simplify system design.
This application note describes the design and
implementation of a 400 V, 100 W, CrM boost PFC
converter using the NCP1608. The converter exhibits high
PF, low standby power dissipation, high active mode
efficiency, and a variety of protection features.
Most electronic ballasts and switch-mode power supplies
(SMPS) use a diode bridge rectifier and a bulk storage
capacitor to produce a dc voltage from the utility ac line.
This causes a non-sinusoidal current consumption and
increases the stress on the power delivery infrastructure.
Government regulations and utility requirements mandate
control over line current harmonic content. Active PFC
circuits are the most popular method to comply with these
harmonic content requirements. System solutions consist of
connecting a PFC pre-converter between the rectifier bridge
and the bulk capacitor (Figure 1). The boost converter is the
most popular topology for active PF correction. It produces
a constant output voltage and consumes a sinusoidal input
current from the line.
PFC Pre−Converter
Rectifiers
AC Line
The Need for PFC
+
High
Frequency
Bypass
Capacitor
Converter
+
NCP1608
Bulk
Storage
Capacitor
Load
Figure 1. Active PFC Stage with the NCP1608
Basic Operation of a CrM Boost Converter
operation. This control method causes the frequency to vary
with the instantaneous line input voltage (Vin) and the output
load. The operation and waveforms of a CrM PFC boost
converter are illustrated in Figure 2. For detailed
information on the operation of a CrM boost converter for
PFC applications, please refer to AND8123/D.
For medium power (< 350 W) applications, CrM is the
preferred control method. CrM operates at the boundary
between discontinuous conduction mode (DCM) and
continuous conduction mode (CCM). In CrM, the drive on
time begins when the inductor current reaches zero.
CrM combines the reduced peak current of CCM
operation with the zero current switching of DCM
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 1
1
Publication Order Number:
AND8396/D
AND8396/D
Diode Bridge
Diode Bridge
IL
+
Vin
IL
+
L
Vin
Vdrain
L
+
+
+
AC Line
Vdrain
Vout
AC Line
−
−
The power switch is ON
The power switch is OFF
With the power switch voltage being about zero, the
input voltage is applied across the inductor. The inductor current linearly increases with a (Vin/L) slope.
Inductor
Current
The inductor current flows through the diode. The inductor
voltage is (Vout − Vin) and the inductor current linearly decays
with a (Vout − Vin)/L slope.
(Vout − Vin)/L
Vin/L
Critical Conduction Mode:
Next current cycle starts
when the core is reset.
IL(peak)
Vdrain
Vout
Vin
If next cycle does not start
then Vdrain rings towards Vin
Figure 2. Schematic and Waveforms of an Ideal CrM Boost Converter
Features of the NCP1608
The NCP1608 is an excellent controller for robust
medium power CrM boost PFC applications due to its
integrated safety features, low impedance driver, high
precision error amplifier, and low standby current
consumption.
Vin
For detailed information on the operation of the
NCP1608, please refer to NCP1608/D.
A CrM boost pre-converter featuring the NCP1608 is
shown in Figure 3.
L
Vout
D
NB:NZCD
LOAD
(Ballast,
SMPS, etc.)
RZCD
Rout1
+
AC Line
EMI
Filter
1
Cin
2
3
Rout2
4
CCOMP
Ct
NCP1608
FB
VCC
Control DRV
Ct
GND
CS
ZCD
VCC
8
7
+
M
Cbulk
6
5
Rsense
Figure 3. CrM Boost PFC Stage Featuring the NCP1608
A combination of resistors and capacitors connected
between the Control and ground pins forms a compensation
network that limits the bandwidth of the converter. For high
PF, the bandwidth is set to less than 20 Hz. A capacitor
connected to the Ct pin sets the maximum on time. The CS
pin provides cycle-by-cycle overcurrent protection. The
The FB pin senses the boost output voltage through the
resistor divider formed by Rout1 and Rout2. The FB pin
includes overvoltage protection (OVP), undervoltage
protection (UVP), and floating pin protection (FPP). This
pin is the input to the error amplifier. The output of the error
amplifier is the Control pin.
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AND8396/D
The VCC pin is the supply pin of the controller. When VCC
is less than the turn on voltage (VCC(on)), the current
consumption of the device is less than 35 mA. This results in
fast startup times and reduced standby power losses.
internal comparator compares the voltage developed across
Rsense (VCS) to an internal reference (VILIM). The driver
turns off when VCS reaches VILIM. The ZCD pin senses the
demagnetization of the boost inductor to turn on the drive.
The drive on time begins after the ZCD pin voltage (VZCD)
exceeds VZCD(ARM) and then decreases to less than
VZCD(TRIG). A resistor in series with the ZCD winding
limits the ZCD pin current.
The NCP1608 features a powerful output driver on the
DRV pin. The driver is capable of switching the gates of
large MOSFETs efficiently because of its low source and
sink impedances. The driver includes active and passive
pull-down circuits to prevent the output from floating high
when the NCP1608 is disabled.
Design Procedure
The design of a CrM boost PFC converter is discussed in
many ON Semiconductor application notes. Table 1 lists
some examples.
This application note describes the design procedure for
a 400 V, 100 W converter using the features of the
NCP1608. A dedicated NCP1608 design tool that enables
users to determine component values quickly is available at
www.onsemi.com.
Table 1. Additional Resources for the Design and Understanding of CrM Boost PFC Circuits
AND8123/D
AND8123JP/D
Power Factor Correction Stages Operating in Critical Conduction Mode
AND8016/D
Design of Power Factor Correction Circuits Using the MC33260
AND8154/D
NCP1230 90 W, Universal Input Adapter Power Supply with Active PFC
HBD853/D
Power Factor Correction Handbook
DESIGN STEP 1: Define the Required Parameters
The converter parameters are shown in Table 2.
Table 2. CONVERTER PARAMETERS
Parameter Name
Minimum Line Input Voltage
Maximum Line Input Voltage
Symbol
Value
Units
VacLL
85
Vac
VacHL
265
Vac
Minimum Line Frequency
fline(MIN)
47
Hz
Maximum Line Frequency
fline(MAX)
63
Hz
Vout
400
V
Full Load Output Current
Iout
250
mA
Full Load Output Power
Pout
100
W
Maximum Output Voltage
Vout(MAX)
440
V
Minimum Switching Frequency
fSW(MIN)
40
kHz
h
92
%
PF
0.9
−
Output Voltage
Minimum Full Load Efficiency
Minimum Full Load Power Factor
ǒ
DESIGN STEP 2: Calculate the Boost Inductor
Vac 2 @
Lv
ǒ
Ǔ
V out
* Vac @ h
Ǹ2
Ǹ2 @ V @ P @ f
out
out
SW(MIN)
Ǔ
85 2 @ 400 * 85 @ 0.92
Ǹ2
L LL v
+ 581 mH
Ǹ2 @ 400 @ 100 @ 40 k
The value of the boost inductor (L) is calculated using
Equation 1:
Where LLL is the inductor value calculated at VacLL.
(eq. 1)
ǒ
Ǔ
265 2 @ 400 * 265 @ 0.92
Ǹ2
L HL v
+ 509 mH
Ǹ2 @ 400 @ 100 @ 40 k
To ensure that the switching frequency exceeds the
minimum frequency, L is calculated at both the minimum
and maximum rms input line voltage:
Where LHL is the inductor value calculated at VacHL.
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AND8396/D
A value of 400 mH is selected. The inductance tolerance
is ±15%. The maximum inductance (LMAX) value is
460 mH. Equation 2 is used to calculate the minimum
frequency at full load.
ǒ
Ǹ2 @ Vac
Vac 2 @ h
f SW +
@ 1*
2 @ L MAX @ P out
V out
f SW(LL) +
Ǔ
winding turns ratio (N = NB:NZCD) is calculated using
Equation 5.
Nv
(eq. 2)
ǒ
Ǔ
ǒ
Ǔ
Nv
85 2 @ 0.92 @ 1 * Ǹ2 @ 85 + 50.5 kHz
400
2 @ 460 m @ 100
V out * ǒǸ2 @ Vac HLǓ
V ZCD(ARM)
400 * ǒǸ2 @ 265Ǔ
1.55
(eq. 5)
+ 16
MOSFET Conduction
Diode Conduction
tz
IL
Ǹ2 @ 265
2
+ 44.3 kHz
f SW(HL) + 265 @ 0.92 @ 1 *
400
2 @ 460 m @ 100
IL(peak)
fSW is equal to 50.5 kHz at VacLL and 44.3 kHz at VacHL.
IL(NEG)
DRV
0A
DESIGN STEP 3: Size the Ct Capacitor
The Ct capacitor is sized to set the maximum on time for
minimum line input voltage and maximum output power.
The maximum on time is calculated using Equation 3:
t on(MAX) +
t on(MAX) +
2 @ L MAX @ P out
h @ Vac LL 2
(eq. 3)
2 @ 460 m @ 100
+ 13.8 ms
0.92 @ 85 2
2 @ P out @ L MAX @ I charge
h @ Vac LL 2 @ V Ct(MAX)
VZCD(WIND),off
0V
VZCD(WIND),on
VZCD
VCL(POS)
VZCD(ARM)
VZCD(TRIG)
VCL(NEG)
(eq. 4)
0V
tdiode
ton
Where Icharge and VCt(MAX) are specified in the NCP1608
datasheet. To ensure that the controller sets the maximum on
time to a value sufficient to deliver the required output
power, the maximum Icharge and the minimum VCt(MAX)
values are used in the calculations for Ct.
From the NCP1608 datasheet:
• VCt(MAX) = 4.775 V (minimum)
• Icharge = 297 mA (maximum)
toff
RZCD
Delay
TSW
Figure 4. Realistic CrM Waveforms Using a ZCD
Winding with RZCD and the ZCD Pin Capacitance
A turns ratio of 10 is selected for this design. RZCD is
connected between the ZCD winding and the ZCD pin to
limit the ZCD pin current. This current must be limited
below 10 mA. RZCD is calculated using Equation 6:
Ct is equal to:
Ct w
0V
Minimum Voltage Turn on
VZCD(WIND)
Sizing Ct to an excessively large value causes the
application to deliver excessive output power and reduces
the control range at VacHL or low output power. It is
recommended to size the Ct capacitor to a value slightly
larger than that calculated by Equation 4:
Ct w
0V
Vdrain
Vout
2 @ 100 @ 460 m @ 297 m
+ 860 pF
0.92 @ 85 2 @ 4.775
A normalized value of 1 nF (±10%) provides sufficient
margin. A value of 1.22 nF is selected for Total Harmonic
Distortion (THD) reduction (see the Additional THD
Reduction section of this application note for more
information).
R ZCD w
Ǹ2 @ Vac
HL
I ZCD(MAX) @ N
R ZCD w
Ǹ2 @ 265
+ 3.75 kW
10 m @ 10
(eq. 6)
The value of RZCD and the parasitic capacitance of the
ZCD pin determine when the ZCD winding signal is
detected and the drive turn on begins. A large RZCD value
creates a long delay before detecting the ZCD event. In this
case, the controller operates in DCM and the PF is reduced.
If the RZCD value is too small, the drive turns on when the
DESIGN STEP 4: Determine the ZCD Turns Ratio
To activate the ZCD detector of the NCP1608, the ZCD
turns ratio is sized such that at least VZCD(ARM) (1.55 V
maximum) is applied to the ZCD pin during all operating
conditions (see Figure 4). The boost winding to ZCD
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AND8396/D
drain voltage is high and efficiency is reduced. A popular
strategy for selecting RZCD is to use the RZCD value that
achieves minimum drain voltage turn on. This value is found
experimentally.
During the delay caused by RZCD and the ZCD pin
capacitance, the equivalent drain capacitance (CEQ(drain))
discharges through the path shown in Figure 5.
L
Vout
IL
D
Iin
+
AC Line
+
Cin
EMI
Filter
CEQ(drain)
Cbulk
Figure 5. Equivalent Drain Capacitance Discharge Path
Rout2 is dependent on Vout, Rout1, and the internal
feedback resistor (RFB, shown in the NCP1608 specification
table). Rout2 is calculated using Equation 8:
CEQ(drain) is the combined parasitic capacitances of the
MOSFET, the diode, and the inductor. Cin is charged by the
energy discharged by CEQ(drain). The charging of Cin reverse
biases the bridge rectifier and causes the input current (Iin)
to decrease to zero. The zero input current causes THD to
increase. To reduce THD, the ratio (tz / TSW) is minimized,
where tZ is the period from when IL = 0 A to when the drive
turns on. The ratio (tz / TSW) is inversely proportional to the
square root of L.
R out2 +
R out2 +
DESIGN STEP 5: Set the FB, OVP, and UVP Levels
Rout1 and Rout2 form a resistor divider that scales down
Vout before it is applied to the FB pin. The error amplifier
adjusts the on time of the drive to maintain the FB pin
voltage equal to the error amplifier reference voltage
(VREF). The divider network bias current (Ibias(out))
selection is the first step in the calculation. The divider
network bias current is selected to optimize the tradeoff of
noise immunity and power dissipation. Rout1 is calculated
using the optimized bias current and output voltage using
Equation 7:
R out1 +
V out
I bias(out)
ǒ
R out1 @ R FB
Ǔ
(eq. 8)
Vout
R FB @
* 1 * R out1
VREF
4 M @ 4.6 M
+ 25.3 kW
4.6 M @ 400 * 1 * 4 M
2.5
ǒ
Ǔ
Rout2 is selected as 25.5 kW for this design.
Using the selected resistor, the resulting output voltage is
calculated using Equation 9:
ǒ
V out + V REF @ R out1 @
ǒ
V out + 2.5 @ 4 M @
Ǔ
R out2 ) R FB
)1
R out2 @ R FB
(eq. 9)
Ǔ
25.5 k ) 4.6 M
) 1 + 397 V
25.5 k @ 4.6 M
The low bandwidth of the PFC stage causes overshoots
during transient loads or during startup. The NCP1608
includes an integrated OVP circuit to prevent the output
from exceeding a safe voltage. The OVP circuit compares
VFB to the internal overvoltage detect threshold voltage to
determine if an OVP fault occurs. The OVP detection
voltage is calculated using Equation 10:
(eq. 7)
A bias current of 100 mA provides an acceptable tradeoff
of power dissipation to noise immunity.
R out1 + 400 + 4 MW
100 m
The output voltage signal is delayed before it is applied to
the FB pin due to the time constant set by Rout1 and the FB
pin capacitance. Rout1 must not be sized too large or this
delay may cause overshoots of the OVP detection voltage.
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AND8396/D
V out(OVP) +
VCC
(eq. 10)
ǒ
Ǔ
V OVP
) R FB
R
@ V REF @ R out1 @ out2
)1
V REF
R out2 @ R FB
ǒ
V out(OVP) + 1.06 @ 2.5 @ 4 M @
VCC(on)
VCC(off)
Ǔ
25.5 k ) 4.6 M
) 1 + 421 V
25.5 k @ 4.6 M
Vout
Vout
The output capacitor (Cbulk) value is sized to be large
enough so that the peak-to-peak output voltage ripple
(Vripple(peak-peak)) is less than the OVP detection voltage.
Cbulk is calculated using Equation 11:
C bulk w
P out
2 @ p @ V ripple(peak−peak) @ f line @ V out
Loop is Opened
VFB
VREF
VUVP
VControl
(eq. 11)
VEAH
Where fline = 47 Hz is the worst case for the ripple voltage
and Vripple(peak-peak) < 42 V.
C bulk w
Ct(offset)
UVP Fault
100
+ 20 mF
2 @ p @ 42 @ 47 @ 400
The value of Cbulk is selected as 68 mF to reduce
Vripple(peak-peak) to less than 15 V. This results in a peak
output voltage of 406.25 V, which is less than the peak
output OVP detection voltage (421 V).
The NCP1608 includes undervoltage protection (UVP).
During startup, Cbulk charges to the peak of the ac line
voltage. If Cbulk does not charge to a minimum voltage, the
NCP1608 detects an UVP fault. The UVP detection voltage
is calculated using Equation 12:
ǒ
V out(UVP) + V UVP @ R out1 @
ǒ
V out(UVP) + 0.31 @ 4 M @
Ǔ
R out2 ) R FB
)1
R out2 @ R FB
Figure 6. UVP Operation if Loop is Opened During
Operation
DESIGN STEP 6: Size the Power Components
The power components are sized such that there is
sufficient margin to sustain the currents and voltages applied
to them. At minimum line input voltage and maximum
output power the inductor peak current is at the maximum,
which causes the greatest stress to the power components.
The components are referenced in Figure 3.
1. The inductor peak current (IL(peak)) is calculated
using Equation 13:
(eq. 12)
Ǔ
25.5 k ) 4.6 M
) 1 + 49 V
25.5 k @ 4.6 M
I L(peak) +
The UVP feature protects against open loop conditions in
the feedback loop. If the FB pin is inadvertently floating
(perhaps due to a bad solder joint), the coupling within the
system may cause VFB to be within the regulation range
(i.e. VUVP < VFB < VREF). The controller responds by
delivering maximum power. The output voltage increases
and over stresses the components. The NCP1608 includes a
feature to protect the system if FB is floating. The internal
pull-down resistor (RFB) ensures that VFB is below the UVP
threshold if the FB pin is floating.
If the FB pin floats during operation, VFB begins
decreasing from VREF. The rate of decrease depends on RFB
and the FB pin parasitic capacitance. As VFB decreases,
VControl increases, which causes the on time to increase until
VFB < VUVP. When VFB < VUVP, the UVP fault is detected
and the controller is disabled. The sequence is depicted in
Figure 6.
I L(peak) +
Ǹ2 @ 2 @ P
out
h @ Vac
Ǹ2 @ 2 @ 100
0.92 @ 85
(eq. 13)
+ 3.62 A
The inductor rms current (IL(RMS)) is calculated using
Equation 14:
I L(RMS) +
2 @ P out
Ǹ3 @ Vac @ h
(eq. 14)
2 @ 100
I L(RMS) +
+ 1.48 A
Ǹ3 @ 85 @ 0.92
2. The output diode (D) rms current (ID(RMS)) is
calculated using Equation 15:
I D(RMS) + 4 @
3
ǸǸ2p@ 2 @
I D(RMS) + 4 @
3
Ǹ
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Ǹ2 @ 2
p @
P out
h @ ǸVac @ V out
(eq. 15)
100
+ 0.75 A
0.92 @ Ǹ85 @ 400
AND8396/D
The diode maximum voltage is equal to VOVP (421 V)
plus the overshoot caused by parasitic contributions. For this
demonstration board, the maximum voltage is 450 V.
A 600 V diode provides a 25% derating factor.
The MUR460 (4 A/600 V) diode is selected for this design.
The value of Cbulk is calculated in Step 5 to ensure a ripple
voltage that is sufficiently low to not trigger OVP. The value
of Cbulk may need to be increased so that the rms current
does not exceed the ratings of Cbulk.
The voltage rating of Cbulk is required to be greater than
Vout(OVP). Since Vout(OVP) is 421 V, Cbulk is selected to have
a voltage rating of 450 V.
3. The MOSFET (M) rms current (IM(RMS)) is
calculated using Equation 16:
Ǹ ǒ
ǓǸ ǒ
ǒ
Ǔ
P out
I M(RMS) + 2 @
@
Ǹ3
h @ Vac
ǒ
100
I M(RMS) + 2 @
@
Ǹ3 0.92 @ 85
1*
Ǹ2 @ 8 @ Vac
3 @ p @ V out
Ǔ
Ǔ
DESIGN STEP 7: Supply VCC Voltage
The typical method to charge the VCC capacitor (CVcc) to
VCC(on) is to connect a resistor between Vin and VCC. The
low startup current consumption of the NCP1608 enables
most of the resistor current to charge CVcc during startup.
The low startup current consumption enables faster startup
times and reduces standby power dissipation. The startup
time (tstartup) is approximated with Equation 20:
(eq. 16)
Ǹ2 @ 8 @ 85
1−
+1.27 A
3 @ p @ 400
The MOSFET maximum voltage is equal to VOVP
(421 V) plus the overshoot caused by parasitic
contributions. For this demonstration board, the maximum
voltage is 450 V. A 560 V MOSFET provides a 20%
derating factor. The SPP12N50C3 (11.6 A/560 V) MOSFET
is selected for this design.
t startup +
V ILIM
I L(peak)
t startup +
(eq. 17)
The current sense resistor is selected as 0.125 W for
decreased power dissipation. The resulting maximum
inductor peak current is 4 A. Since the MOSFET continuous
current rating is 7 A (for TC = 100°C as specified in the
manufacturer’s datasheet) and the inductor saturation
current is 4.7 A, the maximum peak inductor current of 4 A
is sufficiently low.
The power dissipated by Rsense is calculated using
Equation 18:
sense
PR
sense
Ǹ
I C(RMS) +
Ǹ
47 m @ 12
+ 3.57 s
[email protected]
* 24 m
660 k
RZCD
(eq. 18)
C3
+ 1.27 2 @ 0.125 + 0.202 W
R1
IAUX
DAUX
D1
Rstart
5. The output capacitor (Cbulk) rms current is
calculated using Equation 19:
I C(RMS) +
(eq. 20)
[email protected]
* I CC(startup)
Rstart
Once VCC reaches VCC(on), the internal references and
logic of the NCP1608 turn on. The NCP1608 includes an
undervoltage lockout (UVLO) feature that ensures that the
NCP1068 remains enabled unless VCC decreases to less than
VCC(off). This hysteresis ensures sufficient time for another
supply to power VCC.
The ZCD winding is a possible solution, but the voltage
induced on the winding may be less than the required
voltage. An alternative is to implement a charge pump to
supply VCC. A schematic is illustrated in Figure 7.
R sense + 0.5 + 0.138 W
3.62
+ I M(RMS) 2 @ R sense
@ V CC(on)
If CVcc is selected as a 47 mF capacitor and Rstart is
selected as 660 kW, tstartup is equal to:
Where VILIM is specified in the NCP1608 datasheet.
PR
CC
Where ICC(startup) = 24 mA (typical).
4. The current sense resistor (Rsense) limits the
maximum inductor peak current of the MOSFET
and is calculated using Equation 17:
R sense +
CV
NCP1608
8
FB
VCC
2
7
Control DRV
3
6
Ct
GND
5
4
CS
ZCD
1
Ǹ2 @ 32 @ P 2
out
* I load(RMS) 2
9 @ p @ Vac @ V out @ h 2
+
Cin
(eq. 19)
Ǹ2 @ 32 @ 100 2
* 0.25 2 + 0.7 A
9 @ p @ 85 @ 400 @ 0.92 2
+
CVcc
Figure 7. The ZCD Winding Supplies VCC using
a Charge Pump Circuit
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AND8396/D
C3 stores the energy for the charge pump. R1 limits the
current by reducing the rate of voltage change. DAUX supplies
current to C3 when its cathode is negative. When its cathode
is positive it limits the maximum voltage applied to VCC.
The voltage change across C3 over one period is
calculated using Equation 21:
DV C3 +
V out
* V CC
N
For off-line ac-dc applications that require PFC, a 2-stage
approach is typically used. The first stage is the CrM boost
PFC. This supplies the 2nd stage, which is traditionally an
isolated flyback or forward converter. This solution is
cost-effective and exhibits excellent performance. During
low output power conditions the PFC stage is not required
and reduces efficiency. Advanced controllers, such as the
NCP1230 and NCP1381 detect the low output power
condition and shut down the PFC stage by removing
PFC(VCC) (Figure 8).
(eq. 21)
The current that charges CVcc is calculated using
Equation 22:
(eq. 22)
ǒ
Ǔ
V out
I AUX + C3 @ f SW @ DV C3 + C3 @ f SW @
* V CC
N
D
+
1
8
2
3
PFC(VCC)
Cbulk
1
8
7
2
7
6
3
6
+
VCC
+
+
4
5
NCP1608
4
5
+
+
−
NCP1230
Figure 8. Using the SMPS Controller to Supply Power to the NCP1608
DESIGN STEP 8: Limit the Inrush Current
NTC
Vin
The sudden application of the ac line voltage to the PFC
pre-converter causes an inrush current and a resonant
voltage overshoot that is several times the normal value.
Resizing the power components to handle inrush current and
a resonant voltage overshoot is cost prohibitive.
1. External Inrush Current Limiting Resistor
A NTC (negative temperature coefficient) thermistor
connected in series with the diode limits the inrush current
(Figure 9). The resistance of the NTC decreases from a few
ohms to a few milliohms as the NTC is heated by the I2R
power dissipation. However, an NTC resistor may not be
sufficient to protect the inductor and Cbulk from inrush
current during a brief interruption of the ac line voltage, such
as during ac line dropout and recovery.
2. Startup Bypass Rectifier
A rectifier is connected from Vin to Vout (Figure 10). This
bypasses the inductor and diverts the startup current directly
to Cbulk. Cbulk is charged to the peak ac line voltage without
resonant overshoot and without excessive inductor current.
After startup, Dbypass is reverse biased and does not interfere
with the boost converter.
+
NCP1608
Vout
Vac
Figure 9. Use a NTC to Limit the Inrush Current
Through the Inductor
Dbypass
Vin
+
NCP1608
Vac
Figure 10. Use a Second Diode to Route the
Inrush Current Away from the Inductor
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Vout
AND8396/D
DESIGN STEP 9: Develop the Compensation Network
C COMP1 +
The pre-converter is compensated to ensure stability over
the input voltage and output power range. To compensate the
loop, a compensation network is connected between the
Control and ground pins. To ensure high PF, the bandwidth
of the loop is set below 20 Hz. A type 2 compensation
network is selected for this design to increase the phase
margin. The type 2 compensation network is shown in
Figure 11.
C COMP1 +
E/A
+
RFB
Rout2
gm
CCOMP
VControl
RCOMP1
R COMP1 +
1
2 @ p @ f zero @ C COMP
R COMP1 +
1
+ 19.3 kW
2 @ p @ 2.5 @ 3.3 m
VREF
Control
110 m
+ 3.5 mF
[email protected]@5
A normalized value of 3.3 mF is selected, which sets
fCROSS to 5.3 Hz.
The addition of RCOMP1 causes a zero in the loop
response. The zero frequency (fzero) is typically set to half
the crossover frequency, which is 2.5 Hz for this case.
RCOMP1 is calculated using Equation 24:
Rout1
−
+
(eq. 23)
For this design, fCROSS is set to 5 Hz at the average input
voltage (175 Vac) to decrease THD and gm is specified in the
NCP1608 datasheet:
Vout
FB
gm
2 @ p @ f CROSS
(eq. 24)
RCOMP1 is selected as 20 kW. CCOMP is used to filter high
frequency noise and is set to between 1/10 and 1/5 of
CCOMP1. For this design, CCOMP is selected to be 1/5 of
CCOMP1.
Compensation
Network
ǒǓ
C COMP + 1 @ 3.3 m + 0.66 mF
5
CCOMP1
CCOMP is selected as 0.68 mF.
Figure 11. Type 2 Compensation Network
The phase margin and crossover frequency change with
the ac line voltage. It is critical that the gain and phase are
measured for all operating conditions. The measurement
setup using a network analyzer is shown in Figure 12.
The type 2 network is composed of CCOMP, CCOMP1, and
RCOMP1. CCOMP1 sets the crossover frequency (fCROSS) and
is calculated using Equation 23:
Ch A
High−Voltage
(> 450 V)
Isolation Probe
Ch B
High−Voltage
(> 450 V)
Isolation Probe
Network Analyzer
D
L
Vout
Isolator
RZCD
+
EMI
Filter
1 kW
Rout1
1
Cin
2
AC Line
3
Rout2
Ct
4
NCP1608
FB
VCC
Control DRV
Ct
GND
CS
ZCD
Load
VCC
8
7
+
M
6
5
CCOMP
Rsense
Figure 12. Gain-Phase Measurement Setup for a Boost PFC Pre-Converter
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9
Cbulk
AND8396/D
1. Improve the THD/PF at Maximum Output Power by
Increasing the On Time at the Zero Crossing:
There is a tradeoff of transient response for PF and THD.
The low bandwidth of the feedback loop reduces the Control
pin ripple voltage. The reduction of the Control pin ripple
voltage increases PF and reduces THD, but increases the
magnitude of overshoots and undershoots.
One disadvantage of constant on time CrM control is that
at the zero crossing of the ac line, the instantaneous input
voltage is not large enough to store sufficient energy in the
inductor during the constant on time. Minimal energy is
processed and “zero crossing distortion” is produced as
shown in Figure 13.
Additional THD Reduction
The constant on time architecture of the NCP1608
provides flexibility in optimizing each design.
The following design guidelines provide methods to
further improve PF and THD.
Vin (100V/div)
Iin (500mA/div)
Vout (10V/div, ac coupled)
Zero
Crossing
Distortion
Figure 13. Full Load Input Current (Vin = 230 Vac 50 Hz, Iout = 250 mA)
reduces the instantaneous input voltage at which the
distortion begins.
This method is implemented by connecting a resistor from
Vin to Ct as shown in Figure 14. The resistor current (ICTUP)
is proportional to the instantaneous line voltage and is
summed with Icharge to increase the charging current of Ct.
ICTUP is maximum at the peak of Vin and is approximately
zero at the zero crossing.
The zero crossing distortion increases the THD and
decreases the PF of the pre-converter. To meet
IEC61000−3−2 requirements, this is generally not an issue
as the NCP1608 reduces input current distortion with
sufficient margin. If improved THD or PF is required, then
zero crossing distortion must be reduced. To reduce the zero
crossing distortion, the on time is increased as the
instantaneous input voltage is decreasing to zero. This
increases the time for the inductor current to build up and
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10
AND8396/D
L
Vin
I CTUP +
V in
R CTUP
+
Cin
VDD
RCTUP
VControl
AC Line
PWM
−
+
Icharge
Ct
ton
DRV
Ct
Ct(offset)
Figure 14. .Add RCTUP to Modulate the On Time and Reduce Zero Crossing Distortion
The increased charging current at the peak of Vin enables
the increased sizing of the Ct capacitor without reducing the
control range at VacHL or low output power. The larger value
of the Ct capacitor increases the on time near the zero
crossing and reduces the zero crossing distortion as shown
in Figure 15. This reduces the frequency variation over the
ac line cycle. The tradeoff is that the standby power
dissipation is increased by RCTUP. The designer must
balance the desired THD and PF performance with the
standby power dissipation requirements.
Vac(t)
with RCTUP
ton
no RCTUP
no RCTUP
fSW
with RCTUP
time
Figure 15. On Time and Switching Frequency With and Without RCTUP
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11
AND8396/D
The dependency of THD on RCTUP is illustrated in
Figure 16.
14
Vout
12
VFB
RCTUP = open
Ct = 1 nF
10
THD (%)
Vout
VREF
8
VControl
6
RCTUP = 1.5 MW
Ct = 1.22 nF
4
Ct(offset)
2
DRV
0
85
115
145
175
Vin (Vac)
205
235
265
Figure 16. Dependency of THD on RCTUP
(Iout = 250 mA)
Figure 17. Required On Time Less Than the
Minimum On Time
This sequence increases the input current distortion.
There are two solutions to improve THD/PF at maximum
input voltage or low output current:
1. Properly size the Ct capacitor. As previously
mentioned, the Ct capacitor is sized to set the
maximum on time for minimum line input voltage
and maximum output power. Sizing Ct to an
excessively large value reduces the control range
at VacHL or low output power.
2. Compensate for propagation delays. If optimizing
the Ct capacitor does not achieve the desired
performance, then it may be necessary to
compensate for the PWM propagation delay by
connecting a resistor (RCT) in series with Ct.
When the Ct voltage reaches the VControl setpoint,
the PWM comparator sends a signal to end the on
time of the driver as shown in Figure 18.
2. Improve the THD/PF at Maximum Input Voltage or
Low Output Current:
If the required on time at maximum input voltage or low
output current is less than the minimum on time (tPWM), then
DRV pulses must be skipped to prevent excessive power
delivery to the output. This results in the following
sequence:
1. The excessive on time causes VControl to decrease
to Ct(offset).
2. When VControl < Ct(offset), the drive is disabled.
3. The drive is disabled and Vout decreases.
4. As Vout decreases, VControl increases.
5. The sequence repeats. Figure 17 depicts the
sequence:
VControl
Control
Iswitch
VDD
PWM
−
+
Icharge
Ct
Driver
VCt(off)
RCT
Ct
Vgate
DRV
RDRV
DRV
Rsense
Ct(offset)
Figure 18. Block Diagram of the Propagation Delay Components
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12
AND8396/D
A value of RCT = 365 W compensates for the propagation
delays. Figure 20 shows the decrease of THD at VacHL and
low output power by compensating for the propagation delay.
There is a delay (tdelay) from when VCt(off) is reached to
when the MOSFET completely turns off. tdelay is caused by
the propagation delay of the PWM comparator (tPWM) and
the time for the gate voltage of the MOSFET to decrease to
zero (tgate). The delays are illustrated in Figure 19.
50
40
VCt(off)
THD (%)
RCT = 0 W
Ct
tPWM
Vgate
30
DRV Pulse Skipping Begins
20
RCT = 365 W
10
0
25
30
35
Pout (W)
Iswitch
40
45
50
Figure 20. Low Output Power THD Reduction with
RCT (Vin = 265 Vac 50 Hz, RCTUP = Open, Ct = 1 nF)
tgate
tdelay
Both THD reduction techniques can be combined to
decrease the THD for the entire output power range.
Figure 21 shows the decreased THD at the maximum input
voltage across the output power range by decreasing zero
crossing distortion and by compensating for the propagation
delay.
Figure 19. Turn Off Propagation Delays
The total delay is calculated using Equation 25:
t delay + t PWM ) t gate
(eq. 25)
tdelay increases the effective on time of the MOSFET.
If a resistor (RCT) is connected in series with the Ct
capacitor, then the total on time reduction is calculated using
Equation 26:
DV RCT
+ Ct @ R CT
DI RCT
40
(eq. 26)
THD (%)
Dt on + Ct @
50
The value of RCT to compensate for the propagation delay
is calculated using Equation 27:
R CT +
t delay
Ct
(eq. 27)
30
DRV Pulse Skipping Begins
RCTUP = open
RCT = 0 W Ct = 1 nF
20
10
The NCP1608 datasheet specifies the maximum tPWM as
130 ns. tgate is a dependent on the gate charge of the
MOSFET and RDRV. For this demo board, the gate delay is
measured as 230 ns.
RCTUP = 1.5 MW
RCT = 365 W Ct = 1.22 nF
0
25
35
45
65
55
Pout (W)
75
85
95
Figure 21. THD Reduction with RCTUP and RCT
(Vin = 265 Vac 50 Hz)
360 n
R CT +
+ 360 W
1n
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AND8396/D
Design Results
The completed demonstration board schematic is shown
in Figure 22.
Rstart1
Rstart2
Lboost
Dboost
J3
NTC
t°
Bridge
F1
L1
L2
J2
C1
C3
D1
Daux
CVcc
R1
Rctup1
+
Ro1a
Dvcc
Rzcd
C2
Ro1b
Rctup2
Cin
Rct
Rcomp1
Ccomp
Ccomp1
U1
NCP1608
J1
1
FB
2
Control
3
Ct
4
CS
Cbulk +
8
Vcc
DRV 7
GND 6
ZCD 5
CVcc2 Ddrv
Q1
Rdrv
Rout2a
Rout2b
Rcs
Ct2 Ct1
Czcd
Ccs
Rs3 Rs2 Rs1
Figure 22. 100 W Pre-Converter Using the NCP1608
• The Input Power, PF, and THD are Measured Using
The bill of materials (BOM), layout, and summary of
boost equations are shown in Appendix 1, Appendix 2, and
Appendix 3 respectively. This pre-converter exhibits
excellent THD (Figure 23 and Figure 24), PF (Figure 25),
and efficiency (Figure 26). All measurements are performed
with the following conditions:
• After the Board is Operated at Full Load and Minimum
Line Input Voltage for 30 Minutes
• At an Ambient Temperature of 25°C, Open Frame,
and without Forced Air Flow
a PM3000A Power Meter
• The Output Voltage is Measured Using a HP34401A
Multimeter
• The Output Current is Set Using a PLZ1003WH
Electronic Load
• The Output Current is Measured Using a HP34401A
Multimeter
• The Output Power is Calculated by Multiplying the
Output Voltage and Output Current
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AND8396/D
0.7
12
0.6
HARMONIC CURRENT (A)
14
Pout = 50 W
THD (%)
10
8
6
Pout = 100 W
4
2
0.5
Pin = 75 W
0.4
0.3
IEC61000−3−2 Class D Limits
0.2
0.1
0
0
80
130
180
230
1
280
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Vin (Vac)
Nth HARMONIC
Figure 23. THD vs. Input Voltage
Figure 24. Individual Harmonic Current
100
1.00
0.99
Pout = 100 W
0.98
98
Pout = 50 W
EFFICIENCY (%)
0.97
0.96
PF
115 Vac 60 Hz
230 Vac 50 Hz
0.95
0.94
0.93
96
Pout = 100 W
94
Pout = 50 W
92
0.92
0.91
0.90
90
80
115
150
185
220
255
290
80
115
150
185
220
255
Vin (Vac)
Vin (Vac)
Figure 25. PF vs. Input Voltage
Figure 26. Efficiency vs. Input Voltage
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290
AND8396/D
Input Current and Output Voltage
starting up the pre-converter with no load as shown in
Figure 28. The NCP1608 detects an OVP fault when Vout
reaches 421 V and restarts when Vout decreases to 410 V.
The input current and output voltage ripple are shown in
Figure 27. The overvoltage protection is observed by
Vin (50V/div)
Iin (1A/div)
Vout (10V/div, ac coupled)
Figure 27. Input Current and Output Voltage Ripple (Vin = 115 Vac 60 Hz, Iout = 250 mA)
VCC (10V/div)
VDRV (10V/div)
Vout (100V/div)
Vin (100V/div)
Figure 28. Startup Transient Showing OVP Detection and Recovery (Vin = 115 Vac 60 Hz, Iout = 0 mA)
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AND8396/D
Frequency Response
crossover frequency is 2 Hz and the phase margin is 71°.
Figure 30 shows that at maximum input voltage, the
crossover frequency is 10 Hz and the phase margin is 53°.
100
150
80
120
60
90
Phase
GAIN (dB)
40
Phase Margin
20
60
30
0
0
−30
−20
Gain
−40
−60
PHASE (degrees)
The frequency response is measured at the minimum and
maximum input voltages and maximum output power.
Figure 29 shows that at minimum input voltage, the
−90
−60
−80
−100
1
fCROSS
10
FREQUENCY (Hz)
−120
−150
100
Figure 29. Frequency Response Vin = 85 Vac 60 Hz Iout = 250 mA
100
150
80
120
60
GAIN (dB)
40
Phase Margin
20
60
30
0
0
Gain
−20
−30
−40
−60
−60
−90
−80
−100
−120
1
10
PHASE (degrees)
90
Phase
−150
100
fCROSS
FREQUENCY (Hz)
Figure 30. Frequency Response Vin = 265 Vac 50 Hz Iout = 250 mA
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AND8396/D
Floating Pin Protection (FPP) Jumper
The demonstration board includes a jumper (J1) between
the FB pin and the feedback network to demonstrate the FPP
feature of the NCP1608. If J1 is removed before applying the
line input voltage, the drive is never enabled as shown in
Figure 31. If J1 is removed during operation, the drive is
disabled as shown in Figure 32. J1 is for FPP demonstration
purposes only and should not be included in manufactured
systems.
Vin (100V/div)
VCC (5V/div)
VDRV (5V/div)
Vout (100V/div)
No DRV Pulses
Figure 31. Startup with Jumper Removed (Vin = 265 Vac 50 Hz, Iout = 0 mA)
t(4ms/div)
Vin (100V/div)
DRV Pulses Stop
Vout (100V/div)
VCC (5V/div)
VDRV (5V/div)
t(8μs/div)
(Zoomed In)
Figure 32. Removing the Jumper During Operation (Vin = 265 Vac 50 Hz, Iout = 250 mA)
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AND8396/D
The demonstration board can be configured for THD
reduction or power dissipation reduction. Table 3 shows the
configuration results.
Table 3. DEMONSTRATION BOARD CONFIGURATION RESULTS
Efficiency (Pout = 100 W)
THD (Pout = 100 W)
Ct
(RCT = 0 W)
Shutdown Power Dissipation (VFB = 0 V)
(Vin = 265 Vac 50 Hz)
115 Vac
230 Vac
115 Vac
RCTUP
60 Hz
50 Hz
60 Hz
50 Hz
open
1 nF
224 mW
93.5%
95.7%
8.4%
12.5%
1.5 MW
1.22 nF
294 mW
93.5%
95.5%
4.4%
6.2%
Safety Precautions
230 Vac
The demonstration board includes the following
unpopulated footprints to enable user experimentation:
1. CCS to add a decoupling capacitor to the CS pin.
2. CZCD to add a decoupling capacitor to the ZCD
pin.
3. DDRV to add a diode for faster turn off of Q1.
4. DVCC to add a diode to clamp VCC.
5. ROUT2B to add a resistor for a more accurate
output voltage.
6. RS3 to add a resistor for a more accurate inductor
peak current limit or to reduce the heating of the
current sense resistors.
Since the FPP feature is only intended to protect the
system in the case of a floating FB pin, care must be taken
when removing the jumper. Do not attach any wires to the
jumper pins with the jumper removed. Connecting wires
to the FB pin couples excessive noise to the FB pin. This
prevents the correct operation of FPP and causes maximum
power to be delivered to the output. This can cause excessive
voltage to be applied to Cbulk. Always wear proper eye
protection when the jumper is removed.
The jumper is located next to high voltage components.
Do not remove the jumper during operation with bare
fingers or non-insulated metal tools.
Summary
Layout Considerations
A universal input voltage 100 W converter is designed
using the boost topology. The converter is implemented with
the NCP1608. Over the input voltage range and with an
output power of 100 W, the PF, THD, and efficiency are
measured as greater than 0.97, less than 8%, and greater than
92% respectively. The converter complies with
IEC61000−3−2 Class D limits for an input power of 75 W.
The converter is stable over the input voltage range with
a measured phase margin greater than 50 degrees. Finally,
the overvoltage protection and floating pin protection
features protect the converter from excessive output voltage.
The demonstration board is designed to showcase the
features and flexibility of the NCP1608. This design is
a guideline only and does not guarantee performance for any
manufacturing or production purposes.
Careful consideration must be given to the placement of
components during layout of switching power supplies.
Noise generated by the large voltages and currents can be
coupled to the pins of the NCP1608. The following
guidelines reduce the probability of excessive coupling:
1. Place the following components as close as
possible to the NCP1608:
a. Ct capacitor
b. VCC decoupling capacitor
c. Control pin compensation components
2. Minimize trace length, especially for high current
loops.
3. Use wide traces for high current connections.
4. Use a single point ground connection between
power ground and signal ground.
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AND8396/D
Appendix 1: BILL OF MATERIALS (BOM)*
Description
Value
Tolerance
Manufacturer
Manufacturer
Part Number
Designator
Qty
BRIDGE
1
Bridge Rectifier, 4 A, 600 V
−
−
Vishay
KBL06−E4/51
C1, C2
2
Capacitor, EMI Suppression, 305 Vac
0.47 mF
20%
EPCOS
B32923C3474M
C3
1
Capacitor, Ceramic, SMD, 50 V
8.2 nF
5%
TDK Corporation
C3216C0G1H822J
CBULK
1
Capacitor, Electrolytic, 450 V
68 mF
20%
United Chemi−Con
EKXG451ELL680MMN3S
CCOMP
1
Capacitor, Ceramic, SMD, 25 V
0.68 mF
10%
TDK Corporation
C3216X7R1E684K
CCOMP1
1
Capacitor, Ceramic, SMD, 25 V
3.3 mF
10%
TDK Corporation
C3216X7R1E335K
CCS, CZCD
2
Capacitor, Ceramic, SMD
open
−
−
−
CIN
1
Capacitor, EMI Suppression, 305 Vac
0.1 mF
20%
EPCOS
B32921A2104M
CT1
1
Capacitor, Ceramic, SMD, 50 V
1 nF
10%
Yageo
CC1206KRX7R9BB102
CC1206KRX7R9BB221
CT2
1
Capacitor, Ceramic, SMD, 50 V
220 pF
10%
Yageo
CVCC
1
Capacitor, Electrolytic, 25 V
47 mF
20%
Panasonic
EEU−FC1E470
CVCC2
1
Capacitor, Ceramic, SMD, 50 V
0.1 mF
10%
Yageo
CC1206KRX7R9BB104
D1
1
Diode, Switching, 100 V
−
−
ON Semiconductor
MMSD4148T1G
DAUX
1
Diode, Zener, 18 V
−
−
ON Semiconductor
MMSZ4705T1G
DBOOST
1
Diode, Ultrafast, 4 A, 600 V
−
−
ON Semiconductor
MUR460RLG
DDRV
1
Diode, Switching
open
−
−
−
DVCC
1
Diode, Zener
open
−
−
−
F1
1
Fuse, SMD, 2 A, 600 V
−
−
Littelfuse
0461002.ER
J1
1
Header 1 Row of 2, 100 mil
−
−
3M
929400−01−36−RK
J2, J3
2
Connector, 156 mil 3 pin
−
−
MOLEX
26−60−4030
L1
1
Inductor, Radial, 4 A
180 mH
10%
Coilcraft
PCV−2−184−05L
L2
1
Line Filter, 2.7 A
4.7 mH
−
Panasonic
ELF−20N027A
LBOOST
1
Inductor, 400 mH, NB:NZCD = 10:1
−
−
Coilcraft
JA4224−AL
MECHANICAL
1
Shorting Jumper
−
−
3M
929955−06
MECHANICAL
1
Heatsink
−
−
Aavid
590302B03600
MECHANICAL
1
Screw, Phillips, 4−40, 1/4″, Steel
−
−
Building Fasteners
PMSSS 440 0025 PH
MECHANICAL
1
Nut, Hex 4−40, Steel
−
−
Building Fasteners
HNSS440
MECHANICAL
1
Shoulder Washer #4, Nylon
−
−
Keystone
3049
MECHANICAL
1
TO−220 Thermal Pad, 9 mil
−
−
Wakefield
173−9−240P
MECHANICAL
4
Standoffs, Hex 4−40, 0.75″, Nylon
−
−
Keystone
4804K
MECHANICAL
4
Nut, Hex 4−40, Nylon
−
−
Building Fasteners
NY HN 440
NTC
1
Thermistor, Inrush Current Limiter
4.7 W
20%
EPCOS
B57238S479M
Q1
1
MOSFET, N−Channel, 11.6 A, 560 V
−
−
Infineon
SPP12N50C3
R1
1
Resistor, SMD
100 W
1%
Vishay
CRCW1206100RFKEA
RCOMP1
1
Resistor, SMD
20 kW
1%
Vishay
CRCW120620K0FKEA
RCS
1
Resistor, 0.25 W Axial
510 W
5%
Yageo
CFR−25JB−510R
RCT
1
Resistor, SMD
0W
−
Vishay
CRCW12060000Z0EA
RCTUP1,
RCTUP2
2
Resistor, 0.25 W Axial
750 kW
5%
Yageo
CFR−25JB−750K
RDRV
1
Resistor, SMD
10 W
1%
Vishay
CRCW120610R0FKEA
RO1A, RO1B
2
Resistor, SMD
2 MW
1%
Vishay
CRCW12062M00FKEA
ROUT2A
1
Resistor, SMD
25.5 kW
1%
Vishay
CRCW120625K5FKEA
ROUT2B
1
Resistor, SMD
open
−
−
−
RS1, RS2
2
Resistor, SMD, 1 W
0.25 W
1%
Vishay
WSL2512R2500FEA
RS3
1
Resistor, SMD
open
−
−
−
RSTART1,
RSTART2
2
Resistor, 0.25 W Axial
330 kW
5%
Yageo
CFR−25JB−330K
RZCD
1
Resistor, 0.25 W Axial
100 kW
5%
Yageo
CFR−25JB−100K
U1
1
CrM PFC Controller
NCP1608
−
ON Semiconductor
NCP1608BDR2G
*All products listed are Pb−Free.
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20
AND8396/D
Appendix 2: LAYOUT
Figure 33. Top View of the Layout
Figure 34. Bottom View of the Layout
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AND8396/D
Appendix 3: SUMMARY OF BOOST EQUATIONS Components are identified in Figure 3
P out
h @ Vac
h (the efficiency of only the PFC
stage) is generally in the range of
90−95%. Vac is the rms ac line input
voltage.
Ǹ2 @ 2 @ P
out
h @ Vac
The maximum inductor peak current
occurs at the minimum line input
voltage and maximum output power.
Input rms Current
Iac +
Inductor Peak Current
I L(peak) +
Inductor Value
Vac 2 @
Lv
ǒ
Ǔ
Ǹ2 @ V @ P @ f
out
out
SW(MIN)
On Time
t on +
Vout
[email protected] [email protected]
ǒ
Ct w
Output Voltage and
Output Divider
V out * ǒǸ2 @ Vac HLǓ
Ǹ2 @ Vac
HL
I ZCD(MAX) @ (N B : N ZCD)
ǒ
R FB @
Output Voltage Ripple and
Output Capacitor Value
Ǔ
ǒǒ
ǒ
R out1 @ R FB
Vout
VREF
Ǔ
* 1 * R out1
ǒ
Ǔ
VOVP
V REF
Ǔǒ
Ǔ
@ V REF −V OVP(HYS) @ R out1 @
R out2 ) R FB
R out2 @ R FB
V ripple(peak−peak) t 2 @ ǒV out(OVP) * V outǓ
I C(RMS) +
Where VREF is the internal
reference voltage and RFB is the
pull-down resistor used for FPP.
VREF and RFB are shown in the
specification table. Ibias(out) is the
bias current of the output voltage
divider.
R out2 ) R FB
)1
R out2 @ R FB
V OVP
R
) R FB
@ V REF @ R out1 @ out2
)1
V REF
R out2 @ R FB
C bulk w
Output Capacitor rms
Current
Where IZCD(MAX) is maximum rated
current for the ZCD pin (10 mA).
V out
I bias(out)
R out2 +
V out(OVPL) +
Where VacHL is the maximum line
input voltage. VZCD(ARM) is shown in
the specification table.
V ZCD(ARM)
V out + V REF @ R out1 @
V out(OVP) +
Where VacLL is the minimum line
input voltage and LMAX is the
maximum inductor value. Icharge and
VCt(MAX) are shown in the
specification table.
h @ Vac LL 2 @ V Ct(MAX)
R ZCD w
R out1 +
Output Voltage OVP
Detection and Recovery
Ǔ
2 @ P out @ L MAX @ I charge
N B : N ZCD v
Resistor from ZCD
Winding to the ZCD pin
*1
Vac 2 @ h
Vac @ |sin q| @ Ǹ2
@ 1*
2 @ L @ P out
V out
On Time Capacitor
Inductor Turns to ZCD
Turns Ratio
The off time is a maximum at the
peak of the ac line voltage and
approaches zero at the ac line zero
crossings. Theta (q) represents the
angle of the ac line voltage.
t on
t off +
f SW +
The maximum on time occurs at the
minimum line input voltage and
maximum output power.
2 @ L @ P out
h @ Vac 2
Off Time
Switching Frequency
fSW(MIN) is the minimum desired
switching frequency. The maximum
L is calculated at both the minimum
line input voltage and maximum line
input voltage.
V out
* Vac @ h
Ǹ2
P out
2 @ p @ V ripple(peak−peak) @ f line @ V out
Ǹ
Ǹ2 @ 32 @ P 2
out
* I load(RMS) 2
9 @ p @ Vac @ V out @ h 2
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22
VOVP/VREF and VOVP(HYS) are
shown in the specification table.
Ǔ
)1
Where fline is the ac line frequency
and Vripple(peak-peak) is the
peak-to-peak output voltage ripple.
Use fline = 47 Hz for universal input
worst case.
Where Iload(RMS) is the rms load
current.
AND8396/D
Appendix 3: SUMMARY OF BOOST EQUATIONS Components are identified in Figure 3 (Continued)
Output Voltage UVP
Detection
ǒ
V out(UVP) + V UVP @ R out1 @
Inductor rms Current
Output Diode rms
Current
MOSFET rms Current
I L(RMS) +
I D(RMS) + 4 @
3
ǒ
ǸǸ2p@ 2 @
Ǔ
Ǹ
R sense +
PR
Type 1 Compensation
sense
R out2 @ R FB
Ǔ
)1
VUVP is shown in the specification
table.
2 @ P out
Ǹ3 @ Vac @ h
P out
I M(RMS) + 2 @
@
Ǹ3
h @ Vac
Current Sense Resistor
R out2 ) R FB
P out
h @ ǸVac @ V out
1*
ǒ
Ǹ2 @ 8 @ Vac
3 @ p @ V out
Ǔ
V ILIM
I L(peak)
VILIM is shown in the specification
table.
+ I M(RMS) 2 @ R sense
gm
C COMP +
2 @ p @ f CROSS
Where fCROSS is the crossover
frequency and is typically less than
20 Hz. gm is shown in the
specification table.
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AND8396/D