3A Ultra-Small Controlled Load Switch with Auto Discharge Path

NCP436, NCP437
3A Ultra-Small Controlled
Load Switch with
Auto-Discharge Path
The NCP436 and NCP437 are very low Ron MOSFET controlled
by external logic pin, allowing optimization of battery life, and
portable device autonomy.
Indeed, due to a current consumption optimization with PMOS
structure, leakage currents are eliminated by isolating connected IC on
the battery when not used.
Output discharge path is also embedded to eliminate residual
voltages on the output rail for the NCP437 part only.
Proposed in a wide input voltage range from 1.0 V to 3.6 V, in a
small 1 x 1.5 mm WLCSP6, pitch 0.5 mm.
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MARKING DIAGRAM
A
Y
W
G
Features
•
•
•
•
•
•
•
XXX
AYW
G
WLCSP6
CASE 567FH
1.0 V − 3.6 V Operating Range
20 mW P MOSFET at 3.6 V
DC Current Up to 3 A
Output Auto−discharge
Active High EN Pin
WLCSP6 1 x 1.5 mm
These are Pb−Free Devices
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN DIAGRAM
A
OUT
IN
B
OUT
IN
C
GND
EN
Typical Applications
•
•
•
•
•
Mobile Phones
Tablets
Digital Cameras
GPS
Portable Devices
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
V+
LS
NCP437
DCDC Converter
A2
B2
LDO
EN
OUT
OUT
Platform IC’n
B1
C1
C2
A1
IN
IN
GND
or
ENx
EN
0
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 1
1
Publication Order Number:
NCP436/D
NCP436, NCP437
PIN FUNCTION DESCRIPTION
Pin Name
Pin Number
Type
Description
IN
A2, B2
POWER
Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as
close as possible to the IC.
GND
C1
POWER
Ground connection.
EN
C2
INPUT
OUT
A1, B1
OUTPUT
Enable input, logic high turns on power switch.
Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as
possible to the IC is recommended.
BLOCK DIAGRAM
IN: Pin A2, B2
OUT: Pin A1, B1
Gate driver and soft
start control
Control
logic
EN: Pin C2
Optional: NCP437
EN block
GND: Pin C1
Figure 2. Block Diagram
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2
NCP436, NCP437
MAXIMUM RATINGS
Symbol
Value
Unit
−0.3 to + 4
V
0 to + 4
V
−40 to + 125
°C
Human Body Model (HBM) ESD Rating are (Notes 2 and 3)
8000
V
Machine Model (MM) ESD Rating are (Notes 2 and 3)
250
V
Charge Device Model (CDM) ESD Rating are (Notes 2 and 3)
2000
V
LU
Latch−up Protection (Note )
− Pins IN, OUT, EN
100
mA
TSTG
Storage Temperature Range
−40 to + 150
°C
MSL
Moisture Sensitivity (Note 2)
Level 1
VEN , VIN,
VOUT
VIN ,
VOUT
TJ
ESD
HBM
ESD MM
ESD
CDM
Rating
IN, OUT, EN, Pins: (Note 1)
From IN to OUT Pins: Input/Output (Note 1)
Maximum Junction Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108.
2. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
3. This device series contains ESD protection and passes the following tests
Human Body Model (HBM) ±8.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins.
Charge Device Model (CDM) ±2.0 kV per JEDEC standard: JESD22−C101 for all pins.
4. Latch−up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 Class II.
OPERATING CONDITIONS
Symbol
Parameter
VIN
Operational Power Supply
VEN
Enable Voltage
Conditions
Min
Typ
Max
Unit
1.0
3.6
V
0
3.6
TA
Ambient Temperature Range
−40
25
+85
°C
TJ
Junction Temperature Range
−40
25
+125
°C
CIN
Decoupling input capacitor
1
mF
COUT
Decoupling output capacitor
1
mF
RqJA
Thermal Resistance Junction to Air
IOUT
Maximum DC current
PD
Power Dissipation Rating (Note 6)
WLCSP package (Note 5)
°C/W
100
3
A
TA ≤ 25°C
WLCSP package
0.66
W
TA = 85°C
WLCSP package
0.26
W
5. The RqJA is dependent of the PCB heat dissipation and thermal via.
6. The maximum power dissipation (PD) is given by the following formula:
PD +
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3
T JMAX * T A
R qJA
NCP436, NCP437
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C for VIN between 1.0 V to 3.6 V
(Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 3.3 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
15
26
Unit
POWER SWITCH
I = 200 mA, 25°C
VIN = 3.6 V
I = 200 mA, TA = 85°C
28
TJ = 125°C
29
I = 200 mA, 25°C
VIN = 2.5 V
RDS(on)
Static drain−source on−state
resistance
18
I = 200 mA, TA = 85°C
32
TJ = 125°C
35
I = 200 mA, 25°C
23
I = 200 mA, Full Ta
VIN = 1.8 V
TJ = 125°C
Rdis
Output discharge path
VIH
High−level input voltage
VIL
Low−level input voltage
40
44
45
80
I = 200 mA, Full Ta
84
TJ = 125°C
85
VIN = 1.1 V
I = 200 mA, 25°C
VIN = 3.3 V
EN = low
mW
42
I = 200 mA, 25°C
VIN = 1.2 V
30
62
50
65
90
W
1.1
0.5
V
QUIESCENT CURRENT
Istd
Standby current
VIN = 3.3 V
EN = low, No load
0.01
0.6
Iq
Quiescent current
VIN = 3.3 V
EN = high, No load
0.2
0.6
mA
TIMINGS
TEN
Enable time
RL = 25 W, COUT = 1 mF
20
39
55
TR
Output rise time
RL = 25 W, COUT = 1 mF
10
25
40
RL = 25 W, COUT = 1 mF
30
64
95
TON
ON time (TEN + TR)
TDIS
Disable time
TF
VIN = 3.6 V
(Note 8)
RL = 25 W, COUT = 1 mF
NCP437. RL = 25 W,
COUT = 1 mF
Output fall time
20
20
7. Guaranteed by design and characterization
8. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground
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4
55
80
ms
NCP436, NCP437
TIMINGS
VIN
EN
VOUT
TEN
TDIS
TR
TF
TOFF
TON
Figure 3. Enable, Rise and Fall Time
FUNCTIONAL DESCRIPTION
Overview
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path (Pull down NMOS) stays activated as
long as EN pin is set at low level and VIN > 1.2 V.
In order to limit the current across the internal discharge
N−MOSFET, the typical value is set at 65 W.
The NCP437 is a high side P channel MOSFET power
distribution switch designed to isolate ICs connected on the
battery in order to save energy. The part can be turned on,
with a wide range of battery from 1.0 V to 3.6 V.
Enable Input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing P MOS switch off.
The IN/OUT path is activated with a minimum of VIN of
1.2 V and EN forced to high level.
CIN and COUT Capacitors
IN and OUT, 1 mF, at least, capacitors must be placed as
close as possible the part to for stability improvement.
Auto Discharge
NMOS FET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
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NCP436, NCP437
APPLICATION INFORMATION
TJ + RD
Power Dissipation
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
equations:
P D + R DS(on)
PD
RDS(on)
IOUT
ǒIOUTǓ
TJ
RqJA
TA
R qJA ) T A
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
PCB Recommendations
2
The NCP437 integrates an up to 3 A rated PMOS FET, and
the PCB design rules must be respected to properly evacuate
the heat out of the silicon. By increasing PCB area,
especially around IN and OUT pins, the RqJA of the package
can be decreased, allowing higher power dissipation.
Routing example: 2 oz, 4 layers with vias across two
internal inners.
= Power dissipation (W)
= Power MOSFET on resistance (W)
= Output current (A)
Figure 4.
Example of application definition.
T J * T A + R qJA
P D + R qJA
R DS(on)
At 3 A, 25°C ambient temperature, RDS(on 20 mW @ VIN
5 V, the junction temperature will be:
I2
T J + R qJA
TJ: Junction Temperature.
TA: Ambient Temperature.
Rq = Thermal resistance between IC and air, through PCB.
RDS(on): Intrinsic resistance of the IC MOSFET.
I: Load DC current.
P D + 25 ) ǒ0.02
3 2Ǔ
100 + 43° C
Taking into account of Rq obtain with:
• 2 oz, 4 layers: 60°C/W.
At 3 A, 65°C ambient temperature, RDS(on) 24 mW @ VIN
5 V, the junction temperature will be:
Taking into account of Rq obtain with:
• 1 oz, 2 layers: 100°C/W.
TJ + TA ) Rq
P D + 65 ) ǒ0.024
3 2Ǔ
60 + 78° C
ORDERING INFORMATION
Marking
Option
Package
Shipping†
NCP437FCT2G
AR
Auto discharge
WLCSP 1 x 1.5 mm
(Pb−Free)
3000 / Tape & Reel
NCP436FCT2G
AQ
Without Auto discharge
WLCSP 1 x 1.5 mm
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NCP436, NCP437
PACKAGE DIMENSIONS
WLCSP6, 1.00x1.50
CASE 567FH
ISSUE O
ÈÈ
ÈÈ
D
PIN A1
REFERENCE
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
E
DIM
A
A1
A2
b
D
E
e
0.05 C
2X
0.05 C
2X
TOP VIEW
A2
0.05 C
RECOMMENDED
SOLDERING FOOTPRINT*
A
0.05 C
NOTE 3
PACKAGE
OUTLINE
A1
A1
SIDE VIEW
MILLIMETERS
MIN
MAX
0.54
0.63
0.22
0.28
0.33 REF
0.29
0.34
1.00 BSC
1.50 BSC
0.50 BSC
C
SEATING
PLANE
eD/2
6X
eD
b
0.05 C A B
eE
0.50
PITCH
C
6X
0.25
0.50
PITCH
0.03 C
B
DIMENSIONS: MILLIMETERS
A
1 2 3
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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NCP436/D