Designing a Quasi‐Resonant Adaptor Driven by the NCP1339

AND9176/D
Designing a Quasi‐Resonant
Adaptor Driven by
the NCP1339
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APPLICATION NOTE
Quasi-square wave resonant converters also known as
Quasi-Resonant (QR) converter are widely used in the
adaptor market. They allow designing flyback
Switched-Mode Power Supply (SMPS) with reduced
Electro-Magnetic Interference (EMI) signature and
improved efficiency. However, a major drawback of the
structure is that the frequency can become dramatically high
at light load.
In traditional QR converters, the frequency is limited by
a frequency clamp. But, when the switching frequency of the
system reaches the frequency clamp limit, valley jumping
occurs: the controller hesitates between two valleys
resulting in an instable operation and noise in the
transformer at medium and light output loads.
In order to overcome this problem, the NCP1339 features
a proprietary “valley lockout” circuit: the switching
frequency is decreased step by step by changing valley from
valley n to valley (n+1) as the load decreases. Once the
controller selects a valley, it stays locked in this valley until
the output power changes significantly. This technique
extends the QR operation of the system towards lighter loads
without degrading the efficiency.
In addition, in order to limit the stand-by consumption,
the NCP1339 integrates an HV current source that charges
the VCC capacitor during start-up phase and an automatic
X2-capacitor discharge circuitry that saves the need for
power-consuming discharge resistors across the front-end
filtering capacitors.
This application note focuses on the design of an adapter
driven by the NCP1339.
The equations developed are further used to design
a 45-W adapter.
Vout
Vaux
+
+
+
GND
PSM_OFF
NCP1339C
X2
1
14
REM
2
13
3
12
4
11
5
10
6
9
7
8
N
EMI
FILTER
FB
L1
VCC
GND
CS
+
+
Rsense
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 0
1
Publication Order Number:
AND9176/D
AND9176/D
INTRODUCTION
The NCP1339 implements a standard quasi-resonant
current-mode architecture. This component represents the
ideal candidate where low part-count and cost effectiveness
are the key parameters, particularly in low-cost ac-dc
adapters, open-frame power supplies etc. The NCP1339
brings all the necessary components normally needed in
modern power supply designs, bringing several
enhancements such as non-dissipative OPP, brown-out
protection or sophisticated frequency reduction
management for an optimized efficiency over the power
range. Accounting for the new needs of extremely low
standby power requirements, the part includes an automatic
X2-capacitor discharge circuitry which can save the
power-consuming resistors otherwise needed across the
front-end filtering capacitors. The controller is also able to
enter Power Savings Mode (PSM) that is, a deep sleep mode
via its dedicated remote (“REM”) pin.
• High-Voltage Start-Up: low standby power results
cannot be obtained with the classical resistive start-up
network. In this part, a high-voltage current-source
provides the necessary current at start-up and turns off
afterwards.
• Internal Brown-Out Protection: the bulk voltage is
internally sensed via the high-voltage pin monitoring
(pin 14). When Vpin14 is too low, the part stops pulsing.
No re-start attempt is made until Vpin14 recovers its
normal range. At that moment, the brown-out
comparator sends a general reset to the controller
(de-latch occurs) and authorizes to re-start.
• X2-Capacitors Discharge Capability: per IEC-950
standard, the time constant of the front-end filter
capacitors and their associated discharge resistors must
be less than 1 s. This is to avoid electrical stress when
users unplug the converter and inadvertently touch the
power cord terminals. The circuitry for discharging the
X2 capacitors can save the need for discharge resistors,
helping to further save power.
• PSM Control: a dedicated pin allows the IC to enter
a deep sleep mode when the REM input pin is brought
above a certain level. This option offers an efficient
means to operate the adapter in a power savings mode
and draw the least input power from the mains in this
mode. When the REM is actively pulled down via
a dedicated optocoupler, the adapter immediately
re-starts. The component that controls PSM is then
active in normal operation (active-ON) and OFF in
PSM (wasting no energy).
• Quasi-Resonant, Current-Mode Operation: QR
operation is an efficient mode where the MOSFET
turns on when its drain-source is at the minimum
(valley). However, at light load, the switching
frequency tends to get high. The NCP1339 valley
lock-out and frequency foldback technique eliminate
•
•
•
•
•
•
•
this drawback so that the efficiency remains at the
highest over the power range.
Valley Lockout: a continuous flow of pulses is not
compatible with no-load/light-load standby power
requirements. To excel in this domain, the controller
observes the feedback pin voltage (FB) and when it
reaches a level of 1.4 V, the circuit enters a valley
lockout mode where the circuit skips a valley. If FB
further decreases, more valleys are skipped until 6th
valley is reached.
Frequency Fold-Back: if FB continues declining and
reaches 0.8 V, the current setpoint is frozen to Vfreeze
and the circuit regulates by modulating the switching
frequency until it reaches 25 kHz (typically).
Skip Cycle: to avoid acoustic noise, the circuit prevents
the switching frequency from decaying below 25 kHz.
Instead, the circuit contains the power delivery by
entering skip cycle mode when the system would
otherwise need to further lower the switching frequency
below 25 kHz.
Internal OPP (Over Power Protection): by routing
a portion of the negative voltage present during the
on-time on the auxiliary winding to the OPP pin
(pin 3), the user has a simple and non-dissipative means
to alter the maximum current setpoint as the bulk
voltage increases. If the pin is grounded, no OPP
compensation occurs.
Internal Soft-Start: a 4-ms soft-start precludes the
main power switch from being stressed upon start-up.
It is activated whenever a startup sequence occurs
including autorecovery hiccup.
Fault Input: the NCP1339 includes a dedicated fault
input (pin 5). It can be used to sense an overvoltage
condition and latch off the controller by pulling up the
pin above the upper fault threshold, VFault(OVP),
typically 3.0 V. The controller is also disabled if the
Fault pin voltage, VFault, is pulled below the lower fault
threshold, VFault(OTP_in), typically 0.4 V. The lower
threshold is normally used for detecting an
overtemperature fault (by the means of an NTC).
Short-Circuit/Overload Protection: short-circuit and
especially overload protections are difficult to
implement when a strong leakage inductance between
auxiliary and power windings affects the transformer
(the aux winding level does not properly collapse in
presence of an output short). Here, every time the
internal 0.8-V maximum peak current limit is activated
(or less when OPP is used), an error flag is asserted and
a 160-ms timer begins counting. When the timer has
elapsed, the fault is validated. Please note that the
NCP1339C offers an low duty-cycle (< 10%),
auto-recovery mode.
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AND9176/D
SPECIFICATIONS OF THE ADAPTER
In order to illustrate this application note, a 19-V, 45-W
adapter will be the design example. The specifications are
detailed in Table 1.
The experimental results of the 45-W adapter are detailed
in the evaluation board user’s manual EVBUM2248 [1].
For details concerning the QR transformer calculation,
you can refer to the tutorial TND348 [2].
Table 1. SPECIFICATIONS OF THE 19-V, 45-W
ADAPTER
Symbol
Value
Minimum Input Voltage
Parameter
Vin,min
85 Vrms
Maximum Input Voltage
Vin,max
265 Vrms
Output Voltage
Nominal Output Power
Switching Frequency at Vin,min,
Pout(nom)
Maximum Startup Time
Vout
19 V
Pout(nom)
45 W
Fsw
45 kHz
Tstartup
<1s
PREDICTING THE SWITCHING FREQUENCY
As the controller changes valley as the load decreases,
the switching frequency of the power supply is naturally
limited by the valley lockout. But equations are needed to
predict the switching frequency evolution with respect with
the output power.
The datasheet gives the FB thresholds at which the
controller transitions from valley n to valley (n+1), Pout
falling and at which the controller transitions from valley
(n+1) to valley n, Pout rising.
Operating Mode
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VFB Decreases
FF
VFB Increases
Valley 6
Valley 5
Valley 4
Fault!
Valley 3
Valley 2
Valley 1
0.8
0.9
1.0
1.1
1.2
1.4
1.5
1.6
1.7
1.8
2.0
3.2
VFB (V)
Figure 2. Operating Valley According to FB Voltage
With these thresholds, we can calculate the maximum
switching frequency inside each valley depending if the
output power decreases or increases:
F SW +
ǒ
V FB
4R sense
) V in,rms @ Ǹ2 @
t prop
Lp
Ǔ
@ Lp @
ǒ
1
1
V in,[email protected]
Where:
• VFB is the FB threshold at which the controller changes
valley
• Rsense is the sense resistor value
• Vin,rms is the rms value of the input voltage
• tprop is the propagation delay
• Lp is the primary inductance
)
N ps
Ǔ
V out)V f
) (2n * 1) @ p @ ǸL p @ C lump
(eq. 1)
• Vout is the output voltage
• Vf is the forward voltage drop of the output diode
• Clump regroups all capacitances surrounding the drain
node (MOSFET capacitor, transformer parasitics…).
As a first approximation, the MOSFET drain-source
capacitance COSS can be used instead of Clump.
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AND9176/D
ǒ
• n is an integer representing the operating valley: n = 1
•
•
t prop
V FB
1
P out + L p @
) V in,rms Ǹ2
2
4R sense
Lp
for 1st valley, n = 2 for 2nd valley, n = 3 for 3rd valley
and n = 4 for the 4th valley, n = 5 for 5rd valley and
n = 6 for the 6th valley.
NPS is the NS/NP turns ratio where NS and NP
respectively, are the secondary and primary number of
turns.
Tprop is the propagation delay between the moment
when the MOSFET current exceeds the setpoint target
and the actual MOSFET turn off.
6th 5th 4th
3rd
2
sw
h (eq. 2)
Using the previous equations, we can calculate the
maxima of the switching frequency and the corresponding
output power for our 45-W adapter.
In order to help the power supply designer, the previous
equations have been entered inside a Mathcad spreadsheet
that automatically predicts the evolution of the switching
frequency as a function of the output power (Figure 3).
For more calculation details, please refer to the Mathcad
file on website.
The corresponding output power can be calculated using
the traditional formula:
1.2×105
Ǔ @F
2nd
1st
VCO
mode
1×105
FSW (Hz)
8×104
6×104
6th
5th 4th
3rd
2nd
1st
4×104
VCO
mode
2×104
0
0
10
20
30
40
POUT (W)
Figure 3. Switching Frequency vs. Output Power at Vin = 115 Vrms
FREQUENCY FOLDBACK MODE
Operating Details
MOSFET turn on until the 6th valley is detected. Hence,
there is no discontinuity and the frequency smoothly reduces
as FB goes below 0.8 V. The ramp slope is proportional to
the FB voltage. Practically, the circuit embeds a current
source that depends on the FB pin voltage: Isource = FB / R
where R is an internal resistor. A second current
Isink = (0.4 V / R) is subtracted to the first current so that
(Isource − Isink = (FB −0.4 V) / R) charges the ramp. When
the ramp reaches an internal threshold, the dead-time is
finished and a clock is generated so that a new DRV pulse
can be generated.
At nominal power, the power supply operates in a variable
frequency system where discrete frequency steps occur as
the controller looks for the different valley positions.
At low output power, the controller enters a Frequency
Foldback (FF) mode. This mode is entered when VFB drops
below 0.8 V. The controller remains in this mode until VFB
increases above 1 V. During the FF operation (VFB < 0.8 V),
the peak current is frozen to 25% of its maximum value and
the frequency diminishes as the output power decreases. To
reduce the switching frequency, the system adds some
dead-time controlled by a ramp. The ramp is grounded from
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AND9176/D
VFB
Vdrain
Ipk_max
Idrain
Freeze Peak Current (25% of Ipk_max)
FF Ramp
Lower FB Voltage
→ Lower Slope
Figure 4. VFB, Idrain, Vdrain, FF Ramp, at Different Output Loads in VCO Mode
ZERO CROSSING DETECTION
The NCP1339 integrates the inductor reset (or Zero
Current) detection (ZCD). ZCD is achieved by observing
the auxiliary winding voltage (VAUX).
ZCD
+
−
+
The VAUX positive part (when the MOSFET is off) is used
for zero crossing detection. The schematic of the
zero-crossing detection block is shown in Figure 5.
COMP
DEMAG
VZCD(th)
Minimum
Frequency
QR
Logic
TEB
Timeout
Blanking
Time TZCD(blank)
Soft-Start
Complete
DRV
(Internal)
Steady State
Timeout
(tout2) R
Steady State
Timeout
(tout1) R
Figure 5. Zero-crossing Detection Bloc Schematic
timeout was used in this condition, a DRV pulse would be
generated every 6 ms. This delay is generally too short that
leads to a continuous conduction mode operation (CCM)
when the power supply enters operation. To cope with this
situation (that only lasts for a few cycles until the voltage on
ZCD pin becomes high enough to be detected by the ZCD
comparator), the time-out duration is extended to 100 ms
during the soft-start period in order to ensure that the
transformer is fully demagnetized before the MOSFET is
turned-on.
In case of extremely damped free oscillations, the ZCD
comparator can be unable to detect valleys. To avoid such
a situation, NCP1339 integrates a Time Out function that
acts as a substitute clock for the decimal counter inside the
logic block. The controller thus continues its normal
operation. To avoid having a too big step in frequency,
the time out duration is set to 6 ms.
The NCP1339 also features an extended time out during
the soft-start. Indeed, at startup, the output voltage reflected
on the auxiliary winding is low, the ZCD comparator might
be unable to detect the valleys. If the 6-ms steady-state
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AND9176/D
OVER POWER PROTECTION
Operating Details
Higher accuracy can be obtained in narrow mains
applications.
The technique implemented in the NCP1339 takes benefit
of the auxiliary winding voltage whose negative amplitude
is proportional to the input rail voltage. When the power
MOSFET is on, the auxiliary winding voltage becomes the
input voltage Vin affected by the auxiliary to primary turn
ratio (Np,aux = Naux / Np ):
The power capability of a flyback operated in Quasi
Resonance is not constant over the line range. Instead, as
suggested by Eq. 2, it dramatically increases when the input
voltage rises. Two main reasons cause this:
• The peak current is higher at high line due to the Tprop
propagation delay between the moment when the
MOSFET current reaches the target and the moment
when the MOSFET actually opens.
• The frequency is also higher at high line leading to
a higher power capability
V aux + * N p,aux @ V in
By applying this voltage through a resistor divider on the
OPP pin, we have an image of the input voltage transferred
to the controller via this pin. This voltage is added internally
to the 0.8-V reference and affects the maximum peak current
(Figure 6). As the OPP voltage is negative, an increase of
input voltage implies a decrease of the maximum peak
current setpoint:
To cope with safety requirements, the designer needs to
limit the power output capability over the input voltage
range. The NCP1339 features a function named Over Power
Protection (OPP) to contain the power variations. It
generally gives the capability of maintaining the power
deviation within ±20% in a universal mains application.
V CS,max + 0.8 ) V OPP
CS
+
LEB
Auxiliary
Winding
COPP
+
0.8 V
ROPU
(eq. 3)
(eq. 4)
PWM Latch Reset and
Overload Counter Block
−
OPP
ROPL
Figure 6. OPP Circuit
It is wise noting that this capacitor delays the OPP voltage
settling to its final value. It is then necessary to check that
this delay is shorter than the on-time at full load.
The maximum OPP voltage that can be applied to OPP pin
is –250 mV, which corresponds to peak current decrease of
31.25%.
The auxiliary winding voltage can be the seat of ringing.
Therefore, it may be needed to add a capacitor (COPP of
Figure 6) to filter the voltage.
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AND9176/D
Calculating the Needed OPP Amount for the Design
P out(high) +
Because of the propagation delay, the maximum peak
current at high line is:
I pk(high) +
0.8
R sense
) V in(max),dc @
(eq. 5)
The corresponding switching period and output power
can be deduced from Eq. 1 and Eq. 2:
T sw(high) + I pk(high) @ L p @
ǒ
1
V in(max),dc
)
Ǔ
N ps
V out ) V f
ǒ
1
V in(max),dc
)
1
2
@ L p @ I pk(high) @
T sw(high)
@h
(eq. 7)
)
(eq. 6)
) p @ ǸL p @ C lump
Lp @
2
We would like to limit the output power to Pout(limit) >
Pout(nom) at maximum input voltage. In order to perform
over power compensation, we need to calculate the peak
current Ipk(limit) corresponding to Pout(limit) .
t prop
Lp
1
Ǔ
N ps
Ǹ
)
V out)V f
ǒ
2
Lp @
1
V in(max),dc
I pk(limit) +
)
N ps
V out)V
Ǔ
2
)2@
f
L [email protected]
P out(limit)
@ p @ ǸL p @ C lump
(eq. 8)
L [email protected]
P out(limit)
The amount of OPP voltage needed is thus:
V OPP + * 0.8 @
I pk(high) +
ǒ
1*
0.8
R sense
I pk(limit)
Ǔ
(eq. 9)
I pk(max)
) V in(max),dc @
T sw(high) + I pk(high) @ L p @
ǒ
As an example, in order to provide a 25% power margin
to our 45-W adapter, we want to limit the output power to
57 W at high line.
Using equations Eq. 5 to Eq. 7, we obtain:
t prop
Lp
1
V in(max),dc
+
)
0.8
) 375 @
0.31
Ǔ
N ps
V out ) V f
600 @ 10 *9
345 @ 10 *6
+ 3.23 A
(eq. 10)
) p @ ǸL p @ C lamp +
(eq. 11)
+ 3.23 @ 345 @ 10 *6 @
P out(high) +
1
2
0.25
1
ǒ375
Ǔ ) p @ Ǹ345 @ 10
)
19 ) 0.8
1
2
@ L p @ I pk(high) @
T sw(high)
@h+
1
2
@ 345 @ 10 *6 @ 3.23 2 @
If no over power compensation is applied, the adapter will
be able to deliver 85 W at high line! In order to limit the
Lp @
ǒ
1
V in(max),dc
)
N ps
Ǔ
V out)V f
)
Ǹ
2
Lp @
ǒ
1
V in(max),dc
I pk(limit) +
)
*6 @ 250 @ 10 *12
1
18.0 @ 10 *6
+ 18.0 ms
@ 0.85 + 85 W
(eq. 12)
output power to 57 W at 265 Vrms, the peak current must be
reduced to:
N ps
V out)V
Ǔ
2
)2@
f
L [email protected]
P out(limit)
@ p @ ǸL p @ C lump
+
L [email protected]
(eq. 13)
P out(limit)
345
+
10 *6 @
0.25
1
ǒ375
Ǔ ) Ǹǒ345
)
19)0.8
10 *6Ǔ @ ǒ
2
1
375
)
0.25
19)0.8
Ǔ
2
)2@
345
10 [email protected]
57
@ p @ Ǹ345 @ 10 *6 @ 250 @ 10 *12
+
[email protected] [email protected]
57
+ 2.21 A
The amount of OPP voltage that must be applied to the
design is:
V OPP + * 0.8 @
ǒ
1*
I pk(limit)
Ǔ
I pk(max)
ǒ
+ * 0.8 @ 1 *
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2.21
3.23
Ǔ + * 253 mV
(eq. 14)
AND9176/D
Calculating the OPP Resistors
In addition, in frequency foldback mode, the switching
frequency reduces. Thus, the average current in the OPP
bridge decreases. Let us calculate the average current
circulating in the OPP bridge at light load:
Looking at Figure 6, if we apply the resistor divider law
on the pin 2 during the on-time, we obtain the following
relationship:
R opu
R opl
+
* N p,aux @ V in,dc * V OPP
(eq. 15)
V OPP
I bridge,mean +
By choosing a value for Ropl (for example 1.5 kW), we can
easily deduce Ropu value.
Following our example from before, we need 253 mV of
OPP voltage to limit the output power to 57 W at 265 Vrms.
We choose:
I bridge,avg +
+
0.18 @ 375 * (* 0.253)
(* 0.253)
@ 1500 + 399 kW
Finally, we choose a 300-kW resistor for Ropu .
A Non-dissipative OPP
+
1
R opu ) R opl
1
300k ) 1k
@
@
t on
T sw
@ N p,aux @ V in @ Ǹ2 )
1.1m
30.3m
V aux(t)
R opu ) R opl
Ť
dt
(eq. 17)
1
R opu ) R opl
@
t on
T sw
@ N p,aux @ V in @ Ǹ2 )
1
R opu ) R opl
@
t demag
T sw
@ ǒV CC ) V fǓ
We can calculate the OPP bridge current at highest input
voltage (265 V rms):
The input voltage information is given by the auxiliary
winding which offers lower voltage values compared to the
bulk rail.
I bridge,mean +
0
Ť
On our 45-W adapter, for an output power of 8 W, we
measured:
• ton = 1.1 ms
• toff = 29.2 ms
• tdemag = 5.6 ms
• Tsw = 30.3 ms
• VCC + Vf = 13.45 V
(eq. 16)
@ R opl +
V OPP
T sw
(eq. 18)
)
N p,aux @ V in,dc * ǒV OPPǓ
T sw
ŕ
We obtain:
R opl + 1.5 kW
R opu +
1
@ 0.18 @ 265 @ Ǹ2 )
1
R opu ) R opl
1
300k ) 1k
@
@
t demag
T sw
5.6m
30.3m
@ ǒV CC ) V fǓ +
(eq. 19)
@ 13.45 + 16.4 mA
As the average current it sees, is very low, the power
dissipated by the OPP bridge can be neglected.
FAULT PIN
a dc voltage on the OTP pin. When the temperature
increases, the NTC’s resistance reduces bringing the pin 5
voltage down until it reaches a typical value of 0.4 V:
the comparator trips and latches-off the controller. During
the latch-off phase, the VCC drops to the 5.5-V VCC(bias)
voltage level. The power supply needs to be un-plugged to
reset the part.
During start-up and soft-start, the output of the OTP
comparator is blanked to give the OTP pin voltage time to
reach its steady-state value if a filtering capacitor is installed
across the NTC. The filtering capacitor value should be 1 nF.
In the NCP1339, the OTP trip point corresponds to
a resistance of:
The Fault pin combines two different safety features to
help design a compact power supply. The first one is an Over
Voltage Protection (OVP) and the second one is an Over
Temperature Protection (OTP).
Over Temperature Protection
The adapter operating in a confined area, e.g. the plastic
case protecting the converter, it is important to monitor the
internal ambient temperature. If this temperature increases
beyond a certain point, catastrophic failures can occur
through semiconductors thermal runaway or transformer
saturation. To prevent this, the NCP1339 embeds an Over
Temperature Protection (OTP) circuitry which can be
combined with an Over Voltage Protection as sketched by
Figure 7.
The IFault(OTP) current (45.5 mA typ.) biases the Negative
Temperature Coefficient sensor (NTC), naturally imposing
R NTC +
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V OTP
I OTP(REF)
+
0.4
45.5m
+ 8.79 kW
(eq. 20)
AND9176/D
Vaux
5V
Fault
Q
Ifault(OTP)
Latch!
Q
3V
OK
R
NTC
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
VFault
Latch
S
Vfault(OVP)
0.4 V
Rfault(clamp)
Latch!
Vfault(OTP)
BONOK
time
Vfault(clamp)
Figure 7. OTP/OPP Combination in NCP1339
Over Voltage Protection
RFault(clamp) thus causing the pin 5 voltage to increase. When
this voltage reaches the OVP threshold (3 V typ.), the
controller is latched-off.
The amount of current that must be injected inside the
controller by the zener diode can be calculated as follows:
The NCP1339 features a protection against an over
voltage condition, e.g in case of the optocoupler destruction.
This over voltage protection is combined with an OTP as
shown previously on Figure 7.
Only a Zener diode needs to be added between the VCC rail
and the Fault pin in order to detect an over voltage condition.
In case of over voltage, the Zener diode starts to conduct
and injects current inside the internal clamp resistor
I Fault +
V OVP * V Fault(Clamp)
R Fault(Clamp)
+
3 * 1.7
1.55 @ 10 3
+ 838.7 mA
(eq. 21)
CONCLUSION
This application note has described the equations needed
to design a QR adapter driven by the NCP1339.
All the equations presented have been implemented inside
a Mathcad spreadsheet that can be downloaded from our
website: http://www.onsemi.com/
REFERENCES
[1] Yann Vaquette, “A 45-W adaptor with NCP1339
Quasi-Resonant controller”, Evaluation Board User’s
Manual EVBUM2248/D.
[2] Stéphanie Conseil, “QR − Analysis and Design of
Quasi-Resonant Converters”, Tutorial TND348.
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