NBSG16VS 2.5 V/3.3 V SiGe Differential Receiver/Driver with Variable Output Swing Description The NBSG16VS is a differential receiver/driver targeted for high frequency applications that require variable output swing. The device is functionally equivalent to the EP16VS device with much higher bandwidth and lower EMI capabilities. This device may be used for applications driving VCSEL lasers. Inputs incorporate internal 50 termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The output amplitude is varied by applying a voltage to the VCTRL input pin. Outputs are variable swing ECL from 100 mV to 750 mV amplitude, optimized for operation from VCC − VEE = 3.0 V to 3.465 V. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used as a reference voltage for single-ended NECL or PECL inputs and the VMM pin is used as a reference voltage for LVCMOS inputs. For single-ended input operation, the unused complementary differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC-coupled inputs. When used, decouple VBB and VMM via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. Features • • • • • • • • • • • Maximum Input Clock Frequency up to 12 GHz Typical Maximum Input Data Rate up to 12 Gb/s Typical 40 ps Typical Rise and Fall Times (VCTRL = VCC − 1 V) 120 ps Typical Propagation Delay (VCTRL = VCC − 1 V) Variable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Variable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V Output Level (100 mV to 750 mV Peak-to-Peak Output; VCC − VEE = 3.0 V to 3.465 V), Differential Output Only 50 Internal Input Termination Resistors Compatible with Existing 2.5 V/3.3 V EP Devices VBB and VMM Reference Voltage Output These are Pb-Free Devices © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 14 1 http://onsemi.com 1 QFN−16 MN SUFFIX CASE 485G MARKING DIAGRAMS* ÇÇÇ ÇÇÇ ÇÇÇ 16 1 SG 16VS ALYWG G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Publication Order Number: NBSG16VS/D NBSG16VS VEE 16 VTD 1 D 2 VBB VMM VEE 15 13 14 Exposed Pad (EP) 12 VCC 11 Q NBSG16VS D 3 10 Q VTD 4 9 VCC 5 VEE 6 7 8 NC VCTRL VEE Figure 1. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VTD − 2 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Internal 75 k to VEE and 36.5 k to VCC. 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. Internal 75 k to VEE. 4 VTD − Internal 50 Termination Pin. See Table 2. 5,8,13,16 VEE − Negative Supply Voltage 6 NC − No Connect 7 VCTRL 9,12 VCC − 10 Q RSECL Output Noninverted Differential Output. Typically Terminated with 50 to VTT = VCC − 2 V 11 Q RSECL Output Inverted Differential Output. Typically Terminated with 50 to VTT = VCC − 2 V 14 VMM − LVCMOS Reference Voltage Output. (VCC − VEE)/2 15 VBB − ECL Reference Voltage Output − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to VEE on the PC board. Internal 50 Termination Pin. See Table 2. Output Amplitude Swing Control. Bypass Pin to VCC through 0.1 F Capacitor. Positive Supply Voltage 1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit. 2. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. http://onsemi.com 2 NBSG16VS +3.3 V VCC + 0.1 F VCTRL VCTRL VTD VCC 50 Q D D Q D D Q OUT Q OUT Q OUT Q OUT 50 Q 50 75 K VMM 36.5 K VTD VMM 36.5 K 50 VCTRL VCC RVAR 75 K 50 50 75 K 75 K Q VTD 140 140 VBB VBB VTD VCC − 2 V VEE VEE Figure 2. Logic Diagram/ Voltage Source Implementation Figure 3. Alternative Voltage Source Implementation Table 2. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD Together AC−COUPLED Bias VTD and VTD Inputs within Common Mode Range (VIHCMR) RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL An external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. LVCMOS VMM should be connected to the unused complementary differential input. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (D, D) 75 k Internal Input Pullup Resistor (D) ESD Protection 36.5 k Human Body Model Machine Model > 2 kV > 100 V Pb-Free Level 1 Moisture Sensitivity (Note 3) Flammability Rating Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 192 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NBSG16VS Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Power Supply VEE = 0 V 3.6 V VEE Negative Power Supply VCC = 0 V −3.6 V Positive Input Negative Input VEE = 0 V VCC = 0 V 3.6 −3.6 V V VCC − VEE w 2.8 V VCC − VEE t 2.8 V 2.8 |VCC − VEE| V V Continuous Surge 25 50 mA mA Static Surge 45 80 mA mA VI Parameter VINPP Differential Input Voltage IOUT Output Current Condition 1 |D − D| Condition 2 VI ≤ VCC VI ≥ VEE IIN Input Current Through RT (50 Resistor) IBB VBB Sink/Source 1 mA IMM VMM Sink/Source 1 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction-to-Ambient) (Note 4) 0 lfpm 500 lfpm 41.6 35.2 °C/W JC Thermal Resistance (Junction-to-Case) 2S2P (Note 4) 4.0 °C/W Tsol Wave Solder 265 °C Pb-Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 4. JEDEC standards multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NBSG16VS Table 5. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT (VCC = 2.5 V; VEE = 0 V) (Note 5) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 18 25 32 18 25 32 18 25 32 mA mV POWER SUPPLY CURRENT IEE Negative Power Supply Current VARIABLE PECL OUTPUTS (Note 6) VOH Output HIGH Voltage 1315 1440 1565 1305 1430 1555 1305 1430 1555 VOL Output LOW Voltage Max Swing VCTRL = VCC − 600 mV 645 1090 765 1210 885 1330 605 1035 725 1155 845 1275 600 1010 720 1130 840 1250 mV DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 9 & 11) (Note 7) VIH Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VIL Input LOW Voltage 0 VIH − 150 0 VIH − 150 0 VIH − 150 mV Vth Input Threshold Voltage Range (Note 8) 950 VCC – 75 950 VCC – 75 950 VCC – 75 mV VISE Single-Ended Input Voltage (VIH – VIL) 150 2600 150 2600 150 260 mV VBB PECL Output Voltage Reference 1080 1200 1080 1200 1080 1200 mV 1140 1140 1140 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 10 & 12) (Note 9) VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VILD Differential Input LOW Voltage 0 VIHD − 75 0 VIHD − 75 0 VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV 1200 2500 1200 2500 1200 2500 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 10) (Figure 13) IIH Input HIGH Current (@VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@VIL) 25 50 25 50 25 50 A 1100 1250 1400 1100 1250 1400 1100 1250 1400 mV 45 50 55 45 50 55 45 50 55 LVCMOS CONTROL PIN VMM CMOS Output Voltage Reference (VCC – VEE) / 2 TERMINATION RESISTORS RTIN Internal Input Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. All loading with 50 to VCC − 2.0 V. 7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 9. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NBSG16VS Table 6. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT (VCC = 3.3 V; VEE = 0 V) (Note 11) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 20 27 34 20 27 34 20 27 34 mA mV POWER SUPPLY CURRENT IEE Negative Power Supply Current VARIABLE PECL OUTPUTS (Note 12) VOH Output HIGH Voltage 2095 2220 2345 2085 2210 2335 2075 2200 2325 VOL Output LOW Voltage Max Swing VCTRL = VCC − 600 mV 1275 1750 1395 1870 1515 1990 1285 1730 1405 1850 1525 1970 1295 1715 1415 1835 1535 1955 mV DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 9 & 11) (Note 13) VIH Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VIL Input LOW Voltage 0 VIH − 150 0 VIH − 150 0 VIH − 150 mV Vth Input Threshold Voltage Range (Note 14) 950 VCC – 75 950 VCC – 75 950 VCC – 75 mV VISE Single-Ended Input Voltage (VIH – VIL) 150 2600 150 2600 150 260 mV VBB PECL Output Voltage Reference 1800 2000 1800 2000 1800 2000 mV 1940 1940 1940 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 10 & 12) (Note 15) VIHD Differential Input HIGH Voltage 1200 VCC 1200 VCC 1200 VCC mV VILD Differential Input LOW Voltage 0 VIHD − 75 0 VIHD − 75 0 VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV 1200 3300 1200 3300 1200 3300 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 16) (Figure 13) IIH Input HIGH Current (@VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@VIL) 25 50 25 50 25 50 A 1500 1650 1800 1500 1650 1800 1500 1650 1800 mV 45 50 55 45 50 55 45 50 55 LVCMOS CONTROL PIN VMM CMOS Output Voltage Reference (VCC – VEE) / 2 TERMINATION RESISTORS RTIN Internal Input Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. 12. All loading with 50 to VCC − 2.0 V. 13. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 14. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 15. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 6 NBSG16VS Table 7. DC CHARACTERISTICS, INPUT WITH VARIABLE NECL OUTPUT (VCC = 0 V; VEE = −3.465 V to −2.375 V) (Note 17) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 20 27 34 20 27 34 20 27 34 mA −1205 −1185 −1080 −1060 −955 −935 −1215 −1195 −1090 −1070 −965 −945 −1225 −1195 −1100 −1070 −975 −945 mV −2000 −1560 −1910 −1440 −1820 −1320 −1990 −1580 −1900 −1460 −1810 −1340 −1980 −1595 −1890 −1475 −1800 −1355 −1855 −1410 −1620 −1215 −1290 −1000 −1895 −1460 −1705 −1290 −1425 −1100 −1900 −1490 −1730 −1330 −1470 −1150 POWER SUPPLY CURRENT IEE Negative Power Supply Current VARIABLE NECL OUTPUTS (Note 18) VOH Output HIGH Voltage VOL Output LOW Voltage Max Swing VCTRL = VCC − 600 mV −3.0 V < VEE ≤ −2.375 V Max Swing VCTRL = VCC − 600 mV mV DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 9 & 11) (Note 19) VIH Input HIGH Voltage VEE + 1200 VCC VEE + 1200 VCC VEE + 1200 VCC mV VIL Input LOW Voltage VEE VIH − 150 VEE VIH − 150 VEE VIH − 150 mV Vth Input Threshold Voltage Range (Note 20) VEE + 950 VCC – 75 VEE + 950 VCC – 75 VEE + 950 VCC – 75 mV 150 2600 150 2600 150 260 mV −1300 −1420 −1300 −1420 −1300 mV VISE Single-Ended Input Voltage (VIH – VIL) VBB NECL Output Voltage Reference −1420 −1360 −1360 −1360 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 10 & 12) (Note 21) VIHD Differential Input HIGH Voltage VEE + 1200 VCC VEE + 1200 VCC VEE + 1200 VCC mV VILD Differential Input LOW Voltage VEE VIHD − 75 VEE VIHD − 75 VEE VIHD − 75 mV VID Differential Input Voltage (VIHD – VILD) 75 2600 75 2600 75 2600 mV VEE + 1200 0 VEE + 1200 0 VEE + 1200 0 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 22) (Figure 13) IIH Input HIGH Current (@VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@VIL) 25 50 25 50 25 50 A VMM − 150 VMM VMM + 150 VMM − 150 VMM VMM + 150 VMM − 150 VMM VMM + 150 mV 45 50 55 45 50 55 45 50 55 LVCMOS CONTROL PIN (Note 23) VMM CMOS Output Voltage Reference TERMINATION RESISTORS RTIN Internal Input Termination Resistor Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 to VCC − 2.0 V. 19. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 20. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2. 21. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously. 22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 23. VMM typical = |VCC − VEE| / 2 + VEE = VMMT http://onsemi.com 7 NBSG16VS Table 8. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V) −40°C Symbol Characteristic fmax Maximum Input Clock Frequency (See Figure 7) (Note 24) tPLH, tPHL Propagation Delay to Output Differential (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q tSKEW Duty Cycle Skew (Note 25) tJITTER RMS Random Clock Jitter Min Typ 10 (Note 27) 12 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 26) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q Max Min Typ 10 (Note 27) 12 85°C Max Min Typ 10 (Note 27) 12 Max Unit GHz ps 100 100 140 135 180 180 3 0.5 100 100 140 135 180 180 20 3 2 0.5 100 80 140 135 180 220 15 3 10 2 0.5 2 ps ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C 5 5 75 2600 75 5 2600 75 2600 mV ps 30 30 45 40 55 50 30 30 45 40 55 50 30 30 45 40 55 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 24. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%). 25. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 14. 26. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE < 2600 mV). 27. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 7). Table 9. AC CHARACTERISTICS (VCC = 0 V; −3.0 V < VEE ≤ −2.375 V or 2.375 V ≤ VCC < 3.0 V; VEE = 0 V) −40°C Symbol Characteristic fmax Maximum Input Clock Frequency (See Figure 8) (Note 28) tPLH, tPHL Propagation Delay to Output Differential (VCTRL = VCC − 2 V) D → Q, Q (VCTRL = VCC − 1 V) D → Q, Q tSKEW Duty Cycle Skew (Note 29) tJITTER RMS Random Clock Jitter Typ 10 (Note 31) 12 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 30) tr tf Output Rise/Fall Times (20% − 80%) @ 1 GHz (VCTRL = VCC − 2 V) Q, Q (VCTRL = VCC − 1 V) Q, Q Max Min Typ 10 (Note 31) 12 85°C Max Min Typ 10 (Note 31) 12 Max Unit GHz ps 100 100 140 135 180 180 3 0.5 100 100 140 135 180 180 20 3 3 0.5 80 100 140 135 180 220 15 3 10 3 0.5 3 ps ps fin < 10 GHz Peak−to−Peak Data Dependent Jitter fin < 10 Gb/s VINPP 25°C Min 5 5 75 2600 75 5 2600 75 2600 mV ps 25 22 50 45 70 60 25 22 50 45 70 60 25 22 50 45 70 60 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 28. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%). 29. tSKEW = |tPLH−tPHL| for a nominal 50% differential clock input waveform. See Figure 14. 30. VINPP(MAX) cannot exceed VCC − VEE (applicable only when VCC − VEE < 2600 mV). 31. Conditions include input amplitude of 500 mV and VCTRL = VCC − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P Spec in Figure 8), 80 mV at −40°C.. http://onsemi.com 8 NBSG16VS 100 OUTPUT AMPLITUDE (%) 90 80 70 60 50 40 30 20 10 0 VCC − 0.0 VCC − 0.5 VCC − 1.0 VCC − 1.5 VCC − 2.0 VCTRL (V) Figure 4. Output Amplitude % vs. VCTRL (pin #A3) VOH AMPLITUDE DECREASES OUTPUT AMPLITUDE MIN. AMPLITUDE REGION MAX. AMPLITUDE REGION VOL 2.375 V v VCC − VEE < 3.0 V 3.0 V v VCC − VEE v 3.465 V VCC − 1.3 VCC − 0.0 VCC − 0.5 VCC − 1.0 VCC − 1.5 VCC − 2.0 VCTRL (V) Figure 5. Output Amplitude vs. VCTRL (pin #A3) 3.40 3.20 VOLTAGE (V) 3.00 VCTRL 2.80 2.60 2.40 2.20 2.00 Q/Q 1.80 1.60 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) Figure 6. Output Response Under Amplitude Modulation of VCTRL (Conditions Include VCC − VEE = 3.3 V at 255C, fIN (VCTRL) = 200 MHz, and fIN (D, D) = 2 GHz) http://onsemi.com 9 NBSG16VS 9 800 8 VCTRL = VCC − 2 V 700 7 600 JITTEROUT ps (RMS) OUTPUT VOLTAGE AMPLITUDE (mV) 900 6 VCTRL = VCC − 1 V 500 5 VCTRL = VCC − 0 V 400 4 OUTPUT P−P SPEC (AMPLITUDE GUARANTEE) 300 3 200 2 100 1 RMS JITTER 0 1 2 3 4 5 6 7 8 9 10 11 12 0 INPUT FREQUENCY (GHz) Figure 7. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) See Table 8 (VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V 9 8 VCTRL = VCC − 2 V 700 7 600 VCTRL = VCC − 1 V 6 500 5 400 300 VCTRL = VCC − 0 V OUTPUT P−P SPEC (AMPLITUDE GUARANTEE) 3 200 2 100 1 RMS JITTER 0 4 JITTEROUT ps (RMS) OUTPUT VOLTAGE AMPLITUDE (mV) 800 1 2 3 4 5 6 7 8 9 10 11 12 0 INPUT FREQUENCY (GHz) Figure 8. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) See Table 9 (VCC = 0 V; −3.0 V VEE −2.375 V or 2.375 V VCC 3.0 V; VEE = 0 V) http://onsemi.com 10 NBSG16VS IN VIH Vth IN VIL IN IN Vth Figure 9. Differential Input Driven Single-Ended VCC Vthmax Figure 10. Differential Inputs Driven Differentially VIHmax VILmax Vth IN Vthmin VEE VIH Vth VIL IN IN VID = |VIHD(IN) − VILD(IN)| VIHD VILD VIHmin VILmin Figure 11. Vth Diagram Figure 12. Differential Inputs Driven Differentially VCC VIHDmax VIHCMRmax VILDmax VIHCMR VIHDtyp VID = VIHD − VILD IN IN VILDtyp VIHDmin VIHCMRmin VILDmin VEE Figure 13. VIHCMR Diagram http://onsemi.com 11 NBSG16VS D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 14. AC Reference Measurement Q Zo = 50 D Receiver Device Driver Device Q Zo = 50 D 50 50 VTT VTT = VCC − 2.0 V Figure 15. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NBSG16VSMNG QFN-16 (Pb-Free / Halide-Free) 123 Units / Tube NBSG16VSMNR2G QFN-16 (Pb-Free / Halide-Free) 3000 / Tape & Reel NBSG16VSMNHTBG QFN-16 (Pb-Free / Halide-Free) 100 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NBSG16VS PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE F D ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ PIN 1 LOCATION 0.10 C 2X L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉÉ ÉÉÉ TOP VIEW DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L EXPOSED Cu 0.10 C 2X A B (A3) ÉÉ ÉÉ ÇÇ MOLD CMPD A3 A1 DETAIL B A 0.05 C ALTERNATE CONSTRUCTIONS NOTE 4 A1 SIDE VIEW C SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.18 0.24 0.30 3.00 BSC 1.65 1.75 1.85 3.00 BSC 1.65 1.75 1.85 0.50 BSC 0.18 TYP 0.30 0.40 0.50 0.00 0.08 0.15 RECOMMENDED SOLDERING FOOTPRINT* 16X 0.10 C A B 16X L DETAIL A 0.58 PACKAGE OUTLINE D2 8 4 1 9 2X E2 16X 2X 1.84 3.30 K 1 16X 16 e e/2 BOTTOM VIEW 0.30 16X b 0.50 PITCH 0.10 C A B 0.05 C NOTE 3 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NBSG16VS), may be covered by U.S. patents including 6,362,644. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. 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