NTLUS3C18PZ Power MOSFET −12 V, −7.0 A, mCoolt Single P−Channel, 1.6x1.6x0.5 mm mCool UDFN6 Package Features • Ultra Low RDS(on) • UDFN Package with Exposed Drain Pads for Excellent Thermal • • Conduction Low Profile UDFN 1.6 x 1.6 x 0.5 mm for Board Space Saving These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com MOSFET RDS(on) MAX V(BR)DSS −12 V Applications • Optimized for Power Management Applications for Portable • • Products, Such as Smart Phones and Media Tablets Battery Switch High Side Load Switch ID MAX 24 mW @ −4.5 V −7.0 A 27 mW @ −3.7 V −6.6 A 30 mW @ −3.3 V −6.3 A 36 mW @ −2.5 V −5.7 A 70 mW @ −1.8 V −4.1 A S MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Symbol Value Unit Drain-to-Source Voltage VDSS −12 V Gate-to-Source Voltage VGS ±8 V ID −7.0 A Continuous Drain Current (Note 1) Power Dissipation (Note 1) Continuous Drain Current (Note 2) Steady State TA = 25°C TA = 85°C −5.1 t≤5s TA = 25°C −10.5 Steady State TA = 25°C t≤5s TA = 25°C Steady State G D P−Channel MOSFET PD MARKING DIAGRAM W 1.71 6 TA = 25°C 3.83 ID TA = 85°C A −4.4 −3.1 Power Dissipation (Note 2) TA = 25°C PD 0.66 W Pulsed Drain Current tp = 10 ms IDM −21 A TJ, TSTG -55 to 150 °C Source Current (Body Diode) (Note 2) IS −1.7 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Operating Junction and Storage Temperature 1 AA M G UDFN6 (mCOOL]) CASE 517AU 1 AAMG G = Specific Device Code = Date Code = Pb−Free Package (*Note: Microdot may be in either location) PIN CONNECTIONS Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2014 April, 2014 − Rev. 0 1 Publication Order Number: NTLUS3C18PZ/D NTLUS3C18PZ THERMAL RESISTANCE RATINGS Symbol Max Junction-to-Ambient – Steady State (Note 3) Parameter RθJA 72 Junction-to-Ambient – t ≤ 5 s (Note 3) RθJA 32.6 Junction-to-Ambient – Steady State min Pad (Note 4) RθJA 190.4 Unit °C/W 3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min −12 Typ Max Units OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA Drain-to-Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = −250 mA, ref to 25°C Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = −9.6 V Gate-to-Source Leakage Current IGSS VDS = 0 V, VGS = ±8 V VGS(TH) VGS = VDS, ID = −250 mA V 7.3 TJ = 25°C mV/°C −1.0 mA ±10 mA −1.0 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temp. Coefficient Drain-to-Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS −0.4 3.0 mV/°C mW VGS = −4.5 V, ID = −7.0 A 20 24 VGS = −3.7 V, ID = −6.6 A 22 27 VGS = −3.3 V, ID = −5.7 A 24 30 VGS = −2.5 V, ID = −5.1 A 29 36 VGS = −1.8 V, ID = −2.0 A 44 70 VDS = −5 V, ID = −7.0 A 21.8 S 1570 pF CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 240 Total Gate Charge QG(TOT) 15.8 Threshold Gate Charge QG(TH) 0.7 Gate-to-Source Charge QGS Gate-to-Drain Charge QGD 4.6 td(ON) 8.5 VGS = 0 V, f = 1 MHz, VDS = −6.0 V VGS = −4.5 V, VDS = −6.0 V; ID = −7.0 A 200 nC 1.9 SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time tr td(OFF) Fall Time VGS = −4.5 V, VDD = −6 V, ID = −7.0 A, RG = 1 W tf ns 52.5 40 59 DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, IS = −1.7 A TJ = 25°C 0.71 TJ = 125°C 0.58 1.0 V 5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://onsemi.com 2 NTLUS3C18PZ TYPICAL CHARACTERISTICS −4.5 V to −2.5 V −ID, DRAIN CURRENT (A) 15 −ID, DRAIN CURRENT (A) TJ = −55°C VDS ≤ −10 V VGS = −2.0 V VGS = −1.8 V 10 5 15 TJ = 25°C TJ = 125°C 10 5 . 0 0 0.5 1.0 1.5 0 2.0 1.5 2.0 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = −7 A 0.06 0.05 0.04 0.03 0.02 0.01 0 2.0 2.5 3.0 3.5 4.0 4.5 VGS = −1.8 V 0.05 2.5 TJ = 25°C 0.04 VGS = −2.5 V 0.03 VGS = −4.5 V 0.02 0.01 0 0 5 10 15 20 −VGS, GATE VOLTAGE (V) −ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.6 1.5 1.4 1E−05 VGS = −4.5 V ID = −7 A −IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE (W) 1.0 −VGS, GATE−TO−SOURCE VOLTAGE (V) 0.07 1.5 0.5 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 1.3 1.2 1.1 1.0 0.9 TJ = 125°C 1E−06 1E−07 TJ = 85°C 1E−08 0.8 0.7 −50 1E−09 −25 0 25 50 75 100 125 150 2 4 6 8 10 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 12 NTLUS3C18PZ 2000 VGS = 0 V TJ = 25°C f = 1 MHz CISS 1500 1000 COSS 500 CRSS 0 0 2 4 6 8 10 12 5 16 4 12 2 10 QGS QGD 8 VDS = −6 V TJ = 25°C ID = −10 A 6 4 1 2 0 0 2 4 6 8 10 12 14 0 18 16 −VDS, DRAIN−TO−SOURCE (V) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge −IS, SOURCE CURRENT (A) 10 VGS = −4.5 V VDD = −6 V ID = −10 A td(off) tf tr 100 td(on) 10 TJ = 25°C TJ = 125°C TJ = −55°C 1 0.1 1 1 10 0.3 100 0.4 0.5 0.6 0.7 0.8 0.9 1.0 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 0.95 100 −ID, DRAIN CURRENT (A) 0.85 0.75 −VGS(th) (V) 14 VGS 3 1000 T, TIME (ns) 18 QT −VDS, DRAIN−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 2500 −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 0.65 0.55 0.45 ID = −250 mA 0.35 10 ms 10 100 ms 1 ms VGS = −8 V Single Pulse TC = 25°C 1 10 ms dc 0.1 RDS(on) Limit Thermal Limit Package Limit 0.25 0.15 −50 0.01 −25 0 25 50 75 100 125 150 0.1 1 10 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Threshold Voltage Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 100 NTLUS3C18PZ TYPICAL CHARACTERISTICS 225 200 POWER (W) 175 150 125 100 75 50 25 0 1E−05 1E−03 1E−01 1E+01 1E+03 SINGLE PULSE TIME (s) Figure 13. Single Pulse Maximum Power Dissipation R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 80 70 60 50 40 Duty Cycle = 0.5 30 0.05 20 0.20 10 0.10 0.02 0.01 RqJA = 72°C/W Single Pulse 0 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03 t, TIME (s) Figure 14. FET Thermal Response DEVICE ORDERING INFORMATION Package Shipping† NTLUS3C18PZTAG UDFN6 (Pb−Free) 3000 / Tape & Reel NTLUS3C18PZTBG UDFN6 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTLUS3C18PZ PACKAGE DIMENSIONS UDFN6 1.6x1.6, 0.5P CASE 517AU ISSUE O A B D 2X 0.10 C ÉÉ ÉÉ PIN ONE REFERENCE 2X L1 L E DETAIL A OPTIONAL CONSTRUCTION 0.10 C EXPOSED Cu ÉÉ ÉÉ TOP VIEW A DETAIL B (A3) 0.05 C A1 0.05 C 0.10 C A B MOLD CMPD A3 DETAIL B SEATING PLANE D2 3 1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 1.60 BSC 1.60 BSC 0.50 BSC 0.62 0.72 0.15 0.25 0.57 0.67 0.55 BSC 0.25 BSC 0.20 0.30 −−− 0.15 SOLDERMASK DEFINED MOUNTING FOOTPRINT* e F 6X C SIDE VIEW DIM A A1 A3 b D E e D1 D2 E2 F G L L1 OPTIONAL CONSTRUCTION A1 NOTE 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 0.82 E2 G L 0.16 0.43 0.10 C A B 0.68 2X 6 DETAIL A 4 D1 BOTTOM VIEW 0.35 6X b 0.10 C A B 0.05 C 1.90 NOTE 3 0.28 1 6X 0.50 PITCH 0.32 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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