1/4 STRUCTURE PRODUCT SERIES Silicon Monolithic Integrated Circuit 7-Channel Switching Regulator Controller for Digital Camera TYPE PIN ASSIGNMENT BLOCK DIAGRAM PACKAGE Functions Fig.1 Fig.1 Fig.2 BD９３５０MWV ●1.5V minimum input operating ●Supplies power for the internal circuit by using charge-pump circuit which outputs a voltage twice bigger than VBATvoltage. or a equal voltage as VBAT + VIN. ●Contains step-up converter(1ch), step-down converter(2ch), cross converter(1ch), configurable for step-up/step-down converter(1ch), with 32 step brightness controller for step-up converter(1ch). ●Contains 4FETs for the cross converter channe.l ●3channels contain transistor for synchronous rectifying action mode. ●2channels contain FETs for the step-up converter. ●All channels contain internal compensation between inputs outputs of error amps. ●Contains sequence control circuit for ch1,2 and 4. ●Operating frequency 1.2MHz(CH1～4), 600kHz(CH5～7). ●Contains output interception circuit when over load. ●2 channels have high side switches with soft start function, one channel has PMOS back gate control circuit. ●Thermally enhanced UQFN044V6060 package.(6mm x 6mm, 0.4mm pitch) ○Absolute maximum ratings (Ta=25℃) Parameter P o w e r S u p p l y V o l t a g e P o w e r I n p u t V o l t a g e O P O S J u t o w p e r t o r u n c p e a a t u t C u r r e n t r D i s s i p a t i o t i n g T e m p e r a t u r g e T e m p e r a t u r i o n T e m p a r e t u r n e e e Symbol Limit Unit VBAT VHx1～4 HS67H VLx6～7 VIN IomaxLx1 IomaxHx2 IomaxHx3～4 IomaxHS6～7 IomaxLx6～7 Pd Topr Tstg Tjmax －0.3～7 －0.3～7 －0.3～7 －0.3～20 -0.3～7 ±1.2 ±1.5 ±1.2 ±1.2 ±0.8 0.54 (*1) －25～+85 －55～+150 +150 V V V V V A A A A A W ℃ ℃ ℃ (*1) Without external heat sink, the power dissipation reduces by 4.32mW/℃ over 25℃。 ○Recommended operating conditions Parameter Power Supply Voltage VREF Pin Connecting Capacitor VREGA Pin Connecting Capacitor SCP Pin Connecting Capacitor C+H to C+L connecting Capacitor 【Oscillator】 Oscillator Frequency OSC Timing Resistor Symbol VBAT CVREF CVREGA CSCP CF fosc RT ○CH7 recommended operating conditions MIN Limit TYP MAX 1.5 0.47 0.47 － 1.0 1.0 1.0 - 5.5 4.7 4.7 0.47 - 0.6 47 1.2 62 1.5 120 MIN Limits TYP MAX T(ON) T(OFF) T(H) T(L) 65X1/fosc 65X1/fosc 420 420 - 10000 10000 Fixed H when EN start-up T(EN) 5X1/fosc - - [S] Fixed L before setting brightness Brightness setting time When start-up T(CLR) T(SET) 5X1/fosc - - 63X1/fosc 2048X1/fosc [S] [S] Unit Parameter Symbol V μF μF μF μF Fixed H when determine brightness Fixed L when OFF Fixed H when setting brightness Fixed L when setting brightness MHz kΩ Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority. REV. A Unit [S] [S] [nS] [nS] 2/4 ○Electrical characteristics （Ta=25℃, VBAT=3V, RT=62k, STB1～6=3V,UPIC7=2.5V） Parameter Symbol 【Charge Pump Circuit】 Output Voltage Vcpout1 (Regulated) Output Voltage ( X2 Step up) Vcpout2 MIN Standard value TYP MAX Units Conditions 5.4 － V 4.5 4.8 － V 50 Ω CF=1μF, VBAT=2.5V 90 kHz RT=62kΩ － V 2.6 V 2.30 200 V mA VREGA Monitor 0.54 V INV monitor CH4 170 mV Max Duty Dmax1u 86 1,4（Step Up） Max Duty 5,6,7 Dmax2 86 Max Duty Dmax3 － CH2 LX21 Max Duty Dmax4 78 CH2 LX22 【Error AMP】 Input Biias Current IINV － INV Threshold VINV1 0.79 Voltage1 INV Threshold VINV2 0.99 Voltage2 INV Threshold VINV3 513 Voltage3 【Base Bias Voltage Vref for inverted Channel】 CH5 VOUT5 -6.09 OutputVoltage Line Regulation DVLi － Output Current Ios 0.2 When shorted 【Soft Start】 CH1,2,4 Tss1,2,4 1.5 Soft Start Time CH3 Tss3 0.5 Soft Start Time CH5 Tss5 1.5 Soft Start Time CH6 Tss6 2.0 Soft Start Time CH7 Tss7 4.7 Soft Start Time 92 6 μA 1.1 V 【Output Driver】 CH1 Highside SW ON Resistance CH1 Lowside SW ON Resistance CH2 LX21Pin Highside SW ON Resistance CH2 LX21Pin Lowside SW ON Resistance CH2 LX22Pin Highside SW ON Resistance CH2 LX22Pin Lowside SW ON Resistance CH3 Highside SW ON Resistance CH3 Lowside SW ON Resistance CH4 Highside SW ON Resistance CH4 Lowside SW ON Resistance CH6 NMOS SW ON Resistance CH6,7 Load SW ON Resistance CH5 Driver Output Voltage H Io=1mA,, INV1～7=1.2V NON5= -0.2V Only for internal Current VBAT=2.5V, INV1～7=1.2V NON5= -0.2V 5.2 Output Vcpro － 35 Resistance Operating fcp 60 75 Frequency Minimum VBAT Vst1 1.5 － Voltage 【Internal Regulator VREGA】 Output Voltage VREGA 2.4 2.5 【Prevention Circuit of Miss Operation by Low voltage Input】 Threshold Voltage Vstd1 － 2.15 Hysteresis Width ⊿Vstd1 50 100 【Short Circuit Protection】 Timer start Vtcinv 0.42 0.48 threshold voltage SCP Stand by Vssc － 22 Voltage SCP Out Source Iscp 2 4 Current SCP Threshold Vscp 0.9 1.0 Voltage 【Oscillator】 Frequency fosc1 1.0 1.2 CH1～4 Frequency fosc2 0.5 0.6 CH5～7 Max Duty Dmax1d － － 1,3,4（Step Down） Parameter Io=5mA Vscp=0.1V 1.4 MHz RT=62kΩ 0.7 MHz RT=62kΩ 100 % 96 % Vscp=0V (※1) 130 200 mΩ CPOUT=5.4V RON22P － 180 280 mΩ VOUT2=5.0V RON22N － 130 200 mΩ CPOUT=5.4V RON3P － 160 260 mΩ HX3=3.0V, CPOUT=5.4V RON3N － 130 200 mΩ CPOUT=5.4V RON4P － 280 380 mΩ HX4=5.0V RON4N － 130 200 mΩ CPOUT=5.4V RON6N － 500 800 mΩ CPOUT=5.4V RON67P － 200 300 mΩ Vout5H PVCC5 -1.5 PVCC5 -1.0 － V － 0.5 1.0 V V kΩ Active VUPIH 2.05 － 4.0 V Non Active VUPIL 0 － 0.4 V ISTB1 － － 5 μA ISTB2 － － 5 μA ISTB3 － － 5 μA Step –down UDSEL4=CPOUT ISTB4 － － 5 μA Step-up UDSEL4=0V Icc1 － 7.0 11.0 mA INV1～7=1.2V, NON5=-0.2V, VBAT=3.0V Icc2 － 3.0 5.0 mA 540 567 mV CH7I 【Circuit Current】 -5.91 V 12.5 mV 1.0 － mA Vref=0V Stand-by Current VBAT terminal HS67H terminal HX terminal LX terminal Circuit Current1 (VBAT current when voltage supplied for the terminal) Circuit Current2 (CPOUT current when voltage supplied for the terminal) (※1)The protective circuit start working when circuit is operated by 100% duty. So it is possible to use only for transition time shorter than charge time for SCP. (※2)Recommend resistor value over 20kΩ between VREF to NON5, because VREF current is under 100uA. (※3)UPIC7 is not connected pull-down resistor. UPIC7 must input H or L level voltage when CH1～6 is active. ◎This product is not designed for normal operation with in a radioactive environment REV. A HS67H=3.0V CPOUT=5.4V IOUT5=50mA, NON5=0.2V, PVCC5=3V IOUT5=50mA, NON5=0.2V V UPIC7 control Voltage RT=62kΩ － 0.3 700 CH6, 7V msec RON21N 5.5 V 6.7 HX2=3.0V, CPOUT=5.4V － 400 1.01 5.7 mΩ － 1.00 RT=62kΩ 240 1.5 Pull down Resistance 【UPIC7】 msec 160 -0.3 250 CH1～4 4.0 － VSTBL1 RSTB1 V 3.0 RON21P VSTBH1 0.81 RT=62kΩ CPOUT=5.4V Non Active 0.80 msec mΩ Active INV1～7, NON5=3.0V 3.5 180 V nA 2.5 130 V 50 RT=62kΩ － CPOUT ×0.3 0 msec RON1N CPOUT 【STB1～6】 2.5 HX1=3V, CPOUT=5.4V － % 1.5 mΩ － 90 RT=62kΩ 380 0 84 msec 160 VUDUP UDSEL4 Control Voltage 3.5 － Step up % 4.0 Conditions CPOUT ×0.7 % -6.00 Units VUDDO 96 100 NON5 resistor12kΩ, 72kΩ (※2) CPOUT=1.5～5.5V Standard value TYP MAX Step down 92 STB control Voltage Min RON1P CH5 Driver Vout5L Output Voltage L 【Switch to configure step up/down】 － 2.5 Symbol INV1～7=1.2V, NON5=-0.2V, CPOUT=5.4V C+H, C+L=OPEN 3/4 NON5 INV6 35 INV7 36 INV7I 37 UPIC7 38 HS6L 39 HS67H 40 HS7L 41 VREGA CPOUT C+H VBAT VIN C+L GND RT SCP INV1 33 32 31 30 29 28 27 26 25 24 23 1.0V VREF CHARGE PUMP OSC + UVLO REF + 1.0V REF + 1.0V + TSD + + DAC PWM & LOGIC BLOCK OCP PRE D RIVER HI-SIDE SW OCP Lx7 42 PGND567 43 Lx6 44 + SCP 2.5V REG + PRE DRIVER REF 0V 34 VREF ○Pin Assignment ・Block Diagram PRE DRIVER PRE DRIVER PRE DRIVER REF 0.8V REF 0.8V REF 0.8V REF 0.8V 22 INV3 21 INV2 20 INV4 19 Hx4 18 Lx4 17 PGND4 16 Hx2 15 Lx21 14 PGND2 13 Lx22 12 VOUT2 B.G.CTL OCP PRE DRIVER 400k 2 3 4 5 6 7 8 9 10 11 STB56 OUT5 Hx1 Lx1 PGND13 Lx3 Hx3 STB3 STB124 UDSEL4 400k 1 PVCC5 400k PRE DRIVER Fig. 1 ○Pin Description Pin Name Description VBAT Input for battery voltage Returning voltage from output terminal Output terminal for Charge Pump Ground terminal Terminal for connecting flying capacitor for Charge Pump(H side) Terminal for connecting flying capacitor for Charge Pump(L side) Ground terminal for internal FET VREGA output CH5 base bias voltage CH5 PMOS VCC input for driver VIN CPOUT GND C+H C+L PGND13,2,4,567 VREGA VREF PVCC5 Pin Name OUT5 Hx1,3,4 Lx1,3,4,6,7 Hx2 Lx21 Lx22 VOUT2 HS67H HS6L,HS7L ○Package INV1,2,3,4,6,7 NON5 Description Pin Name Description Terminal for connecting gate of CH5 PMOS Input terminal for synchronous High side switch, Power supply for Pch Driver Terminal for connecting inductors Power supply for channel 2 Terminal for connecting inductor for CH2 input Terminal for connecting inductor for CH2 output CH2 output voltage Power supply for internal load switch Output terminal for internal load switch Error AMP inverted input Error AMP non-inverted input INV7I Error AMP inverted input For connecting a resistor to set the OSC frequency For connecting a capacitor to set up the delay time of the SCP Step-up/down switching mode selection(H: step-down, L:step-up) ON/OFF switch H: operating over 1.5V ON/OFF switch for CH7 brightness control RT SCP UDSEL4 STB124,3,56 UPIC7 B D 9 3 5 0 M W LOT No. Fig. 2 REV. A 4/4 ○Operation Notes １.) Absolute maximum ratings This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. ２.) GND potential Make sure GND is connected at lowest potential. All pins except NON5, must not have voltage below GND. Also, NON5 pin must not have voltage below - 0.3V on start up. ３.) Setting of heat Make sure that power dissipation does not exceed maximum ratings. ４.) Pin short and mistake fitting Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output to GND condition will not happen because this may damage the IC. ５.) Actions in strong magnetic field Exposing the IC within a strong magnetic field area may cause malfunction. ６.) Mutual impedance Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and capacitor network to keep the ripple voltage minimum. ７.) Voltage of STB pin The threshold voltages of STB pin are 0.3V and 1.5V. STB state is set below 0.3V while action state is set beyond 1.5V. The region between 0.3V and 1.5V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF. ８.) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. ９.)Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply injection. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. １０.)IC Terminal Input This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed. For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.15): ○When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. ○When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other elements in the proximity of the aforementioned parasitic diode. Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to the input terminal. Transistor (NPN) B （Terminal B）C Resistor （Terminal A） E GND （TerminalＡ） P P＋ N N P-board P P＋ P＋ N N Ｎ Parasitic element ～ ～ N P＋ Parasitic element N P-board Parasitic element GND Fig - 3 Simplified structure of a Bipolar IC REV. A GND Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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