(H) x 2504 (V) Full Frame CCD Image Sensor

KAF-8300
3326 (H) x 2504 (V) Full
Frame CCD Image Sensor
Description
The KAF−8300 Image Sensor is a 22.5 mm diagonal (Four Thirds
Format) high performance color or monochrome full frame CCD
(charge-coupled device) image sensor designed for a wide range of
image sensing applications including digital imaging. Each pixel
contains blooming protection by means of a lateral overflow drain
thereby preventing image corruption during high light level
conditions. For the color version, the 5.4 mm square pixels are
patterned with an RGB mosaic color filter with overlying microlenses
for improved color response and reproduction. Several versions of
monochrome devices are available with or without microlenses.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Full Frame CCD; with Square Pixels
Total Number of Pixels
3448 (H) × 2574 (V) = approx. 8.9 Mp
Number of Effective Pixels
Color Device
Monochrome Device
3358 (H) × 2536 (V) = approx. 8.6 Mp
3366 (H) × 2544 (V) = approx. 8.6 Mp
Number of Active Pixels
3326 (H) × 2504 (V) = approx. 8.3 Mp
Pixel Size
5.4 mm (H) × 5.4 mm (V)
Active Image Size
17.96 mm (H) × 13.52 mm (V)
22.5 mm (Diag.), 4/3″ Optical Format
Aspect Ratio
4:3
Horizontal Outputs
1
Saturation Signal
> 25.5 ke−
Output Sensitivity
23 mV/e−
Figure 1. KAF−8300 Full Frame CCD
Image Sensor
Features
• TRUESENSE Transparent Gate Electrode
for High Sensitivity
• High Resolution
• High Dynamic Range
• Low Noise Architecture
Applications
Quantum Efficiency (Color)
R (450 nm)
G (550 nm)
B (650 mm)
33%
40%
33%
Quantum Efficiency
(Monochrome)
Microlens, Clear Glass (540 nm)
Microlens, No Glass (540 nm)
Microlens, AR Glass (540 nm)
No Microlens, Clear G. (560 nm)
54%
60%
56%
37%
Total Sensor Noise
16 e−
Dark Signal
< 200 e−/s
Dark Current Doubling Temp.
5.8°C
Linear Dynamic Range
64.4 dB
Linear Error at 12°C
±10%
Charge Transfer Efficiency
0.999995
Blooming Protection
(1 ms Integration Time)
1000X Saturation Exposure
Maximum Date Rate
28 MHz
Package
32-pin CERDIP, 0.070″ Pin Spacing
Cover Glass
Clear or AR Coated, 2 Sides
• Digitization
• Medical
• Scientific
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: Parameters above are specified at T = 60°C and a data rate of 28 MHz
unless otherwise noted
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 2
1
Publication Order Number:
KAF−8300/D
KAF−8300
The sensor utilizes the TRUESENSE Transparent Gate Electrode to
improve sensitivity compared to the use of a standard front side
illuminated polysilicon electrode.
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAF−8300 IMAGE SENSOR
Part Number
Description
Marking Code
KAF−8300−AAB−CB−AA
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Standard Grade
KAF−8300−AAB−CB−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Grade
KAF−8300−AXC−CB−AA
Monochrome, Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Standard Grade
KAF−8300−AXC−CB−AE
Monochrome, Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Grade
KAF−8300−AXC−CP−AA
Monochrome, Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Standard Grade
KAF−8300−AXC−CP−AE
Monochrome, Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Engineering Grade
KAF−8300−AXC−CD−AA
Monochrome, Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coatings (Both Sides), Standard Grade
KAF−8300−AXC−CD−AE
Monochrome, Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coatings (Both Sides), Engineering Grade
KAF−8300−CXB−CB−AA−Offset
Color (Bayer RGB), Special Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Standard Grade, Offset
KAF−8300−CXB−CB−AE−Offset
Color (Bayer RGB), Special Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Grade, Offset
KAF−8300XE
Serial Number
KAF−8300−AXC
Serial Number
KAF−8300CE
Serial Number
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KAF−8300−12−28−A−EVK
Description
Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−8300
DEVICE DESCRIPTION
Architecture
1 Active (CTE Monitor)
3 Dark Dummy
4 Blue Pixel Buffer
16 Active Buffer
V1
V2
1163 pixels
SUB
OG
R
B
GB
B
GR
R
GR
5.4 microns X 5.4 microns
4:3 Aspect Ratio
GR
1162 pixels
H1L
RD
RG
VDD
VOUT
VSS
GR
248 pixels
ÉÉ
Ä
ÄÄÄÄÄ
ÉÉÄÄÄÄÄ
Ä
ÉÉ
Ä
ÉÉÄÄÄÄÄ
Ä
ÄÄÄÄÄ
ÉÉ
Ä
ÄÄÄÄÄ
ÉÉÄÄÄÄÄ
Ä
3326 (H) X 2504 (V)
3358 (H) X 2536 (V)
2504 Active Lines/Frame
Active Image Area
Effective Image Area
LODT
LODB
Last Hccd Phase: H1
Last Vccd Phase: V2
3326 Active Pixels (typical active line format)
16 Active Buffer
4 Blue Pixel Buffer
5 Dark Dummy
5 Dummy
1 Active (CTE Monitor)
8 Dummy
4 Virtual Dummy Column
16 Active Buffer
4 Blue Pixel Buffer
8 Dark Dummy
39 Dark
6 Dark Dummy
3 Dummy
1 Active (CTE Monitor)
2 Dummy
Figure 2. Block Diagram (Color)
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3
H1
H2
16 Active Buffer
4 Blue Pixel Buffer
8 Dark Dummy
12 Dark
6 Dark Dummy
KAF−8300
1 Active (CTE Monitor)
3 Dark Dummy
20 Active Buffer
V1
V2
1163 pixels
3326 (H) X 2504 (V)
3366 (H) X 2544 (V)
248 pixels
5.4 microns X 5.4 microns
4:3 Aspect Ratio
2504 Active Lines/Frame
Active Image Area
Effective Image Area
1162 pixels
H1L
RD
RG
VDD
VOUT
VSS
SUB
OG
LODT
LODB
Last Hccd Phase: H1
Last Vccd Phase: V2
3326 Active Pixels (typical active line format)
20 Active Buffer
5 Dark Dummy
5 Dummy
1 Active (CTE Monitor)
8 Dummy
4 Virtual Dummy Column
20 Active Buffer
8 Dark Dummy
39 Dark
6 Dark Dummy
3 Dummy
1 Active (CTE Monitor)
2 Dummy
H1
H2
20 Active Buffer
8 Dark Dummy
12 Dark
6 Dark Dummy
Figure 3. Block Diagram (Monochrome)
Dummy Pixels
Within the horizontal shift register there are 13, (8 + 5),
leading and 5, (2 + 3), trailing additional shift phases that are
not electrically associated with any columns of pixels within
the vertical register. These pixels contain only horizontal
shift register dark current signal and do not respond to light
and therefore, have been designated as dummy pixels. For
this reason, they should not be used to determine a dark
reference level.
Dark Reference Pixels
Surrounding the periphery of the device is a border of light
shielded pixels creating a dark region. Within this dark
region there are light shielded pixels that include 39 trailing
dark pixels on every line. There are also 12 full dark lines at
the start of every frame. Under normal circumstances, these
pixels do not respond to light and may be used as a dark
reference.
Dark Dummy Pixels
Within the dark region some pixels are in close proximity
to an active pixel, or the light sensitive regions that have
been added for manufacturing test purposes, (CTE
Monitor). In both cases, these pixels can scavenge signal
depending on light intensity and wavelength. These pixels
should not be used as a dark reference. These pixels are
called dark dummy pixels.
Within the dark region, dark dummy pixels have been
identified. There are 5 leading and 14 (6 + 8) trailing dark
pixels on every line. There are also 14 (6 + 8) dark dummy
lines at the start of every frame along with 3 dark dummy
lines at the end of each frame.
Virtual Dummy Columns
Within the horizontal shift register there is 4 leading shift
phases that are not physically associated with a column of
pixels within the vertical register. These pixels contain only
horizontal shift register dark current signal and do not
respond to light and therefore, have been designated as
virtual dummy columns. For this reason, they also should
not be used to determine a dark reference level.
Active Buffer Pixels
For color devices, sixteen buffer pixels adjacent to the
blue pixel buffer region contain a RGB mosaic color pattern.
This region is classified as active buffer pixels. These pixels
are light sensitive but they are not tested for defects and
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4
KAF−8300
exposure time and non-linearly dependent on wavelength.
When the pixel’s capacity is reached, excess electrons are
discharged into the lateral overflow drain to prevent
crosstalk or ‘blooming’. During the integration period, the
V1 and V2 register clocks are held at a constant (low) level.
non-uniformities. The response of these pixels will not be
uniform.
For monochrome devices, 20 buffer pixels adjacent to the
dark dummy pixels are classified as active buffer pixels.
These pixels are light sensitive but they are not tested for
defects and non-uniformities. The response of these pixels
will not be uniform.
Charge Transport
The integrated charge from each photogate is transported
to the output using a two-step process. Each line (row) of
charge is first transported from the vertical CCD’s to
a horizontal CCD register using the V1 and V2 register
clocks. The horizontal CCD is presented a new line on the
falling edge of V2 while H1 is held high. The horizontal
CCD’s then transport each line, pixel by pixel, to the output
structure by alternately clocking the H1 and H2 pins in
a complementary fashion. A separate connection to the last
H1 phase (H1L) is provided to improve the transfer speed of
charge to the floating diffusion. On each falling edge of H1
a new charge packet is dumped onto a floating diffusion and
sensed by the output amplifier.
Blue Pixel Buffer
For color devices, four buffer pixels adjacent to any
leading or trailing dark reference regions contain a blue filter
and is classified as a blue pixel buffer. These pixels are light
sensitive but they are not tested for defects and
non-uniformities. The response of these pixels will not be
uniform.
Monochrome devices do not contain a blue pixel buffer.
CTE Monitor Pixels
Within the horizontal dummy pixel region two light
sensitive test pixels (one each on the leading and trailing
ends) are added and within the vertical dummy pixel region
one light sensitive test pixel has been added. These CTE
monitor pixels are used for manufacturing test purposes. In
order to facilitate measuring the device CTE, the pixels in
the CTE Monitor region in the horizontal and vertical
portion is coated with blue pigment on the color version
only. The monochrome device is uncoated).
Horizontal Register
Output Structure
Charge presented to the floating diffusion (FD) is
converted into a voltage and is current amplified in order to
drive off-chip loads. The resulting voltage change seen at the
output is linearly related to the amount of charge placed on
the FD. Once the signal has been sampled by the system
electronics, the reset gate (RG) is clocked to remove the
signal and FD is reset to the potential applied by reset drain
(RD). Increased signal at the floating diffusion reduces the
voltage seen at the output pin. To activate the output
structure, an off-chip load must be added to the VOUT pin
of the device. See Figure 5.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the device. These photon-induced
electrons are collected locally by the formation of potential
wells at each photogate or pixel site. The number of
electrons collected is linearly dependent on light level and
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5
KAF−8300
H2
HCCD
Charge
Transfer
H1
H1L
VDD
OG
RG
RD
Floating
Diffusion
VOUT
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 4. Output Architecture (Left of Right)
Output Load
VDD = 15 V
0.1 mF
IOUT = | 5.4 mA |
VOUT
2N3904 or Equivalent
Buffered Video Output
130 W
680 W
NOTE: Component values may be revised based on operating conditions and other design considerations.
Figure 5. Recommended Output Structure Load Diagram
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6
KAF−8300
Physical Description
Pin Description and Device Orientation
Pin 1 Indicator
SUB
1
32
N/C
OG
2
31
LODT
RG
3
30
V1
RD
4
29
V1
RD
5
28
V2
VSS
6
27
V2
VOUT
7
26
SUB
VDD
8
25
N/C
SUB
9
24
V2
H1L 10
23
V2
N/C 11
22
V1
SUB 12
21
V1
H1 13
20
SUB
H1 14
19
N/C
H2 15
18
N/C
H2 16
17
LODB
Figure 6. Pinout Diagram
Table 4. PIN DESCRIPTION
Pin
Name
Substrate
17
LODB
OG
Output Gate
18
N/C
No Connection
3
RG
Reset Gate
19
N/C
No Connection
4
RD
Reset Drain Bias
20
SUB
Substrate
5
RD
Reset Drain Bias
21
V1
Vertical Phase 1
6
VSS
Output Amplifier Return
22
V1
Vertical Phase 1
7
VOUT
Output
23
V2
Vertical Phase 2
8
VDD
Output Amplifier Supply
24
V2
Vertical Phase 2
Pin
Name
1
SUB
2
Description
Description
Lateral Overflow Drain Bottom
9
SUB
Substrate
25
N/C
No Connection
10
H1L
Horizontal Phase 1, Last Gate
26
SUB
Substrate
11
N/C
No Connection
27
V2
Vertical Phase 2
12
SUB
Substrate
28
V2
Vertical Phase 2
13
H1
Horizontal Phase 1
29
V1
Vertical Phase 1
14
H1
Horizontal Phase 1
30
V1
Vertical Phase 1
15
H2
Horizontal Phase 2
31
LODT
16
H2
Horizontal Phase 2
32
N/C
1. Wherever possible, all N/C pins (11, 18, 19, 25, 32) should be connected to GND (0 V).
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7
Lateral Overflow Drain Top
No Connection
KAF−8300
IMAGING PERFORMANCE
Table 5. TYPICAL OPERATIONAL CONDITIONS
Description
Condition − Unless otherwise Noted
Readout Time (tREADOUT)
Notes
370.36 ms
Integration Time (tINT)
Includes tVoverclock & tHoverclock
33 ms
Horizontal Clock Frequency
28 MHz
Light Source (LED)
Red, Green, Blue, Orange
Mode
Flush − Integrate − Readout Cycle
Table 6. SPECIFICATIONS
Symbol
Min.
Nom.
Max.
Unit
Notes
Verification
Plan
MinColumn
575
−
−
mV
1, 4
Die18
Ne-SAT
25.5
−
−
ke-
1, 3, 4
Design19
Q−V
22.5
23.0
−
mV/e-
LeLow10
LeLow33
LeHigh
−10
−10
−10
−
−
−
10
10
10
%
2, 5, 6
2, 5, 6
2, 4, 5
Die18
Dark Signal (Active Area Pixels)
AA_DarkSig
−
−
200
e-/s
4, 8
Die18
Dark Signal (Dark Reference Pixels)
DR_DarkSig
−
−
200
e-/s
4, 8
Die18
Readout Cycle Dark Signal
Dark_Read
−
−
15
mV/s
Die18
Flush Cycle Dark Signal
Dark_Flush
−
43
90
mV/s
Die18
Dark Signal Non-Uniformity
DSNU
DSNU_Step
DSNU_H
−
−
−
1.30
0.14
0.40
3.0
0.5
1.0
mV p-p
DT
−
5.8
−
°C
Dark Reference Difference,
Active Area
DarkStep
−3.5
0.15
3.5
mV
4
Die18
Total Noise
Dfld_noi
−
−
1.08
mV
4, 10
Die18
N
−
16
−
e- rms
19
Design19
DR
−
64.4
−
dB
11
Design19
Horizontal Charge Transfer
Efficiency
HCTE
0.999990
0.999995
−
%
4, 13, 21
Die18
Vertical Charge Transfer Efficiency
VCTE
0.999997
0.999999
−
%
4, 21
Die18
X_b
1,000
−
−
x ESAT
14
Design19
Vertical Bloom on Transfer
VBloomF
−20
−
20
mV
4
Die18
Horizontal Crosstalk
H_Xtalk
−20
−
20
mV
4
Die18
Horizontal Overclock Noise
Hoclk_noi
0
−
1.08
mV
4
Die18
Output Amplifier Bandwidth
f−3dB
88
−
159
MHz
4, 6, 16
Die18
Output Impedance, Amplifier
ROUT
100
−
180
W
6
Die18
Hclk Feedthru
VHFT
−
−
70
mV
4, 17
Die18
Reset Feedthru
VRFT
500
710
1,000
mV
Description
ALL DEVICES
Minimum Column
Linear Saturation Signal
Charge to Voltage Conversion
Linearity Error
Dark Signal Doubling Temperature
Total Sensor Noise
Linear Dynamic Range
Blooming Protection
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8
Design19
4, 9
Die18
Design19
Design19
KAF−8300
Table 6. SPECIFICATIONS (continued)
Description
Unit
Notes
Verification
Plan
Symbol
Min.
Nom.
Max.
RRESP
GRESP
BRESP
260
442
230
−
−
−
420
638
420
Quantum Efficiency
R (600 nm)
G (540 nm)
B (480 nm)
QERED
QEGREEN
QEBLUE
−
−
−
33
40
33
−
−
−
Off-Band Response
Green Inband
Red Response
Blue Response
Red Inband
Green Response
Blue Response
Blue Inband
Red Response
Green Response
Gr_GRESP
Gr_RRESP
Gr_BRESP
Rd_RRESP
Rd_GRESP
Rd_BRESP
Bl_BRESP
Bl_RRESP
Bl_GRESP
362
0
0
180
0
0
90
0
0
−
−
−
−
−
−
−
−
−
630
130
260
430
120
45
420
40
120
Linearity Balance
Red_Bal
Blu_Bal
−14
−8
6.4
0.2
14
8
&
2, 6
Die18
Photo Response Non-Uniformity
R_PRNU
G_PRNU
B_PRNU
−
−
−
−
−
−
15
15
15
% p-p
7
Die18
High Frequency Noise
R_Nois
GRr_Nois
GBr_Nois
B_Nois
−
−
−
−
−
−
−
−
2
2
2
2
% rms
Red-Green Hue Shift
RGHueUnif
−
−
10
%
12
Die18
Blue-Green Hue Shift
BGHueUnif
−
−
12
%
12
Die18
GRr/GBr Hue Uniformity
GrGbHueUnf
−
−
7
%
12
Die18
Green Light GRr/GBr Hue
Uniformity
Gr_GHueUnf
−
−
9
%
Die18
Low Hue Uniformity
RGLoHueUnf
BGLoHueUnf
−
−
−
−
12
10
%
Die18
GrnStreak
RedStreak
BluStreak
−
−
−
−
−
−
40
20
20
%
W_GNU_Min
W_GNU_Max
Gr_GNU_Min
Gr_GNU_Max
R_GNU_Min
R_GNU_Max
B_GNU_Min
B_GNU_Max
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
4
6
4
4
65
65
40
40
Chroma Test
UL_Chroma
UR_Chroma
LL_Chroma
LR_Chroma
−
−
−
−
−
−
−
−
Hue Test
UL_UR_Hue
UL_LR_Hue
UL_LL_Hue
UR_LR_Hue
UR_LL_Hue
LR_LL_Hue
−
−
−
−
−
−
−
−
−
−
−
−
COLOR DEVICES
Sensitivity
Red
Green
Blue
Streak/Spot
Local Green Difference
White Light, min
White Light, max
Green Light, min
Green Light, max
Red Light, min
Red Light, max
Blue Light, min
Blue Light, max
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9
mV
Die18
%
Design19
mV
Die18
Die18
%
Die18
7
7
7
7
%
Die18
6
6
6
6
6
6
%
Die18
KAF−8300
Table 6. SPECIFICATIONS (continued)
Description
Notes
Verification
Plan
Symbol
Min.
Nom.
Max.
Unit
Resp
465
−
655
mV
Die18
%
Design19
−
−
−
−
54
60
56
37
−
−
−
−
MONOCHROME DEVICES
Sensitivity − Monochrome
Quantum Efficiency
Microlens, Clear Glass (540 nm)
Microlens, No Glass (540 nm)
Microlens, AR Glass (540 nm)
No Microlens, Clear G. (560 nm)
QE
1. Increasing output load currents to improve bandwidth will decrease these values.
2. Specified from 12°C to 60°C.
3. Saturation signal level achieved while meeting Le specification. Specified from 0°C to 40°C.
4. Operating temperature = 60°C.
5. Worst case deviation, (from 10 mV to VSAT min), relative to a linear fit applied between 0 and 500 mV exposure.
6. Operating temperature = 25°C.
7. Peak to peak non-uniformity test based on an average of 185 × 185 blocks.
8. Average non-illuminated signal with respect to over clocked horizontal register signal.
9. Absolute difference between the maximum and minimum average signal levels of 185 × 185 blocks within the sensor.
10. Dark rms deviation of a multi-sampled pixel as measured using the KAF−8300 Evaluation Board.
11. 20Log (VSAT / N).
12. Gradual variations in hue (red with respect to green pixels and blue with respect to green pixels) in regions of interest of 185 × 185 blocks.
13. Measured per transfer at 80% of VSAT.
14. ESAT equals the exposure required to achieve saturation. X_b represents the number of ESAT exposures the sensor can tolerate before
failure. X_b characterized at 25°C.
15. Video level DC offset with respect to ground at clamp position. Refer to Figure 17.
16. Last stage only. CLOAD = 10 pF. Then f−3dB = (1 / (2p ⋅ ROUT ⋅ CLOAD)).
17. Amount of artificial signal due to H1 coupling.
18. A parameter that is measured on every sensor during production testing.
19. A parameter that is quantified during the design verification activity.
20. Calculated value subtracting the noise contribution from the KAF−8300 Evaluation Board.
21. Process optimization has effectively eliminated vertical striations.
22. CTE = 1 − CTI. Where CTE is charge transfer efficiency and CTI is charge transfer inefficiency. CTI is the measured value.
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KAF−8300
TYPICAL PERFORMANCE CURVES
KAF−8300 Quantum Efficiency
45%
R
Absolute Quantum Efficiency
40%
B
GRr
GBr
35%
30%
25%
20%
15%
10%
5%
0%
350
450
550
650
750
850
950
1,050
1,150
Wavelength (nm)
Figure 7. Typical Quantum Efficiency (Color Version)
KAF−8300 Quantum Efficiency
70%
Absolute Quantum Efficiency
60%
No Microlens, Clear Glass
Microlens, Clear Glass
50%
Microlens, No Glass
Microlens, MAR Glass
40%
30%
20%
10%
0%
350
450
550
650
750
850
950
Wavelength (nm)
Figure 8. Typical Quantum Efficiency (All Monochrome Versions)
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11
1,050
1,150
KAF−8300
KAF−8300 Angle Response − White Light
1.0
0.9
Normalized Response
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Horizontal − White Light
Vertical − White Light
0.1
0.0
−25
−20
−15
−10
−5
0
5
10
15
20
25
Angle (Deg)
NOTE: The center location of the die is as shown. The effective optical shift is 6° center-to-edge, along the diagonal.
Figure 9. Typical Angular Response (Color Version)
KAF−8300 Vertical Angle Response − Green Light
Normalized Response
1.0
0.8
0.6
0.4
Top
Center
Bottom
0.2
0.0
−30
−25
−20
−15
−10
−5
0
5
10
15
20
Incident Angle (Deg)
NOTE: The effective optical shift is 6° center-to-edge, along the diagonal.
Figure 10. Typical Angular Response (Monochrome with Microlens)
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12
25
30
KAF−8300
DEFECT DEFINITIONS
Table 7. OPERATIONAL CONDITIONS
(The Defect Specifications are measured using the following conditions.)
Description
Test Condition
Notes
Integration Time (tINT)
33 ms
Unless Otherwise Noted
Operating Temperature
60°C
Unless Otherwise Noted
Table 8. SPECIFICATIONS
Symbol
Description
Definition
Threshold
Maximum
Number
Allowed
Notes
COLOR DEVICES
BPnt33_7
Point Defect
Bfld_Pnt_D
Dark Point in an Illuminated Field
11%
Point Defect
Bfld_Pnt_B
Bright Point in an Illuminated Field
7%
Point Defect
BPnt33_100
Dark Field, Major, Short Integration Time
10 mV
Point Defect
BPnt33_500
Dark Field, Major, Short Integration Time
500 mV
0
3
Point Defect
BPnt333_13
Dark Field, Minor, Long Integration Time, tINT = 1/3 s
13 mV
32,500
1, 3, 4
Point Defect
DR_BPnts
Bright Point in the Dark Reference Region
7.5 mV
0
5
Cluster Defect
Total_Clst
A Cluster is a Group of 2 or more Defective Pixels
that do not Exceed the Perpendicular Pattern Defect
−
6 Total
3
Cluster Defect
Dfld_Vperp
Dark Field Very Long Exposure Bright Cluster where
9 or more Adjacent Point Defects Exist, Very Long
Integration Time, tINT = 1 s
3.04 mV
0
3
Cluster Defect −
Perpendicular Pattern
Defect
Dfld_Perp
Bfld_Perp
Total_Perp
Three or more Adjacent Point Defects in the Same
Color Plane, along a Row or Column
−
0
2, 3
Column Defect,
Illuminated
Bfld_Col_D
Bfld_Col_B
A Column which Deviates above or below
Neighboring Columns under Illuminated Conditions
(> 300 mV Signal) greater that the Threshold
1.5%
1.5%
0
3
Column Defect,
Dark Field
Dfld_Col2
Dfld_Col4
Lo_Col_B
Lo_Col_D
Lo_Col_B1
Lo_Col_D1
A Column which Deviates above or below
Neighboring Columns under Non-Illuminated or Low
Light Level Conditions (~10 mV) greater than the
Threshold
1 mV
1 mV
1 mV
1 mV
1 mV
1 mV
0
3
3
5
5
5
5
Row Defect if Row Average Deviates above
Threshold
1 mV
0
3
Row Defect
Dfld_Row
LOD Bright Col, Dark
Dark Field, Minor, Short Integration Time
7.5 mV
800 Total
Points
Allowed for
this Group of
Tests
Point Defect
3
3
3
3
Dfld_LodCol
Defines Functionality and Uniform Efficiency of LOD
Structure
1.5 mV
0
3
GrnStreak
RedStreak
BluStreak
Maximum Defect Density Gradient Allowed in a Color
Bit Plane (Note 4)
40%
20%
20%
0
Streak
Test,
Color
BPnt33_7
Dark Field, Minor, Short Integration Time
7.5 mV
800
Point Defect, Dark Field
BPnt33_100
Dark Field, Major, Short Integration Time
100 mV
6
Point Defect, Dark Field
DfBP_33_200
Dark Field, Major, Short Integration Time
200 mV
0
Point Defect, Dark Field
BPnt33_500
Dark Field, Major, Short Integration Time
500 mV
0
Point Defect,
Bright Field
Bfld_Pnt_D
Dark Point in an Illuminated Field, Short Integration
Time
11%
800
Point Defect,
Bright Field
Bfld_Pnt_B
Bright Point in an Illuminated Field, Short Integration
Time
7%
800
Streak Test, Color
MONOCHROME DEVICES
Point Defect, Dark Field
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13
KAF−8300
Table 8. SPECIFICATIONS (continued)
Description
Symbol
Threshold
Maximum
Number
Allowed
Notes
Bright Point in the Dark Reference Region
7.5 mV
0
5
13 mV
32,500
Definition
MONOCHROME DEVICES
Point Defect,
Dark Reference
DR_BPnts
Dim Points, Dark Field
BPnt333_13
Dark Field, Minor, Long Integration Time, tINT = 1/3 s
Total Points
Bright and
Dark Points
BPnt33_7 + Bfld_Pnt_D + Bfld_Pnt_B
−
800
−
6
3.04 mV
0
Cluster Defect
Total_Clst
A Cluster is a Group of 2 or 10 Adjacent Defective
Dark or Bright Points
Perpendicular Pattern
Defect
Total_Perp
Dark Field Very Long Exposure Bright Cluster where
9 or more Adjacent Point Defects Exist, Very Long
Integration Time, tINT = 1 s
Column Defect,
Bright Field
Bfld_Col_D
Bfld_Col_B
A Column which Deviates above or below
Neighboring Columns under Illuminated Conditions
(> 300 mV Signal) greater that the Threshold
1.5%
1.5%
0
Column Defect,
Dark Field
Dfld_Col2
Dfld_Col4
Lo_Col_B
Lo_Col_D
Lo_Col_B1
Lo_Col_D1
A Column which Deviates above or below
Neighboring Columns under Non-Illuminated or Low
Light Level Conditions (~10 mV) greater than the
Threshold
1 mV
1 mV
1 mV
1 mV
1 mV
1 mV
0
Row Defect if Row Average Deviates above
Threshold
1 mV
0
1.5 mV
0
Row Defect
LOD Bright Col, Dark
Dfld_Row
Dfld_LodCol
Defines Functionality and Uniform Efficiency of LOD
Structure
5
5
5
5
1. This parameter is only a quality metric and these points will not be considered for cluster and point criteria.
2. For the color version of this device, the green pixels in a red row (GR) are considered a different color plane than the green pixels in a blue
row (GB). For monochrome version the entire active area is treated as a single color plane.
3. Operating temperature = 60°C.
4. As the gradient threshold is defined as 8.5 mV maximum across a 16 × 16 pixel region about each pixel.
5. Operating temperature = 25°C.
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14
KAF−8300
OPERATION
Table 9. ABSOLUTE MAXIMUM RATINGS
Description (Note 9)
Symbol
Minimum
Maximum
Unit
Notes
Diode Pin Voltages
VDIODE
−17.5
17.5
V
1, 2
Gate Pin Voltages
VGATE1
−13.5
13.5
V
1, 3
V1−2
−13.5
13.5
V
4
Non-Overlapping Gate Voltages
Vg−g
−13.5
13.5
V
5
V1, V2 − LOD Voltages
VVVL
−13.5
13.5
V
6
Output Bias Current
IOUT
−
−30
mA
7
LODT Diode Voltage
VLODT
−13.0
13.0
V
8
LODB Diode Voltage
VLODB
−18.0
18.0
V
8
Operating Temperature
TOP
−10
70
°C
10
Guaranteed Temperature of Performance
TSP
0
60
°C
11
Overlapping Gate Voltages
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to pin SUB.
2. Includes pins: RD, VDD, VSS, and VOUT.
3. Includes pins: V1, V2, H1, H1L, H2, RG, OG.
4. Voltage difference between overlapping gates. Includes: V1 to V2; H1, H1L to H2; H1L to OG; V1 to H2.
5. Voltage difference between non-overlapping gates. Includes: V1 to H1, H1L; V2, OG to H2.
6. Voltage difference between V1 and V2 gates and LODT, LODB diode.
7. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher currents and
lower load capacitance at the expense of reduced gain (sensitivity). Operation at these values will reduce MTF.
8. V1, H1, V2, H2, H1L, OG, and RD are tied to 0 V.
9. Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or condition
is exceeded, the device will be degraded and may be damaged.
10. Noise performance will degrade at higher temperatures.
11. See section for Imaging Performance Specifications.
Power-Up Sequence
The sequence chosen to perform an initial power-up is not
critical for device reliability. A coordinated sequence may
minimize noise and the following sequence is
recommended:
1. Connect the ground pins (SUB).
2. Supply the appropriate biases and clocks to the
remaining pins.
Table 10. DC BIAS OPERATING CONDITIONS
Symbol
Minimum
Nominal
Maximum
Unit
Maximum DC
Current (mA)
RD
11.3
11.5
11.7
V
IRD = 0.01
Output Amplifier Return
VSS
1.05
1.25
1.45
V
ISS = −3.0
Output Amplifier Supply
VDD
14.5
15.0
15.5
V
IOUT + ISS
Substrate
SUB
−
GND
−
V
−0.01
Output Gate
OG
−3.0
−2.8
−2.6
V
0.1
Lateral Drain
LODT, LODB
9.5
9.75
10.0
V
0.2
2
IOUT
−3
−5
−8
mA
−
1
Description
Reset Drain
Video Output Current
1. An output load sink must be applied to VOUT to activate output amplifier − see Figure 5.
2. Maximum current expected up to saturation exposure (ESAT).
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15
Notes
2
KAF−8300
AC Operating Conditions
Table 11. CLOCK LEVELS
Symbol
Level
Min.
Nom.
Max.
Unit
Effective
Capacitance
Notes
V1 Low Level
V1L
Low
−9.5
−9.25
−9.0
V
76 nF
1
V1 High Level
V1H
High
2.4
2.6
2.85
V
V2 Low Level
V2L
Low
−9.5
−9.25
−9.0
V
V2 High Level
V2H
High
2.4
2.6
2.8
V
RG, H1, H2, Amplitude
RGAMP
H1AMP
H2AMP
Amplitude
5.5
6.0
6.5
V
RG = 7 pF
H1 = 224 pF
H2 = 168 pF
1
H1L, Amplitude
H1LAMP
Amplitude
7.5
8.0
8.5
V
7 pF
1
H1 Low Level
H1LOW
Low
−4.7
−4.5
−4.3
V
H1L Low Level
H1LLOW
Low
−6.7
−6.5
−6.3
V
H2 Low Level
H2LOW
Low
−5.2
−5.0
−4.8
V
RG Low Level
RGLOW
Low
1.8
2.0
2.2
V
Description
1
81 nF
1
1
1
1
1. All pins draw less than 10 mA DC current. Capacitance values relative to SUB (substrate).
Table 12. CLOCK VOLTAGE DETAIL CHARACTERISTICS
Description
Symbol
Min.
Nom.
Max.
Unit
Notes
V1 High-Level Variation
V1HH
−
0.50
1.0
V
High-Level Coupling
V2 High-Level Variation
V2HL
−
0.28
1.0
V
High-Level Coupling
V2 Low-Level Variation
V2LH
−
0.46
1.0
V
Low-Level Coupling
V1 Low-Level Variation
V1LL
−
0.14
1.0
V
Low-Level Coupling
V1−V2 Cross-Over
V1CR
−2.0
−0.5
1.0
V
Referenced to Ground
H1 High-Level Variation
H1HH
−
0.30
1.0
V
H1 High-Level Variation
H1HL
−
0.07
1.0
V
H1 Low-Level Variation
H1LH
−
0.16
1.0
V
H1 Low-Level Variation
H1LL
−
0.25
1.0
V
H2 High-Level Variation
H2HH
−
0.40
1.0
V
H2 High-Level Variation
H2HL
−
0.06
1.0
V
H2 Low-Level Variation
H2LH
−
0.10
1.0
V
H2 Low-Level Variation
H2LL
−
0.27
1.0
V
H1−H2 Cross-Over
H1CR1
−3.0
−1.23
0
V
Rising Side of H1
H1−H2 Cross-Over
H1CR2
−3.0
−0.59
0
V
Falling Side of H1
H1L High-Lever Variation
H1LHH
−
0.64
1.0
V
H1L High-Lever Variation
H1LHL
−
0.32
1.0
V
H1L Low-Lever Variation
H1LLH
−
0.27
1.0
V
H1L Low-Lever Variation
H1LLL
−
0.23
1.0
V
H1LCR1
−1.0
−
−3.0
V
RG High-Level Variation
RGHH
−
0.19
1.0
V
RG High-Level Variation
RGHL
−
0.20
1.0
V
RG Low-Level Variation
RGLH
−
0.11
1.0
V
RG Low-Level Variation
RGLL
−
0.30
1.0
V
H1L−H2 Cross-Over
Rising Side of H1L
1. H1, H2 clock frequency: 28 MHz. The maximum and minimum values in this table are supplied for reference. The actual clock levels were
measured using the KAF−8300 Evaluation Board. Testing against the device performance specifications is performed using the nominal
values.
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16
KAF−8300
Capacitance Equivalent Circuit
CfV12
V1
V2
CfV2
CfV1
SUB
CfH1L
H1L
RH1LH1
H2
H1
CfH12
CfH1
CfH2
Notes:
1. The external pin names are actual pins on this image sensor. See the pinout diagram (Figure 6) for more information.
2. The components shown in this schematic model do not correspond to actual components inside the image sensor.
Figure 11. Equivalent Circuit Model
Table 13.
Parameter
Value (Typical)
Unit
CfV1
61
nF
CfV12
15
nF
CfV2
67
nF
CfH1
153
pF
CfH12
36
pF
CfH2
97
pF
CfH1L
7
pF
RH1LH1
52
kW
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17
KAF−8300
TIMING
Table 14. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Unit
Notes
H1, H2 Clock Frequency
fH
−
−
28
MHz
1, 2
V1, V2 Clock Frequency
fV
−
−
125
kHz
2
2
Pixel Period (1 Count)
te
35.7
−
−
ns
H1, H2 Set-up Time
tHS
1
−
−
ms
H1L−VOUT Delay
tHV
0
3
−
ns
RG−VOUT Delay
tRV
0
1
−
ns
tREADOUT
340.2
−
−
ms
tINT
−
−
−
Line Time
tLINE
132.2
−
−
ms
4
Flush Time
tFLUSH
21.23
−
−
ms
6
Readout Time
Integration Time
1.
2.
3.
4.
5.
6.
4, 5
3, 4
50% duty cycle values.
CTE will degrade above the nominal frequency.
Integration time is user specified.
Longer times will degrade noise performance.
tREADOUT = tLINE ⋅ 2574 lines.
See Figure 19 for a detailed description.
Table 15. CLOCK SWITCHING CHARACTERISTICS
Description
Symbol
Min.
Nom.
Max.
Unit
Notes
V1 Rise Time
tV1r
−
0.26
1
ms
3
V2 Rise Time
tV2r
−
0.55
1
ms
3
V1 Fall Time
tV1f
−
0.43
1
ms
3
V2 Fall Time
tV2f
−
0.31
1
ms
3
V1 Pulse Width
tV1w
5.0
−
−
ms
4, 5
V2 Pulse Width
tV2w
3.0
−
−
ms
4, 5
H1 Rise Time
tH1r
−
9.0
10
ns
3
H2 Rise Time
tH2r
−
6.9
10
ns
3
H1 Fall Time
tH1f
−
5.8
10
ns
3
H2 Fall Time
tH2r
−
5.4
10
ns
3
tH1w, tH2w
14
18
22
ns
tH1Lr
−
1.8
4
ns
3
3
H1−H2 Pulse Width
H1L Rise Time
H1L Fall Time
tH1Lf
−
2.5
4
ns
H1L Pulse Width
tH1Lw
14
19
22
ns
RG Rise Time
tRGr
−
2.0
4
ns
3
RG Fall Time
tRGf
−
2.2
4
ns
3
RG Pulse Width
tRGw
−
6.7
−
ns
2
1. H1, H2 clock frequency: 28 MHz. The maximum and minimum values in this table are supplied for reference. The actual clock timing was
measured using the KAF−8300 Evaluation Board. Testing against the device performance specifications is performed using the nominal
values.
2. RG should be clocked continuously.
3. Relative to the pulse width (based on 50% of high/low levels).
4. CTE
5. Longer times will degrade noise performance.
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18
KAF−8300
Edge Alignment
tH1w
tH2w
H1HH
H2HH
H2HL
H1HL
H1
H2
100%
100%
90%
90%
H2
H2
H1CR2
H1CR1
50%
50%
H1
H1
10%
0%
10%
0%
H1LH
tH1r
H1LL
tH1f
H2LH
tH2r
H2LL
Figure 12. H1 and H2 Edge Alignment
tH1Lw
H1LHH
H1LHL
100%
90%
H1LCR1
50%
H1L
H2
10%
0%
tH1Lr
tH1Lf
H1LLH
H1LLL
Figure 13. H1L and H2 Edge Alignment
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19
tH2f
KAF−8300
Frame Timing
tINT
Line
V1
tREADOUT
1
2
3
2573
2574
V2
H2
H1,
H1L
Figure 14. Frame Timing (Minimum)
Frame Timing Detail
V1HH
tV1w
tV2w
V1
V2
100%
90%
V2HL
V1CR
(Referenced to Ground)
50%
10%
0%
V2LH
V1LL
tr
tf
Figure 15. Frame Timing Edge Alignment
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20
te
Quantity Grouping:
Pixel Count:
RG
H2
H1, H1L
V2
V1
tHS
28
27
24
23
22
19
18
14
13
12
11
1
ÍÍ
ÍÍ
ÉÉ
ÍÍ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÄÄ
ÄÄ
ÄÄ
⊗
tLINE
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
(39) Dark Pixels
3391
3390
3389
(8) Dark Dummy Pixels
3386
3385
(4) Blue Pixel Buffer
3370
3369
3368
3367
3366
3365
(16) Active Buffer Pixels
47
46
45
44
43
(3326) Active Pixels
(16) Active Buffer Pixels
(4) Blue Pixel Buffer
(5) Dark Dummy Pixels
(5) Dummy Pixels
5
4
(1) CTE Monitor Pixels
(8) Dummy Pixels
(4) Virtual Dummy Columns
Figure 16. Line Timing
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21
* Lines 7−18 are lines mostly composed of dark reference pixels.
** Lines 31−46 and 2555−2570 are lines mostly composed of photoactive buffer pixels.
*** Lines 27−30 and 2551−2554 are lines mostly composed of blue photoactive buffer pixels.
(6) Dark Dummy Pixels
ÉÉÉÉ
ÉÉÉÉ
⊗ For lines 1 thru 1163 are as shown above with the following exception: pixel 13 are denoted as a test pixel,
of which all are dark dummy except for one photoactive pixel for which row location may vary.
⊗ For lines 1412 thru 2570 are as shown above with the following exception: pixel 13 are denoted as a dark
dummy pixels for these lines.
**** Lines 1−6, 19−26, and 2571−2574 are lines mostly composed of dark dummy pixels and are not to be
used for imaging purposes or as a dark reference.
3438
3437
3436
test
3398
3397
3396
3395
The device output for the other lines are detailed below:
3448
3447
3446
3445
3444
3443
3442
3441
KAF−8300 has 2574 lines (rows) in a single frame. Line shown above represents
the device output for lines 1164−1411 only.
KAF−8300
Line Timing
(2) Dummy Pixels
(1) CTE Monitor Pixels
(3) Dummy Pixels
NOTE: Schematic reference regions that contain a blue filter represent the color version only; monochrome version is uncoated for these
pixels.
KAF−8300
Pixel Timing
te
1 Count
tGRw
RG
RGAMP
RGLow
H1AMP
H1
H1Low
H2
H2AMP
H2Low
H1L
H1LAMP
H1LLow
tHV
tRV
VOUT
VRFT
VODC
VDARK + VHFT
VSAT
GND
Figure 17. Pixel Timing
Pixel Timing Detail
tRGw
RGHL
RGHH
100%
90%
RG
50%
10%
0%
tRGr
tRGf
RGLH
RGLL
Figure 18. Pixel Timing Detail
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22
KAF−8300
MODE OF OPERATION
Power-Up Flush Cycle
tINT
tVflush
tREADOUT
V2
2574+64 (min)
V1
te
H2
3448 (min)
H1,
H1L
Figure 19. Power-Up Flush Cycle
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23
KAF−8300
MECHANICAL INFORMATION
Visual Mechanical Specifications
Table 16. LASER MARK
Item
Description
Device Name
KAF−8300CE, KAF−8300XE, KAF−8300−AXC (Multiple versions available).
See Ordering Information section of this document.
Serial Number
nnn −a numeric field containing a maximum of three characters denoting a unique unit identifier for a device
from the before mentioned production lot. The start of the sequence starts with “1”. “001” is not a valid
marking.
NOTE: All markings shall be readable, consistent in size with no unusual debris left on the package.
Table 17. ASSEMBLY/PACKAGE INTEGRITY
Criteria
Description
Cracks
None allowed.
Corner and Edge
Chip-Outs
None − exceeding 0.020″ (0.50 mm).
Chip-Outs Exposing
Buried Metal Traces
None allowed.
Chip-Outs, Other
None allowed deeper than 50% of the ceramic layer thickness in which it resides.
Scratches
None − that exceed 0.020″ (0.50 mm) in the major dimension and are deeper than 50% of the ceramic layer
thickness in which it resides.
Lead Conditions
No bent, missing, damaged, or short leads. No lead cut-off burrs exceeding 0.005″ (0.13 mm) in the
dimension away from the lead.
Internal Appearance
and Die Condition
Local Non-Uniformity: Local Non-Uniformity region (LNU) is allowed whose size is not greater than 200 mm2
within the effective image area. Inspection equipment for these steps are performed using a microscope
7−50X and direct lighting (ring-light). LNU is described as a spot or streak that tends to change from light to
dark in appearance as the operator rotates the part under angled lighting conditions. These non-uniformities
are not visible or very hard to see under direct lighting. They tend to disappear or become much less visible
under higher magnification.
Conditions Other than LNU: No scratches, digs, contamination, marks, or blemishes that is attached to the
die that touches 9 or more pixels in the effective image area. No loose contamination allowed when viewed
at 7X and 50X magnification. No scratches, digs, contamination, marks, or blemishes greater than 10 mm are
allowed on the bottom side of the cover glass region that is contained in or extends into the effective image
area. Tools used to verify are 7X and 50X magnification.
Table 18. GLASS
Criteria
Description
Tilt
The reject condition is when the glass is incorrectly seated on the package or is not parallel to glass seal
area. (“parallel” is defined as 0.25 mm maximum end to end).
Seal
Glass seal must be greater than 50% of the width of the epoxy bond line and must not extend over the
ceramic package.
Alignment
There are 4 “+” fiducials on the corners the die that must not be covered by the epoxy light shield.
The 4 “+” marks must be in total view when the lid is placed looking directly down on the device with
a microscope. All 4 “+” alignment marks are required to be visible in their entirety with a zero clearance
tolerance.
Chips
None allowed.
Appearance
No fogged cover allowed.
Contamination
No immobile scratches, digs, contamination, marks, or blemishes are allowed on the cover glass region that
is contained in or extends into the effective image area. Within the effective image area, the limit for such
conditions is 10 mm or less. This criterion pertains to either the top or the bottom glass surface. Tools used to
verify are 7X and 50X magnification.
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KAF−8300
Completed Assembly
Figure 20. Completed Assembly (1 of 2)
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25
KAF−8300
Figure 21. Completed Assembly (2 of 2)
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KAF−8300
Cover Glass
Clear Cover Glass, AR Coated (Both Sides) − Specification
1. Scratch and Dig: 10 micron max
2. Substrate Material Schott D263T Eco or Equivalent
3. Multilayer Anti-Reflective Coating
Table 19.
Wavelength
Total Reflectance
420−450
≤ 2%
450−630
≤ 1%
630−680
≤ 2%
Transmission (%)
Clear Cover Glass − Specification
1. Scratch and Dig: 10 micron max
2. Substrate Material Schott D263T Eco or Equivalent
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
300
350
400
450
500
550
600
650
700
750
800
Wavelength (nm)
Figure 22. Clear Cover Glass Transmission (Typical)
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27
850
900
KAF−8300
REFERENCES
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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28
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
KAF−8300/D