Single-chip Type with Built-in FET Switching Regulator Series Output 2A or More High-efficiency Step-down Switching Regulator with Built-in Power MOSFET No.09027EAT37 BD9141MUV ●Description ROHM’s high efficiency step-down switching regulator BD9141MUV is a power supply designed to produce a low voltage including 5.0/3.3 volts from 2 lithium cell power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. ●Features 1) Offers fast transient response with current mode PWM control system. 2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) and SLLM (Simple Light Load Mode) 3) Incorporates soft-start function. 4) Incorporates thermal protection and ULVO functions. 5) Incorporates short-current protection circuit with time delay function. 6) Incorporates shutdown function 7) Employs small surface mount package : VQFN020V4040 ●Applications Power supply for LSI including DSP, Micro computer and ASIC ●Line up matrix Parameter VCC Voltage PVCC Voltage EN Voltage SW,ITH Voltage,VREG Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating temperature range Storage temperature range Maximum junction temperature ＊１ ＊２ ＊３ ＊４ ＊５ Symbol VCC PVCC VEN VSW,VITH, VREG Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax Limits BD9141MUV -0.3～+15 ＊1 -0.3～+15 ＊1 -0.3～+15 -0.3～+15 0.34＊2 0.70＊3 2.21 *4 3.56 *5 -40～+105 -55～+150 +150 Unit V V V V W W W W ℃ ℃ ℃ Pd should not be exceeded. IC only. 2 1 layer, mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB (Copper foil area : 10.29mm ) 4 layers, mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB st th 2 nd rd 2 (1 ,4 Copper foil area : 10.29mm 2 ,3 Copper foil area : 5505mm ) ,. 2 4 layers, mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB (Copper foil area : 5505mm ) , copper foil in each layers. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/18 2009.06 - Rev.A Technical Note BD9141MUV ●Operating Conditions (Ta=-40～+105℃) Parameter VCC Voltage PVCC Voltage EN Voltage SW average output current Output voltage Setting Range ＊6 ＊7 Symbol VCC *6 PVCC *6 VEN Isw *6 VOUT*7 Min. 4.5*7 4.5*7 0 2.5 BD9141MUV Typ. 8.0 8.0 - Unit Max. 13.2 13.2 VCC 2.0 6.0 V V V A V Pd should not be exceeded. VccMin. = Vout + 1.3V. ●Electrical Characteristics ◎BD9141MUV (Ta=25℃, VCC=PVCC=8.0V, EN=VCC, R1=8.2kΩ, R2=43kΩ, unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit Conditions Standby current ISTB 0 10 μA EN=GND Bias current ICC 300 500 μA EN Low voltage VENL GND 0.8 V Standby mode EN High voltage VENH 2.0 VCC V Active mode EN input current IEN 1.6 10 μA VEN=8V Oscillation frequency FOSC 400 500 600 KHz Pch FET ON resistance RONP 150 300 mΩ PVCC=8V Nch FET ON resistance RONN 80 160 mΩ PVCC=8V ADJ Voltage VADJ 0.788 0.800 0.812 V ITH SInk current ITHSI 10 20 μA VADJ=1.0V ITH Source Current ITHSO 10 20 μA VADJ=0.6V UVLO threshold voltage VUVLO1 3.90 4.10 4.30 V VCC=8V→0V UVLO release voltage VUVLO2 3.95 4.20 4.50 V VCC=0V→8V Soft start time TSS 0.5 1 2 ms Timer latch time TLATCH 1 2 3 ms SCP/TSD operated Output Short circuit 0.4 0.56 V VADJ=0.8V→0V VSCP Threshold Voltage www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/18 2009.06 - Rev.A Technical Note BD9141MUV ●Block Diagram, Application Circuit VCC 【BD9141MUV】 EN VREG 4.0±0.1 5V VCC 4.0±0.1 VREF D9141 Input 0.8V Current Comp 1.0Max. Lot No. PVCC R Q Current Sense/ Protect S + S C0.2 2.1±0.1 16 10 1.0 15 Driver Logic SW UVLO Soft Start 5 6 Output CLK VCC TSD 2.1±0.1 0.4±0.1 1 20 SLOPE OSC 0.02 +0.03 -0.02 (0.22) 0.08 S Gm Amp. SCP PGND GND ITH ADJ 11 +0.05 RITH 0.25 -0.04 0.5 Fig.1 BD9141MUV View R1 CITH R2 Fig.2 BD9141MUV Block Diagram ●Pin No. & function table Pin No. 1,2,3,4,5 6,7,8 9 10 11 12 13 14 15,16 17 18,19,20 Pin Name SW PVCC N.C. Vcc GND ADJ ITH VREG N.C. EN PGND BD9141MUV Pin Function Pch/Nch FET drain output pin Pch FET source pin Non connection VCC power supply input pin Ground Output voltage detect pin GmAmp output pin/Connected phase compensation capacitor Reference Voltage Non connection Enable pin(Active High) Nch FET source pin www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/18 2009.06 - Rev.A Technical Note BD9141MUV ●Characteristics data【BD9141MUV】 6.0 6.0 【VOUT=5V】 Ta=25℃ Io=2A 4.0 3.0 2.0 1.0 5.0 4.0 3.0 2.0 VCC=8V Ta=25℃ Io=0A 1.0 0 2 4 6 8 10 INPUT VOLTAGE:VCC[V] 0 12 1 2 3 4 EN VOLTAGE:VEN[V] Fig.3 VCC-VOUT 4.95 600 【VOUT=5V】 VCC=8V Ta=25℃ 70 60 50 40 30 4.90 20 4.85 10 60 TEMPERATURE:Ta[℃] Fig. 6 Ta-VOUT 1.8 VCC=8V 10 100 1000 OUTPUT CURRENT:IOUT[mA] 100 80 NMOS 60 40 ON RESISTANCE:RON[Ω] PMOS 120 -40 -15 10 35 60 85 TEMPERATURE:Ta[℃] Fig.9 Ta-RONN, RONP www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8 VCC=8V 200 -40 -15 10 35 60 85 Fig.8 Ta-FOSC 400 VCC=8V 1.4 1.2 1.0 0.8 0.6 0.2 0 7 TEMPERATURE:Ta[℃] 0.4 20 6 300 10000 1.6 140 5 400 CIRCUIT CURRENT:I CC[μA] 2.0 180 4 500 Fig.7 Efficiency 200 3 0 1 85 2 100 0 4.80 1 OUTPUT CURRENT:IOUT[A] VCC=8V Fig.5 IOUT-VOUT FREQUENCY:FOSC[kHz] EFFICIENCY:η[%] OUTPUT VOLTAGE:VOUT[V] 5.00 160 VCC=8V Ta=25℃ 700 80 35 【VOUT=5V】 1.0 0 90 5.05 10 2.0 5 100 【VOUT=5V】 VCC=8V 5.10 Io=0A 5.15 -15 3.0 Fig.4 VEN-VOUT 5.20 -40 4.0 0.0 0.0 0.0 ON RESISTANCE:RON[Ω] 5.0 OUTPUT VOLTAGE:VOUT[V] 5.0 OUTPUT VOLTAGE:VOUT[V] OUTPUT VOLTAGE:VOUT[V] 【VOUT=5V】 350 VCC=8V 300 250 200 150 100 50 0 -40 0.0 -40 -15 10 35 60 TEMPERATURE:Ta[℃] Fig.10 Ta-VEN 4/18 85 -15 10 35 60 85 TEMPERATURE:Ta[℃] Fig.11 Ta-Icc 2009.06 - Rev.A Technical Note BD9141MUV FREQUENCY:FOSC[kHz] 530 VCC=PVCC =EN 520 【VOUT=5V】 SW 【SLLM control VOUT=5V】 510 Ta=25℃ 500 VOUT VOUT 490 VCC=8V Ta=25℃ Io=0A 480 470 5 6 7 8 9 10 11 INPUT VOLTAGE:VCC[V] 12 13 Fig.13 Soft start waveform Fig.12 VCC-FOSC 【PWM control VCC=8V Ta=25℃ Io=0A Fig.14 SW waveform Io=10mA 【VOUT=5V】 VOUT=5V】 SW VOUT VOUT VOUT IOUT IOUT VCC=8V Ta=25℃ VCC=8V Ta=25℃ Fig.15 SW waveform Io=2000mA www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Fig. 16Transient response Io=0.5A→1A(10μs) 5/18 VCC=8V Ta=25℃ Fig.17 Transient response Io=1A→0.5A(10μs) 2009.06 - Rev.A Technical Note BD9141MUV ●Information on advantages Advantage 1：Offers fast transient response with current mode control system. BD9141MUV (Load response IO=0.5A→1A) Conventional product (Load response IO=0.5A→1A) VOUT VOUT 50mV 110mV IOUT IOUT Voltage drop due to sudden change in load was reduced by about 50%. Fig.18 Comparison of transient response Advantage 2： Offers high efficiency for all load range. ・For lighter load: Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load. Achieves efficiency improvement for lighter load. ・For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of P-channel MOS FET : 150mΩ(Typ.) ON resistance of N-channel MOS FET : 80mΩ(Typ.) Efficiency η[%] 100 Achieves efficiency improvement for heavier load. SLLM ② 50 ① PWM ①improvement by SLLM system ②improvement by synchronous rectifier 0 0.001 Offers high efficiency for all load range with the improvements mentioned above. 0.01 0.1 Output current Io[A] 1 Fig.19 Efficiency Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated. ・Output capacitor Co required for current mode control: 22μF ceramic capacitor ・Inductance L required for the operating frequency of 1MHz: 2.2μH inductor (BD9141MUV:Co=22μF, L=4.7μH) Reduces a mounting area required. VCC 15mm Cin CIN DC/DC Convertor Controller RITH L RITH L VOUT 10mm CITH Co CO CITH Fig.20 Example application www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/18 2009.06 - Rev.A Technical Note BD9141MUV ●Operation BD9141MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. ○Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. ○Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. ・PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 500kHz. SET signal form OSC turns ON a P-channel MOS FET (while a N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. ・SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency. SENSE Current Comp RESET VOUT Level Shift R Q FB SET Gm Amp. ITH IL Driver Logic S VOUT SW Load OSC Fig.21 Diagram of current mode PWM control PVCC Current Comp SENSE PVCC SENSE Current Comp FB FB SET GND SET GND RESET GND RESET GND SW GND SW IL GND IL(AVE) IL 0A VOUT VOUT VOUT(AVE) Fig.22 PWM switching timing chart www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. VOUT(AVE) Fig.23 SLLM 7/18 TM Not switching switching timing chart 2009.06 - Rev.A Technical Note BD9141MUV ●Description of operations ・Soft-start function EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. ・Shutdown function With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μA (Typ.). ・UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 100mV (Typ.) is provided to prevent output chattering. Hysteresis 100mV VCC EN VOUT Tss Tss Tss Soft start Standby mode Operating mode UVLO Standby mode Operating mode UVLO Standby mode EN Operating mode Standby mode UVLO Fig.24 Soft start, Shutdown, UVLO timing chart www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/18 2009.06 - Rev.A Technical Note BD9141MUV ・Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO. EN Output OFF latch Output Short circuit Threshold Voltage VOUT IL Limit IL t1<TLATCH Standby mode t2=TLATCH Operating mode Standby mode Timer latch EN Operating mode EN Fig.25 Short-current protection circuit with time delay timing chart ●Switching regulator efficiency Efficiency ŋ may be expressed by the equation shown below: η= VOUT×IOUT Vin×Iin ×100[%]= POUT Pin ×100[%]= POUT POUT+PDα ×100[%] Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FET：PD(I R) 2) Gate charge/discharge dissipation：PD(Gate) 3) Switching dissipation：PD(SW) 4) ESR dissipation of capacitor：PD(ESR) 5) Operating current dissipation of IC：PD(IC) 2 2 1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output current.) 2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET) Vin2×CRSS×IOUT×f 3)PD(SW)= (CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.) IDRIVE 2 4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.) 5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/18 2009.06 - Rev.A Technical Note BD9141MUV ●Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation. ① Power dissipation:Pd [W] 4.0 ①3.56W ② ③ 3.0 ④ 2 4 layers (Copper foil area : 5505mm ) copper foil in each layers. θj-a=35.1℃/W 2 4 layers (Copper foil area : 10.29m ) copper foil in each layers. θj-a=56.6℃/W 2 4 layers (Copper foil area : 10.29m ) θj-a=178.6℃/W IC only. θj-a=367.6℃/W 2 P=IOUT ×RON RON=D×RONP+(1-D)RONN D：ON duty (=VOUT/VCC) RCOIL：DC resistance of coil RONP：ON resistance of P-channel MOS FET RONN：ON resistance of N-channel MOS FET IOUT：Output current ②2.21W 2.0 1.0 ③0.70W ④0.34W 0 0 25 50 75 100105 125 150 Ambient temperature:Ta [℃] Fig.26 Thermal derating curve (VQFN020V4040) If VCC=8V, VOUT=5V, RONP=0.15Ω, RONN=0.08Ω IOUT=2A, for example, D=VOUT/VCC=5/8=0.625 RON=0.625×0.15+(1-0.625)×0.08 =0.09375+0.03 =0.12375[Ω] P=22×0.12375＝0.495[W] As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/18 2009.06 - Rev.A Technical Note BD9141MUV ●Selection of components externally connected 1. Selection of inductor (L) IL The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. (VCC-VOUT)×VOUT ΔIL= [A]・・・(1) L×VCC×f ΔIL VCC IL Appropriate ripple current at output should be 20% more or less of the maximum output current. VOUT L ΔIL=0.2×IOUTmax. [A]・・・(2) Co (VCC-VOUT)×VOUT L= Fig.27 Output ripple current ΔIL×VCC×f [H]・・・(3) (ΔIL: Output ripple current, and f: Switching frequency) *Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=3.3V, VOUT=1.8V, f=1MHz, ΔIL=0.2×2A=0.4A, for example,(BD9141MUV) (8-5)×5 L= 0.6×8×500k =6.25μ → 6.3[μH] *Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO) VCC Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4)： VOUT L ESR ΔVOUT=ΔIL×ESR [V]・・・(4) Co (ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor) Fig.28 Output capacitor www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. *Rating of the capacitor should be determined allowing sufficient margin against output voltage. A 22μF to 100μF ceramic capacitor is recommended. Less ESR allows reduction in output ripple voltage. 11/18 2009.06 - Rev.A Technical Note BD9141MUV 3. Selection of input capacitor (Cin) VCC Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (5): Cin VOUT IRMS=IOUT× L √VOUT(VCC-VOUT) [A]・・・(5) VCC Co < Worst case > IRMS(max.) IOUT When Vcc is twice the VOUT, IRMS= 2 If VCC=8V, VOUT=5V, and IOUTmax.=2A, (BD9140MUV) Fig.29 Input capacitor √ 5(8-5) IRMS=2× 3.3 =0.97[ARMS] A low ESR 22μF/25V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. 4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier. fp(Min.) A Gain [dB] 0 fz(ESR) IOUTMin. Phase [deg] 1 2π×RO×CO 1 fz(ESR)= 2π×ESR×CO fp= fp(Max.) IOUTMax. Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. 0 -90 fp(Min.)= 1 [Hz]←with lighter load 2π×ROMax.×CO fp(Max.)= 1 2π×ROMin.×CO Fig.30 Open loop gain characteristics A fz(Amp.) Gain [dB] [Hz] ←with heavier load Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole 0 frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR 0 Phase [deg] -90 reduces to half.) fz(Amp.)= 1 2π×RITH×CITH Fig.31 Error amp phase compensation characteristics www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/18 2009.06 - Rev.A Technical Note BD9141MUV Cin VCC EN VOUT L VCC,PVCC SW ESR VOUT ITH VOUT RO CO GND,PGND RITH CITH Fig.32 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2π×RITH×CITH = 1 2π×ROMax.×CO 5. Determination of output voltage The output voltage VOUT is determined by the equation (6): VOUT=(R2/R1+1)×VADJ・・・(6) VADJ: Voltage at ADJ terminal (0.8V Typ.) With R1 and R2 adjusted, the output voltage may be determined as required. L 6 Output SW Co R2 1 ADJ R1 Adjustable output voltage range : 2.5V～6.0V Fig.33 Determination of output voltage Use 1 kΩ～100 kΩ resistor for R1. if you can use the resistance more than 100kΩor they have a big range between the setting value of output voltage and input voltage. 8 7.5 The minimum input voltage depends on the setting output voltage. Basically, it is recommended to use in the condition : VCCmin = VOUT+1.3V. It is shown the necessary output current value at the minimum input voltage. (DCR of inductor : 0.1Ω)See Fig.34. This data is the characteristic value, so it doesn’t guarantee the operation range. INPUT VOLTAGE : VCC[V] Vo=6.0V 7 6.5 Vo=5.0V 6 5.5 Vo=4.0V 5 Vo=3.3V 4.5 0 6.Selection of the reference voltage capacitor (CVREG) www.rohm.com 1 1.5 2 OUTPUT CURRENT : IOUT[A] VREG voltage is the reference voltage created by Input voltage (Vcc Voltage). CVREG capacitor should be selected 0.1uF or more. © 2009 ROHM Co., Ltd. All rights reserved. 0.5 13/18 Fig.34 minimum input voltage in each output voltage 2009.06 - Rev.A Technical Note BD9141MUV ●BD9141MUV Cautions on PC Board layout VCC R2 EN ADJ VCC R1 EN PVCC VREG CVREG RITH ③ CITH ① L SW ITH GND PGND VOUT CIN ② Co GND Fig.34 Layout diagram ① ② For the sections drawn with heavy line, use thick conductor pattern as short as possible. Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. ③ Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. ④ The Non connection pin must be left open or connected to GND. ※ VQFN020V4040 (BD9141MUV) has thermal FIN on the reverse of the package. The package thermal performance may be enhanced by bonding the FIN to GND plane which take a large area of PCB. ●Recommended components Lists on above application Symbol Value Manufacturer Series Coil 4.7uH TDK RLF7030T-4R7M3R4 CIN Ceramic capacitor 22uF kyocera CM32X5R226M25A CO Ceramic capacitor 22uF kyocera CM32X5R226M10A CVREG Ceramic capacitor 0.1uF murata GRM188B31H104KA92 CITH Ceramic capacitor L RITH Part Resistance Vo=3.3V 1000pF murata GRM1882C1H102JA01 Vo=5V 1000pF murata GRM1882C1H102JA01 Vo=3.3V Vo=5V 20kΩ 47kΩ Rohm Rohm MCR03 Series MCR03 Series *The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode established between the SW and PGND pins. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/18 2009.06 - Rev.A Technical Note BD9141MUV ●I/O equivalence circuit 【BD9141MUV】 ・EN pin PVCC ・SW pin PVCC PVCC EN SW ・ADJ pin ・ITH pin VCC ADJ ITH ・VREG pin VCC VCC VREG Fig.35 I/O equivalence circuit www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 15/18 2009.06 - Rev.A Technical Note BD9141MUV ●Cautions on use 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4.Operation in Strong electromagnetic field Be noted that using the IC in the strong electromagnetic radiation can cause operation failures. 5. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 6. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 7. Input to IC terminals This is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 37. ○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and ○if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements. Resistor Transistor (NPN) Pin A Pin B C B Pin B E Pin A N N N P+ P+ P N P+ Parasitic element P substrate Parasitic element GND B N P+ P N C E Parasitic P substrate Parasitic element GND GND GND Other adjacent elements Fig.36 Simplified structure of monorisic IC www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 16/18 2009.06 - Rev.A Technical Note BD9141MUV 8. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 9 . Selection of inductor It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between external devices and this IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 17/18 2009.06 - Rev.A Technical Note BD9141MUV ●Ordering part number B D 9 1 ROHM part number 4 1 M Type U V ― Package 41 : Adjustable (2.5～6V) MUV : VQFN020V4040 E 2 Package specification E2 : Embossed taping VQFN020V4040 <Tape and Reel information> 4.0±0.1 4.0±0.1 2.1±0.1 1.0 0.4±0.1 1 6 16 0.5 Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 5 20 10 15 2500pcs (0.22) S C0.2 Embossed carrier tape Quantity 11 2.1±0.1 0.08 S +0.03 0.02 –0.02 1.0MAX 1PIN MARK Tape +0.05 0.25 –0.04 1pin (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 18/18 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.06 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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