1/4 ■ S t r u c t u r e ■ P r o d u c t Semiconductor integrated circuit DSC/DVC system power LSI ■ M BD9639MWV o d e l ■ F u n c t i o n s (1) (2) (3) 6ch DC/DC converter ・CH1 Boost FET embedded ・CH2 Buck FET embedded ・CH3 Buck-Boost FET embedded ・CH4 Buck-Boost FET embedded ・CH5 Buck FET embedded ・CH6 Boost FET embedded Low voltage operation 2.5[V] CH1 supply voltage output for internal circuit (4) (5) (6) (7) (8) (9) (10) (11) CH1 PWM/PFM selectable CH3,CH4 Boost-Buck auto switching CH6 integrated Boost output shutdown (CH6 Load switch embedded) Soft-start correspondence to each channel Ground short protection（CH2～CH6） Error amp phase compensation(CH1～CH6) Operating frequency 1.5[MHz] (CH1～CH6) Package of mounting on high heat radiation side （UQFN056V7070） Start-up ch,Motor Core CMOS Digital CMOS, Memory LED ■ Absolute maximum ratings （Ta=25[℃]） ITEM SYMBOL Rating VBAT Supply voltage -0.3～7 VBAT2・3・4・5・6 SW6 permissible voltage SW6 24.0 VOUT1 permissible current output IVOUT1 1.0 SW1 permissible current output ISW１ 1.0 SW2 permissible current output ISW2 2.0 VOUT3 permissible current output IVOUT3 1.0 DSW3 permissible current output IDSW3 1.0 USW3 permissible current output IUSW3 1.0 VOUT4 permissible current output IVOUT4 1.0 DSW4 permissible current output IDSW４ 1.0 USW4 permissible current output IUSW４ 1.0 SW5 permissible current output ISW5 1.0 SW6 permissible current output ISW6 0.2 Power dissipation Pd 4.83 (*1) Operating temperature range Topt -20～+85 Storage temperature range Tstg -55～+150 Junction temperature Tjmax +150 (*1) Implemented on Glass epoxy board （ROHM standard board：74.2×74.2×1.6[mm3] 4 layers） Power dissipation depends on the mounted wiring pattern. ■ Operating supply voltage LIMIT ITEM Symbol MIN TYP VBAT 2.5 3.7 VBAT2 2.5 3.7 VBAT3 2.5 3.7 VBAT supply voltage VBAT4 2.5 3.7 VBAT5 2.5 3.7 VBAT6 2.5 3.7 No radiation-proof design REV. C Unit V V A A A A A A A A A A A W ℃ ℃ ℃ MAX 5.5 5.5 5.5 5.5 5.5 5.5 Unit V V V V V V 2/4 ■ Electrical characteristics（Unless otherwise specified、VBAT=VBAT2,3,4,5,6=3.7[V]、VCC=3.7[V]、Ta=25[℃]） ITEM Symbol MIN LIMIT TYP MAX Unit Current consumption (PFM) ICC1 - 72 150 μA Current consumption (PWM) ICC2 1.57 2.35 3.53 mA Shut current consumption ICC3 - 0 10 μA H input voltage 1 VIH1 VBAT -0.3 - - V L input voltage 1 VIL1 - - H input voltage 2 VIH3 2.5 - L input voltage 2 VIL3 - - H Input current 1 IIH1 4.63 FOSC1 VUVLO1 VUVLO2 Oscillating frequency 1 Reduced-voltage detection voltage Reduced-voltage return voltage 【CH1】 Start-up time 85％ Error amp reference voltage PMOS On resistance NMOS On resistance Maximum duty 【CH2】 Error amp reference voltage Soft-start period 85％ PMOS On resistance NMOS On resistance 【CH3】 Error amp reference voltage Soft-start period 85％ PMOS On resistance DOWN side NMOS On resistance DOWN side PMOS On resistance UP side NMOS On resistance UP side Maximum duty 【CH4】 Error amp reference voltage Soft-start period 85％ PMOS On resistance DOWN side NMOS On resistance DOWN side PMOS On resistance UP side NMOS On resistance UP side Maximum duty 【CH5】 Error amp reference voltage Soft-start period 85％ PMOS On resistance NMOS On resistance 【CH6】 Error amp reference voltage 1 NOTE ・XSHDN1=H, XSHDN24=L ・FB1=0.5[V] ・sum of VBAT terminal, and VOUT1 terminal ・XSHDN1=H, XSHDN24=H, TEST1=H ・FB1=0.5[V] ・sum of VBAT terminal, and VOUT1 terminal ・all setting terminal=L ・sum of VBAT terminal, and VOUT1 terminal XSHDN1 GND +0.3 GND +0.3 V 9.25 18.5 μA 1.2 1.75 1.95 1.5 1.95 2.15 1.8 2.15 2.35 MHz V V TSS1 310 620 930 μs EREF1 RONP1 RONN1 DMAX1 0.388 76.5 0.400 0.24 0.14 85.0 0.412 0.38 0.23 93.5 V Ω Ω ％ Start-up period 100％ 730[us](TYP) XSHDN24=L XSHDN24=H Power supply 3.7[V] Power supply 3.7[V] XSHDN24=H EREF2 TSS2 RONP2 RONN2 0.390 0.43 - 0.400 0.85 0.13 0.08 0.410 1.27 0.21 0.14 V ms Ω Ω Start-up period 100％ 1.0[ms]（TYP） Power supply 3.7[V] Power supply 3.7[V] EREF3 TSS3 RONPD3 RONND3 RONPU3 RONNU3 DMAX3 0.390 0.85 65 0.400 1.70 0.24 0.25 0.26 0.16 80 0.410 2.55 0.39 0.40 0.42 0.27 95 V ms Ω Ω Ω Ω ％ Start-up period 100％ 2.0[ms]（TYP） Power supply 3.7[V] Power supply 3.7[V] Power supply 3.7[V] Power supply 3.7[V] EREF4 TSS4 RONPD4 RONND4 RONPU4 RONNU4 DMAX4 0.390 1.28 65 0.400 2.55 0.16 0.21 0.24 0.16 80 0.410 3.83 0.26 0.33 0.38 0.26 95 V ms Ω Ω Ω Ω ％ Start-up period 100％ 3.0[ms]（TYP） Power supply 3.7[V] Power supply 3.7[V] Power supply 3.7[V] Power supply 3.7[V] EREF5 TSS5 RONP5 RONN5 0.390 0.85 - 0.400 1.70 0.26 0.17 0.410 2.55 0.42 0.28 V ms Ω Ω V V EREF6 0.380 0.400 0.420 V Error amp reference voltage 2 EREF6.1 0.380 0.400 0.420 V Soft-start period 85％ Load switch On resistance NMOS On resistance Maximum duty TSS6 RONP6 RONN6 DMAX6 2.55 83 5.10 0.23 0.47 90 7.65 0.37 0.73 97 ms Ω Ω ％ REV. C XSHDN24,XSHDN3,XSHDN5,XSHDN6 Power supply 3.7[V] XSHDN24,XSHDN3,XSHDN5,XSHDN6 RT=10[kΩ] Start-up period 100％ 2.0[ms]（TYP） Power supply 3.7[V] Power supply 3.7[V] Constant voltage control side Constant current control side Start-up period 100％ 6.0[ms]( TYP) Power supply 3.7[V] Power supply 3.7[V] 3/4 ■ Package outline ■ Block diagram ＢＤ9639ＭＷ Ｌｏｔ Ｎｏ． ■ Terminal No./Terminal name ■ Terminal description Terminal No. Name 1 SW1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SW1 PGND1 PGND1 TEST1 VBAT XSHDN1 AGND1 XSHDN24 FB5 PGND5 SW5 VBAT5 XSHDN5 FB4 VOUT4 VOUT4 USW4 USW4 PGND4 PGND4 DSW4 DSW4 VBAT4 VBAT4 DPG4 Reserve 28 FB61 Equivalent circuit CH1 switching terminal CH1 switching terminal CH1 DRIVER GND terminal CH1 DRIVER GND terminal Test terminal Battery input terminal CH1 shutdown terminal Analog GND terminal CH2・4 shutdown terminal CH5 feed buck terminal CH5 DRIVER GND terminal CH5 switching terminal CH5 DRIVER power supply terminal CH5 shutdown terminal CH4 feed buck terminal CH4 output terminal CH4 output terminal CH4 Boost side switching terminal CH4 Boost side switching terminal CH4 DRIVER GND terminal CH4 DRIVER GND terminal CH4 Buck side switching terminal CH4 Buck side switching terminal CH4 DRIVER power supply terminal CH4 DRIVER power supply terminal CH4 gate connecting terminal Reserve terminal CH6 feed buck terminal （Constant current side） Terminal No Name O 29 FB6 O G G O･G V G G O･G G G O V O･G G O O O O G G O O V V O O･G 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 PGND6 SW6 LSO6 VBAT6 XSHDN6 RT AGND2 VCC PGND2 PGND2 SW2 SW2 VBAT2 VBAT2 FB2 TEST2 XSHDN3 VBAT3 DSW3 DPG3 PGND3 USW3 VOUT3 FB3 FB1 VOUT1 G 56 VOUT1 The alphabet on a right edge of the above-mentioned terminal explanation is processing of unused. O・・・OPEN G・・・GND O･G・・・OPEN or GND V・・・Power supply (VBAT) (*1)・・・10[KΩ]Pull-down REV. C Equivalent circuit CH6 feed buck terminal （Constant current side） CH6 DRIVER GND terminal CH6 switching terminal CH6 Load switch output terminal CH6 Load switch input terminal CH6 shutdown terminal Triangle wave setting resistor terminal Analog GND terminal Analog power supply terminal CH2 DRIVER GND terminal CH2 DRIVER GND terminal CH2 switching terminal CH2 switching terminal CH2 DRIVER power supply terminal CH2 DRIVER power supply terminal CH2 feed buck terminal Test terminal CH3 shutdown terminal CH3 DRIVER power supply terminal CH3 Buck side switching terminal CH3 gate connecting terminal CH3 DRIVER GND terminal CH3 Boost side switching terminal CH3 output terminal CH3 feed buck terminal CH1 feed buck terminal CH1 output terminal CH1 output terminal G G O O V O･G (*1) G V G G O O V V G O･G O･G V O O G O O G G O O 4/4 ■Instruction for use 1．Board patterning ・VBAT,VBAT2,VBAT3,VBAT4,VBAT5,VBAT6 are must be connected to power supply on the board. ・VCC must be connected to VOUT1 output on the board. ・ALL PGND and AGND must be connected to GND on the board. ・ALL power supply line and GND terminals must be wired with wide/short pattern in order to achieve substantially low impedance. 2. Peripheral circuitry ・Use low ESR ceramic capacitor for bypass condenser between power supply and GND terminal and place capacitor right next to the IC pins. ・Place external components such as L and C by IC with wide/short pattern. ・Draw output voltage from each end of capacitor. ・Causing short circuit at CH1 output will overload the external diode and may breakdown the component. Prepare physical countermeasures by adding poli-switches and fuses to avoid excess current flow. 3．Start-up ・Keep light load condition by starting up the device. ・Make it to PWM mode (XSHDN24=L→H) after CH1 is started up in PFM mode (XSHDN1=L→H), and the VOUT1 output voltage stands up. Moreover, start it about the start of CH3・CH5・CH6 since the PWM mode (Contain it simultaneously). 4．Absolute maximum ratings ・The quality control of the product has exercised adequate care, however operating above the absolute maximum ratings of supply voltage and/or operational temperature range may cause decay and destroy the IC. If specific mode such that exceeding the Absolute Maximum ratings is expected, please have physical countermeasure such as adding fuses and poli-switches etc. 5．Thermal design ・Take consideration of power dissipation at actual device usage to ensure the satisfactory thermal design margin. (Refer page 6) 6．Terminal to Terminal short / mis-mounting ・While mounting IC on the board, check direction and shift of the IC. If inadequately mounted, IC might be breakdown. Additionally short circuit from unwanted contamination at power supply and GND and/or between any terminals also may cause the defect. 7．Operating in strong electromagnetic field ・Please pay attention using device in the strong electromagnetic field. Device may cause malfunction. 8．Thermal shut down.(TSD) ・Main purpose of TSD is to shutting IC down from runaway effect. It is not to compensate or to protect IC itself . Therefore, please do not continuously operate the IC after TSD circuit is activated and/or premise operations such that TSD circuit function to be used. 9．Inspection with set board ・While connecting capacitor to Low impedance pins, please discharge capacitor by one process by another to prevent stressing the IC. While mounting and removing the IC to/from the Board in the inspection process, be sure to turn off the power supply by each action. Moreover equip ground earth in assembling process for ESD protection and handle with care during the test and/or transportation. 10．Input terminals ・This IC is a monolithic IC, and has P+ isolation and P substrate for the element separation. Therefore, a parasitic PN junction is firmed in this P-layer and N-layer of each element. For example shown in below picture, the resistor or the transistor is connected to the terminal. When the GND voltage potential is greater than the voltage potential at Terminals A or B, the PN junction operates as a parasitic diode. In addition, the parasitic NPN transistor is formed in said parasitic diode and the N layer of surrounding elements close to said parasitic diode. These parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes the wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic elements by applying lower voltage than GND (P substrate) to input terminals. Moreover, please apply each input terminal with lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power-supply voltage being applied Transistor (NPN) Resistor Terminal B Terminal A C B Terminal B E Terminal A B P+ N Stray component P N P+ N P substrat e GND Stray component E N P+ N Stray component C P N P+ N P substrat e GND Neighborhood component Stray component GND GND implified IC structure 11．Usage of this product ・This IC is designed to be used in DSC/DVD application. ・Upon using our product to equipments or devices other than above mentioned application, please be sure to consult with our sales representative in advance. REV. C Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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