Low Capacitance ESD Protection Array CPDVR105V0USP-HF RoHS Device Halogen Free Features SLP2510P8 - IEC61000-4-2 Level 4 ESD Protection. - IEC61000-4-4 Level 4 FET protection. 0.102(2.60) 0.094(2.40) - Protects four high speed I/O lines - Low clamping voltage - Working Voltage: 5V 0.043(1.10) 0.035(0.90) - Low leakage current Mechanical data - Case: SLP2510P8 small outline plastic package - Terminals: Matte tin plated, solderable per MIL-STD-202,method 208 - Mounting Compound Flammability Rating: UL 94V-0 - High temperature soldering guaranteed: 260°C/10 second - Weight: 0.015 grams(approx.). 0.026(0.65) 0.020(0.50) 0.02(0.50)BSC 0.002(0.05) 0.000(0.00) 0.018(0.45) 0.014(0.35) Circuit Diagram 1 2 3 4 5 0.010(0.25) 0.006(0.15) Dimensions in inches and (millimeter) 10 9 8 7 6 Electrical Characteristics (at TA=25 C unless otherwise noted) O Parameter Conditions Symbol Min Typ Max Unit 5.0 V Reverse working voltage I/O Pins to GND (Note 1) VRWM Breakdown voltage IT = 1mA,I/O Pin to GND V(BR) Reverse Leakage current VRWM = 5V, I/O Pin to GND IR 1.0 uA Junction capacitance VR =0V, f =1MHz between I/Os CJ 0.4 pF Junction capacitance VR =0V, f =1MHz between I/Os GND CJ 0.8 pF IEC 61000-4-2(Air) VESD ±15 kV IEC 61000-4-2(Contact) VESD ±8 kV ESD capability 6.0 V Clamping voltage IPP = 1A,I/O Pin to GND(8/20µs) VC 15 V Peak pulse power Tp=8/20µs waveform PPP 150 W Junction temperature range TJ -55 150 °C Storage temperature range TSTG -55 150 °C Note: 1. ESD devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. Company reserves the right to improve product design , functions and reliability without notice. REV:A Page 1 QW-JP041 Comchip Technology CO., LTD. Comchip Low Capacitance ESD Protection Array SMD Diode Specialist RATING AND CHARACTERISTIC CURVES (CPDVR105V0USP-HF) Fig.1- Non-Repetitive Peak Pulse Power vs. Pulse Time Fig.2- Clamping Voltage vs. Peak Pulse Current 30 Camping Voltage, (V) Peak Pulse Power, PPP( KW ) 10 1 0.1 20 10 0 0.01 0 1 10 100 1000 0 1 2 Pulse Duration, (us) 4 5 6 Peak Current, Ipp( A ) Fig.4- Pulse Waveform Fig.3- Admissible Power Dissipation Curve 120% 120% Waveform parameters tf=8us td=20us Ta=25°C 100% 100% Percentage of Ipp Power Dissipation, (mW) 3 80% 60% 40% 80% 60% e-t 40% td=t│Ipp/2 20% 20% 0% 0% 0 20 40 60 80 100 140 160 180 Ambient temperature, ( °C ) 0 5 10 15 20 25 t-Time, (us) Company reserves the right to improve product design , functions and reliability without notice. QW-JP041 Comchip Technology CO., LTD. 30 Reverse voltage, (%) REV:A Page 2 Low Capacitance ESD Protection Array Reel Taping Specification d P0 P1 T E Index hole F W B P C A 12 o 0 D2 D1 D W1 Trailer Device ....... ....... End ....... ....... Leader ....... ....... 10 pitches (min) ....... ....... Start 10 pitches (min) Direction of Feed SLP2510P8 SLP2510P8 SYMBOL A B C d D D1 D2 (mm) 1.23 ± 0.10 2.77 ± 0.10 0.70 ± 0.10 1.50 ± 0.10 178 ± 1 54.4 ± 0.40 13.0 ± 0.20 (inch) 0.048 ± 0.004 0.109 ± 0.004 0.028 ± 0.004 0.059 ± 0.004 7.008 ± 0.039 2.142 ± 0.016 0.512 ± 0.008 SYMBOL E F P P0 P1 T W W1 (mm) 1.75 ± 0.10 3.50 ± 0.05 4.00 ± 0.10 4.00 ± 0.10 2.00 ± 0.05 0.229 ± 0.013 8.10 ± 0.20 12.3 ± 0.20 (inch) 0.069 ± 0.004 0.138 ± 0.002 0.157 ± 0.004 0.157 ± 0.004 0.079 ± 0.002 0.009 ± 0.001 0.319 ± 0.008 0.484 ± 0.008 Company reserves the right to improve product design , functions and reliability without notice. REV:A Page 3 QW-JP041 Comchip Technology CO., LTD. Comchip Low Capacitance ESD Protection Array SMD Diode Specialist Marking Code Part Number Marking Code CPDVR105V0USP-HF P524 • P524 Suggested PAD Layout D SLP2510P8 SIZE (mm) (inch) A 0.875 0.034 B 0.200 0.008 C 0.500 C + H A + + + + + G + B 0.020 + D 1.000 0.039 E 0.200 0.008 F 0.400 0.016 G 0.675 0.027 H 1.550 0.061 + E F Standard Packaging Qty Per Reel Reel Size (Pcs) (inch) 3,000 7 Case Type SLP2510P8 Company reserves the right to improve product design , functions and reliability without notice. REV:A Page 4 QW-JP041 Comchip Technology CO., LTD.