3.3V CMOS 16-BIT LATCHED TRANSCEIVER IDT74FCT163543/A/C ADVANCE INFORMATION Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP • Extended commercial range of -40°C to +85°C • VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range • CMOS power levels (0.4µW typ. static) • Rail-to-Rail output swing for increased noise margin • Low Ground Bounce (0.3V typ.) • Inputs (except I/O) can be driven by 3.3V or 5V components The FCT163543/A/C 16-bit latched transceivers are built using advanced dual metal CMOS technology. These highspeed, low-power devices are organized as two independent 8bit D-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. For example, the A-to-B Enable (xCEAB) must be LOW in order to enter data from the A port or to output data from the B port. xLEAB controls the latch function. When xLEAB is LOW, the latches are transparent. A subsequent LOW-toHIGH transition of xLEAB signal puts the A latches in the storage mode. xOEAB performs output enable function on the B port. Data flow from the B port to the A port is similar but requires using xCEBA, xLEBA, and xOEBA inputs. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT163543/A/C have series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. FUNCTIONAL BLOCK DIAGRAM 1OEBA 2OEBA 1CEBA 2CEBA 1LEBA 2LEBA 1OEAB 2OEAB 1CEAB 2CEAB 2LEAB 1LEAB C C 2A1 1A1 D 1B1 D C C D D 2 B1 TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS 3250 drw 01 3250 drw 02 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. SEPTEMBER 1996 8.7 DSC-3250/2 1 IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS PIN DESCRIPTION Pin Names Description xOEAB A-to-B Output Enable Input (Active LOW) xOEBA B-to-A Output Enable Input (Active LOW) 1OEAB 1 56 1OEBA 1LEAB 2 55 1LEBA 1CEAB 3 54 1CEBA GND 4 53 GND xLEBA B-to-A Latch Enable Input (Active LOW) 1A1 5 52 1B1 xAx A-to-B Data Inputs or B-to-A 3-State Outputs xBx B-to-A Data Inputs or A-to-B 3-State Outputs xCEAB A-to-B Enable Input (Active LOW) xCEBA B-to-A Enable Input (Active LOW) xLEAB A-to-B Latch Enable Input (Active LOW) 1A2 6 51 1B2 VCC 7 50 VCC 1A3 8 49 1B3 1A4 9 48 1B4 1A5 10 47 1B5 GND 11 46 GND 1A6 12 45 1B6 1A7 13 44 1B7 1A8 14 1B8 2A1 15 SO56-1 43 SO56-2 SO56-3 42 2A2 16 41 2B2 2A3 17 40 2B3 GND 18 39 GND 2A4 19 38 2B4 2A5 20 37 2B5 2A6 21 36 2B6 VCC 22 35 VCC 2A7 23 34 2B7 2A8 24 33 2B8 FUNCTION TABLE(1, 3) GND 25 32 GND For A-to-B (Symmetric with B-to-A) 2CEAB 26 31 2CEBA 2LEAB 27 30 2LEBA xCEAB 2OEAB 28 29 2OEBA 3250 tbl 01 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) Symbol CIN Input Capacitance CI/O I/O Capacitance DC Output Current VTERM(4) Max. –0.5 to +4.6 Unit V –0.5 to +7.0 V –0.5 to VCC + 0.5 –65 to +150 V °C –60 to +60 mA 3250 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals. Inputs 3250 drw 03 CAPACITANCE (TA = +25°C, f = 1.0MHz) Parameter(1) I OUT VTERM(3) 2B1 SSOP/ TSSOP/TVSOP TOP VIEW TSTG Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature Conditions VIN = 0V Typ. 3.5 VOUT = 0V 3.5 NOTE: 1. This parameter is measured at characterization but not tested. Output Buffers xLEAB xOEAB xAx to xBx xBx H X X Storing High Z X H X Storing X L L L Transparent Current A Inputs L L L H L H L H H Storing Transparent Storing Previous(2) A Inputs High Z High Z NOTES: 3250 tbl 02 1. A-to-B data flow shown; B-to-A flow control is the same, except using xCEBA, x LEBA and xOEBA. 2. Before xLEAB LOW-to-HIGH Transition 3. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Max. Unit 6.0 pF 8.0 Latch Status pF 3250 lnk 04 8.7 2 IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V Symbol VIH Test Conditions(1) Guaranteed Logic HIGH Level Min. 2.0 Guaranteed Logic LOW Level VI = 5.5V Input HIGH Current (I/O pins) Input LOW Current (Input pins) Parameter Input HIGH Level (Input pins) Typ.(2) — Max. 5.5 2.0 — VCC+0.5 –0.5 — 0.8 V — — ±1 µA VI = VCC — — ±1 VI = GND — — ±1 Input HIGH Level (I/O pins) VIL Input LOW Level Unit V (Input and I/O pins) II H II L Input HIGH Current (Input pins) VCC = Max. Input LOW Current (I/O pins) VI = GND — — ±1 — — ±1 VO = GND — — ±1 — –0.7 –1.2 V –36 –60 –110 mA 90 200 mA V High Impedance Output Current I OZL (3-State Output pins) VIK Clamp Diode Voltage VCC = Min., IIN = –18mA I ODH Output HIGH Current VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3) I ODL Output LOW Current VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3) 50 VOH Output HIGH Voltage VOL Output LOW Voltage I OS Short Circuit Current(4) VH Input Hysteresis I CCL I CCH I CCZ Quiescent Power Supply Current VCC = Max. VO = V CC I OZH µA VCC = Min. I OH = –0.1mA VCC– 0.2 — — VIN = VIH or V IL I OH = –3mA 2.4 3.0 — VCC = 3.0V VIN = VIH or V IL VCC = Min. I OH = –8mA 2.4 (5) 3.0 — I OL = 0.1mA — — 0.2 VIN = VIH or V IL I OL = 16mA — 0.2 0.4 I OL = 24mA — 0.3 0.55 VCC = 3.0V I OL = 24mA VIN = VIH or V IL VCC = Max., VO = GND(3) — 0.3 0.50 –60 –135 –240 mA — 150 — mV — 0.1 10 µA — VCC = Max., VIN = GND or VCC NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC –0.6V at rated current. 8.7 V 3250 lnk 05 3 IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions(1) ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC –0.6V(3) ICCD Dynamic Power Supply Current(4) VCC = Max., Outputs Open xCEAB and xOEAB = GND xCEBA = VCC One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) Min. Typ.(2) Max. Unit — 2.0 30 µA VIN = VCC VIN = GND — 60 100 µA/ MHz VCC = Max., Outputs Open fi = 10MHz 50% Duty Cycle xLEAB, xCEAB and xOEAB= GND xCEBA = VCC One Bit Toggling VIN = VCC VIN = GND — 0.6 1.0 mA VIN = VCC –0.6V VIN = GND — 0.6 1.0 VCC = Max., Outputs Open fi = 2.5MHz 50% Duty Cycle xLEAB, xCEAB and xOEAB= GND xCEBA = VCC Sixteen Bits Toggling VIN = VCC VIN = GND — 2.4 4.0(5) VIN = VCC –0.6V VIN = GND — 2.4 4.3(5) NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 8.7 3250 tbl 06 4 IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4) FCT163543 Symbol tPLH tPHL Parameter Propagation Delay Transparent Mode xAx to xBx or xBx to xAx tPLH Propagation Delay tPHL xLEBA to xAx, xLEAB to xBx tPZH Output Enable Time tPZL xOEBA or xOEAB to xAx or xBx xCEBA or xCEAB to xAx or xBx tPHZ Output Disable Time tPLZ xOEBA or xOEAB to xAx or xBx xCEBA or xCEAB to xAx or xBx tSU Set-up Time HIGH or LOW xAx or xBx to xLEAB or xLEBA tH Hold Time HIGH or LOW xAx or xBx to xLEAB or xLEBA tW xLEBA or xLEAB Pulse Width LOW tSK(o) Output Skew (3) Condition(1) Min.(2) CL = 50pF RL = 500Ω FCT163543A FCT163543C Max. Min.(2) Max. Min.(2) Max. Unit 1.5 8.5 1.5 6.5 1.5 5.3 ns 1.5 12.5 1.5 8.0 1.5 7.0 ns 1.5 12.0 1.5 9.0 1.5 8.0 ns 1.5 9.0 1.5 7.5 1.5 6.5 ns 3.0 — 2.0 — 2.0 — ns 2.0 — 2.0 — 2.0 — ns 5.0 — 5.0 — 5.0 — ns — 0.5 — 0.5 — 0.5 ns NOTES: 3250 tbl 07 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 8.7 5 IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests 6V ← V CC 500Ω V V IN Pulse Generator Open GND OUT D.U.T. 50pF R T C 500Ω L SET-UP, HOLD AND RELEASE TIMES tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU 6V GND Open DEFINITIONS: 3250 lnk 08 CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 3250 drw 05 DATA INPUT Switch PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW HIGH-LOW-HIGH PULSE 1.5V 3250 drw 07 3V 1.5V 0V tH 3250 drw 06 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V CONTROL INPUT 1.5V OUTPUT NORMALLY SWITCH 6V LOW tPZH 3V 1.5V 0V OUTPUT NORMALLY HIGH 3250 drw 08 SWITCH GND 0V tPLZ tPZL 3V 3V 1.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V 3250 drw 09 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 3. If VCC is below 3V, input voltage swings should be adjusted not to exceed VCC. 8.7 6 IDT74FCT163543/A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT FCT XXXX X Device Temperature Type Range X Package PV PA PF Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 163543 16-Bit Latched Transceiver 163543A 163543C 74 –40°C to +85°C 3250 drw 10 8.7 7