64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 64Mb: 3V Parallel NOR Flash Embedded Memory • Common Flash interface Features • 64-bit security code • Supply voltage • 128-word extended memory block • VCC = 2.7–3.6V (program, erase, read) • Extra block used as security block or to store additional information • VPP = 12V for fast program (optional) • Low power consumption: Standby and automatic mode • Asynchronous random/page read • Page width: 4 words • 100,000 PROGRAM/ERASE cycles per block • Page access: 25ns • Electronic signature • Manufacturer code: 0020h • Random access: 70ns • Device summary: part number and device code • Fast program commands • M29W640GB: bottom boot block 227Eh + 2210h + 2200h • 2-word/4-byte program (without VPP = 12V) • 4-word/8-byte program (with VPP = 12V) • 16-word/32-byte write buffer • Programming time • 10μs per byte/word TYP • Chip program time: 10 s (4-word program) • Double word/quadruple byte program • Memory organization • M29W640GB 127 main blocks, 64KB each and 8 boot blocks, 8KB each • Program/erase controller OptionsCode • Embedded byte/word program algorithms • Package (Sn63 Pb37 solder) • Program/erase suspend and resume • Read from any block during a PROGRAM SUSPEND operation Package (Sn63 Pb37 solder) 48-ball TFBGA (6mm x 8mm) 0.8mm pitch • Read or program another block during an ERASE SUSPEND operation Operating Temperature Industrial (-40°C ≤ Ta ≤ +85°C) • Hardware block protection • VPP/WP# pin for fast program and write protect BG ZA IT • Part Marking Label (L), or Dot (D) • Temporary block unprotect mode MYX29W640GB70ZABG Revision 1.0 - 04/13/16 1 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table of Contents 1 2 3 3.1 3.2 3.3 3.4 4 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . Write to Buffer and Program Abort Bit (DQ1) . . . . . . . . . . . 7.15 11 12 12 12 12 13 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 READ/RESET Command . . . . . . . . . . . . . . . . . . . . . . . . . . 17 READ CFI Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AUTO SELECT Operations . . . . . . . . . . . . . . . . . . . . . . 17 6.1 7 10 10 10 11 READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 5.2 6 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby and Automatic Standby . . . . . . . . . . . . . . . . . . . Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 4.2 4.3 4.4 4.5 4.6 5 7.8 7.9 7.10 7.11 7.12 7.13 7.14 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AUTO SELECT Command . . . . . . . . . . . . . . . . . . . . . . . . 25 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 7.2 7.3 7.4 7.5 7.6 7.7 READ/RESET Command . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AUTO SELECT Command . . . . . . . . . . . . . . . . . . . . . . . . . 18 READ CFI QUERY Command . . . . . . . . . . . . . . . . . . . . . . 19 PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PROGRAM SUSPEND Command . . . . . . . . . . . . . . . . . . . . 20 PROGRAM RESUME Command . . . . . . . . . . . . . . . . . . . . . 20 Fast Program Commands . . . . . . . . . . . . . . . . . . . . . . . . 20 MYX29W640GB70ZABG Revision 1.0 - 04/13/16 8 9 10 11 DOUBLE BYTE PROGRAM Command . . . . . . . . . . . . . . . . 21 QUADRUPLE BYTE PROGRAM Command . . . . . . . . . . . . . 21 OCTUPLE BYTE PROGRAM Command . . . . . . . . . . . . . . . 21 DOUBLE WORD PROGRAM Command . . . . . . . . . . . . . . . 22 QUADRUPLE WORD PROGRAM Command . . . . . . . . . . . 22 WRITE TO BUFFER AND PROGRAM Command . . . . . . . . 23 WRITE TO BUFFER AND PROGRAM CONFIRM Command . . . . . . . . . . . . . . . . . . . . . . . . 24 WRITE TO BUFFER AND PROGRAM ABORT AND RESET Command . . . . . . . . . . . . . . . . . . . . . . . . 24 UNLOCK BYPASS Command . . . . . . . . . . . . . . . . . . . . . 24 UNLOCK BYPASS PROGRAM Command . . . . . . . . . . . . . 25 UNLOCK BYPASS RESET Command . . . . . . . . . . . . . . . . 25 CHIP ERASE Command . . . . . . . . . . . . . . . . . . . . . . . . 25 BLOCK ERASE Command . . . . . . . . . . . . . . . . . . . . . . . . 26 ERASE SUSPEND Command . . . . . . . . . . . . . . . . . . . . . 26 ERASE RESUME Command . . . . . . . . . . . . . . . . . . . . . . . 27 ENTER EXTENDED BLOCK Command . . . . . . . . . . . . . . . 27 EXIT EXTENDED BLOCK Command . . . . . . . . . . . . . . . . 28 BLOCK PROTECT and CHIP UNPROTECT Commands . . . . 28 BLOCK PROTECT Command . . . . . . . . . . . . . . . . . . . . . . 28 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . 28 IN-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . Absolute Ratings and Operating Conditions . . . . . . . Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 54 55 2 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG List of Figures List of Tables Figure 1: Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2: 48-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3: Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . 15 Figure 4: Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5: Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 6: Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 7: In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8: In-System Equipment Chip Protect Flowchart . . . 33 Figure 9: AC Measurement Load Circuit . . . . . . . . . . . . . . . . 39 Figure 10: AC Measurement I/O Waveform . . . . . . . . . . . . . 39 Figure 11: Random AC Timing . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 12: Page Read AC Timing . . . . . . . . . . . . . . . . . . . . . . 43 Figure 13: WE#-Controlled AC Timing . . . . . . . . . . . . . . . . . 45 Figure 14: CE#-Controlled AC Timing . . . . . . . . . . . . . . . . . . 47 Figure 15: Toggle/Alternative Toggle, CE# Controlled . . . . . 48 Figure 16: Toggle/Alternative Toggle, OE# Controlled . . . . . 49 Figure 17: WE# Controlled Program Waveform . . . . . . . . . . 51 Figure 18: CE# Controlled Program Waveform . . . . . . . . . . . 52 Figure 19: Chip/Block Erase Waveform . . . . . . . . . . . . . . . . 53 Figure 20: Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 21: Accelerated Programming Timing Waveform . . . 54 Figure 22: 48-Pin TSOP – 12mm x 20mm . . . . . . . . . . . . . . . 55 MYX29W640GB70ZABG Revision 1.0 - 04/13/16 Table 1: Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2: Protection Granularity on the M29W640GH . . . . . . . 6 Table 3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4: Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5: Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6: Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7: Programmer Technique Bus Operations . . . . . . . . . 31 Table 8: Commands – 16-Bit Mode (BYTE# = VIH) . . . . . . . . 34 Table 9: Commands – 8-Bit Mode (BYTE# = VIL) . . . . . . . . . 36 Table 10: Absolute Maximum/Minimum Ratings . . . . . . . . . 38 Table 11: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . 38 Table 12: Input/Output Capacitance . . . . . . . . . . . . . . . . . . . 39 Table 13: DC Current Characteristics . . . . . . . . . . . . . . . . . . 40 Table 14: DC Voltage Characteristics . . . . . . . . . . . . . . . . . . . 40 Table 15: Read AC Characteristics . . . . . . . . . . . . . . . . . . . . 41 Table 16: WE#-Controlled Write AC Characteristics . . . . . . . 44 Table 17: CE#-Controlled Write AC Characteristics . . . . . . . 46 Table 18: Toggle and Alternative Toggle AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 19: Program/Erase Times and Endurance Cycles . . . .50 Table 20: Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 54 3 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 1 General Description The MYX29W640GB70ZABG is a 64Mb (8Mb x8 or 4Mb x16) nonvolatile memory that can be read, erased, and reprogrammed. These operations can be performed using a single low voltage 2.7–3.6V) supply. Upon power-up, the device defaults to read mode. The memory is divided into blocks that can be erased independently so that valid data can be preserved while old data is erased. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards. The M29W640GB features an asymmetric memory block, having an array of 135 blocks divided into 8 parameter blocks of 8KB each (or 4 Kwords each), and 127 main blocks of 64KB each (or 32Kwords each). The M29W640GT has the parameter blocks at the bottom of the memory array. Blocks are protected by groups to prevent accidental PROGRAM or ERASE commands from modifying the memory. The M29W640G supports asynchronous random read and page read from all blocks of the array. Chip enable, output enable, and write enable signals control the bus operation. They enable simple connection to most microprocessors, often without additional logic. The VPP/WP# signal is used to enable faster programming of the device. Protection from PROGRAM/ERASE commands can be obtained by holding VPP/WP# to VSS: • On the M29W640GB, the last two and first two boot blocks are protected. The M29W640G device features a full set of fast program commands to improve programming throughput: • 2-byte PROGRAM (it is not necessary to raise VPP/WP# to 12V before issuing this command) • 2 words/4-byte PROGRAM (it is not necessary to raise VPP/WP# to 12V before issuing this command) • 4 word/8-byte PROGRAM (VPP/WP# must be raised to 12V before issuing this command) • WRITE TO BUFFER and PROGRAM (enables program in one shot a buffer of 16 words/32 bytes) The M29W640G has an extra block, the extended block, of 128 words in x16 mode or 256 bytes in x8 mode that can be accessed using a dedicated command. The extended block can be protected, and therefore, is useful for storing security information. However, protection is not reversible; once protected, the protection cannot be undone. The memory is delivered with all bits erased (set to 1). MYX29W640GB70ZABG Revision 1.0 - 04/13/16 4 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 1: Logic Diagram Table 1: Signal Names Table Description Direction A0-A21 Address inputs Inputs CE# Chip enable Input CE# Output enable Input WE# Write enable Input RP# Reset/Block temporary unprotect Input RY/BY# Ready/Busy Input BYTE# Byte/Word organization select Input DQ0–DQ7 Data input/outputs I/O DQ8–DQ14 Data input/outputs I/O DQ15A-1 (or DQ15) Data input/output or address input (or data I/O) I/O VCC Supply voltage Supply voltage VPP/WP# Supply voltage for FAST PROGRAM (optional) or WRITE PROTECT command Supply voltage VSS Ground — NC Not connected internally — Note: 1. VPP/WP# may be left floating because it is internally connected to a pull-up resistor to enable PROGRAM/ERASE commands. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 5 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 2: Protection Granularity on the M29W640GB Block KB/Kwords Protection Block Group (x8) (x16) 0 to 7 8x 8/41 Block level 000000h-00FFFFh2 000000h-007FFFh2 8 to 10 3 x 64/32 Protection group 010000h-03FFFFh 008000h-01FFFFh 11 to 14 4 x 64/32 Protection group 040000h-07FFFFh 020000h-03FFFFh — — — — — 127 to 130 4 x 64/32 Protection group 780000h-7BFFFFh 3C0000h-3DFFFFh 131 to 134 4 x 64/32 Protection group 7C0000h-7FFFFFh 3E0000h-3FFFFFh Notes: 1. Boot blocks. 2. Used as the extended block addresses in extended block mode. Figure 2: 48-Ball TFBGA MYX29W640GB70ZABG Revision 1.0 - 04/13/16 6 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 2 Signal Descriptions The following table is a comprehensive list of signals for this device family. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device Table 3: Signal Descriptions Name Type Description A[MAX:0] Input Address: Select the cells in the memory array to access during bus READ operations. During bus WRITE operations they control the commands sent to the command interface of the program/ erase controller. CE# Input Chip enable: Activates the memory, allowing bus READ and bus WRTE operations to be performed. When CE# is HIGH, all other pins are ignored. OE# Input Output enable: Controls the bus READ operation of the memory. WE# Input Write enable: Controls the bus WRITE operation of the memory’s command interface. VPP/WP# Input VPP/WP#: Provides two functions: VPP enables the memory to use an external high-voltage power supply to reduce the time required for UNLOCK BYPASS PROGRAM operations. WP# protects the first two boot blocks at the beginning of the addressable area (M29W640GB). VPP/WP# may be left floating or unconnected (see DC Characteristics). When VPP/WP# is LOW, the first two blocks in the M29W640GB, are protected. PROGRAM and ERASE operations in this block are ignored while VPP/WP# is LOW, even when RST# is at VID. When VPP/WP# is HIGH, VIH, the device reverts to the previous protection status of the outermost blocks. PROGRAM and ERASE operations can now modify the data in the outermost blocks unless the block is protected using block protection. Applying 12V to VPP/WP# will temporarily unprotect any block previously protected (including the outermost blocks) using a high-voltage block protection technique (in-system or programmer technique). (See Hardware Protection for details. When VPP/WP# is raised to VPP, the device automatically enters the unlock bypass mode. When VPP/WP# returns to VIH or VIL,normal operation resumes. During UNLOCK BYPASS PROGRAM operations, the device draws IPP from the pin to supply the programming circuits. (See UNLOCK BYPASS Command.) The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP (See the Accelerated Program Timing waveforms). Never raise VPP/WP# to VPP from any mode except read mode; otherwise, the device may be left in an indeterminate state. A 0.1μF capacitor should be connected between VPP/WP# and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during an UNLOCK BYPASS PROGRAM operation, IPP. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 7 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 3: Signal Descriptions (Continued) Name Type Description DQ15/A-1 I/O Data I/O or address input: When HIGH, behaves as a data I/O pin (as DQ8–DQ14). When LOW, behaves as an address pin; DQ15A–1 LOW will select the LSB of the addressed word; DQ15A–1 HIGH will select the MSB. Throughout the text, consider references to the data I/O to include this pin when BYTE# is HIGH and references to the address inputs to include this pin when BYTE# is LOW, except when stated explicitly otherwise. RST# Input Reset/Block temporary unprotect: Applies a hardware reset to the memory or temporarily unprotect all blocks that have been protected. Note that if VPP/WP is at VIL, then the first two blocks in the M29W640GB, will remain protected, even if RST# is at VID. A hardware reset is achieved by holding RST# LOW for at least tPLPX. After RST# goes HIGH, the memory will be ready for bus READ and bus WRITE operations after tPHEL or tRHEL, whichever occurs last. (See Reset Characteristics for more details.) Holding RST# at VID will temporarily unprotect the protected blocks in the memory. PROGRAM and ERASE operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 DQ[14:8] I/O Data I/O: Outputs the data stored at the selected address during a bus READ operation when BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During bus WRITE operations, the command register does not use these bits. When reading the status register these bits should be ignored. DQ[7:0] I/O Data I/O: Outputs the data stored at the selected address during a bus READ operation. During bus WRITE operations, they represent the commands sent to the command interface of the program/erase controller. RY/BY# Output BYTE# Input Ready busy: Open-drain output that identifies when the device is performing a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW, and is High-Z during read mode, auto select mode, and erase suspend mode. After a hardware reset, bus READ and WRITE operations cannot begin until RY/BY# becomes High-Z. (See Reset Characteristics for more details.) The use of an open-drain output enables RY/BY# pins from several devices to be connected to a single pull-up resistor. A LOW will then indicate that one, or more, of the devices is busy. BYTE#/Word organization select: Switches between the x8 and x16 bus modes of the device. When LOW, the device is in x8 mode; when HIGH, it is in x16 mode. 8 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 3: Signal Descriptions (Continued) Name Type Description VCC Supply Supply voltage: Provides the power supply for all operations (READ, PROGRAM, and ERASE). The command interface is disabled when the VCC supply voltage is less than the lockout voltage, VLKO. This prevents bus WRITE operations from accidentally damaging the data during power-up, power-down, and power surges. If the program/erase controller is programming or erasing during this time, then the operation aborts and the memory contents being altered will be invalid. A 0.1 μF capacitor should be connected between the VCC supply voltage pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during PROGRAM and ERASE operations, ICC3. VSS Supply RFU — Ground: Reference for all voltage measurements. The device features two VSS pins which must be both connected to the system ground. Reserved for future use: RFUs should be not connected. Table 4: Hardware Protection VPP/WP# VIL MYX29W640GB70ZABG Revision 1.0 - 04/13/16 RST# Function VIH M29W640GB First 2 blocks at the beginning of the addressable area (M29W640GB) protected from program/erase operations VID M29W640GT and M29W640GB All blocks temporarily unprotected except the first 2 blocks at the beginning of the addressable area (M29W640GB) VIH or VID VID All blocks temporarily unprotected VPP VIH or VID All blocks temporarily unprotected 9 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 3 Bus Descriptions Table 5: Bus Operations Notes 1 and 2 apply to entire table 8-Bit Mode 16-Bit Mode Operation CE# OE# WE# A[MAX:0], DQ15/A-1 DQ[14:8] DQ[7:0] A[MAX:0] DQ15/A-1, DQ[14:0] READ L L H Cell address High-Z Data output Cell address Data output WRITE L H L Command address High-Z Data input4 Command address Data input4 STANDBY H X X X High-Z High-Z X High-Z OUTPUT DISABLE X H H X High-Z High-Z X High-Z Notes: 1. Typical glitches of less than 5ns on CE# and WE# are ignored by the device and do not affect bus operations. 2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 3. If WP# = LOW, the highest/lowest block remains protected, depending on the line item. 4. Data input is required when issuing a command sequence or performing data polling or block protection. 3.1 Read Bus READ operations read from the memory cells, registers, or CFI space. A valid READ operation requires setting the appropriate address on the address inputs, taking CE# and OE# LOW and holding WE# HIGH. Data I/O signals output the value. 3.2 Write Bus WRITE operations write to the command interface. A valid WRITE operation requires setting the appropriate address on the address inputs. These are latched by the command interface on the falling edge of CE# or WE#, whichever occurs last. Values on data I/O signals are latched by the command interface on the rising edge of CE# or WE#, whichever occurs first. OE# must remain HIGH during the entire operation. 3.3 Standby and Automatic Standby When the device is in read mode, driving CE# HIGH places the device in standby mode and drives data I/Os to High-Z. Supply current is reduced to standby (ICC2), by holding CE# within VCC ±0.2V. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 10 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG During PROGRAM or ERASE operations, the device continues to use the program/erase supply current (ICC3) until the operation completes. Automatic standby enables low power consumption during read mode. When CMOS levels (VCC ± 0.2 V) drive the bus, and following a READ operation and a period of inactivity specified in DC Characteristics, the memory enters automatic standby as internal supply current is reduced to ICC2. Data I/O signals still output data if a READ operation is in progress. 3.4 Output Disable Data I/Os are High-Z when OE# is HIGH. 4 Status Register Bus READ operations from any address, always read the status register during PROGRAM and ERASE operations. It is also read during erase suspend when an address within a block being erased is accessed. 4.1 Data Polling Bit (DQ7) The data polling bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. The data polling bit is output on DQ7 when the status register is read. During PROGRAM operations, DQ7 outputs the complement of the bit being programmed to DQ7. After successful completion of the PROGRAM operation, the memory returns to read mode and bus READ operations from the address just programmed output DQ7, not its complement. During ERASE operations DQ7 outputs 0, the complement of the erased state of DQ7. After successful completion of the ERASE operation the memory returns to read mode. In erase suspend mode, DQ7 will output a 1 during a bus READ operation within a block being erased. DQ7 will change from a 0 to a 1 when the program/erase controller has suspended the ERASE operation. The Data Polling Flowchart gives an example of how to use DQ7. A valid address is the address being programmed or an address within the block being erased. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 11 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 4.2 Toggle Bit (DQ6) The toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. The toggle bit is output on DQ6 when the status register is read. During PROGRAM and ERASE operations, DQ6 changes from 0 to 1 to 0, and so forth, with successive bus READ operations at any address. After successful completion of the operation, the memory returns to read mode. During erase suspend mode, DQ6 will output when addressing a cell within a block being erased. DQ6 will stop toggling when the program/erase controller has suspended the ERASE operation. The Data Toggle Flowchart gives an example of how to use DQ6 and the toggle and alternative toggle waveforms describe toggle bit timing. 4.3 Error Bit (DQ5) The error bit can be used to identify errors detected by the program/erase controller. DQ5 is set to 1 when a PROGRAM, BLOCK ERASE, or CHIP ERASE operation fails to write the correct data to the memory. If DQ5 is set, a READ/RESET command must be issued before other commands are issued. The error bit is output on DQ5 when the status register is read. Note that the PROGRAM command cannot change a bit set to 0 back to 1 and attempting to do so will set DQ5 to 1. A bus READ operation to that address will show the bit remains 0. One of the ERASE commands must be used to set all the bits in a block or in the whole memory from 0 to 1. 4.4 Erase Timer Bit (DQ3) The erase timer bit can be used to identify the start of program/erase controller operation during a BLOCK ERASE command. After the program/erase controller starts erasing, DQ3 is set to 1. Before the program/erase controller starts, DQ3 is set to 0 and additional blocks to be erased may be written to the command interface. The erase timer bit is output on DQ3 when the status register is read. 4.5 Alternative Toggle Bit (DQ2) The alternative toggle bit can be used to monitor the program/erase controller during ERASE operations. It is output on DQ2 when the status register is read. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 12 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG During CHIP ERASE and BLOCK ERASE operations, DQ2 changes from 0 to 1 to 0, and so forth, with successive bus READ operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. After the operation completes, the memory returns to read mode. During erase suspend, DQ2 changes from 0 to 1 to 0, and so forth, with successive bus READ operations from addresses within the blocks being erased. Bus READ operations to addresses within blocks not being erased will output the memory cell data as if in read mode. After an ERASE operation that causes DQ5 to be set, DQ2 can be used to identify which block or blocks have caused the error. DQ2 changes from 0 to 1 to 0, and so forth, with successive bus READ operations from addresses within blocks that have not erased correctly. DQ2 does not change if the addressed block has erased correctly. 4.6 Write to Buffer and Program Abort Bit (DQ1) DQ1 is set to 1 when a WRITE TO BUFFER AND PROGRAM operation aborts. Otherwise, DQ1 is set to 0. The WRITE TO BUFFER AND PROGRAM ABORT AND RESET command must be issued to return the device to read mode (see Command Interface for more information). MYX29W640GB70ZABG Revision 1.0 - 04/13/16 13 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 6: Status Register Bits Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY# PROGRAM Any address DQ7# Toggle 0 — — 0 0 PROGRAM DURING ERASE SUSPEND Any address DQ7# Toggle 0 — — — 0 WRITE TO BUFFER AND PROGRAM ABORT Any address DQ7# Toggle 0 — — 1 0 WRITE TO BUFFER AND PROGRAM Any address DQ7# Toggle 0 — — 0 0 PROGRAM ERROR Any address DQ7# Toggle 1 — — — High-Z CHIP ERASE Any address 0 Toggle 0 1 Toggle — 0 BLOCK ERASE BEFORE TIMEOUT Erasing block 0 Toggle 0 0 Toggle — 0 Non-erasing block 0 Toggle 0 0 No Toggle — 0 Erasing block 0 Toggle 0 1 Toggle — 0 Non-erasing block 0 Toggle 0 1 No Toggle — 0 Erasing block 1 No Toggle 0 — Toggle — High-Z — High-Z BLOCK ERASE ERASE SUSPEND Non-erasing block ERASE ERROR Data read as normal Good block address 0 Toggle 1 1 No Toggle — High-Z Faulty block address 0 Toggle 1 1 Toggle — High-Z Note 1. Unspecified data bits should be ignored. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 14 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 3: Data Polling Flowchart MYX29W640GB70ZABG Revision 1.0 - 04/13/16 15 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 4: Data Toggle Flowchart MYX29W640GB70ZABG Revision 1.0 - 04/13/16 16 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 5 READ Operations 5.1 READ/RESET Command The READ/RESET (F0h) command returns the device to read mode and resets the errors in the status register. One or three bus WRITE operations can be used to issue the READ/ RESET command. To return the device to read mode, this command can be issued between bus WRITE cycles before the start of a PROGRAM or ERASE operation. If the READ/RESET command is issued during the timeout of a BLOCK ERASE operation, the device requires up to 10μs to abort, during which time no valid data can be read. 5.2 READ CFI Command The READ CFI (98h) command puts the device in read CFI mode and is valid only when the device is in read array or auto select mode. One bus WRITE cycle is required to issue the command. Once in read CFI mode, bus READ operations will output data from the CFI memory area. A READ/RESET command must be issued to return the device to the previous mode (read array or auto select ). A second READ/RESET command is required to put the device in read array mode from auto select mode. 6 AUTO SELECT Operations 6.1 AUTO SELECT Command At power-up or after a hardware reset, the device is in read mode. It can then be put in auto select mode by issuing an AUTO SELECT (90h) command or by applying VID to A9. Auto select mode enables the following device information to be read: • Electronic signature, which includes manufacturer and device code information. • Block protection, which includes the block protection status and extended memory block protection indicator. Electronic signature or block protection information is read by executing a READ operation with control signals and addresses set. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 17 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 7 Command Interface All bus WRITE operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus WRITE operations. Failure to observe a valid sequence of bus WRITE operations will result in the memory returning to read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16-bit or 8-bit mode. See the x8 and x16 command tables, depending on the configuration that is being used, for a summary of the commands. 7.1 READ/RESET Command The READ/RESET command returns the memory to its read mode. It also resets the errors in the status register. Either one or three bus WRITE operations can be used to issue the READ/RESET command. The READ/RESET command can be issued, between bus WRITE cycles before the start of a PROGRAM or ERASE operation, to return the device to read mode. If the READ/RESET command is issued during the timeout of a BLOCK ERASE operation, then the device will take up to 10μs to abort. During the abort period, no valid data can be read from the device. The READ/RESET command will not abort an ERASE operation when issued while in erase suspend. 7.2 AUTO SELECT Command The AUTO SELECT command is used to read the manufacturer code, the device code, the block protection status, and the extended memory block verify code. Three consecutive bus WRITE operations are required to issue the AUTO SELECT command. After the AUTO SELECT command is issued, the memory remains in auto select mode until a READ/RESET command is issued. READ CFI QUERY and READ/RESET commands are accepted in auto select mode, all other commands are ignored. In auto select mode, the manufacturer code and the device code can be read by using a bus READ operation with addresses and control signals set, as shown Bus Operations, except for A9 (which is “Don’t Care”). The block protection status of each block can be read using a bus READ operation with addresses and control signals set, as shown in Bus Operations, except for A9 (which is “Don’t Care”). If the addressed block is protected, then 01h is output on DQ0–DQ7; otherwise, 00h is output (in 8-bit mode). MYX29W640GB70ZABG Revision 1.0 - 04/13/16 18 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG The protection status of the extended memory block, or extended memory block verify code, can be read using a bus READ operation with addresses and control signals, except for A9 (which is “Don’t Care”). If the extended block is “factory-locked.” then 80h is output on DQ0–DQ7; otherwise, 00h is output (8-bit mode). 7.3 READ CFI QUERY Command The READ CFI QUERY command is used to read data from the CFI. This command is valid when the device is in the read array mode, or when the device is in auto select mode. One bus WRITE cycle is required to issue the READ CFI QUERY command. After the command is issued, subsequent bus READ operations read from the CFI. The READ/RESET command must be issued to return the device to the previous mode (the read array mode or auto select mode). A second READ/RESET command would be needed if the device is to be put in the read array mode from auto selected mode. 7.4 PROGRAM Command The PROGRAM command can be used to program a value to one address in the memory array at a time. The command requires four bus WRITE operations; the final WRITE operation latches the address and data, and starts the program/erase controller. Programming can be suspended and then resumed by issuing a PROGRAM SUSPEND command and a PROGRAM RESUME command, respectively. If the address falls in a protected block, then the PROGRAM command is ignored, the data remains unchanged. The status register is never read and no error condition is given. During a PROGRAM operation, the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Bus READ operations during the PROGRAM operation will output the status register on the data I/Os. (See Status Register for more details.) After the PROGRAM operation has completed, the memory will return to the read mode, unless an error has occurred. When an error occurs, the memory will continue to output the status register. A READ/RESET command must be issued to reset the error condition and return to read mode. Note that the PROGRAM command cannot change a bit set to 0 back to 1. One of the ERASE commands must be used to set all the bits in a block or in the whole memory from 0 to 1. (Refer to Program/Erase Characteristics.) MYX29W640GB70ZABG Revision 1.0 - 04/13/16 19 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 7.5 PROGRAM SUSPEND Command The PROGRAM SUSPEND command allows the system to interrupt a PROGRAM operation so that data can be read from any block. When the PROGRAM SUSPEND command is issued during a PROGRAM operation, the device suspends the PROGRAM operation within the program suspend latency time and updates the status register bits (see Program/ Erase Characteristics). After the PROGRAM operation has been suspended, the system can read array data from any address. However, data read from program-suspended addresses is not valid. The PROGRAM SUSPEND command may also be issued during a PROGRAM operation while an erase is suspended. In this case, data may be read from any addresses not in ERASE SUSPEND or PROGRAM SUSPEND. If a read is needed from the extended block area (one-time program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the AUTO SELECT command sequence when the device is in the program suspend mode. The system can read as many auto select codes as required. When the device exits the auto select mode, the device reverts to the program suspend mode, and is ready for another valid operation. 7.6 PROGRAM RESUME Command After the PROGRAM RESUME command is issued, the device reverts to programming. The controller can determine the status of the PROGRAM operation using the DQ7 or DQ6 status bits, just as in the standard PROGRAM operation. The system must write the PROGRAM RESUME command, to exit the program suspend mode and to continue the programming operation. Further issuing of the RESUME command is ignored. Another PROGRAM SUSPEND command can be written after the device has resumed programming. 7.7 Fast Program Commands There are five fast program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel: • QUADRUPLE and OCTUPLE BYE PROGRAM, available for x8 operations • DOUBLE and QUADRUPLE WORD PROGRAM, available for x16 operations • WRITE TO BUFFER AND PROGRAM MYX29W640GB70ZABG Revision 1.0 - 04/13/16 20 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Fast program commands can be suspended and then resumed by issuing a PROGRAM SUSPEND command and a PROGRAM RESUME command, respectively. 7.8 DOUBLE BYTE PROGRAM Command The DOUBLE BYTE PROGRAM command is used to write a page of two adjacent bytes in parallel. The two bytes must differ only in DQ15A-1. Three bus WRITE cycles are necessary to issue the DOUBLE BYTE PROGRAM command: The first bus cycle sets up the DOUBLE BYTE PROGRAM command; the second bus cycle latches the address and the data of the first byte to be written; and the third bus cycle latches the address and the data of the second byte to be written. It is not necessary to raise VPP/WP# to 12V before issuing this command. 7.9 QUADRUPLE BYTE PROGRAM Command The QUADRUPLE BYTE PROGRAM command is used to write a page of four adjacent bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the QUADRUPLE BYTE PROGRAM command: The first bus cycle sets up the QUADRUPLE BYTE PROGRAM command; the second bus cycle latches the address and the data of the first byte to be written; the third bus cycle latches the address and the data of the second byte to be written; the fourth bus cycle latches the address and the data of the third byte to be written; and the fifth bus cycle latches the address and the data of the fourth byte to be written and starts the program/ erase controller. It is not necessary to raise VPP/WP# to 12V before issuing this command. 7.10 OCTUPLE BYTE PROGRAM Command This is used to write eight adjacent bytes, in x8 mode, simultaneously. The addresses of the eight bytes must differ only in A1, A0 and DQ15A-1. 12V must be applied to VPP/Wp# prior to issuing an OCTUPLE BYTE PROGRAM command. Care must be taken because applying a 12V voltage to VPP/WP#, because it will temporarily unprotect any protected block. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 21 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 7.11 DOUBLE WORD PROGRAM Command The DOUBLE WORD PROGRAM command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus WRITE cycles are necessary to issue the DOUBLE WORD PROGRAM command: The first bus cycle sets up the DOUBLE WORD PROGRAM command; the second bus cycle latches the address and the data of the first word to be written; and the third bus cycle latches the address and the data of the second word to be written and starts the program/ erase controller. After the PROGRAM operation has completed, the memory will return to the read mode, unless an error has occurred. When an error occurs, bus READ operations will continue to output the status register. A READ/RESET command must be issued to reset the error condition and return to read mode. Note that the fast program commands cannot change a bit set to 0 back to 1. One of the ERASE commands must be used to set all the bits in a block or in the whole memory from 0 to 1. Typical program times are given in Program/Erase Characteristics. Note:It is not necessary to raise VPP/WP# to 12V before issuing this command. 7.12 QUADRUPLE WORD PROGRAM Command This is used to write a page of four adjacent words (or 8 adjacent bytes), in x16 mode, simultaneously. The addresses of the four words must differ only in A1 and A0. 12V must be applied to VPP/WP# prior to issuing a QUADRUPLE BYTE PROGRAM command. Care must be taken because applying a 12V voltage to VPP/WP#, because it will temporarily unprotect any protected block. Five bus WRITE cycles are necessary to issue the command: The first bus cycle sets up the command; the second bus cycle latches the address and the data of the first word to be written; the third bus cycle latches the address and the data of the second word to be written; the fourth bus cycle latches the address and the data of the third word to be written; and the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 22 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 7.13 WRITE TO BUFFER AND PROGRAM Command The WRITE TO BUFFER AND PROGRAM command makes use of the device’s 32-byte write buffer to speed up programming. 16 words/32 bytes can be loaded into the write buffer. Each write buffer has the same A4–A22 addresses. The WRITE TO BUFFER AND PROGRAM command dramatically reduces system programming time compared to the standard nonbuffered PROGRAM command. When issuing a WRITE TO BUFFER AND PROGRAM command, VPP/WP# can be either held HIGH or raised to VPPH. Five successive steps are required to issue the WRITE TO BUFFER AND PROGRAM command: The WRITE TO BUFFER AND PROGRAM command starts with two UNLOCK cycles. The third bus WRITE cycle sets up the WRITE TO BUFFER AND PROGRAM command. The setup code can be addressed to any location within the targeted block. The fourth bus WRITE cycle sets up the number of words to be programmed. Value n is written to the same block address, where n + 1 is the number of words to be programmed. The value of n + 1 must not exceed the size of the write buffer or the operation will abort. The fifth cycle loads the first address and data to be programmed. The value of n bus WRITE cycles is used to load the address and data for each word into the write buffer. Addresses must lie within the range from the start address+1 to the start address + n - 1. Optimum performance is obtained when the start address corresponds to a 64-byte boundary. If the start address is not aligned to a 64-byte boundary, the total programming time is doubled. All the addresses used in the WRITE TO BUFFER AND PROGRAM operation must lie within the same page. If an address is written several times during a WRITE TO BUFFER AND PROGRAM operation, the address/data counter will be decremented at each data load operation, and the data will be programmed to the last word loaded into the buffer. Invalid address combinations or failing to follow the correct sequence of bus WRITE cycles will abort the WRITE TO BUFFER AND PROGRAM operation. DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a WRITE TO BUFFER AND PROGRAM operation. It is possible to detect PROGRAM operation fails when changing programmed data from 0 to 1; that is, when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. To program the content of the write buffer, this command must be followed by a WRITE TO BUFFER AND PROGRAM CONFIRM command. A WRITE TO BUFFER AND PROGRAM ABORT AND RESET command must be issued to abort the WRITE TO BUFFER AND PROGRAM operation and reset the device in read mode. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 23 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG The write buffer programming sequence can be aborted in the following ways: • Load a value that is greater than the page buffer size during the number of locations to program step • Write to an address in a block different than the one specified during the WRITEBUFFER-LOAD command • Write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation • Write data other than the CONFIRM command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5 = 0. A WRITE TO BUFFER ABORT AND RESET command sequence must be written to reset the device for the next operation. Note that the full threecycle WRITE TO BUFFER ABORT AND RESET command sequence is required when using write-buffer-programming features in unlock bypass mode. 7.14 WRITE TO BUFFER AND PROGRAM CONFIRM Command The WRITE TO BUFFER AND PROGRAM CONFIRM command is used to confirm a WRITE TO BUFFER AND PROGRAM command and to program the n + 1 words loaded in the write buffer by this command. 7.15 WRITE TO BUFFER AND PROGRAM ABORT AND RESET Command The WRITE TO BUFFER AND PROGRAM ABORT AND RESET command is used to reset the device after a WRITE TO BUFFER AND PROGRAM command has been aborted. 7.16 UNLOCK BYPASS Command The UNLOCK BYPASS command is used in conjunction with the UNLOCK BYPASS PROGRAM command to program the memory faster than with the standard PROGRAM commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three bus WRITE operations are required to issue the UNLOCK BYPASS command. After the UNLOCK BYPASS command has been issued, the memory will only accept them UNLOCK BYPASS PROGRAM command and the UNLOCK BYPASS RESET command. The memory can be read as if in read mode. When VPP is applied to VPP/WP#, the memory automatically enters the unlock bypass MYX29W640GB70ZABG Revision 1.0 - 04/13/16 24 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG mode and the UNLOCK BYPASS PROGRAM command can be issued immediately. 7.17 UNLOCK BYPASS PROGRAM Command The UNLOCK BYPASS command is used in conjunction with the UNLOCK BYPASS PROGRAM command to program the memory. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three bus WRITE operations are required to issue the UNLOCK BYPASS command. After the UNLOCK BYPASS command has been issued, the memory will only accept the UNLOCK BYPASS PROGRAM command and the UNLOCK BYPASS RESET command. The memory can be read as if in read mode. The memory offers accelerated PROGRAM operations through VPP/WP#. When the system asserts VPP on VPP/WP#, the memory automatically enters the unlock bypass mode. The system may then write the two-cycle UNLOCK BYPASS PROGRAM command sequence. The memory uses the higher voltage on VPP/WP# to accelerate the UNLOCK BYPASS PROGRAM operation. Never raise VPP/WP# to VPP from any mode except read mode; otherwise, the memory may be left in an indeterminate state. 7.18 UNLOCK BYPASS RESET Command The UNLOCK BYPASS RESET command can be used to return to read/reset mode from unlock bypass mode. Two bus WRITE operations are required to issue the UNLOCK BYPASS RESET command. A READ/RESET command does not exit from unlock bypass mode. 7.19 CHIP ERASE Command The CHIP ERASE command can be used to erase the entire chip. Six bus WRITE operations are required to issue the CHIP ERASE command and start the program/erase controller. If any blocks are protected, then these are ignored and all the other blocks are erased. If all of the blocks are protected the CHIP ERASE operation appears to start but will terminate within about 100μs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the ERASE operation the memory will ignore all commands, including the ERASE SUSPEND command. It is not possible to issue any command to abort the operation. All bus READ operations during the CHIP ERASE operation will output the status register on the data I/Os. After the CHIP ERASE operation has completed, the memory will return MYX29W640GB70ZABG Revision 1.0 - 04/13/16 25 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG to the read mode, unless an error has occurred. When an error occurs the memory will continue to output the status register. A READ/RESET command must be issued to reset the error condition and return to read mode. The CHIP ERASE command sets all of the bits in unprotected blocks of the memory to 1. All previous data is lost. 7.20 BLOCK ERASE Command The BLOCK ERASE command can be used to erase a list of one or more blocks. Six bus WRITE operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth bus WRITE operation using the address of the additional block. The BLOCK ERASE operation starts the program/erase controller about 50μs after the last bus WRITE operation. After the program/erase controller starts, it is not possible to select any more blocks. Each additional block must therefore be selected within 50μs of the last block. The 50μs timer restarts when an additional block is selected. The status register can be read after the sixth bus WRITE operation. ( See the status register section for details on how to identify whether the program/ erase controller has started the BLOCK ERASE operation.) If any selected blocks are protected, then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected, the BLOCK ERASE operation appears to start but will terminate within about 100μs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the BLOCK ERASE operation, the memory will ignore all commands except the ERASE SUSPEND command. (Typical block erase times are given in the Program/Erase Characteristics.) All bus READ operations during the BLOCK ERASE operation will output the status register on the data I/Os. After the BLOCK ERASE operation has completed, the memory will return to the read mode, unless an error has occurred. When an error occurs, the memory will continue to output the status register. A READ/RESET command must be issued to reset the error condition and return to read mode. The BLOCK ERASE command sets all of the bits in the unprotected selected blocks to 1. All previous data in the selected blocks is lost. 7.21 ERASE SUSPEND Command The ERASE SUSPEND command may be used to temporarily suspend a BLOCK ERASE operation and return the memory to read mode. The command requires one bus WRITE operation. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 26 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG The program/erase controller will suspend within the erase suspend latency time of the ERASE SUSPEND command being issued. After the program/erase controller has stopped, the memory will be set to read mode and the erase will be suspended. If the ERASE SUSPEND command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts), then the erase is suspended immediately and will start immediately when the ERASE RESUME command is issued. It is not possible to select any further blocks to erase after the ERASE RESUME. During ERASE SUSPEND, it is possible to read and program cells in blocks that are not being erased; both READ and PROGRAM operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block, then the PROGRAM command is ignored and the data remains unchanged. The status register is not read and no error condition is given. Reading from blocks that are being erased will output the status register. It is also possible to issue the AUTO SELECT, READ CFI QUERY, and UNLOCK BYPASS commands during an ERASE SUSPEND. The READ/RESET command must be issued to return the device to read array mode before the RESUME command will be accepted. 7.22 ERASE RESUME Command The ERASE RESUME command must be used to restart the program/erase controller after an erase suspend. The device must be in read array mode before the RESUME command will be accepted. An erase can be suspended and resumed more than once. 7.23 ENTER EXTENDED BLOCK Command The device has an extra 256-byte block (extended block) that can only be accessed using the ENTER EXTENDED BLOCK command. Three bus WRITE cycles are required to issue the ENTER EXTENDED BLOCK command. After the command has been issued, the device enters extended block mode where all bus READ or WRITE operations to the boot block addresses access the extended block. The extended block (with the same address as the boot blocks) cannot be erased, and can be treated as OTP memory. In extended block mode, the boot blocks are not accessible. The extended block can be protected; however, once protected, the protection cannot be undone. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 27 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 7.24 EXIT EXTENDED BLOCK Command The EXIT EXTENDED BLOCK command is used to exit from the extended block mode and return the device to read mode. Four bus WRITE operations are required to issue the command. 7.25 BLOCK PROTECT and CHIP UNPROTECT Commands Groups of blocks can be protected against accidental program or erase. (See Memory Organization for the protection groups.) The whole chip can be unprotected to allow the data inside the blocks to be changed. 7.26 BLOCK PROTECT Command Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each block can be protected individually. Once protected, PROGRAM and ERASE operations on the block fail to change the data. There are three techniques that can be used to control block protection. These are programmer technique, in-system technique, and temporary unprotect. Temporary unprotect is controlled by RST#. Unlike the command interface of the program/erase controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. Care should be taken when changing drivers for one part to work on another. 7.27 Programmer Technique The programmer technique uses high voltage levels (VID) on some of the bus pins. These cannot be achieved using a standard microprocessor bus; therefore, the technique is recommended only for use in programming equipment. To protect a block, follow the steps in the following figure. To unprotect the whole chip, it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. (See the Programmer Equipment Chip Protect Flowchart.) The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 28 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 5: Programmer Equipment Block Protect Flowchart MYX29W640GB70ZABG Revision 1.0 - 04/13/16 29 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 6: Programmer Equipment Chip Unprotect Flowchart MYX29W640GB70ZABG Revision 1.0 - 04/13/16 30 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 7: Programmer Technique Bus Operations Notes 1 and 2 apply to entire table Operation CE# OE# WE# Address Inputs Data I/Os A[MAX:0] DQ15/A-1, DQ[14:0] BLOCK PROTECT L VID L pulse A9 = VID A[21:12] block addresses others = X X CHIP UNPROTECT VID VID L pulse A9 = VID A12 = VIH A15 = VIH others = X X BLOCK PROTECTION VERIFY L L VIH A0, A2, A3 = VIL A1 = VIH A6 = VIL A9 = VID A[21:12] block addresses others = X Pass = XX01h Retry = XX00h BLOCK UNPROTECT VERIFY L L VIH A0, A2, A3 = VIL A1 = VIH A6 = VIH A9 = VID A[21:12] block addresses others = X Retry = XX01h Pass = XX00h Note 1. Typical glitches of less than 5ns on CE# and WE# are ignored by the device and do not affect bus operations. 2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 7.28 In-System Technique The in-system technique requires a high-voltage level on RST#. This can be achieved without violating the maximum ratings of the components on the microprocessor bus; therefore, this technique is suitable for use after the Flash has been fitted to the system. To protect a block, follow the steps in the following figure. To unprotect the whole chip, it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. (See the In-System Equipment Chip Unprotect Flowchart.) The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 31 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 7: In-System Equipment Block Protect Flowchart MYX29W640GB70ZABG Revision 1.0 - 04/13/16 32 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 8: In-System Equipment Chip Protect Flowchart MYX29W640GB70ZABG Revision 1.0 - 04/13/16 33 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 8: Commands – 16-Bit Mode (BYTE# = VIH) Bus WRITE Operations 1st MYX29W640GB70ZABG Revision 1.0 - 04/13/16 2nd Command Length Addr Data READ/RESET 1 X FO 3 555 AUTO SELECT 3 READ CFI QUERY 3rd 4th Addr Data Addr Data AA 2AA 55 X F0 555 AA 2AA 55 555 90 1 55 98 PROGRAM 4 555 AA 2AA 55 555 A0 DOUBLE WORD PROGRAM 3 555 50 PA0 PD0 PA1 PA1 QUADRUPLE WORD PROGRAM 5 555 56 PA0 PD0 PA1 PA1 UNLOCK BYPASS 3 555 AA 2AA 55 555 20 UNLOCK BYPASS PROGRAM 2 X AO PA PD UNLOCK BYPASS RESET 2 X 90 X 00 WRITE TO BUFFER AND PROGRAM N+5 555 AA 2AA 55 BA 25 WRITE TO BUFFER AND PROGRAM ABORT AND RESET 3 555 AA 2AA 55 555 F0 WRITE TO BUFFER AND PROGRAM CONFIRM 1 BA on page 29 CHIP ERASE 6 555 AA 2AA 55 555 BLOCK ERASE 6+ 555 AA 2AA 55 PROGRAM/ ERASE SUSPEND 1 X B0 PROGRAM/ ERASE RESUME 1 X 30 ENTER EXTENDED BLOCK 3 555 AA 2AA 55 5th Addr Data PA PD PA2 6th Addr Data Addr Data PD2 PA3 PD3 BA N on page PA on page PD WBL on page PD 80 555 AA 2AA 55 555 10 555 80 555 AA 2AA 55 BA 30 555 88 34 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 8: Commands – 16-Bit Mode (BYTE# = VIH) (Continued) Bus WRITE Operations 1st 2nd 3rd 4th 5th Command Length Addr Data Addr Data Addr Data Addr Data EXIT EXTENDED BLOCK 4 555 AA 2AA 55 555 90 X 00 Notes: Addr 6th Data Addr Data 1. X = “ Don’t Care;” PA = Program address; PD = Program data; BA = Any address in the block. All values in the table are in hexadecimal. The command interface only uses A-1; A0–A10 and DQ0–DQ7 to verify the commands; A11–A20, DQ8–DQ14 and DQ15 are “Don’t Care.” DQ15A-1 is A-1 when BYTE# is VIL or DQ15 when BYTE# is VIH. 2. The maximum number of cycles in the command sequence is 36. N + 1 is the number of words to be programmed during the WRITE TO BUFFER AND PROGRAM operation. 3. Each buffer has the same A4–A22 addresses. A0–A3 are used to select a word within the N + 1 word page. 4. The 6th cycle has to be issued N time. WBL scans the word inside the page. 5. BA must be identical to the address loaded during the WRITE TO BUFFER AND PROGRAM 3rd and 4th cycles. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 35 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 9: Commands – 8-Bit Mode (BYTE# = VIL) Bus WRITE Operations 1st 2nd Length Addr Data READ/RESET 1 X FO 3 AAA AUTO SELECT 3 READ CFI QUERY 4th Addr Data Addr Data AA 555 55 X F0 AAA AA 555 55 555 90 1 AA 98 PROGRAM 4 AAA AA 555 55 555 A0 DOUBLE BYTE PROGRAM 3 AAA 50 PA0 PD0 PA1 PD1 QUADRUPLE BYTE PROGRAM 5 AAA 56 PA0 PD0 PA1 OCTUPLE BYTE PROGRAM 9 AAA 8B PA0 PD0 WRITE TO BUFFER AND PROGRAM N+5 AAA AA 555 WRITE TO BUFFER AND PROGRAM ABORT AND RESET 3 AAA AA WRITE TO BUFFER AND PROGRAM CONFIRM 1 BA6 29 UNLOCK BYPASS 3 AAA UNLOCK BYPASS PROGRAM 2 UNLOCK BYPASS RESET MYX29W640GB70ZABG Revision 1.0 - 04/13/16 Command 3rd 5th Addr Data PA PD PD1 PA2 PA1 PD1 55 BA 25 555 55 AAA F0 AA 555 55 AAA 20 X A0 PA PD 2 X 90 X 00 CHIP ERASE 6 AAA AA 555 55 AAA BLOCK ERASE 6+ AAA AA 555 55 AAA PROGRAM/ ERASE SUSPEND 1 X B0 PROGRAM/ ERASE RESUME 1 X 30 6th Addr Data Addr Data PD2 PA3 PD3 PA2 PD2 PA3 PD3 PA4 PD42 BA N2 PA4 PD WBL5 PD 80 AAA AA 555 55 AAA 10 80 AAA AA 555 55 BA 30 36 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG TABLE 9: Commands – 8-Bit Mode (BYTE# = VIL) (Continued) Bus WRITE Operations 1st 2nd 3rd 4th Command Length Addr Data Addr Data Addr Data ENTER EXTENDED BLOCK 3 AAA AA 555 55 AAA 88 EXIT EXTENDED BLOCK 4 AAA AA 555 55 AAA 90 Notes 5th Addr Data X 00 Addr 6th Data Addr Data 1. X = “ Don’t Care;” PA = Program address; PD = Program data; BA = Any address in the block. All values in the table are in hexadecimal. The command interface only uses A-1, A0–A10, and DQ0– DQ7 to verify the commands; A11–A20, DQ8–DQ14, and DQ15 are “Don’t Care.” DQ15A-1 is A-1 when BYTE# is VIL or DQ15 when BYTE# is VIH. 2. The following is content for address: Data cycles 7 through 10: PA5–PD5, PA6–PD6, PA7– PD7, PA8–PD8. 3. The maximum number of cycles in the command sequence is 68. N + 1 is the number of words to be programmed during the WRITE TO BUFFER AND PROGRAM operation. 4. Each buffer has the same A4–A22 addresses. A0–A3 and DQ15A-1 are used to select a word within the N + 1 word page. 5. The 6th cycle has to be issued N time. WBL scans the word inside the page. 6. BA must be identical to the address loaded during the WRITE TO BUFFER AND PROGRAM 3rd and 4th cycles. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 37 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 8 Common Flash Interface The common Flash interface (CFI) is a JEDEC-approved, standardized data structure that can be read from the Flash memory device. It allows a system’s software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. 9 Absolute Ratings and Operating Conditions Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 10: Absolute Maximum/Minimum Ratings Parameter Symbol Min Max Unit Temperature under bias TBIAS –50 125 °C Storage temperature TSTG –65 150 °C Input/output voltage VIO –0.6 VCC + 0.6 V Supply voltage VCC –0.6 4 V Program voltage VPP –0.6 13.5 V Identification voltage VID –0.6 13.5 V Notes Notes 1, 2 3 1. During signal transitions, minimum voltage may undershoot to −2V for periods less than 20ns. 2. During signal transitions, maximum voltage may overshoot to VCC + 2V for periods less than 20ns. 3. VPP must not remain at 12V for more than a total of 80 hours. Table 11: Operating Conditions M29W640GB Parameter MYX29W640GB70ZABG Revision 1.0 - 04/13/16 Symbol Min Max Unit Supply voltage VCC 2.7 3.6 V Ambient operating temperature TA -40 85 °C Load capacitance CL Input rise and fall times — Input rise and fall times — 0 to VCC V Input and output timing reference voltages — VCC/2 V 30 — Notes pF 10 ns 38 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 9: AC Measurement Load Circuit Figure 10: AC Measurement I/O Waveform Table 12: Input/Output Capacitance Parameter Input capacitance Output capacitance Note MYX29W640GB70ZABG Revision 1.0 - 04/13/16 Symbol Test Condition Min Max Unit CIN VIN = 0V — 6 pF COUT VOUT = 0V — 12 pF 1. Sampled only, not 100% tested. 39 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 13: DC Current Characteristics Parameter Symbol Conditions Typ Max Unit Notes Input leakage current ILI 0V ≤ VIN ≤ VCC — ±1 μA 1 Output leakage current ILO 0V ≤ VOUT ≤ VCC — ±1 μA Read current ICC1 CE# = VIL, OE# = VIH, f = 6 MHz 10 mA Standby current ICC2 CE# = VCC ±0.2V RST# = VCC ±0.2V 100 μA 2 Program/Erase current ICC3 Program/Erase controller active: VPP/WP# = VIL or VIH; VPP/WP# = VPP — 20 mA 3 Current for VPP/WP# program acceleration IPP VCC = 2.7V ±10% — 15 mA Note 1. The maximum input leakage current is ±5uA on VPP/WP#. 2. When the bus is inactive for 300ns or more, the memory enters automatic standby. 3. Sampled only; not 100% tested. Table 14: DC Voltage Characteristics Parameter Symbol Conditions Typ Max Unit Notes Input LOW voltage VIL — — ±1 μA 1 Input HIGH voltage VIH — — ±1 μA Voltage for VPP/WP# program acceleration VPP VCC = 2.7V ±10% 10 mA Output LOW voltage VOL IOL = 1.8mA 100 μA 2 Output HIGH voltage VOH IOH = –100μA — 20 mA 3 Identification voltage VID — — 15 mA Program/erase lockout supply voltage VLKO — Note MYX29W640GB70ZABG Revision 1.0 - 04/13/16 1. Sampled only; not 100% tested. 40 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 15: Read AC Characteristics Symbol Parameter Legacy JEDEC Conditions Min/Max 70ns Unit tRC tAVAV CE# = VIL, OE# = VIL Min 70 ns Address valid to output valid tACC tAVQV CE# = VIL, OE# = VIL Max 70 ns Address valid to output valid (page) tPAGE tAVQV1 CE# = VIL, OE# = VIL Max 30 ns CE# LOW to output transition tLZ tELQX OE# = VIL Min 0 ns CE# LOW to output valid tCE tELQV OE# = VIL Max 70 ns OE# LOW to output transition tOLZ tGLQX CE# = VIL Min 0 ns OE# LOW to output valid tOE tGLQV CE# = VIL Max 30 ns CE# HIGH to output High-Z tHZ tEHQZ OE# = VIL Max 30 ns 1 OE# HIGH to output High-Z tDF tGHQZ CE# = VIL Max 30 ns 1 CE#, OE#, or address transition to output transition tOH tEHQX, — Min 0 ns Address valid to next address valid Notes 1 1 tGHQX, tAXQX CE# to BYTE# LOW tELFL tELBL — Max 5 ns CE# to BYTE# HIGH tELFH tELBH — Max 5 ns BYTE# LOW to output High-Z tFLQZ tBLQZ — Max 25 ns BYTE# HIGH to output valid tFHQV tBHQV — Max 30 ns Note MYX29W640GB70ZABG Revision 1.0 - 04/13/16 1. Sampled only; not 100% tested. 41 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 11: Random AC Timing MYX29W640GB70ZABG Revision 1.0 - 04/13/16 42 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 12: Page Read AC Timing MYX29W640GB70ZABG Revision 1.0 - 04/13/16 43 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 16: WE#-Controlled Write AC Characteristics Symbol Parameter Legacy JEDEC Min/Max 70ns Unit Address valid to next address valid tWC tAVAV Min 70 ns CE# LOW to WE# LOW tCS tELWL Min 0 ns WE# LOW to WE# HIGH tWP tWLWH Min 35 ns Input valid to WE# HIGH tDS tDVWH Min 30 ns WE# HIGH to input transition tDH tWHDX Min 0 ns WE# HIGH to CE# HIGH tCH tWHEH Min 0 ns WE# HIGH to WE# LOW tWPH tWHWL Min 25 ns Address valid to WE# LOW tAS tAVWL Min 0 ns WE# LOW to address transition tAH tWLAX Min 45 ns tGHWL Min 0 ns OE# HIGH to WE# LOW WE# HIGH to OE# LOW tOEH tWHGL1 Min 0 ns Program/erase valid to RY/BY# LOW tBUSY tWHRL1 Max 0 ns VCC HIGH to CE# LOW tVCS tVCHEL Min 50 ns Note MYX29W640GB70ZABG Revision 1.0 - 04/13/16 Notes 1 1. Sampled only; not 100% tested. 44 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 13: WE#-Controlled AC Timing MYX29W640GB70ZABG Revision 1.0 - 04/13/16 45 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 17: CE#-Controlled Write AC Characteristics Symbol Parameter Legacy JEDEC Min/Max 70ns Unit Address valid to next address valid tWC tAVAV Min 70 ns WE# LOW to CE# LOW tWS tWLWL Min 0 ns CE# LOW to CE# HIGH tCP tELEH Min 35 ns Input valid to CE# HIGH tDS tDVEH Min 30 ns CE# HIGH to input transition tDH tEHDX Min 0 ns CE# HIGH to WE# HIGH tWH tWHEH Min 0 ns CE# HIGH to CE# LOW tCPH tEHEL Min 25 ns Address valid to CE# LOW tAS tAVEL Min 0 ns CE# LOW to address transition tAH tELAX Min 45 ns OE# HIGH to CE# LOW — tGHEL Min 0 ns CE# HIGH to OE# LOW tOEH tEHGL1 Min 0 ns Program/Erase valid to RY/BY# LOW tBUSY tEHRL1 Max 0 ns VCC HIGH to WE# LOW tVCS tVCHWL Min 50 ns Note MYX29W640GB70ZABG Revision 1.0 - 04/13/16 Notes 1 1. Sampled only; not 100% tested. 46 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 14: CE#-Controlled AC Timing MYX29W640GB70ZABG Revision 1.0 - 04/13/16 47 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 18: Toggle and Alternative Toggle AC Characteristics Symbol Parameter Legacy JEDEC Min/Max 70ns Unit Address setup time to OE# LOW during toggle bit polling tASO tAXGL Min 10 ns Address hold time from OE# during toggle bit polling tAHT tGHAX Min 10 ns tEHAX Min 10 ns CE# HIGH during toggle bit polling tCEPH tEHEL2 Min 10 ns Output hold time during data and toggle bit polling tOEH tWHGL2 Min 20 ns tGHGL2 Min 20 ns Note 1. Data for tELQV and tGLQV are in the Read AC Characteristics table. Figure 15: Toggle/Alternative Toggle, CE# Controlled MYX29W640GB70ZABG Revision 1.0 - 04/13/16 48 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 16: Toggle/Alternative Toggle, OE# Controlled MYX29W640GB70ZABG Revision 1.0 - 04/13/16 49 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Table 19: Program/Erase Times and Endurance Cycles Notes 1 and 2 apply to the entire table Parameter Symbol Min Typ Max Unit Notes — 80 400 s 3 — 0.5 s 4.5 50 μs 6 10 200 μs 3 Program (double byte) 10 200 μs 3 Program (double word/quadruple byte) 10 200 μs 3 Program (quadruple word/octuple byte) 10 200 μs 3 10 μs 3, 7 Program (32-byte 16-word using Write to Buffer and Program) 180 μs Program (32-byte 16-word using Write to Buffer and Program, VPP/WP# = 12V) 45 μs Chip erase tWHWH2 Block erase (64KB) Erase suspend latency time — Program (byte or word) — tWHWH1 Program (single byte and word) Chip program (byte by byte) — — 80 400 s 3 Chip program (word by word) 40 200 s 3 Chip program (double word/quadruple byte) 20 100 s 3 10 50 s 3 4 μs Chip program (quadruple word/octuple byte) — Program suspend latency time — PROGRAM/ERASE cycles (per block) Data retention Note 100,000 cydes 20 years 1. Typical values measured at room temperature and nominal voltages and for not cycled devices. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 PROGRAM/ERASE cycles. 4. Time does not include pre-programming time. 5. Block erase polling cycle time. 6. Maximum value measured at worst case conditions for both temperature and VCC. 7. Programming polling cycle time. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 50 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 17: WE# Controlled Program Waveform MYX29W640GB70ZABG Revision 1.0 - 04/13/16 51 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 18: CE# Controlled Program Waveform MYX29W640GB70ZABG Revision 1.0 - 04/13/16 52 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 19: Chip/Block Erase Waveform MYX29W640GB70ZABG Revision 1.0 - 04/13/16 53 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG 10 Reset Characteristics Table 20: Reset/Block Temporary Unprotect AC Characteristics Symbol Condition/Parameter RST# HIGH to WE# LOW, CE# LOW, OE# LOW Legacy JEDEC Min/Max 70ns Unit Notes tRH tPHWL Min 50 ns 1 1 tPHEL tPHGL RY/BY# HIGH to WE# LOW, CE# LOW, OE# LOW tRB tRHWL tRHEL tRHGL Min 0 ns RST# pulse width tRP tPLPX Min 500 ns tREADY tPLYH Max 50 μs 1 RST# rise time to VID tVIDR tPHPHH Min 500 ns 1, 2 VPP rise and fall time — tVHVPP Min 500 ns 1 RST# LOW to read mode Note 1. Sampled only; not 100% tested. 2. For fast program operations using VPP/WP# at 12V. Figure 20: Reset/Block Temporary Unprotect AC Waveforms Figure 21: Accelerated Programming Timing Waveform MYX29W640GB70ZABG Revision 1.0 - 04/13/16 54 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Figure 22: 48-Ball TFBGA – 6mm x 8mm 11 Ordering Information Part Number Device Grade MYX29W640GB70ZABG-IT Industrial .For more information, contact a Micross sales representative at [email protected]. MYX29W640GB70ZABG Revision 1.0 - 04/13/16 55 Form #: CSI-D-685 Document 007 64Mb: 3V Embedded Parallel NOR Flash MYX29W640GB70ZABG Document Title 64Mb: 3V Parallel NOR Flash Embedded Memory Revision History Revision # History Release Date Status 1.0 Initial release March 28, 2016 Preliminary MYX29W640GB70ZABG Revision 1.0 - 04/13/16 56 Form #: CSI-D-685 Document 007