MYX4DDR2128M16PK 2Gb - 128M x 16 DDR2 SDRAM Advanced information. Subject to change without notice. Features • Tin-lead ball metalurgy Options • VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V • JEDEC-standard 1.8V I/O (SSTL_18-compatible) Code • Configuration 128M x 16 (16M x 16 x 8 banks) 128M16 • Differential data strobe (DQS, DQS#) option • 4n-bit prefetch architecture • Package: FBGA (Sn63 Pb37) • Duplicate output strobe (RDQS) option for x8 Footprint: 84-ball (9mm x 12.5mm) • DLL to align DQ and DQS transitions with CK BG PK • Timing - cycle time • 8 internal banks for concurrent operation 2.5ns @ CL = 5 (DDR2-800) • Programmable CAS latency (CL) -25E • Operating temperature • Posted CAS additive latency (AL) Industrial (-40°C ≤ TC ≤ +95°C; • WRITE latency = READ latency - 1 tCK IT -40°C ≤ TA ≤ +85°C;) • Selectable burst lengths (BL): 4 or 8 • Part Marking: Label (L), Dot (D) • Adjustable data-output drive strength • 64ms, 8192-cycle refresh • On-die termination (ODT) • Industrial temperature (IT) • Supports JEDEC clock jitter specification Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade -25E tRC CL=3 CL=4 CL=5 CL=6 CL=7 400 533 800 800 n/a (ns) 55 Micron Part No. MT47H128M16RT-25E IT:C February 24, 2016 • Revision 1.9 Micross US (Americas) 407.298.7100 • Micross UK (EMEA & ROW) +44 (0) 1603 788967 • [email protected] • www.micross.com Form #: CSI-D-686 Document 006 MYX4DDR2128M16PK • 2Gb - 128M x 16 DDR2 SDRAM 2Gb: x4, x8, x16 DDR2 SDRAM Advanced information. Subject to change without notice.and Descriptions Ball Assignments FBGAAssignments – x16 Ball Assignments (Top 2Gb, View)PK Figure 1: 84-BallFigure FBGA7: -84-Ball x16 Ball (Top View), 1 2 3 4 5 6 7 8 9 V DD NC V SS DQ14 V SSQ UDM UDQS V SSQ DQ15 V DDQ DQ9 V DDQ V DDQ DQ8 V DDQ DQ12 V SSQ DQ11 DQ10 V SSQ DQ13 V DD NC V SS DQ6 V SSQ LDM LDQS V SSQ DQ7 V DDQ DQ1 V DDQ V DDQ DQ0 V DDQ DQ4 V SSQ DQ3 DQ2 V SSQ DQ5 V DDL V REF V SS V SSDL CK V DD CKE WE# RAS# CK# ODT BA0 BA1 CAS# CS# A V SSQ UDQS#/NU V DDQ B C D E V SSQ LDQS#/NU V DDQ F G H J K L BA2 M Figure 9: 84-Ball A1 FBGA Package (9mm x 12.5mm) A2 – x16 A10 A0 V SS A4 N A3 A5 A6 A7 Seating A9 plane A12 RFU R A 0.12 A A11 A8 1.8 CTR RFU Nonconductive overmold A13 2Gb: x4, x8, x16 DDR2 SDRAM Packaging Figure 2: Package Dimensions 84-Ball FBGA Package (9mm x 12.5mm) - x16, PK V DD 0.8 ±0.05 0.155 P V DD 2Gb: x4, x8, x16 DDR2 SDRAM Packaging V SS 84X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. 9 8 7 Ball A1 ID Ball A1 ID 3 2 1 A Figure 9: 84-Ball FBGA Package (9mm x 12.5mm) – x16 B C PDF: 09005aef824f87b6 2Gb_DDR2.pdf – Rev. H 10/11 EN 15 0.8 ±0.05 D right to change products or specifications without notice. Micron Technology, Inc. reserves the 2006 Micron Technology, Inc. All rights reserved. E 0.155 F G Seating plane H 11.2 CTR 0.12 A A 12.5 ±0.1 J K 1.8 CTR Nonconductive overmold L M N 84X Ø0.45 Dimensions apply to solder balls post-reflow Notes: 1. All dimensions 9 8 7 are in millimeters. 3 2 1 on Ø0.35 SMD ball pads. 2. Solder ball material: Sn63/Pb37 3. Micron – MT47H128M16 February 24, 2016 • Revision 1.9 Ball A1 ID P Ball A1 ID 0.8 TYP A B 6.4 CTR C 9 ±0.1 D Notes: E F G 11.2 CTR 0.8 TYP H J K 12.5 ±0.1 R 1.2 MAX 0.25 MIN 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or leaded Eutectic (62% Sn, 36%Pb, 2% Ag). Micross US (Americas) • 407.298.7100 Micross UK (EMEA & ROW) • +44 (0) 1603 788967 [email protected] www.micross.com L M N Form #: CSI-D-686 Document 006