L E A D E R S H I P F O R T H E 90 Nanometer 90 0 S o C G E N E R A T I O N www.umc.com F O U N D R Y 90 Nanometer UMC has been shipping customer products based on its 90-nanometer (0.09-um) logic process since March of 2003. Currently, UMC is in volume production for a wide range of 90nm products from multiple customers. UMC’s mature 90nm technology meets a broad range of market sectors, including wireless RF, baseband, high speed graphics, FPGA, and single chip SoC WLAN products. UMC's comprehensive SoC solutions for 90nm include a process technology platform that features multiple transistor options, design flows and tools, IP solutions that include URAM and e-fuse, DFM resources, fast yield feedback service, and advanced packaging options. UMC's 90-nanometer SoC solution begins with a flexible technology design platform. Customers are able to choose from a variety of process device options optimized for their specific application, such as High Speed or Low Leakage transistors. Technology options can then be implemented including mixed signal/RFCMOS and embedded memories to further customize the process. 90nm Key Features • Integrated flows for Logic, Mixed-Signal/RF • 1.16 / 0.99um (SWL) SRAM bit cells 2 • e-Fuse option • Shallow trench isolation • Retrograde twin well (Triple well option) • 193nm litho for critical layers • Dual / triple gate dielectric options • 70nm min. poly length • Multiple Vt options • CoSi2 process • Up to 1P9M Cu with low-k / FSG dielectric offerings • BOAC (Bonding Over Active Circuit) • Wire Bond / Flip Chip option Technology to Meet Broad Applications UMC 90nm Technology Low Leakage (L90LL) Standard Performance (L90SP) High Speed (L90G) • Portable • Wireless • ASIC • Consumer • Network • Graphics 90nm Logic/MS/RF Devices 90nm Logic/MS/RF Technology I/O Devices Core Devices MS/RF Devices SP_RVt 1.0V(1.2V) 1.8V I/O Native Vt (Thin/Thick Ox.) SP_LVt 1.0V(1.2V) 2.5V I/O Bipolar SP_HVt 1.0V(1.2V) 3.3V I/O Diodes LL_RVt 1.2V Resistor LL_LVt 1.2V MIM/MOM * LL_HVt 1.2V Varactor * G_RVt 1.0V(1.2V) Inductor * G_HVt 1.0V(1.2V) Transformer * SP: Standard Performance *: Not available for 90G LL: Low Leakage G: Graphics : RF Model Available (LL and SP) Silicon Verified IP Solutions UMC offers comprehensive design resources Base Band DTV that enable our customers to fully realize the advantages of UMC's advanced technologies. Mobile DDR, PLL, ADC/DAC, LVDS, USB, Embedded Memory PLL, USB, LVDS, ADC/DAC, Embedded Memory, HDMI, DDR2 UMC's silicon verified fundamental IPs (standard cells, I/Os, and memory compilers) help customers easily migrate their designs to the next process Digital Camera generation to realize significant performance advantages while also reducing die size. Audio Players PLL, USB, LVDS, ADC/DAC, HDMI, SATA, Embedded Memory Customers can also leverage application PLL, USB, LVDS, ADC/DAC, Embedded Memory specific IPs that are specialized for all types of mainstream applications such as digital TVs, cellular baseband controllers, digital cameras, and audio players to overcome time-to-market challenges. Fundamental IP Support for SoC Designs UMC offers comprehensive design resources that support our 90nm process technology. Silicon verified fundamental IPs (standard cells, I/Os, and memory compilers) optimized to UMC technologies are available free-of-charge from several leading vendors. Customers can also leverage application specific IPs for DTV, video/audio, etc. IPs available through UMC are DFM (Design for Manufacturing) compliant for better manufacturability. 90nm Library Provider FARADAY Library SP LVT Standard Cells RVT HVT I/O 2.5Vdd 3.3Vdd Single Port SRAM Compiler Dual Port SRAM Compiler Single Port Register File Dual Port Register File ROM Compiler LL VIRAGE SP LL ARM G SP UMC G SP LL G Low Power Features of Standard Cell Library With today's proliferation of low power applications, lowering energy consumption without sacrificing performance has become a critical concern for designers of power management chips for portable electronics. UMC supports its standard cell library with low power design features, including multiple Vt, clock-gating, level shifter and other features to complement UMC’s complete low power solution. Type Operating Power 28nm 40nm 65nm 90nm 0.13um Þ Þ Þ Þ Þ Clock Gated F/F Þ Þ Þ Þ Þ Multi-Vt cells Þ Þ Þ Þ Þ Power Gating Isolation cells, Retention F/F Headers / Footers, etc. Þ Þ Þ Þ Þ Body Bias Tapless cells Þ Þ Þ Þ Þ Voltage Island & Scaling Clock Gating & Frequency Scaling Level Shifters w / Insulator Multi-Vt Leakage Power Support Support Features Power & Timing Model @ 80% of Vdd Timing / Power Model Low Power Design Support Front-end design Multi VDD Multi Vth Low leakage process Power gating Low power synthesis Voltage and frequency scaling Clock gating Body bias 80% 60% 40% Leakage Power Saving 20% Back-end design 20% 40% 60% Dynamic Power Saving 80% UMC Reference Design Flow Product Definition/Spec & Tech-dependent Setting UMC Reference Design Flow provides a design methodology and flow validated with a “Leon2” design. The flow incorporates 3rd-party EDA vendors’ baseline design flows to address issues such as timing closure, signal integrity, leakage power and design for manufacturability and adopts a hierarchical design approach built upon silicon validated process libraries. UMC Reference Design Flow covers from schematic/RTL coding all the way to GDS-II generation and supports Cadence, Magma, Mentor and Synopsys EDA tools. All of these tools have been correlated to UMC silicon and can be interchanged for added I/O & Memory Simulation View RTL Coding & Simulation Timing View Logic Synthesis Timing Constraint & DFT Requirements Static Timing Analysis & Gate-level Simulation Cell Function, Area, Timing & Power View Floorplan & Partition Physical & Noise View Block & Top Implementation DRC/LVS Rule Deck Physical Verification Tape-out flexibility. Reference Design Flow and Vendor Support UMC works with leading EDA tool companies to provide a verified Reference Design Flow program to ensure the accuracy of customer designs in a proven environment. UMC Reference Design Flow program integrates solutions for digital designs and low power solutions that incorporate the latest DFM resources available from leading third-party providers. Tools can be interchanged for added flexibility. Features of Design Flow Cadence Synopsys Mentor Functional Logic Simulation Schematic Entry Springsoft - - - Logic Synthesis - - Static Timing Analysis - - Timing Closure - - Signal Integrity - - Floor Planning - - Physical Synthesis - - Multi-Vt Low Power - - Multi-Vdd Low Power - - Design For Test - - Design Flow and Vendor Support (cont.) Features of Design Flow Cadence Synopsys Mentor Springsoft Design For Diagnosis - DFM - double via insertion - DFM - dummy metal filling - Circuits Simulation - Power Analysis - - - - - Layout Editor Place & Route - Physical Verification - Formal Verification - Parasitic Extraction - Noise Analysis Note: Available for reference design flow - Available for DFM methodology DFM Methodology UMC offers optimal DFM (Design For Manufacturability) solutions to effectively DFM Methodology Roadmap Restricted Rules and efficiently address factors that may negatively affect yield and performance for Statistical Timing Analysis advanced technology designs. UMC’s DFM Critical Area Analysis solutions include advanced process models incorporated in SPICE and extraction decks Modeling with CMP Effects for predicting random and systematic variations, technology files, DFM-compliant Litho Simulation Checks libraries and IP that embrace the intricacies Modeling with LOD & WPE of the fabrication process. Concise DFM recommendation rules are available along with a comprehensive rule-deck Monte Carlo Models runset strategy to fulfill various design Modeling with WEE requirements. UMC also of fers pre-tapeout Optical Proximity Correction (OPC) and Litho Rule DFM Rules 0.13um 90nm 65nm 40nm 28nm Check (LRC) for custom designs in addition to our standard post-tapeout services that include OPC, Litho Simulation Check (LSC), dummy fill, and metal slotting. At 65nm and below, UMC offers a DFM Design Enablement Kit (DEK) to seamlessly support model-based DFM tools. The DEK has a built-in Graphic User Interface (GUI) for DFM design database setup, and is completed with application notes and qualification reports for design reference. High Density Embedded Memory Solution - URAMTM To meet the future SoC trend of smaller form factor, higher bandwidth/speed and lower power consumption, UMC has developed its own high density memory solution, URAM, to fulfill market needs. Building on a logic compatible process, URAM adopts trench architecture as the cell capacitor with no new materials required. This backend-transparent structure also minimizes the backend model impact and ensures seamless integration with existing IPs. The macro implements the Error Correction Code (ECC) repair scheme with a byte-write feature to eliminate the need for redundant laser fuse/efuse and enhance the Soft Error Rate (SER). The wide on-chip bus boosts overall system performance. Pin count can be reduced by eliminating I/O devices, which can also lower the power consumption. This enabling technology for SoC is now in production for both Standard Performance (SP) and Low Leakage (LL) platforms. URAM for Broad Applications Communications Networking, Wireless Graphics & Imaging Systems Frame Buffer for Image Processors Storage Devices Cache Memory UMC e-Fuse Features To reduce chip area, achieve better reliability performance, and shorten repair time compared to conventional Al fuse, UMC has developed an e-fuse solution to target the needs of a broad range of applications. The fuse array and complete functional Logic Compatible •Noextramasks necessary •Onlyoneextrapad required Complete Functional IP Macros •Fusearray, programming circuit, sensing amplifier •Serialandparallel architecture Design-Friendly Features •Allowsmetal routing over fuses (M6 and above) •Programmableat packagelevel Flexibility •Wafer level fuse options •Packagelevel fuse options macro are offered to ease the integration process for customers. Both wafer level and package level fuse are supported. Moreover, customers can use e-fuse for the OTP (one time programming) function to save overall costs. Virtual Inductor Library UMC has worked with its EDA tool partners to deliver the industry's first parameterized inductor design kit based on full-wave simulation: the Virtual Inductor Library (VIL). The VIL enables RFCMOS designers to create and simulate custom inductor geometries that are compatible with UMC's processes. It is built upon UMC's Electromagnetic Design Methodology (EMDM), which allows engineers to easily and accurately create any RF structure. EMDM gives designers the flexibility to innovate new geometries simply by editing parameters such as diameter, number of turns or width. Spiral Differential w/o center tap Differential with center tap The GUI based VIL can be used to simulate all types of RF inductors. Stack Virtual Capacitor Library UMC and its EDA tool partners have delivered the industry's first parameterized MOM capacitor design kit based on fullwave simulation: the Virtual Capacitor Library (VCL). The VCL enables RFCMOS designers to create and simulate custom capacitor geometries that are compatible with UMC's processes. It is built upon UMC's Electromagnetic Design Methodology (EMDM), which allows engineers to easily and accurately create any RF structure. EMDM gives designers the flexibility to innovate new geometries simply by editing parameters such as number of metal and fingers, arrays, and length of fingers for capacitor. The GUI based VCL can be used to simulate all types of RF capacitors. Vi r t ua l Tr a n s f o r m e r Library UMC has also worked with its EDA tool partners to deliver the industry's first parameterized transformer design kit based on full-wave simulation: the Virtual Transformer Library (VTL). The VTL enables RFCMOS designers to create and simulate custom transformer geometries that are compatible with UMC's processes. Without Center Tape CT on primary coil CT on secondary coil CT on both coils It is built upon UMC's Electromagnetic Design Methodology (EMDM), which allows engineers to easily and accurately create any RF structure. EMDM gives designers the flexibility to innovate new geometries simply by editing parameters such as primary impedance, secondary impedance, number of turns, mode, and frequency for transformer. The GUI based VTL can be used to simulate all types of RF transformers. MS/RF Design Flow and FDK The FDK (Foundry Design Kit) provides IC designers with an automatic design Cadence Schematic (Composer) (Symbols & CDF) Virtual Inductor/ Capacitor/Transformer Spec. environment. The methodology provides access to circuit-level design and simulation, Schematic Driven Layout circuit layout, and layout verification with accurate RF device models. In the frontend, fundamental components of UMC's Circuit Layout Virtuoso(P-cell) MS/RF process are implemented in common cells (P Cell), which include a schematic Virtual Inductor/ Capacitor/Transformer Library Spectre / Spectre RF Artist Spectre / Spectre RF design environments and simulation tools. The back-end includes parameterized Virtual Inductor/ Capacitor/Transformer Library Verification & Extraction (DRC/LVS/LPE) driven layout to provide an automatic and Calibre/XRC Spectre / Spectre RF Simulation with Verified RF/Mixed Signal Models Assura complete design flow. Callback functions are also provided in the design flow to minimize data entry. EDA tools for MS/RF Tape Out designs are also supported. Optimum Inductor Finder (OIF) UMC offers the Optimum Inductor Finder (OIF) in the FDK package. The OIF gives designers the ability to quickly access a large library of inductors calibrated to UMC's silicon. It also allows users to perform inductor optimization through just a few simple steps with the user-friendly interface. For instance, customers can define a desired inductor and make trade-offs between Q-factor and area. The OIF will select a design that best fits the specifications in a matter of seconds. Optimum Capacitor Finder (OCF) UMC offers the Optimum Capacitor Finder (OCF) in the FDK package. The OCF gives designers the ability to quickly access a large library of capacitors calibrated to UMC's silicon. It also allows users to perform capacitor optimization through just a few simple steps with the user-friendly interface. For instance, customers can define a desired capacitor and make trade-offs between Q-factor and area. The OCF will select a design that best fits the specifications in a matter of seconds. Optimum Transformer Finder (OTF) UMC offers the Optimum Transformer Finder (OTF) in the FDK package. The OTF gives designers the ability to quickly access a large library of transformers calibrated to UMC's silicon. It also allows users to perform transformer optimization through just a few simple steps with the user-friendly interface. For instance, customers can define a desired transformer and make trade-offs between impedance and area. The OTF will select a design that best fits the specifications in a matter of seconds. Analog Design Methodology FDK EDA Supported Tools MS/RF Design Flow Cadence Schematic Entry Composer ADS Spectre SpectreRF GoldenGate Pre-simulation Hspice/Spectre Models Physical Design Virtuoso XL Physical Verification (DRC/LVS/RCX) Assura QRC Note: *is available by request MEMO: Mentor ADS Synopsys SpringSoft Laker ADP* HSPICE Laker L3* Calibre Calibre XRC Hercules Star RCXT www.umc.com F O U N D R Y New Customers For new customer inquiries, please direct all questions to [email protected] Worldwide Contacts Headquarters: UMC No. 3, Li-Hsin 2nd Road, Hsinchu Science Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-578-2258 Fax: 886-3-577-9392 Email: [email protected] L E A D E R S H I P F O R In China: UMC Beijing: Room #512, 5F, South Block, Raycom InfoTech Park, No.2, Kexueyuan South Road, Zhongguancun, Haidian District, Beijing 100190, China Tel: 86-10-59822250 86-18913138053 Fax: 86-10-59822588 HeJian Technology (Suzhou): No. 333, Xinghua Street, Suzhou Industrial Park, Suzhou, Jiangsu Province 215025, China Tel: 86-512-65931299 Fax: 86-512-62530172 T H E S o C G E N E R A T I O N In Japan: UMC Group Japan 15F Akihabara Centerplace Bldg., 1 Kanda Aioi-Cho Chiyoda-Ku Tokyo 101-0029 Japan Tel : 81-3-5294-2701 Fax: 81-3-5294-2707 In Singapore: UMC-SG No. 3, Pasir Ris Drive 12, Singapore 519528 Tel: 65-6213-0018 Fax: 65-6213-0005 In North America: UMC USA 488 De Guigne Drive, Sunnyvale, CA 94085, USA Tel: 1-408-523-7800 Fax: 1-408-733-8090 In Europe: UMC Europe BV De entree 77 1101 BH Amsterdam Zuidoost The Netherlands Tel: 31-(0)20-5640950 Fax: 31-(0)20-6977826 In Korea: UMC Korea 1117, Hanshin Intervally24, 322, Teheran-ro, Gangnam-gu, Seoul, Korea Tel: 82-2-2183-1790 Fax: 82-2-2183-1794 Email:[email protected] For more information: visit www.umc.com or e-mail [email protected] 1409