IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in SOIC, SSOP, and TSSOP packages This quadruple 2-input positive-AND gate is built using advanced dual metal CMOS technology. The ALVC08 performs the Boolean function Y = A • B or Y = A + B in positive logic. The ALVC08 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. DRIVE FEATURES: APPLICATIONS: FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION • High Output Drivers: ±24mA • Suitable for Heavy Loads • 3.3V high speed systems • 3.3V and lower voltage computing systems A 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y Y B SOIC/ SSOP/ TSSOP TOP VIEW PIN DESCRIPTION Pin Names FUNCTION TABLE (EACH GATE)(1) Inputs Description Output xA, xB Data Inputs xA xB xY xY Data Outputs H H H L X L X L L NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2000 1 ©2000 Integrated Device Technology, Inc. DSC-4633/1 IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE ABSOLUTE MAXIMUM RATINGS(1) Symbol Description INDUSTRIAL TEMPERATURE RANGE CAPACITANCE (TA = +25°C, F = 1.0MHz) Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC ±50 mA IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA Parameter(1) Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF NOTE: 1. As applicable to the device type. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit 1.7 — — V VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 2 — — VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 10 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2 IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit VCC – 0.2 — V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol CPD Parameter Power Dissipation Capacitance per Gate VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 25 26 pF VCC = 2.5V ± 0.2V VCC = 2.7V SWITCHING CHARACTERISTICS(1) Symbol Parameter tPLH Propagation Delay tPHL xA or xB to xY NOTE: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 3 VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 1 3.2 1.2 3.4 1.2 3.3 ns IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) VIN GND tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω Test Circuit for All Outputs tPHZ VOH VOH - VHZ 0V VT 0V Enable and Disable Times DATA INPUT SWITCH POSITION Test Switch TIMING INPUT Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V tH tREM tSU tH ALVC Quad Link VIH VT 0V tPHL1 Set-up, Hold, and Release Times VOH VT VOL tSK (x) LOW-HIGH-LOW PULSE OUTPUT 2 VT tW VOH VT VOL tPLH2 VLOAD/2 VOL + VLZ VOL ALVC Quad Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. tSK (x) tPLZ VLOAD/2 VT VIH VT 0V NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. OUTPUT 1 DISABLE ENABLE CL tPLH1 VIH VT 0V CONTROL INPUT ALVC Quad Link INPUT tPHL ALVC Quad Link D.U.T. RT tPLH Propagation Delay VOUT Pulse Generator tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION HIGH-LOW-HIGH PULSE VT ALVC Quad Link tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Pulse Width ALVC Quad Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 4 IDT74ALVC08 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX XXX XX ALVC Package Device Type Temp. Range CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 DC PY PG Small Outline IC Shrink Small Outline Package Thin Shrink Small Outline Package 08 Quadruple 2-Input Positive-AND Gate, ±24mA 74 – 40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 5 for Tech Support: [email protected] (408) 654-6459