POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation PHASE CONTROL THYRISTOR POSEICO SPA Via N. Lorenzi 8, 16152 Genova - ITALY Tel. +39 010 6556234 - Fax +39 010 6557519 Sales Office: Tel. +39 010 6556775 - Fax +39 010 6442510 AT620 Repetitive voltage up to Mean on-state current Surge current 1400 V 2100 A 36 kA TARGET SPECIFICATION mar 03 - ISSUE : 1 Symbol Characteristic Conditions Tj [°C] Value Unit BLOCKING V RRM Repetitive peak reverse voltage 125 1400 V V RSM Non-repetitive peak reverse voltage 125 1500 V V DRM Repetitive peak off-state voltage 125 1400 V I RRM Repetitive peak reverse current V=VRRM 125 100 mA I DRM Repetitive peak off-state current V=VDRM 125 100 mA A CONDUCTING I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 2100 I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled 1805 A I TSM Surge on-state current sine wave, 10 ms 36 kA 125 I² t I² t without reverse voltage V T On-state voltage On-state current = V T(TO) Threshold voltage 125 0.81 T On-state slope resistance 125 0.150 mohm From 75% VDRM up to 2200 A, gate 10V 5ohm 125 200 A/µs V/µs r 2900 A 6480 x1E3 25 1.3 A²s V V SWITCHING di/dt Critical rate of rise of on-state current, min. dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 500 td Gate controlled delay time, typical VD=100V, gate source 25V, 10 ohm , tr=.5 µs 25 3 tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM Q rr Reverse recovery charge di/dt=-20 A/µs, I= 1430 A µs 250 µs 125 µC I rr Peak reverse recovery current VR= 50 V I H Holding current, typical VD=5V, gate open circuit 25 300 mA A I L Latching current, typical VD=5V, tp=30µs 25 700 mA GATE V GT Gate trigger voltage VD=5V 25 3.5 V I GT Gate trigger current VD=5V 25 300 mA VD=VDRM 125 V GD Non-trigger gate voltage, min. 0.25 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) P GM Peak gate power dissipation P G Average gate power dissipation R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled R th(c-h) Thermal impedance Case to heatsink, double side cooled T F j Operating junction temperature Mounting force Mass Pulse width 100 µs 5 V 150 W 2 W 21 °C/kW MOUNTING VDRM&VRRM/100 °C/kW 125 24.5 520 ORDERING INFORMATION : AT620 S 14 standard specification 6 -30 / 22.0 / °C kN g AT620 PHASE CONTROL THYRISTOR TARGET SPECIFICATION POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation mar 03 - ISSUE : 1 SURGE CHARACTERISTIC Tj = 125 °C 7000 40 6000 35 5000 30 25 4000 ITSM [kA] On-state Current [A] ON-STATE CHARACTERISTIC Tj = 125 °C 3000 20 15 2000 10 1000 5 0 0.6 1.1 0 1.6 1 On-state Voltage [V] 10 n° cycles TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 25.0 Zth j-h [°C/kW] 20.0 15.0 10.0 5.0 0.0 0.001 0.01 0.1 1 t[s] 10 100 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement ANSALDO reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 100