POSEICO SPA Via Pillea 42-44, 16153 Genova - ITALY Tel. + 39 010 8599400 - Fax + 39 010 8682006 Sales Office: Tel. + 39 010 8599400 - Fax + 39 010 8681180 POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation PHASE CONTROL THYRISTOR AT681 Repetitive voltage up to Mean on-state current Surge current 6000 V 840 A 10 kA FINAL SPECIFICATION mag 06 - ISSUE : 03 Symbol Characteristic Tj [°C] Conditions Value Unit BLOCKING V RRM Repetitive peak reverse voltage 120 6000 V V RSM Non-repetitive peak reverse voltage 120 6100 V V DRM Repetitive peak off-state voltage 120 6000 V I RRM Repetitive peak reverse current V=VRRM 120 150 mA I DRM Repetitive peak off-state current V=VDRM 120 150 mA CONDUCTING I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, dou ble side cooled 840 A I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, dou ble side cooled 705 A I TSM Surge on-state current sine wave, 10 ms 10 kA 120 I² t I² t without reverse voltage V T On-state voltage On-state current = V T(TO) Threshold voltage 120 1,30 V T On-state slope resistance 120 1,150 mohm r 1570 A 500 x1E3 25 2,4 A²s V SWITCHING di/dt Critical rate of rise of on-state current From 75% VDRM up to 1200 A 120 100 A/µs dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 75% of VDRM 120 500 V/µs td Gate controlled delay time, typical VD=200V, gate source 20V, 10 ohm 25 5 µs tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 80% VDRM 650 µs Q rr Reverse recovery charge di/dt=-60 A/µs, I= 1000 A I rr Peak reverse recovery current VR= 50 V 120 µC I H Holding current, typical 25 300 mA I L Latching current, typical 25 700 mA 25 3,5 V mA A GATE V GT Gate trigger voltage I GT Gate trigger current VD=5V 25 400 V GD Non-trigger gate voltage, min. 0.5 VDRM 120 0,5 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) P GM Peak gate power dissipation P G Average gate power dissipation R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled R th(c-h) Thermal impedance Case to heatsink, double side cooled T F j Operating junction temperature Mounting force Mass Pulse width 100 µs 5 V 150 W 2 W MOUNTING ORDERING INFORMATION : AT681 S 60 standard specification VDRM&VRRM/100 21 °C/kW 6 °C/kW 120 22.0 / 24,5 520 °C kN g AT681 PHASE CONTROL THYRISTOR FINAL SPECIFICATION POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation mag 06 - ISSUE : 03 SURGE CHARACTERISTIC Tj = 120 °C 3000 12 2500 10 2000 8 ITSM [kA] On-state Current [A] ON-STATE CHARACTERISTIC Tj = 120 °C 1500 6 1000 4 500 2 0 0 0,6 1,1 1,6 2,1 2,6 3,1 3,6 4,1 1 On-state Voltage [V] 10 n°cycles TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 25,0 Zth j-h [°C/kW] 20,0 15,0 10,0 5,0 0,0 0,001 0,01 0,1 1 t[s] 10 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement POSEICO SpA reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 100