APA6003 15W Stereo Class D Audio Power Amplifier Features • • General Description Supply Voltage is 4.5V ~ 24V The APA6003 is a stereo, high efficiency, Class-D audio Class D operation eliminates heat sink & reduce power supply requirement amplifier available in TSSOP-28P and QFN4x4-28 pins packages. 20,26, 32, 36, 4 steps gain setting 15W/ch into an 8Ω Loads at 10% THD+N from a The Class-D power amplifier has higher efficiency comparing to the tradition Class-AB power amplifier. The fil- • 16-V supply 10W/ch into 8Ω Loads at 10% THD+N from a 12-V ter free Class-D architecture eliminates the external low pass filters. The internal gain setting can minimum the • supply 30W into a 4Ω Mono Load at 10% THD+N from a external component counts, and for the flexible application the gain can be set to 4-step 20, 26, 32, 36dB by gain • 16-V Supply 90% Efficient Class-D Operation Eliminates Need control pins (GAIN0 and GAIN1). The AGC function protects speaker from being out of its power rating but keeps for Heat Sinks External AGC function acceptable performance. The integration of Class-D power amplifier is a best so- Adjustable switch frequency Flow Through Pin Out Facilitates Easy Board Lay- lution for power efficiency and lower the total BOM costs. The operating voltage is from 4.5V to 24V. The APA6003 out Robust Pin-to-Pin Short Circuit Protection and Ther- power amplifiers are capable of driving 15 W at VDD=16V into 8Ω speaker, and provides thermal and over-current mal Protection with Auto Recovery Option Excellent THD+N / Pop-Free Performance protections also can detection the DC that prevent to destroy the speaker voice coil. • • • • • • • • • • • Thermal and Over-Current Protections with AutoRecovery option Applications Dual Differential Inputs with MUX TSSOP-28P with thermal pad packages • • QFN4x4-28B with thermal pad packages LCD Monitor Consumer Audio Equipment Simplified Application Circuit APA6003 LINNA Left Channel Input LOUTP LINN LINP FERRITE BEAD FILTER Left Channel Speaker FERRITE BEAD FILTER Right Channel Speaker LOUTN LINPA RINNA Right Channel Input ROUTN RINN RINP ROUTP RINPA ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 1 www.anpec.com.tw APA6003 VCLAMP 9 22 LBSN SD 3 21 RBSN FLAG 4 20 ROUTN LINPA 5 LINNA 6 AGC 10 19 ROUTP RINN 11 18 RBSP RINP 12 17 RPVDD RINNA 13 16 MONO RINPA 14 15 SEL 22 ROUTP 23 ROUTN 24 RBSN 25 PGND 20 RPVDD 19 MONO APA6003 QFN4x4-28B 18 SEL 17 RINPA 16 RINNA 15 RINP LINP 7 RINN 14 AGND 8 APA6003 TSSOP-28P 23 LOUTN 21 RBSP AGC 13 AVDD 7 LBSP 1 LPVDD 2 VCLAMP 12 GAIN1 6 24 LOUTP LINN 8 GAIN0 5 26 LBSN 25 LBSP AVDD 11 26 LPVDD LINN 4 27 LOUTN 27 SD LINP 3 GAIN1 10 28 FLAG GAIN0 9 LINPA 1 LINNA 2 28 LOUTP Pin Configuration Ordering and Marking Information Package Code R: TSSOP-28P QA: QFN4x4-28B Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA6003 Assembly Material Handling Code Temperature Range Package Code APA6003 R: APA6003 QA: APA6003 XXXXX XXXXX - Date Code APA6003 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 2 www.anpec.com.tw APA6003 Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol VDD Parameter Rating Supply Voltage -0.3 to 30 Input Voltage (/SD, GAIN0 and GAIN1, MONO and /FLAG) VI TJ -0.3 to VDD+0.3 AGC -0.3 to 6.3 LINP, LINN, RINP, RINN -0.3 to 6.3 Maximum Junction Temperature Storage Temperature Range T SDR Maximum Soldering Temperature Range, 10 seconds 260 PVDD > 15V 4.8 PVDD ? 15V 3.2 ο -65 to +150 MONO mode PD V 150 TSTG RL Unit C Ω 3.2 Power Dissipation Internally Limited W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Typical Value Unit Thermal Resistance -Junction to Ambient(Not e 2) θ JA θ JC TSSOP-28P QFN4x4-28B 45 40 TSSOP-28P QFN4x4-28B 8 7 ο C /W Thermal Resistance -Junction to Case(Note 3) Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TSSOP-28P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TSSOP-28P package. Recommended Operating Conditions Symbol Parameter V DD Supply Voltage VIH High Level Threshold Voltage VIL Low Level Threshold Voltage TA Ambient Temperature Range Min. Max. 4.5 24 SD 2.2 - GAIN0, GAIN1, MONO V 2.0 - SD - 0.8 GAIN0, GAIN1, MONO - 0.8 -40 85 o o TJ Junction Temperature Range -40 125 RL Speaker Resistance 3.5 - Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 Unit 3 C C Ω www.anpec.com.tw APA6003 Electrical Characteristics VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted). Symbol Parameter APA6003 Test Condition Unit Min. Typ. Max. 4.5 5 5.5 V VAGC=1V, AV=20dB - 5.5 - Vp VRINP=5V,VRINN=0V - 500 - ms /SD=2.2V - 20 - ms ο VCLAMP IO=2mA,VDD=6~22V,TJ=-40 C ~125 οC Regulated voltage t DCDET Maximum Output Voltage Under AGC Control DCP detect time TSD(ON) Shutdown Turn-On Time T SD(OFF) VO Shutdown Turn-Off Time /SD=0.8V - 2 - μs IDD Quiescent Supply Current No Load - 17 35 mA I SD Quiescent Supply Current in shutdown mode /SD = 0V - 180 250 μA Input Current /SD, GAIN0, GAIN1, MONO=12V - 23 50 μA - 300 - kHz IL=0.5A - 200 - mΩ Gain0=0, Gain1=0 - 20 - Gain0=1, Gain1=0 - 26 - Gain0=0, Gain1=1 - 32 - Gain0=1, Gain1=1 - 36 - Min. Typ. Max. - 14 - - 17 - - 0.05 - - -90 - II F OSC R DSON AV Internal Oscillator Frequency Static Drain-Source On-State Resistance Gain dB Stereo Mode VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted). Symbol Parameter Test Conditions APA6003 Unit V DD=19V, TA=25°C, AV=20dB Po THD+N Crosstalk PSRR SNR Att shutdown |VOS| Vn Total Harmonic Distortion Pulse Noise Channel separation VDD=16V R L = 8Ω THD+N = 1%, F IN = 1KHz, VDD=16V R L = 8Ω THD+N = 10%, FI N = 1kHz VDD=16V FIN = 1kHz, PO= 7.5W , R L = 8Ω VO=1Vrms, FIN = 1kHz, AV=20dB Power Supply Rejection Ratio R L=4Ω,input AC-Ground, FIN =1kHz - -70 - Signal-to-noise ratio Maximum output at THD+N<1%, FIN=1kHz, AV=20dB, A-weighted - 90 - Shutdown Attenuation FIN = 1kHz, RL = 8Ω, Vin= 1VPP - -100 - Offset Voltage AV=20dB - 10 - mV Noise Output Voltage With A-weighted Filter (AV=20dB) - 170 - µV (rms) Output Power Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 4 W % dB www.anpec.com.tw APA6003 Stereo Mode VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted). Symbol Parameter APA6003 Test Conditions Min. Typ. Max. RL = 4 - 28 - RL = 4 - 35 - - 0.05 - Unit V DD=12V, TA=25°C Po THD+N PSRR SNR Att shutdown |VOS| Vn Output Power Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio Signal-to-noise ratio VDD=16 THD+N = 1%, F IN = 1KHz VDD=16 THD+N = 10%, FI N = 1kHz, VDD=16 FIN = 1kHz, PO= 6, RL = 4Ω W % R L=4Ω,input AC-Ground,F IN=1kHz - -50 - Maximum output at THD+N<1%, FIN=1kHz, AV=20dB, A-weighted - 90 - dB Shutdown Attenuation FIN = 1kHz, RL = 8Ω, Vin= 1Vrms - -100 - Offset Voltage AV=20dB - 15 - mV Noise Output Voltage Input AC ground, With A-weighted Filter (AV=20dB) - 150 - µV (rms) Min. APA6003 Typ. Max. - 8 - - 9.5 - - 0.05 - Mono Mode VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted). VDD=12V,TA=25°C Symbol Po THD+N Crosstalk PSRR SNR Attshutdown |VOS| Vn Parameter Test Condition Total Harmonic Distortion Pulse Noise VDD=16V RL = 8 THD+N = 1%, F IN = 1KHz VDD=16V RL = 8 THD+N = 10%, FIN = 1KHz VDD=16V FIN = 1kHz, PO= 6W, R L = 4Ω Channel separation VO=1Vrms, FIN = 1kHz, AV=20dB - -90 - Power Supply Rejection Ratio RL =4Ω,input AC-Ground,FIN=1kHz - -70 - Output Power Unit W % dB - 90 - Shutdown Attenuation Maximum output at THD+N<1%, FIN=1kHz, AV=20dB, A-weighted FIN = 1kHz, RL = 8Ω, Vin = 1Vrms - -100 - Offset Voltage Vin = 0V, AV=20dB - 10 - mV Noise Output Voltage Input AC ground, With A-weighted Filter (AV=20dB) - 170 - µV (rms) Signal-to-noise ratio Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 5 www.anpec.com.tw APA6003 Pin Description Pin NO. Name I/O/P FUNCTION 1 QFN4x4-28 B 5 LINPA I Positive audio input for left channel. 2 6 LINNA I Negative audio input for left channel. 3 7 LINP I Positive audio input for left channel. 4 8 LINN I Negative audio input for left channel. 5 9 GAIN0 I 6 10 GAIN1 I 7 11 AVDD P Gain select least significant bit. TTL logic levels with compliance to AVDD. Gain select least significant bit. TTL logic levels with compliance to AVDD. Analog supply. TSSOP-28P 8 - AGND P Analog signal ground. Connect to the thermal pad. 9 12 VCLAMP I 10 13 AGC I Regulated voltage, Nominal voltage is 5V. AGC level adjust. Connect a resistor divider from VCLAMP to GND to set AGC. Connect directly to VCLAMP for no AGC. 11 14 RINN I Negative audio input for right channel. 12 15 RINP I Positive audio input for right channel. 13 16 RINNA I Negative audio input for right channel. 14 17 RINPA I 15 18 SEL I Positive audio input for right channel. Dual Differential Inputs control, SEL to low: INN / INP input, SEL to high : INNA / INNP input 16 19 MONO I 17 20 RPVDD P 18 21 RBSP I Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally. Bootstrap I/O for right channel, positive high-side FET. 19 22 ROUTP O Class-D H-bridge positive output for right channel. 20 23 ROUTN O Class-D H-bridge negative output for right channel. 21 24 RBSN I Bootstrap I/O for right channel, negative high-side FET. 22 26 LBSN I Bootstrap I/O for left channel, negative high-side FET. 23 27 LOUTN O Class-D H-bridge negative output for left channel. 24 28 LOUTP O Class-D H-bridge positive output for left channel. 25 1 LBSP I Bootstrap I/O for left channel, positive high-side FET. 26 2 LPVDD P 27 3 /SD I 28 4 /FLAG O 29(Thermal Pad) 25 29(Thermal Pad) PGND P Power ground for the H-bridges. GND P Power ground for the H-bridges. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 Parallel BTL mode switch Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally. Shutdown logic input for audio amp (Low=outputs disabled, High=output enabled). . TTL logic levels with compliance to AVDD. Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVDD. Short circuit faults can be set to auto-recovery by connecting /FLAG pin to /SD pin. 6 www.anpec.com.tw APA6003 Block Diagram LBSP VCLAMP LPVDD LPVDD LOUTP FB SEL Control AGC Control MONO Select LOUTP FB Gate Drive LINPA LOUTP LINP PWM Logic Gain Control PGND VCLAMP LPVDD LINN LBSN LPVDD LOUTN FB LINNA AGC Control Gate Drive LOUTN FB LOUTN FLAG Biases and References SD TTL Buffer GAIN0 GAIN Control GAIN1 RAMP GEN. AGC Reference AGC PGND SD Detect DC Detect LPVDD Thermal Detect RPVDD Startup Protection Logic UVLO/OCL O RBSP VCLAMP AVDD LDO Regulator VCLAMP RPVDD VCLAMP AGC Control RPVDD ROUTP FB Gate Drive RINNA ROUTN ROUTN FB RINN PWM Logic Gain Control PGND VCLAMP RPVDD RBSN RPVDD RINP RINPA SEL Control AGC Control ROUTN FB MONO Select Gate Drive ROUTP ROUTP FB MONO TTL Buffer MONO Select PGND AGND SEL SEL Control Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 7 www.anpec.com.tw APA6003 Typical Application Circuit V DD 100µF 0.1µF 1nF 100kΩ (Recommmanded) 1µF Left Channel Input Signal Left Channel Input Signal 1µF LINPA 1 28 FLAG LINNA 2 27 SD 26 LPVDD 25 LBSP LINP 3 1µF LINN 4 GAIN0 5 1µF Gain Setting 1µF GAIN1 6 23 LOUTN AVDD 7 22 LBSN AGND 8 1µF 10kΩ 10kΩ Right Channel Input Signal Right Channel Input Signal APA6003 VCLAMP 9 1µF 1µF 1µF 1µF 1000 pF 0.22µF 21 RBSN BEAD 18 RBSP RINN 11 1000 pF BEAD 20 ROUTN 19 ROUTP AGC 10 1µF BEAD 0.22µF 24 LOUTP 0.22µF 1000pF BEAD 1000 pF 0.22µF RINP 12 RINNA 13 17 RPVDD RINPA 14 15 SEL 16 MONO Dual Differential Inputs Control 29 GND 100µF 0.1µF 1nF VDD Stereo V DD 100µF 0.1µF 1nF 100kΩ (Recommmanded) LINPA 1 28 FLAG LINNA 2 27 SD 26 LPVDD 25 LBSP LINP 3 LINN 4 GAIN0 5 Gain Setting 23 LOUTN AVDD 7 22 LBSN 1µF AGND 8 1µF 24 LOUTP GAIN1 6 APA6003 VCLAMP 9 Right Channel Input Signal Right Channel Input Signal 1µF 1µF 1µF BEAD 1000 pF 21 RBSN BEAD 20 ROUTN 19 ROUTP AGC 10 RINP 12 RINNA 13 17 RPVDD RINPA 14 15 SEL 1000 pF 0.47µF 18 RBSP RINN 11 1µF 0.47µF 16 MONO Dual Differential Inputs Control 29 GND 100µF 0.1µF 1nF VDD MONO Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 8 www.anpec.com.tw APA6003 AGC Gain Table VDD=12V, VGND=0V, TA=25OC, No Load Gain=20dB Gain=26dB Gain=32dB Gain=36dB dB dB dB dB 1 20.15 26.15 32.15 36.15 2 19.65 25.65 31.65 35.65 3 19.15 25.15 31.15 35.15 4 18.65 24.65 30.65 34.65 5 18.15 24.15 30.15 34.15 6 17.65 23.65 29.65 33.65 7 17.15 23.15 29.15 33.15 8 16.65 22.65 28.65 32.65 9 16.15 22.15 28.15 32.15 10 15.65 21.65 27.65 31.65 11 15.15 21.15 27.15 31.15 12 14.65 20.65 26.65 30.65 13 14.15 20.15 26.15 30.15 14 13.65 19.65 25.65 29.65 15 13.15 19.15 25.15 29.15 16 12.65 18.65 24.65 28.65 17 12.15 18.15 24.15 28.15 18 11.65 17.65 23.65 27.65 19 11.15 17.15 23.15 27.15 20 10.65 16.65 22.65 26.65 21 10.15 16.15 22.15 26.15 22 9.65 15.65 21.65 25.65 23 9.15 15.15 21.15 25.15 24 8.65 14.65 20.65 24.65 Step Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 9 www.anpec.com.tw APA6003 AGC Gain Table VDD=12V, VGND=0V, TA=25OC, No Load Gain=20dB Gain=26dB Gain=32dB Gain=36dB dB dB dB dB 25 8.15 14.15 20.15 24.15 26 7.15 13.15 19.15 23.15 27 6.15 12.15 18.15 22.15 28 5.15 11.15 17.15 21.15 29 4.15 10.15 16.15 20.15 30 3.15 9.15 15.15 19.15 31 2.15 8.15 14.15 18.15 32 0.15 6.15 12.15 16.15 Step Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 10 www.anpec.com.tw APA6003 Function Description Class-D Operation reducing the switching current, which reduces any I2R losses in the load. Output = 0 Gain Setting Operation VOUTP VOUTN VOUT (VOUTP-VOUTN) Gain1 Gain0 Gain Input Impedance 0 0 20 60kΩ 0 1 26 30kΩ 1 0 32 15kΩ 1 1 36 9kΩ Table 1 : The Gain Setting The APA6003’s gain can be set by GAIN0, GAIN1. The detail gain setting value is list at table 1. IOUT Output > 0 Shutdown Operation VOUTP In order to reduce power consumption while not in use, the APA6003 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature VOUTN turns the amplifier off when logic low is placed on the SD pin for APA6003. The trigger point between a logic high VOUT (VOUTP-VOUTN) and logic low level is typically 2.2V. It is best to switch between ground and the supply voltage VDD to provide maximum device performance. By switching the SD pin to low level, the amplifier enters a low-consumption- cur- IOUT Output < 0 rent state, IDD for APA6003 is in shutdown mode. On normal operating, APA6003’s SD pin should pull to high VOUTP level to keeping the IC out of the shutdown mode. The SD pin should be tied to a definite voltage to avoid unwanted VOUTN state changes. VOUT (VOUTP-VOUTN) AGC Function Operation The APA6003 provides the non-clipping Control, When the output reaches the maximum power setting value, IOUT the internal Programmable Gain Amplifier (PGA) will decrease the gain for prevent the output waveform clipping. Figure1. The APA6003 Output Waveform The APA6003 uses a modulation scheme that allows op- Using the AGC pin to set the non-clipping function and limit the output power. eration without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switch- VP=5.6 x AGC voltage if AGC<2.5V ing from 0 volts to the supply voltage. The VOUTP and VOUTN are in phase with each other with no input so that there is VCLAMP Supply little or no current in the speaker. The duty cycle of VOUTP is greater than 50% and VOUTN is less than 50% for positive The VCLAMP is used to power the gates of the output full bridge transistors. It can also be used to supply the AGC voltage divider circuit. Add a 1µF capacitor to ground at output voltages. The duty cycle of VOUTP is less than 50% and VOUTN is greater than 50% for negative output voltages. this pin. The voltage across the load sits at 0V throughout most of the switching period, Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 11 www.anpec.com.tw APA6003 Function Description (Cont.) Thermal Protection Thermal protection on the APA6003 prevents damage to the device when the internal die temperature exceeds Stereo/mono switching Operation APA6003 offers the feature of Stereo operation with two outputs of each channel connected directly. If the MONO pin (pin 14) is tied high, the positive and negative outputs 150oC. There is a +15oC tolerance on this trip point from device to device. Once the die temperature exceeds the of each channel (left and right) are synchronized and in phase. To operate in this mono mode, apply the input thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched signal to the RIGHT input and place the speaker between the LEFT and RIGHT outputs. Connect the positive and fault. The thermal fault is cleared once the temperature of the die is reduced by 15 oC. The device begins normal negative output together for best efficiency. Mono mode can increase more output power compare to operation at this point with no external system interaction. Thermal protection faults are NOT reported on the FLAG the stereo mode single channel’s output power. terminal. DC Detect When a DC signal applies to the input of APA6003 and the time excesses 500ms, the APA2621’s DC detect fault will be reported on the FLAG pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVDD supply. Cycling SD will NOT clear a DC detect fault. A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 12% for more than 500 msec at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults. Over-Circuit Protection APA6003 has protection from over-current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FLAG pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state. Connect FLAG to SD pin, the over current protection will be auto recovery. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 12 www.anpec.com.tw APA6003 Application Information Input Resistance, Ri Power-Supply Decoupling Capacitor, CS Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the The APA6003 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents frequency may change when changing gain steps. the oscillations being caused by long lead length between the amplifier and the speaker. The optimum Input Capacitor, Ci decoupling is achieved by using two different types of capacitors that target on different types of noise on the In the typical application, an input capacitor Ci is required to allow the amplifier to bias the input signal to the proper power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent- dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (RI) form a high-pass series-resistance (ESR) ceramic capacitor, typically 0. 1µF placed as close as possible to the device AVDD pin filter with the corner frequency determined in Equation 1. fC(hipass ) = 1 2πRiCi (1) and 1µF placed to the LPVDD and RPVDD leads for works best. For filtering lower frequency noise signals, a large The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the aluminum electrolytic capacitor of 220µF or greater placed near the audio power amplifier is recommended. example where RI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 1 is Output Low-Pass Filter If the traces form APA6003 to speaker are short, it doesn’t require output filter for FCC & CE standard. reconfigured as Equation 2. Ci = 1 2πRi fc (2) A ferrite bead may need if it’s failing the test for FCC or CE tested without the LC filter. The figure 2 is the sample for In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 µF as this value is commonly used. If the added ferrite bead; the ferrite show choosing high impedance in high frequency. gain is known and is constant, use R I from Table 1 to calculate CI. A further consideration for this capacitor is the leakage path from the input source through the input network CI and the feedback network to the load. This Ferrite OUTP Bead leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially 1nF in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When Ferrite OUTN Bead polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applica- 4Ω 1nF tions as the dc level there is held at V /2, which is CLAMP likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset volt- Figure 3. Ferrite Bead Output Filter ages and it is important to ensure that boards are cleaned properly. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 13 www.anpec.com.tw APA6003 Application Information (Cont.) During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to Output Low-Pass Filter (cont.) Figure 4 and Figure 5 are examples for added the LC keep the high-side MOSFETs turned on. filter (Butterworth), it’s recommended for the situation that the trace form amplifier to speaker is too long, and needs Layout Recommendation to eliminate the radiated emission or EMI. OUTP The APA6003 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed 33µH circuit board. The following suggestions will help to meet EMC requirements. 1µF OUTN 33µH 1. The high frequency decoupling capacitors should be placed as close to the PVDD and AVDD terminals as 8Ω 1µF possible. Large (100µF or greater) bulk power supply decoupling capacitors should be placed near the APA6003 on the LPVDD and RPVDD supplies. Local, highfrequency bypass capacitors should be placed as close Figure 4. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8Ω to the PVDD pins as possible. These caps can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 1000pF and 10nF and a OUTP larger mid-frequency cap of value between 0.1µF and 1µF also of good quality to the PVDD connections at each 15µH 2.2µF OUTN 15µH end of the chip. 2. Keep the current loop from each of the outputs through 4Ω the ferrite bead and the small filter cap and back to PGND as small and tight as possible. The size of this current 2.2µF loop determines its effectiveness as an antenna. 3. Grounding - The AVDD (pin 7) decoupling capacitor Figure 5. Typical LC Output Filter, Cutoff Frequency of should be grounded to analog ground (AGND). The PVDD decoupling capacitors should connect to PGND. Analog 27 kHz, Speaker Impedance = 4Ω ground and power ground should be connected at the thermal pad, which should be used as a central ground BSN and BSP Capactiors The full H-bridge output stages use only NMOS connection or star ground for the APA6003. 4. Output filter - The ferrite EMI filter (Figure 3) should be transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 0. placed as close to the output terminals as possible for the best EMI performance. The LC filter (Figure 4 and 22µF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding boot- Figure 5) should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be strap input. Specifically, one 0.22µF capacitor must be connected from OUTP to BSP, and one 0.22µF capacitor grounded to power ground. must be connected from OUTN to BSN. The bootstrap capacitors connected between the BSP or BSN pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 14 www.anpec.com.tw APA6003 Application Information (Cont.) Layout Recommendation (cont.) 5. Thermal Pad - The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35mm. Seven rows of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. 2.0mm 0.3mm 3.0mm 0.65mm 6mm Via diameter = 0.3mm x 8 6.4mm TSSOP-28P Land Pattern Recommendation 1.5mm 2.7mm 0.25mm 0.4mm Via diameter = 0.3mm x 9 0.3mm QFN4x4-28B Land Pattern Recommendation Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 15 www.anpec.com.tw APA6003 Package Information TSSOP-28P D SEE VIEW A E2 EXPOS ED PAD E1 E D1 c 0.25 b S Y M B O L VIEW A L GAUGE PLANE SEATING PLANE 0 A1 A2 A e TSSOP-28P MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 9.60 9.80 0.378 0.386 D1 4.50 6.00 0.177 0.236 E 6.20 6.60 0.244 0.260 E1 4.30 4.50 0.169 0.177 E2 2.50 3.50 0.098 0.138 e 0.65 BSC L 0.45 0 0o 0.026 BSC 0.75 0.018 8o 0o 0.030 8o Note : 1. Followed from JEDEC MO-153 AET. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 16 www.anpec.com.tw APA6003 Package Information QFN4x4-28B D b E A Pin 1 A1 D2 A3 NX aaa c L K E2 Pin 1 Corner e S Y M B O L QFN4x4-28B MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF 0.006 0.010 b 0.15 0.25 D 3.90 4.10 0.154 0.161 0.110 D2 2.50 2.80 0.098 E 3.90 4.10 0.154 0.161 E2 2.50 2.80 0.098 0.110 e 0.4 BSC L 0.30 K 0.20 aaa Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 0.016 BSC 0.012 0.50 0.020 0.008 0.08 0.003 17 www.anpec.com.tw APA6003 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSSOP-28P Application QFN4x4-28B A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 4.00±0.10 12.00±0.10 2.00±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 6.9±0.20 10.20.±0.20 1.50±0.20 (mm) Devices Per Unit Package Type TSSOP-28P QFN4x4-28B Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 Unit Tape & Reel Tape & Reel Quantity 2000 3000 18 www.anpec.com.tw APA6003 Taping Direction Information TSSOP-28P USER DIRECTION OF FEED QFN4x4-28B USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 19 www.anpec.com.tw APA6003 Classification Profile Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 20 www.anpec.com.tw APA6003 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (t p) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 21 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA6003 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 22 www.anpec.com.tw