20160329111539302

APW8855
High Current, High Frequency 7 Outputs Voltage Regulator and Power
Management IC for High Performance Tablet and Ultra Notebook Applications
1.General Description
3.Features
The APW8855 is a Power Management IC (PMIC) designed to provide 7 Voltage regulators for AMD’s Stoney
Voltage Rail
•
Provide 3 Buck PWM Controllers with High
Ridge APU with ability to communicate via an I2C interface.
The IC operates from a wide input voltage of 5.5V to 20V.
Accuracy over Temperature
-VR1 provides 5V, 4A continuous output current.
There are 5 Switching Buck regulators and 2 low power
LDOs that are all controlled and sequenced via the serial
-VR2 provides 3.3V, 8A continuous output current.
-VR5 provides 0.95V, 8A continuous output current.
•
interface. The Buck PWM regulators consists of 3 switching controller driving external power stage such as
Provide 2 Buck PWM Converters with High
Accuracy over Temperature
-VR3 provides 1.8V, 2.5A continuous output current.
APW8703 which is capable of supplying up to 8A supply,
2 single phase switching regulators supplying up to 3A
-VR3 provides 1.5V, 2.5A continuous output current.
•
supply.
The IC is equipped with all the standard protection fea-
Provide 2 LDO Outputs with High Accuracy over
Temperature
tures such as over current, over voltage and internal under voltage lock out protection. The serial interface is an
-VR6 provides a low quiescent LDO output for RTC.
-VR7 provides a 0.65V to1.35V, 0.2A LDO output.
I2C communication interface which allows supply sequencing as well as controlled supply ramp up and ramp
•
down of all supplies except for the always on 1.5V LDO
supplying to RTC load. The IC is offered in TQFN4x4-32A
Serial Interface
Over temperature protection
package.
2.Applications
•
High Performance Tablet PCs
•
Ultra Notebook PCs
•
Netbook PCs
•
High Performance Digital Signage
•
Medical Devices
•
Smart phones
Built in Current limit, Over Voltage protection and
•
I2C communication Interface for SoC Access
•
Support Bit Rate 0.4MBit/s, 1MBit/s and 3.4MBit/s
•
Power Sequence Control by CTL
•
Built-in Thermal Diode and I2C Reading Function
for Temperature Sensing
•
POK Signal for VR power state.
•
4x4 TQFN-32A Package.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
1
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APW8855
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
General Desctiption....................................................................................1
Applications................................................................................................1
Key Features..............................................................................................1
Ordering and Marking Information..............................................................3
Pin Configuration........................................................................................3
Absolute Maximum Ratings........................................................................4
Thermal Chacterestics................................................................................4
Recommended Operation Conditions.........................................................4
Block Diagram............................................................................................5
Typical Application Circuit..........................................................................6
Pin Description...........................................................................................8
Power Sequence
12.1 Power-on Sequence..............................................................................9
12.2 Power-off Sequence............................................................................10
13. Electrical Characteristics
13.1 Regulator Table...................................................................................11
13.2 VR1 Electrical Characteristics..............................................................13
13.3 VR2 Electrical Characteristics..............................................................14
13.4 VR3 Electrical Characteristics..............................................................16
13.5 VR4 Electrical Characteristics..............................................................17
13.6 VR5 Electrical Characteristics..............................................................18
13.7 VR6 Electrical Characteristics..............................................................19
13.8 VR7 Electrical Characteristics..............................................................20
13.9 VSYS&POK&CTL Electrical Characteristics..........................................21
13.10 I2C Electrical Characteristics..............................................................22
14. Register Description
14.1 Register Map.......................................................................................23
14.2 VR1 Register Table...............................................................................24
14.3 VR2 Register Table...............................................................................25
14.4 VR3 Register Table...............................................................................26
14.5 VR4 Register Table...............................................................................27
14.6 VR5 Register Table...............................................................................28
14.7 VR6 Register Table...............................................................................29
14.8 Thermal Report Register Table...............................................................30
14.9 POK Delay Time Register Table.............................................................30
14.10 Version ID Register............................................................................31
15. Function Description
15.1 VR Function Description.......................................................................31
15.2 I2C Function Description......................................................................32
16. Application Information................................................................................36
17. Revision History..........................................................................................38
18. Package Information....................................................................................39
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
2
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APW8855
4.Ordering and Marking Information
A P W 8855
P a ckage C o de
Q B : T Q F N 4 x4-32A
O pe rating A m b ie nt T em pe rature R ang e
I : -4 0 to 85 o C
H and ling C od e
TR : T ape & R eel
A sse m b ly M ate rial
G : H alo gen and Le ad F ree D evice
A ssem bly M aterial
H and lin g C ode
T e m pera ture R ang e
P acka ge C od e
A P W 8855
QB:
.
X - D ate C od e
A P W 8855
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
LDO_RTC_IN
LDO_RTC_OUT
GND
VSYS
I2CDATA
I2CCLK
POK
CTL
5.Pin Configuration
32 31 30 29 28 27 26 25
5V_ALW_LDO
1
24
3V3_ALW_LDO
5V_ALW_BYP
2
23
3V3_ALW_BYP
5V_ALW_FBP
3
22
3V3_ALW_FBP
5V_ALW_PWM
4
21
3V3_ALW_PWM
1V5_ALW_IN
5
20 1V8_ALW_IN
1V5_ALW_LX
6
19 1V8_ALW_LX
1V5_ALW_PGND
7
18
1V5_ALW_FBP
8
17 1V8_ALW_FBP
QFN4x4-32A
Top View
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
3
S5_MUX
VDD_FCH_S5_REFIN
VDD_FCH_S5_IN
VDD_FCH_S5_OUT
VDDP_ALW_PW
M
VDDP_ALW_FBP
10 11 12 13 14 15 16
VDDP_ALW_FBN
VDDP_ALW_GPIO
9
1V8_ALW_PGND
Exposed Pad
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APW8855
6.Absolute Maximum Ratings (Note 1)
Pin or Symbol
VSYS
1V8_ ALW_ LX, 1 V5_ALW_ LX
1 V8_ ALW_ IN, 1 V5_ALW_IN
Para met er
VSYS to GND
1V8_ ALW _LX to 1 V8_ ALW_PGND
1V5_ ALW _LX to 1 V5_ ALW_PGND
1V8_ ALW _IN to 1 V8_A LW_PGND
1V5_ ALW _IN to 1 V5_A LW_PGND
Ra ting
Unit
-0.3~28
V
-0.3 to 6.5
V
5V _ALW_BY P, 3V 3_ALW_BY P
5V_ALW_ BYP, 3 V3_ALW_B YP to
GND
-0.3 to 6.5
V
5 V_A LW_PW M, 3V3_ ALW_ PWM,
VDDP_ALW_PW M
5V_ALW_ PWM, 3V3 _ALW _PWM,
VDDP_ALW_PW M to G ND
-0.3 to 6.5
V
PGND to GND
-0.3 to 0.3
V
All Other Pin s to GND
-0.3 to 6.5
1V8 _ALW _PGND, 1V5_ALW_ PGND
All Othe r P ins
V
TJ
Ju nctio n Tempe rature
1 50
o
T STG
Stor age Temperature
-65 ~ 150
o
TSD R
Ma ximu m Le ad Sol derin g
Tem perature (10 Seco nds)
2 60
o
C
C
C
Note 1: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
7.Thermal Characteristics
S ymbol
θ JA
Param eter
Typica l Value
Unit
o
Ju nctio n-to-Ambi ent Resistance in fre e a ir (Note 2 )
C/W
Note2: θJA is measured with the component mounted on a JESD-51-7 high effective thermal conductivity test board in free air.
8.Recommended Operating Conditions(Note3)
S ymbol
V VSYS
Pa ram ete r
Ra nge
Unit
System Rail From Batter y Manag ement Unit
5.5 ~ 20
V
V1V8_ ALW_IN
1V8_ ALW Reg ulator In put Voltage
3 ~ 5 .5
V
V1V5_ ALW_IN
1V5_ ALW Reg ulator In put Voltage
3 ~ 5 .5
V
VDD_FCH_S5 Regula to r Inpu t Voltage
0.5~1.5
V
0.65 ~ 1.3 5
V
V VDD_ FC H_S5_ IN
VVDD _FC H_S5_ REFIN VDD_FCH_S5 Regula to r Refere nce Inp ut Vo ltage
VCTL_L
CTL Inpu t Low Voltag e
0 ~ 0 .6
V
VC TL_ H
CTL Inpu t High Vol tag e
1 .2 ~ 5.5
V
VPOK
POK P ull High Voltage
~ 5 .5
TA
Ambie nt Tempera tur e
- 40 ~ 85
o
C
TJ
Ju nctio n Temp erature
-40 ~ 1 25
o
C
V
Note 3: Refer to the typical application circuit.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
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APW8855
9.Block Diagram
VSYS
5V_ALW
_BYP
5VLDO
VTHBYP_5V
5V_ALW
_LDO
VR1 PWM
Controller
5V_ALW_
PWM
5V_ALW
_FBP
VSYS
5VLDO
3V3_ALW
_BYP
VTHBYP_3V3
3V3_ALW
_LDO
VR2 PWM
Controller
3V3_ALW
_FBP
LDO_RTC
_IN
LDO_RTC
_OUT
3V3_ALW
_PWM
VR6 1.5V
LDO
VDDP_ALW
_PWM
VDDP_AL
W_GPIO
VR5 PWM
Controller
S5_MUX
VDDP_ALW
_FBP
VDDP_ALW
_FBN
VDD_FCH_
S5_REFIN
Control
Logic
1V8_ALW
_IN
VR3 PWM
Converter
VDD_FCH_
S5_OUT
1V8_ALW
_LX
1V8_ALW
_FBP
1V8_ALW
_GND
VDD_FCH_
S5_IN
LDO
Regulator
0.78V
I2CCLK
Controller
1V5_ALW
_IN
Thermal
Diode
ADC
I2CDATA
VR4 PWM
Converter
1V5_ALW
_LX
1V5_ALW
_FBP
1V5_ALW
_GND
CTL
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
POK
GND
5
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APW8855
10.Typical Application Circuit
10.1 Typical Application Circuit
VSYS(5.5V~19V)
3.3V Battery
RTC([email protected])
10uF
2.2uF
C29
1uF
C30
C36
C5
10uF
10uF
4.7uF
C34
26
3V3_LDO([email protected])
1
5V_ALW_LDO
CTL
28
VIN
5V_LDO([email protected])
R8
C4
RTC_
VIN
50K
RTC_L
DO
25
CTL
VSYS(5.5V~19V)
3V3_ALW_LDO
5V_LDO
C13
5VALW([email protected])
C40 C39
NC
NC
C38 C37
NC
C2
C3
NC
NC
NC
C7
0.1uF
C1
NC
VIN
BST EN PVCC VCC
PWM
APW8703
(TQFN4X4-23) SMOD
OCSET
AGND
PGND OCB
1uF
C6
R11
4
R1 50K
OCB
5V_LDO
2
3
5VALW
C17
1.8VALW([email protected])
C15
22uF
C18
22uF
L3
C16
19
0.47uH
47uF
47uF
18
17
C21
1.8VALW([email protected])
C19
1.8V RUN
22uF
L4
C20
3V3_ALW_BYP
1K
R5
NC
220uF
C42
C27 5V_LDO
C28
1uF
VCC
1V8_ALW_LX
VDDP_ALW_PWM
1V8_ALW_GND
PVCC BST VIN
0.1uF
APW8703
LX
(TQFN4X4-23)
SMOD
OCSET EN
AGND OCB
PGND
12
50K
R10
50K
VDDPALW([email protected])
C23
0.47uH
L5
10uF
C24
10uF
C43
220uF
CTL
R13
R3
5V_LDO
VDDP_ALW_FBN
C26
10uF
PWM
1V8_ALW_FBP
1V5_ALW_IN
C25
10uF
OCB
10
7
8
1K
R4
NC
22
1V8_ALW_IN
C22
22uF
6
47uF
NC
OCB
0K Q3
0.47uH
47uF
R12 0
21 5V_LDO
5V_ALW_FBP
5VALW
5
1uH
L2
C10
C9
C8
R2 50K
5V_ALW_BYP
3V3_ALW_FBP
20
3V3ALW([email protected])
0.1uF
APW8703
LX
(TQFN4X4-23)
SMOD
OCSET
AGND OCB PGND
Q2
PWM
23
C12
C14
VCC PVCC EN BST VIN
3V3_ALW_PWM
10uF
R9
1uF
5V_ALW_PWM
Q1
220uF
C41
C11
10uF
5V_LDO
50K
LX
0
2.2uH
L1
VSYS(5.5V~19V)
4.7uF C35
24
VDDP_ALW_FBP
1V5_ALW_LX
VDDP_ALW-GPIO
11
9
1V5_ALW_GND
VDDP_ALW_GPIO goes low, VDDP_ALW =0.95V
VDDP_ALW_GPIO goes high, VDDP_ALW =1.05V
VDDPALW
1V5_ALW_FBP
FCH_S5_IN
50K
R6
13
30
I2CCLK
29
I2C DATA
FCH_S5([email protected])
I2CDATA
FCH_S5_OUT
14
31
POK
C31
VDDNB(0.65V~1.35V)
POK2
FCH_S5_REFIN
CLT
C32
10uF
I2CCLK
32
15
CTL
CTL Low:Shutdown APW8855
Q4
APW8855
CTL High:Enable APW8855
C33
10uF
22uF
1.8V_RUN
R7 50K
16
S5_MUX
S5_MUX
GND
27
S5_MUX goes high, FCH_S5 VOUT track VDDNB
S5_MUX goes low, FCH_S5 VOUT will track VDDNB & 0.775V
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
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APW8855
10.2 Bill of Materials
De signator
Qu antity
Va lue
C1 , C2, C3,
Pa ckag e
Refere nce
Description
Cap , Ceramic, 1 0V,
X5 R, 10%
Part Number
MFR
GRM31CR61A226K E19 #
Mur ata
GRM31CR70J22 6KE19#
Mur ata
GRM31CR6YA10 6KA1 2
Mur ata
GRM319R60 J1 06K E19#
Mur ata
GRM31CR60J47 6ME19#
Mur ata
GRM219R61 A10 5KA01#
Mur ata
LLL1 85R71A 104 MA 01#
Mur ata
GRM219R7YA1 05K A12#
Mur ata
GRM188R60 J1 05K A01#
Mur ata
GRM319R61 A47 5KA01#
Mur ata
C8 , C9, C1 0, C17,
C1 8, C21 , C22,
C3 7, C38 , C39,
C4 0
14
22u F
C3 1
1
22u F
Cap , Ceramic, 6.3V,
X7 R, 10%
12 06
C4 , C5, C11, C12 ,
C2 5, C26 , C36
7
10u F
Cap , Ceramic, 3 5V,
X5 R, 10% ,
12 06
C2 3,C2 4,C3 2,C3 3
4
10u F
Cap , Ceramic, 6.3V,
X5 R, 10%
12 06
C1 5,C1 6,C1 9,C2 0
4
47u F
Cap , Ceramic, 6.3V,
X5 R, 20%
12 06
C6 , C13,C27
3
1uF
Cap , Ceramic, 1 0V,
X5 R, 10%
08 05
C7 ,C14 ,C28
3
0.1uF
Cap , Ceramic, 1 0V,
X7 R, 20%
06 03
C3 0
1
1uF
Cap , Ceramic, 3 5V,
X7 R, 10%
08 05
C2 9
1
1uF
Cap , Ceramic, 6.3V,
X5 R, 10%
06 03
C3 4, C35
2
4.7uF
Cap , Ceramic, 1 0V,
X5 R, 10%
12 06
C4 1, C42 , C43
3
220 uF
Cap , POSCAP, 1 0V,
20%
18 12
10TPE 220MIL
Panaso nic
L1
1
2.2uH
Indu ctor, SMD Fl at
Wire Coils-SDB,
sh ieldin g,
13.97mOh m
06 30,
XAL6 030 -222MEB
Coi lcr aft
Indu ctor, SMD Fl at
Wire Coils-SDB,
sh ieldin g, 6.18mOhm
06 30,
XAL6 030 -102MEB
Coi lcr aft
Indu ctor, SMD Fl at
Wire Coils-SDB,
sh ieldin g, 6.38mOhm
06 30,
7.5mm x
7.5mm x
1.5mm
XFL701 5-47 1MEB
Coi lcr aft
L2
12 06
1
1.0uH
#
6.76mm x
6.56mm x
3.1mm
6.76mm x
6.56mm x
3.1mm
L3,L4, L5
3
0.47uH
R1 , R2, R3, R6,
R7 , R8, R9, R10
8
50kOh m
R4 , R5
2
1kOhm
RES, 5% ,
04 02
R11,R12,R13
3
0Oh m
RES, 5% ,
04 02
Q1, Q2, Q 3
3
-
Powe r Stag e
TQFN4x4-23
APW8 703
ANPEC
Q4
1
-
PMIC
TDFN4 x4- 32
APW8 855
ANPEC
RES, 5% ,
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
04 02
7
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APW8855
11.Pin Description
P IN
FUNCTION
NO .
NAME
1
5 V_ALW_L DO
5V _ALW _LDO Outpu t Pin .
2
5V_ALW_ BYP
5V _ALW _LDO Input Pin. Co nnect to 5V_ ALW Ou tpu t Voltage.
3
5V_ALW _FBP
5V _ALW Output Voltage Fee dback Pin.
4
5V_ ALW_ PWM
5
1V5 _ALW _IN
1V 5_ALW P WM Reg ulator In put Pin.
6
1V5_ALW_LX
1V 5_ALW P WM Reg ulator LX Pin . Conne ct to e xterna l i nductor for ou tp ut LC fi lte r.
7
1V5 _ALW_PGND
8
1 V5_ALW_ FB P
9
VDDP_ ALW_ GPIO
VDDP_ ALW Ou tp ut Sel ect Pin. Pull hi gh for V PPD_ALW=1 .0 5V, pull low for
VDDP_ ALW=0.95V.
10
VDDP _ALW_FBN
VDDP_ ALW Negative Outpu t Feedb ack Pin . Conne ct to VR5 ’s grou nd.
11
VDDP_A LW_FBP
VDDP_ ALW Positive Output Fe edba ck Pin. Connect to VR5’s output voltage .
12
VDDP _ALW _PWM
VDDP_ ALW PWM Sign al Output P in. Con nect to Exter nal power sta ge’s PWM in put p in.
13
VDD_FCH_S5_ IN
VDD_FCH_S5 LDO Reg ulator In put P in.
5V _ALW PW M Sig nal Outpu t Pin . Co nnect to External po we r stage ’s PWM input pin.
1V 5_ALW P WM Reg ulator PGND Pin.
1V 5_ALW P WM Reg ulator Outpu t Vo lta ge Feedb ack Pin.
14
V DD_ FCH_S 5 _OUT
VDD_FCH_S5 Outp ut Pi n.
15
VDD_FCH_S5_REFIN
VDD_FCH_S5 Tr ack Voltage In put Pin.
16
S 5_MUX
VDD_FCH_S5 Tr ack Sel ect Pin. When S5_ MUX=hig h, VDD_FCH_S5 fully tr ack
VDD_FCH_S5_ REFIN vo lta ge; S5_MUX=lo w, V DD_ FCH_S5 p artially tra ck
VDD_FCH_S5_ REFIN vo lta ge.
17
1 V8_ALW_ FB P
18
1V8 _ALW_PGND
19
1V8_ALW_LX
1V 8_ALW P WM Reg ulator Outpu t LX Pin . Conne ct to external in ducto r for ou tp ut LC filter.
20
1V8 _ALW _IN
1V 8_ALW P WM Reg ulator In put Pin.
21
3V3_ALW_BY P
3V 3_ALW_LDO Inpu t Pin . Conne ct to 3V3_ALW Output Vol tag e.
22
3 V3_ALW_ FB P
3V 3_ALW Output Vo ltag e Fe edba ck Pin.
23
3V3_ALW_PWM
3V 3_ALW P WM S ignal O utp ut Pi n. Conn ect to E xterna l p ower stag e’s PWM inpu t pin .
24
3V3 _ALW_LDO
3V 3_ALW_LDO O utp ut P in.
25
LDO_RTC_IN
26
LDO_RTC_ OUT
1V 8_ALW P WM Reg ulator Outpu t Vo lta ge Feedb ack Pin.
1V 8_ALW P WM Reg ulator Outpu t PGND Pin.
L DO_RTC Input Vo lta ge Pin. Provide a 3.3V po wer in to this pin to e nable LDO _RTC Output.
L DO_RTC Ou tpu t Voltage Pin .
27
GND
28
VSYS
IC An alog Gr ound .
29
I2CDATA
30
I2CCLK
31
PO K
Power Good Ind icato r. Conn ect a resistor from POK to a pull- high voltage.
32
CTL
System P ower Sta te Control Pin . Pul l CTL h igh to e nable V R1/2 /3 /4/5/7.
Exp osed
P ad
PGND
IC Powe r Inp ut Pin.
I2C Data Con nection Pin.
I2C Clock Sig nal Pin.
IC Power Gro und
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
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APW8855
12.Power Sequence
12.1 Power-on Sequence
POR
VSYS
5VALW_LDO
3V3ALW_LDO
LDO_RTC_IN
LDO_RTC(VR6)
CTL
5V_ALW(VR1)
70us
3V3_ALW(VR2)
1V8_ALW(VR3)
100us
1V5_ALW(VR4)
VDDP_ALW(VR5)
1.05V
0.95V
0.95V
VDDP_ALW_GPIO
VDD_FCH_S5(VR7)
0.78V
0.78V
Track VDDNB
Track VDDNB
100us
VDDNB
0.775V
S5_MUX
POK
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
1ms
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APW8855
12.2 Power-off Sequence
VSYS
5VALW_LDO
3V3ALW_LDO
VLDO_RTC(VR6)
CTL
5V_ALW(VR1)
3V3_ALW(VR2)
1V8_ALW(VR3)
1V5_ALW(VR4)
100us
VDDP_ALW(VR5)
VDD_FCH_S5(VR7)
POK
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
10
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APW8855
13.Electrical Characteristics
13.1 Regulator Table
Table 1. PWM Controllers VR1, VR2,VR5
S ymbol
V IN
VOUT
Parame ter
VR1(5VALW)
VR2(3VALW)
V R5 (VDDPALW)
Unit
Inpu t Voltage
VVSYS
VVSYS
VVSYS
V
Defau lt Outpu t Voltage
5 .0 6
3.3
0 .9 5
O utput Voltag e Ran ge
4.5~5 .5
2.6~4
0.5~1 .5
4
8
8
A
IOUT
Con tin uous Output Current
I PEAK
P eak Output Cu rrent
C IN
Inpu t Capacitor
COUT
O utput Cap acito r
ESR
O utput Cap acito r E SR
L
DCR
V
8
-
-
A
>2 x 10
>2 x 1 0
>2x 10
µF
>1 x 220
>1 x 220
>2 x 1 0+1 x2 20
µF
6
6
6
mΩ
O utput Indu ctor
2 .2
1.0
0.47
µH
O utput Indu ctor DCR
<10
<10
<1 0
mΩ
Table 2. PWM Converters VR3, VR4
Symbol
V IN
Pa ram ete r
V R3(1V8 ALW)
VR4(1V5ALW)
Unit
V
V5V_ALW
V5 V_ ALW
Default Output Vo ltag e
1.8
1.5
Ou tpu t Voltage Rang e
1.45 ~2.25
0.8 ~2
2.5
2.5
A
3
3
A
Input Capacitor
>2x 2 2
>2 x 22
µF
C OU T
Ou tpu t Capacitor
>2 x 47
>2 x 47
µF
ESR
Ou tpu t Capacitor ES R
6
6
mΩ
Ou tpu t Inductor
0 .4 7
0.47
µH
Ou tpu t Inductor DCR
<15
<15
mΩ
V OUT
Input Volta ge
I OU T
Continu ous Output Cur rent
I PEAK
Pe ak Outp ut Curre nt
C IN
L
DCR
V
Table 3. LDO Regulators VR6, VR7
S ymbol
V IN
Parame ter
VR6(LDO_ RTC)
V R7(VDD_FCH_S5)
Unit
V LDO_RTC_IN (3.3V Ba ttery)
VVDDP_ ALW or
VVDD _FCH_S5 _REFIN( VDDNB )
V
Defau lt Outpu t Voltage
1.5
0.78
O utput Voltag e Ran ge
-
0 .5~1.5
4.5µ
0.2(LDO)/0 .9 (Switch )
A
1
10
µF
2 .2
22
µF
Inpu t Voltage
VOUT
V
IOUT
Con tin uous Output Current
C IN
Inpu t Capacitor
COUT
O utput Cap acito r
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
11
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APW8855
13.1 Regulator Table
Table 4. LDO Regulators 5V_ALW_LDO, 3V3_ALW_LDO
S ymbol
V IN
VOUT
Parame ter
5V_ ALW_LDO
3 V3_ ALW _LDO
Unit
V
Inpu t Voltage
VVSYS
V VSYS
Defau lt Outpu t Voltage
5.06
3.3
O utput Voltag e Ran ge
4.5~5.5
2 .9~4
V
IOUT
Con tin uous Output Current
1 00
1 00
mA
C IN
Inpu t Capacitor
10
10
µF
O utput Cap acito r
4.7
4.7
µF
COUT
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
12
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APW8855
13.2 VR1 Electrical Characteristics
These specifications apply over VVSYS = 12V, V5V_ALW = 5.06V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR1)
Test Conditions
Unit
Min
Typ
Max
-
-
±0.8
%
±0.2
%
PWM OUTPUT V OLTAGE
O utput Vo ltag e Accuracy
TA = 25°C
O utput Vo ltag e Line/Lo ad
Re gulation
Vin=7.5V to 2 0V, I OUT =1.08A to 4 A
L oad Transient Drop Volta ge
Tr=200n s, IOUT =1 .08 A to 4A, Refer to the
typical circuit
-4
%
L oad Transient Overshoo t
Vo ltag e
Tf=200n s, I OUT =4A to 1.08 A, Refer to the
typical circuit
+4
%
+1 0
%
11
mV/µs
O utput Step Ramp Rate
Accu racy
-1 0
O utput Vo ltag e S oft-start Rate
9
O utput Dischar ge Re sistance
Fe edback Leakag e Cu rrent
10
Ω
10
V5V_ALW_FBP = 5 .5V
-
-
10 0
nA
Switchi ng Fr eque ncy
Accu racy
VVSYS =7.5 to 20 V, V OUT =4V to 5.5V
-
-
±15
%
Switchi ng Fr eque ncy
VVSYS =5.5V, VOUT = 5.06V
30 0
kHz
PWM GATE DRIV ER
Min imum Off Time
200
Min imum Co ntrollab le On
Time
60
80
ns
PWM Sink Resista nce
15
20
Ω
PWM Source Resistance
15
20
Ω
10 0
nA
PWM L eakage Curre nt
V5V_ALW_PWM=5.5V
ns
PROTE CTION
Un der-voltage P rotectio n
( UVP)
UV P Deb ounce Time
O ver-voltage Pro te ction
( OVP )
O VP Debo unce Time
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
13
65
70
75
%
-
2
-
µs
12 5
130
13 5
%
2
-
µs
www.anpec.com.tw
APW8855
13.2 VR1 Electrical Characteristics
These specifications apply over VVSYS = 12V, V5V_ALW = 5.06V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR1)
Test Conditions
Unit
Min
Typ
Max
3.85
4.0
4.15
LDO REGULATO R
VSYS_UVLO
V5V_ LDO_POR
V5 V_ LDO
VSYS Und er-voltage Lo ckou t
( UV LO)
VVSYS Rising , ena ble 5V_ LDO
L DO Re gulator Unde r-voltage
L ockout (UV LO)
V5V_L DO Rising , enab le other VRs
Hysteresis
0.1
0 .15
0 .2
V
4.15
4.3
4.45
V
0 .15
0 .2
V
+2
%
0 .4
V
25 0
mA
Hysteresis
0.1
L DO Re gulator Outp ut
Vo ltag e Accuracy
VVSYS=5.5V to 20V, 10mA
-2
L DO Dro pout Voltage
IOUT =1 00mA, V 5V_LD O=5.06V
L DO Cu rrent Limit
15 0
L DO Di schar ge Resistance
L DO Power-o n De lay
V TH BYP_ 5V
Bypass Threshol d
V
200
Ω
10
VSYS>V SYS_POR to 5V_L DO soft-start starting
µs
20
PWM Vol tag e Rising
91
94
97
%VR1
Hysteresis
2
3
4
%VR1
-
1.5
3
Ω
10 0
nA
Bypass Switch On Resistance
L DO Soft-start Time
COUT =4.7 uF
Bypass Le akage Curre nt
V5V_ALW_BYP=5 .5V, V VSYS=0V
100
-
-
us
EFFICIENCY
Efficiency (Re fe r to th e typical
cir cu it)
VOUT=5 V, IOUT=5mA to 50mA, DCR<10 mΩ
93
%
VOUT=5 V, IOUT=50mA to 500mA , DCR<10m
Ω
93
%
VOUT=5 V, IOUT=2 A, DCR<10mΩ
92
%
VOUT=5 V, IOUT=4 A, DCR<10mΩ
90
%
13.3 VR2 Electrical Characteristics
These specifications apply over VVSYS = 12V, VOUT = 3.3V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR2)
Test Conditions
Unit
Min
Typ
Max
-
-
±0.8
%
±0.2
%
PWM OUTPUT V OLTAGE
Output Vo ltag e Accuracy
TA = 25°C
Output Vo ltag e Line/Lo ad
Re gulation
Vin=7.5V to 2 0V, I OUT =2.16A to 8 A
L oad Transient Drop Volta ge
Tr=200n s, IO UT=2.16A to 8A, Refe r to the
typical circuit
-4
%
L oad Transient Overshoo t
Vo ltag e
Tf=200n s, IO UT=8A to 2.16A, Refe r to the
typical circuit
+4
%
+1 0
%
11
mV/µs
10 0
nA
Output Step Ramp Rate
Accu racy
-1 0
Output Vo ltag e Soft-start Rate
9
Output Dischar ge Re sistance
Fe edback Leakag e Cu rrent
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
10
Ω
10
V3V3_ ALW_FBP = 5.5V
14
-
-
www.anpec.com.tw
APW8855
13.3 VR2 Electrical Characteristics
These specifications apply over VVSYS = 12V, VOUT = 3.3V, TA = 25oC, unless otherwise noted.
Symbol
Param eter
AP W88 55(V R2 )
Tes t Conditions
Min
Unit
Typ
Max
-
±1 5
PWM GATE DRIV ER
Switch ing Frequ ency
Accuracy
VVSYS =5.5 to 2 0V, V OUT=2.6V to 4 V
Minimum Off Time
20 0
%
ns
Minimum Controlla ble On
Time
60
80
ns
PWM Sink Re sistance
15
20
Ω
PWM Sour ce Resista nce
15
20
Ω
1 00
nA
PWM Leakag e Cu rrent
V3 V3 _ALW_ PWM=5.5V
PROTECTION
Under- vol tag e Protection
(UVP)
UVP Deboun ce Time
Over-voltage P rotectio n
(OV P)
65
70
75
%
-
2
-
µs
125
13 0
1 35
%
2
-
µs
OV P Deb ounce Time
LDO REG ULATOR
LDO Regul ato r Un der-voltage
Lockout (UVLO )
V3V3_ LDO
VVSYS Risin g, en able 3V3_LDO
3.8
4 .0
4.2
%
Hysteresis
0.1
0.15
0.2
V
+1
%
1.5
V
2 50
mA
LDO Regul ato r Output
Voltage A ccura cy
LDO Dropo ut Voltage
-1
I OUT =100mA, V3V3 _ALW_ PWM=4 V
LDO Curren t Limit
150
LDO Disch arge Resista nce
LDO Soft-start Time
VTHBYP_3V3
Bypass Thresh old
PWM Vo lta ge Ri si ng
Hysteresis
Bypass S witch On Resistance
Bypass L eakage Curr ent
V3 V3 _ALW_ BYP=5.5V, VVSYS=0 V
91
20 0
10
Ω
10 0
us
94
97
% VR2
2
3
4
% VR2
-
1 .5
3
Ω
-
-
1 00
nA
EFFICIE NCY
Efficien cy (Refer to the typi ca l
circuit)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
VOUT=3.3V, IOUT=5mA to 50mA, DCR<1 0m
Ω
93
%
VOUT=3.3V, IOUT=50mA to 500 mA,
DCR<10mΩ
93
%
VO UT=3.3V, IO UT=3A, DCR<1 0mΩ
88
%
VO UT=3.3V, IO UT=8A, DCR<1 0mΩ
93
%
15
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APW8855
13.4 VR3 Electrical Characteristics
These specifications apply over VVSYS = 12V, VOUT = 1.8V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR3)
Test Conditions
Min
Unit
Typ
Max
-
±10
%
90
93
96
%
-
60
10 0
ns
PWM CONTRO LLER
Switchi ng Fr eque ncy
Accu racy
De fa ult is 2MHz
Ma ximum Duty Cycl e
Min imum Co ntrollab le On
Time
Hig h-side MOS FE T On
Re sistance
V1V8_ ALW_IN=5V
55
mΩ
L ow-side MOS FE T On
Re sistance
V1V8_ ALW_IN=5V
40
mΩ
Inp ut L eakage Curre nt
VR3 is off, V1V8_ ALW_IN=5.5V
1
µA
L X Leakag e Cu rrent
V1V8_ ALW_L X =5.5V, V1V8_ ALW_IN=5.5V
1
µA
5
mV
±0.8
%
±0.2
%
Ze ro Cu rrent Offset
-5
PWM OUTPUT V OLTEGE
Output Vo ltag e Accuracy
TA = 25°C
-
Output Vo ltag e Load
Re gulation
L oad Transient Drop Volta ge
Tr=200n s, IOUT =0 .81 A to 3A, Refer to the
typical circuit
-3
%
L oad Transient Overshoo t
Vo ltag e
Tf=200n s, I OUT =3A to 0.81 A, Refer to the
typical circuit
+3
%
+1 0
%
11
mV/µs
Output Step Ramp Rate
Accu racy
-1 0
Output Vo ltag e Soft-start Rate
9
Output Dischar ge Re sistance
CTL=0V
Fe edback Leakag e Cu rrent
V1V8_ ALW_FBP = 5.5V
10
Ω
10
-
-
10 0
nA
65
70
75
%
-
2
-
µs
12 5
130
13 5
%
2
-
µs
5
6
A
PROTECTION
Un der-voltage Protectio n
( UV P)
UV P Deb ounce Time
Over-voltage Pro te ction
( OVP )
OVP Debo unce Time
I OC P3
Hig h-side MOS FE T
Over-curre ntProtection(O CP )
4
OCP De boun ce TIme
Th ermal Shu tdo wn P rotectio n
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
TJ Rising
16
2
µs
150
?
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APW8855
13.4 VR3 Electrical Characteristics
These specifications apply over VVSYS = 12V, VOUT = 1.8V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR3)
Test Conditions
Min
Typ
Unit
Max
EFFICIENCY
Efficiency (Re fe r to th e typical
cir cu it)
VOUT=1 .8 V, IOUT=5mA to 5 0mA, DCR<25 m
Ω
88
%
VOUT=1 .4 5V, IO UT=0.1 A to 3A, DCR<25 mΩ
82
%
VOUT=1 .8V, IOUT=0 .1A to 3 A, DCR<25m
Ω
85
%
VOUT=2 .2 5V, IO UT=3A, DCR<2 5mΩ
87
%
13.5 VR4 Electrical Characteristics
These specifications apply over VVSYS = 12V, VOUT = 1.5V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR4)
Test Conditions
Min
Unit
Typ
Max
-
±10
%
70
80
90
%
-
70
-
ns
PWM CONTRO LLER
Switchi ng Fr eque ncy
Accu racy
De fa ult is 2MHz
Ma ximum Duty Cycl e
Min imum Co ntrollab le On
Time
Hig h-side MOS FE T On
Re sistance
V1V5_ ALW_IN=5V
55
mΩ
L ow-side MOS FE T On
Re sistance
V1V5_ ALW_IN=5V
40
mΩ
Inp ut L eakage Curre nt
VR4 is off, V1V5_ ALW_IN=5.5V
1
µA
L X Leakag e Cu rrent
V1V5_ ALW_L X =5.5V, V1V5_ ALW_IN=5.5V
1
µA
5
mV
±0.8
%
±0.2
%
Ze ro Cu rrent Offset
-5
PWM OUTPUT V OLTEGE
Output Vo ltag e Accuracy
TA = 25°C
-
Output Vo ltag e Load
Re gulation
L oad Transient Drop Volta ge
Tr=200n s, IOUT =0 .81 A to 3A, Refer to the
typical circuit
-3
%
L oad Transient Overshoo t
Vo ltag e
Tf=200n s, I OUT =3A to 0.81 A, Refer to the
typical circuit
+3
%
+1 0
%
11
mV/µs
Output Step Ramp Rate
Accu racy
-1 0
Output Vo ltag e Soft-start Rate
9
Output Dischar ge Re sistance
CTL=0V
Fe edback Leakag e Cu rrent
V1V5_ ALW_FBP = 5.5V
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
10
Ω
10
17
-
-
10 0
nA
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APW8855
13.5 VR4 Electrical Characteristics
These specifications apply over VVSYS = 12V, VOUT = 1.5V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
APW8855 (VR4)
Test Conditions
Unit
Min
Typ
Max
65
70
75
%
-
2
-
µs
12 5
130
13 5
%
2
-
µs
5
6
A
PROTECTION
Un der-voltage P rotectio n
( UV P)
UV P Deb ounce Time
Over-voltage Pro te ction
( OVP)
OVP Debo unce Time
IOCP
Hig h-side MOS FE T
Over-curre ntProtection(O CP )
4
2
µs
150
?
VOUT=1 .5 V, IOUT=5mA to 5 0mA, DCR<25 m
Ω
85
%
VOUT=1 .4 5V, IO UT=0.1 A to 3A, DCR<25 mΩ
82
%
VOUT=1 .5V, IOUT=0 .1A to 3 A, DCR<25m
Ω
85
%
VOUT=2 .0V, IOUT=3 A, DCR<25mΩ
86
%
OCP De boun ce Time
Th ermal Shu tdo wn Protectio n
TJ Rising
EFFICIENCY
Efficiency (Re fe r to th e typical
cir cu it)
13.6 VR5 Electrical Characteristics
These specifications apply over VVSYS = 12V, VOUT = 0.95V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR5)
Test Conditions
Unit
Min
Typ
Max
-
-
±10
mV
5
mV
PWM OUTPUT V OLTAGE
Output Vo ltag e Accuracy
TA = 25°C
Output Vo ltag e Line/Lo ad
Re gulation
L oad Transient Drop Volta ge
Tr=200n s, IOUT =2 .16 A to 8A, Refer to the
typical circuit
-35
mV
L oad Transient Overshoo t
Vo ltag e
Tf=200n s, I OUT =8A to 2.16 A, Refer to the
typical circuit
+3 5
mV
+1 0
%
11
mV/µs
Output Step Ramp Rate
Accu racy
-1 0
Output Vo ltag e Soft-start Rate
9
Output Dischar ge Re sistance
Fe edback Leakag e Cu rrent
V DDP _ALW_GPIO Thresh old
Ω
10
VVDDP_ ALW_FBP = 5.5 V
-
VDDP_A LW_GP IO r isin g
VDDP_A LW_GP IO falli ng
VDDP _ALW_GPIO Inp ut
L eakag e Cur rent
VVDDP_ ALW_GPIO =5V
VDDP _ALW_GPIO
De bounce Tim e
Hi gh to lo w and l ow to high
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
10
0.6
-
10 0
nA
1.0
1 .2
V
0.8
V
1
18
2
uA
us
www.anpec.com.tw
APW8855
13.6 VR5 Electrical Characteristics
These specifications apply over VVSYS = 12V, VOUT = 0.95V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR5)
Test Conditions
Min
Unit
Typ
Max
-
±15
PWM GATE DRIV ER
Switchi ng Fr eque ncy
Accu racy
VIN=5 .5 to 20V, VOUT =2.6V to 4V
%
Min imum Off Time
200
Min imum Co ntrollab le On
Time
60
80
ns
PWM Sink Resista nce
15
20
Ω
PWM Source Resistance
15
20
Ω
10 0
nA
PWM L eakage Curre nt
ns
VVDDP_ ALW_PWM=5.5V
PROTECTION
Un der-voltage Protectio n
( UV P)
UV P Deb ounce Time
Over-voltage Pro te ction
( OVP )
65
70
75
%
-
2
-
µs
12 5
130
13 5
%
2
-
µs
OVP Debo unce Time
EFFICIENCY
Efficiency (Re fe r to th e typical
cir cu it)
VOUT=0 .9 5V, IO UT=5mA to 10mA,
DCR<10mΩ
87
%
VOUT=0 .9 5V, IO UT=50mA to 500 mA ,
DCR<10mΩ
87
%
VOUT=0 .9 5V, IO UT=3A, DCR<1 0mΩ
86
%
VOUT=0 .9 5V, IO UT=8A, DCR<1 0mΩ
86
%
13.7 VR6 Electrical Characteristics
These specifications apply over VLDO_RTC_IN = 3.3V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR6)
Test Conditions
Unit
Min
Typ
Max
-
1
2
1 .42 5
1.500
1.57 5
SUPPLY VOLTAGE
Inp ut Bias Curr ent
µA
REGULATOR OUTP UT
Output Vo ltag e
IOUT =4 .5µA
Output Cu rrent Capabi lity
Output No ise
f=100 to 100kHz
Power-S upply Rejection
Ra tio n (PSRR)
f=10kHz
100
40
Output Vo ltag e Soft-start
Time
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
µV RMS
dB
1
19
V
µA
4.5
ms
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APW8855
13.8 VR7 Electrical Characteristics
These specifications apply over V5V_ALW = 5.06V, VVDD_FCH_S5 = 0.78V, TA = 25oC, unless otherwise noted.
Symbol
Parame ter
AP W8855 (VR7)
Test Conditions
Unit
Min
Typ
Max
-
-
±1
%
REGULATOR OUTP UT
Output Vo ltag e Accuracy
TA = 25°C
Output Vo ltag e Load
Re gulation
IOUT=0.06A to 0.2A
±0.5
%
Output Load Transient Dr op
Vo ltag e
Tr=1us, IOUT=0 .06 A to 0.2A, Refer to the
typical circuit
-8.5
%
Output Load Transient
Overshoot Volta ge
Tf=1us, IOUT=0.2A to 0.06A , Refer to the
typical circuit
+8.5
%
Dro pout Volta ge
IOUT =2 00mA
50
mV
25
Output Dischar ge Re sistance
Output No ise
f=100 to 100kHz
Power-S upply Rejection
Ra tio n (PSRR)
f=10kHz
10
Ω
100
µV RMS
40
Cu rrent Limit
dB
300
400
50 0
mA
Un der Voltage Pro tection
( UV P)
45
50
55
%
Output Vo ltag e Soft-start Rate
9
10
11
mV/µs
10
20
mΩ
1
µA
SWITCH OUTPUT
Switch On Resista nce
Over Cu rrent-P rotectio n
Inp ut L eakage Curre nt
2
2.5
VVDD_ FC H_S5_ REFIN=5.5V
A
CONTRO L LOGIC
S 5_MUX Input Logic
Th reshold
Ri sin g
Tran sition Thre sh old fr om
Switch to LDO
Fr om switch to LDO
0 .78
Fr om L DO to switch
0.8
S5_MUX Input Leakag e
Cu rrent
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
1.0
Fa lling
0.6
VS5_MU X=5V
1 .2
V
0.8
V
1
20
uA
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APW8855
13.9 VSYS&POK&CTL Electrical Characteristics
These specifications apply over V5V_ALW = 5.06V, TA = 25oC, unless otherwise noted.
Symbol
P aram eter
APW88 55(P OK)
Tes t Condit ions
Min
Typ
Unit
Max
VS YS SUPP LY CCURRENT
V SYS S upply Curren t
VSYS =19 V, CTL=Low, only 5V_L DO ,
3 V3_L DO , LDO _RTC are on
110
µA
CTL=High,
all
VR
a re
VR1/2 /3/4/5 are n o switch ing
TBD
µA
on ,
PO K
PO K Thr eshold
POK in from Lo we r (P OK go es hi gh)
Monitor V R1~5 and V R7 (LDO Ou tp ut
or Switch OCP)
87
90
93
%
POK out to norma l ( POK go es low)
Monitor V R1~5 and V R7 (LDO Ou tp ut
or Switch OCP)
125
13 0
135
%
POK Hysteresis
3
%
? µA?
PO K Leakag e Cu rrent
VPOK = 5V
-
0 .1
1
PO K Low Vol tag e
I POK_ si nk =4mA
-
0 .5
1
V
PO K Enab le Blankin g Time
From VR1~VR5,VR7 rising to 90% of
their set p oint to PO K g oes Hig h
-
1320
-
µs
PO K Disa ble Blan kin g Time
From VR1~VR5, VR7 fa lling to 87% of
their set p oint to PO K g oes Low
µs
2
CTL
VC TL rising
CTL Input Log ic Threshol d
CTL Le akage Curren t
tD CTL
1 .0
VC TL fallin g
0.6
0 .8
VC TL =5V
5V _ALW a nd 3V3_ ALW Timin g
tD 2
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
V
V
1
? µA
? µs
CTL hi gh to 5V_ALW start soft-start
70
CTL lo w to 5V_A LW start so ft-stop
2
? µs
5V_ALW re ady to 1V8_ALW soft- start
10 0
? µs
VR1~5 read y to VR7 so ft-start
10 0
? µs
1V8_ALW off to 5V _ALW soft-stop
10 0
? µs
CTL Debo unce Time
tD 1
1.2
21
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APW8855
13.10 I2C Electrical Characteristics
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
Symbol
Param eter
High Speed
Min.
M ax.
Fa st Speed Plus
Min.
f SC L
Frequ ency, SCL
3 .4
tW(H)
Pul se Dura tio n, SCL High
60
26 0
t W(L )
Pul se Dura tio n, SCL Lo w
16 0
50 0
Max.
Fast Spee d
Min.
1
Unit
Max.
0.4
MHz
6 00
ns
130 0
ns
tr
Rise Time , SCL and SDA
10
40
1 20
20+0.1
CL (pF)
tf
Fall Time, SCL an d SDA
10
80
1 20
20+0.1
CL (pF)
tsetup 1
Setup Time, SCL to SDA
10
1 00
ns
t hol d1
Hold Time, SCL to SDA
0
0
ns
t (buf)
Bus Free Time Betwe en Stop and Sta rt
Condi tio n
130 0
ns
50 0
tsetup 2
Setup Time, SCL to Start Co ndition
16 0
6 00
t hol d2
Hold Time, Star t condition to SCL
16 0
6 00
tsetup 3
Setup Time, SCL to Stop Cond iti on
16 0
6 00
CL
Loa d Ca pacitance fo r Each B us L ine
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
10 0
22
3 00
ns
3 00
ns
4 00
pF
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APW8855
14.Register Description
14.1 Register Map
Channel
VR1
VR2
Regis ter Address
Re ad/Write/Re ad Only
State
De fault Value
5V_ALW DAC
0x01
R/W
0x6d
5V_ALW Con tro l
0x02
R/W
0x08
3V3_ALW DA C
0x03
R/W
0x15
3V3_ALW Co ntrol
0x04
R/W
0x08
1V8_ALW DA C
0x05
R/W
0x24
1V8_ALW Co ntrol
0x06
R/W
0x04
1V5_ALW DA C
0x07
R/W
0x47
1V5_ALW Co ntrol
0x08
R/W
0x04
VDDP_ ALW DAC
0x09
R/W
0x2e
VDDP_ ALW Control
0x0A
R/W
0x08
VDD_FCH_S5 DAC
0x0B
R/W
0x1d
VDD_FCH_S5 Control
0x0 C
R/W
0x00
Therma l Rep ort
0x2 C
R
-
POK Blankin g Time
0x26
R/W
0x7d
Version ID
0xF0
R
0x00
Registe r Name
VR3
VR4
VR5
VR7
Ther mal
POK
ID
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APW8855
14.2 VR1 Register Table
Addres s
0x01
Fie ld Na me
5 V_ALW DAC [7:0 ]
Data B it
D7
D6
D5
D4
Bit Na me
D3
D2
D1
D0
5V _ALW _VS EL
Read/Write
R/W
R/W
R/W
0
1
1
Po wer On De fa ult
Bit Name
R/W
R/W
R/W
R/W
R/W
0
1
1
0
1
D2
D1
D0
Bit Definition
0 0h : shutdown
5 1h : V R1 &V5V_ ALW_L DO Voltage = 45 00mV.
5 2h : V R1 &V5V_ ALW_L DO Voltage = 45 20mV.
5 3h : V R1 &V5V_ ALW_L DO Voltage = 40 40mV.
5V_ALW _VSEL
…
6 dh : V R1 &V5V_ ALW_L DO Voltage = 50 60mV (Default)
….
8 3h : V R1 &V5V_ ALW_L DO Voltage = 55 00mV.
8 4h ~ ffh: Re served.
Addres s
0x0 2
Fie ld Na me
5 V_ALW CONTROL [7: 0]
Data B it
D7
D6
Bit Na me
D5
D4
5 V_ALW_SLEW
Read/Write
Reserved
Po wer On De fa ult
D3
5V _ALW _FSW _SEL
5 V_ALW__ 5V _ALW__
SE L
EN
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
Bit Name
Bit Definition
5V_ALW __EN
0: V R1 o ff (De fau lt)
1: V R1 o n
5V_ALW __SEL
0: V R1 o n/off i s controlle d by CTL (Defaul t)
1: V R1 o n/off i s controlle d by 5V _ALW _EN State
00 : FSW = 1.0MHz at PWM mod e.
5V_ALW _FSW_SE L
5V_ALW _SLEW
01 : FSW = 0.6MHz at PWM mod e.
10 : FSW = 0.8MHz at PWM mod e. (Defau lt)
11 : FSW = 1.2MHz a t PWM mode.
00 : Transition sl ew ra te = 1 0mV/us. (Default)
01 : Transition sl ew ra te = 1 5mV/us.
10 : Transition sl ew ra te = 2 0mV/us.
11 : Tra nsitio n sle w rate = 25mV /u s
Copyright  ANPEC Electronics Corp.
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APW8855
14.3 VR2 Register Table
Addres s
0x03
Fie ld Na me
3V3 _ALW DAC [7:0]
Data B it
D7
D6
D5
D4
Bit Na me
D3
D2
D1
D0
3 V3_ ALW_ VSE L
Read/Write
R/W
R/W
R/W
0
0
0
Po wer On De fa ult
Bit Name
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
D2
D1
D0
Bit Definition
0 0h : shutdown
0 1h : V R2 &V3V3 _ALW_ LDO Vol tag e = 2 900mV.
0 2h : V R2 &V3V3 _ALW_ LDO Vol tag e = 2 920mV.
0 3h : V R2 &V3V3 _ALW_ LDO Vol tag e = 2 940mV.
3V3_ALW_VSEL
…
1 5h : V R2 &V3V3 _ALW_ LDO Vol tag e = 3 300mV (De fau lt)
….
3 8h : V R2 &V3V3 _ALW_ LDO Vol tag e = 4 000mV.
Addres s
0x0 4
Fie ld Na me
3V 3_ALW CONTROL [7:0 ]
Data B it
D7
D6
Bit Na me
D5
D4
3V3_ ALW _SLEW
Read/Write
Reserved
Po wer On De fa ult
R/W
0
Bit Name
D3
3 V3_A LW_ 3V 3_A LW_
3V 3_A LW_FSW _SEL
_ SEL
_ EN
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
Bit Definition
3V3_ALW__EN
0: V R2 o ff (De fau lt)
1: V R2 o n
3V3_ALW__SEL
0: V R2 o n/off i s controlle d by CTL (Defaul t)
1: V R2 o n/off i s controlle d by 3V 3_ALW_EN State
00 : FSW = 1.0MHz at PWM mod e.
3V3_ALW_FSW_S EL
3V3_ALW_SL EW
01 : FSW = 0.6MHz at PWM mod e.
10 : FSW = 0.8MHz at PWM mod e. (Defau lt)
11 : FSW = 1.2MHz a t PWM mode.
00 : Transition sl ew ra te = 1 0mV/us. (Default)
01 : Transition sl ew ra te = 1 5mV/us.
10 : Transition sl ew ra te = 2 0mV/us.
11 : Tra nsitio n sle w rate = 25mV /u s
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APW8855
14.4 VR3 Register Table
Addres s
0x05
Fie ld Na me
1V8 _ALW DAC [7:0]
Data B it
D7
D6
D5
D4
R/W
R/W
R/W
R/W
0
0
1
0
Bit Na me
D3
D2
D1
D0
R/W
R/W
R/W
R/W
0
1
0
0
D2
D1
D0
1 V8_ ALW_ VSE L
Read/Write
Po wer On De fa ult
Bit Name
Bit Definition
0 0h : shutdown
0 1h : V R3 Voltage = 1 450mV.
0 2h : V R3 Voltage = 1 460mV.
0 3h : V R3 Voltage = 1 470mV.
1V8_ALW_VSEL
…
2 4h : V R3 Voltage = 1 800mV (Default)
….
5 1h : V R3 Voltage = 2 250mV.
5 2h~ffh : Reserved
Addres s
0x0 6
Fie ld Na me
1V 8_ALW CONTROL [7:0 ]
Data B it
D7
D6
Bit Na me
D5
D4
1V8_ ALW _SLEW
Read/Write
Reserved
Po wer On De fa ult
D3
1 V8_A LW_ 1V 8_A LW_
1V 8_A LW_FSW _SEL
_ SEL
_ EN
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
0
Bit Name
Bit Definition
1V8_ALW__EN
0: V R3 o ff (De fau lt)
1: V R3 o n
1V8_ALW__SEL
0: V R3 o n/off i s controlle d by CTL (Defaul t)
1: V R3 o n/off i s controlle d by 1V 8_ALW_EN State
00 : FSW = 3.0MHz at PWM mod e.
1V8_ALW_FSW_S EL
1V8ALW _SLEW
01 : FSW = 2.0MHz at PWM mod e. (Defau lt)
10 : FSW = 1.0MHz at PWM mod e.
11 : FSW = 4.0MHz a t PWM mode.
00 : Transition sl ew ra te = 1 0mV/us. (Default)
01 : Transition sl ew ra te = 1 5mV/us.
10 : Transition sl ew ra te = 2 0mV/us.
11 : Tra nsitio n sle w rate = 25mV /u s
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APW8855
14.5 VR4 Register Table
Addres s
0x07
Fie ld Na me
1V5 _ALW DAC [7:0]
Data B it
D7
D6
D5
D4
R/W
R/W
R/W
R/W
0
1
0
0
Bit Na me
D3
D2
D1
D0
R/W
R/W
R/W
R/W
0
1
1
1
D2
D1
D0
1 V5_ ALW_ VSE L
Read/Write
Po wer On De fa ult
Bit Name
Bit Definition
0 0h : shutdown
0 1h : V R4 Voltage = 8 00mV.
0 2h : V R4 Voltage = 8 10mV.
0 3h : V R4 Voltage = 8 20mV.
1V5_ALW_VSEL
…
4 7h : V R4 Voltage = 1 500mV (Default)
….
7 9h : V R4 Voltage = 2 000mV.
8 0h~ffh : Reserved
Address
0 x08
Field Nam e
V1V5 _ALW CO NTROL [7:0]
Da ta B it
D7
D6
Bit Name
D5
D4
1V5_A LW_S LEW
Re ad/Write
Reser ved
Power On Defaul t
R/W
0
Bit Na me
D3
1V 5_A LW_ 1V5 _ALW _
1V 5_ALW_FSW _SE L
_S EL
_E N
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
Bit De finition
1V5 _ALW __EN
0 : VR4 off (Default)
1 : VR4 on
1V5 _ALW __SE L
0 : VR4 on/off is con tro lled by CTL (Defa ult)
1 : VR4 on/off is con tro lled by 1V5_ALW_ EN State
0 0 : FSW = 3.0 MHz at PW M mode.
1V5 _ALW _FSW_SEL
1V5 _ALW _SLEW
0 1 : FSW = 2.0 MHz at PW M mode. (Default)
1 0 : FSW = 1.0 MHz at PW M mode.
11 : FSW = 4.0MHz at PWM mod e.
0 0 : Tran si tio n slew rate = 10mV/us. ( De fa ult)
0 1 : Tran si tio n slew rate = 15mV/us.
1 0 : Tran si tio n slew rate = 20mV/us.
11: Transition slew r ate = 25mV/us
Copyright  ANPEC Electronics Corp.
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APW8855
14.6 VR5 Register Table
Address
0 x09
Field Name
VDDP_ ALW DAC [7: 0]
Da ta B it
D7
D6
D5
D4
Bit Name
D3
D2
D1
D0
V DDP_ALW_VS EL
Re ad/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
1
1
0
D2
D1
D0
Power On Defaul t
Bit Na me
Bit De finition
00 h : shutdown
01 h : VR5 Voltage = 50 0mV.
02 h : VR5 Voltage = 51 0mV.
03 h : VR5 Voltage = 52 0mV.
VDDP_A LW_V SEL
…
2e h : VR5 Voltage = 95 0mV (De fa ult)
….
65 h : VR5 Voltage = 15 00mV.
66 h~ffh : Reserved
Addres s
0x 0A
Fie ld Na me
V DDP_ALW CO NTROL [7:0]
Data B it
D7
D6
Bit Na me
D5
D4
VDDP_ ALW_S LEW
Read/Write
Reserved
Po wer On De fa ult
D3
V DDP_ALW_FSW
_SE L
VDDP_A L VDDP _AL
W__ SEL
W__ EN
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
Bit Name
Bit Definition
VDDP_ ALW_EN
0: V R5 o ff (De fau lt)
1: V R4 o n
VDDP_ ALW_SEL
0: V R5 o n/off i s controlle d by CTL, an d o utput voltage is control by VDDP_ ALW_ GPIO. (Defa ult)
1: V R5 o n/off i s controlle d by VDDP_A LW_E N State a nd output vo ltag e i s control by
VDDP_ALW_VSEL.
VDDP_ ALW_ FSW _SEL
VDDP_ ALW_SLEW
00 : FSW = 0.3MHz at PWM mod e.
01 : FSW = 0.6MHz at PWM mod e.
10 : FSW = 0.5MHz at PWM mod e. (Defau lt)
11 : FSW = 0.8MHz a t PWM mode.
00 : Transition sl ew ra te = 1 0mV/us. (Default)
01 : Transition sl ew ra te = 1 5mV/us.
10 : Transition sl ew ra te = 2 0mV/us.
11 : Tra nsitio n sle w rate = 25mV /u s
Copyright  ANPEC Electronics Corp.
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APW8855
14.7 VR6 Register Table
Address
0x0B
Field Name
V DD_ FCH_S 5 DAC [7 :0]
Da ta B it
D7
D6
D5
D4
Bit Name
D3
D2
D1
D0
VDD_ FCH_S5_VSEL
Re ad/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
1
0
1
D2
D1
D0
Power On Defaul t
Bit Na me
Bit De finition
00 h : shutdown
01 h : VR7 Voltage = 50 0mV.
02 h : VR7 Voltage = 51 0mV.
03 h : VR7 Voltage = 52 0mV.
VDD_FCH_ S5_VSEL
…
1d h : VR7 Voltage = 78 0mV (De fa ult)
….
65 h : VR7 Voltage = 15 00mV.
66 h~ffh : Reserved
Address
0x0C
Field Nam e
Da ta B it
V DD_FCH_S 5 CONTROL [7:0]
D7
D6
D5
D4
D3
VDD_FCH VDD_FCH
_ S5_ SEL
_S5_ EN
Bit Name
Re ad/Write
Reser ved
Reserved
Power On Defaul t
Bit Na me
R/W
R/W
0
0
Bit De finition
VDD_FCH_ S5_EN
0 : VR7 off (Default)
1 : VR7 on
VDD_FCH_ S5_SEL
0 : VR7 on/off is con tro lled by CTL. (Defa ult)
1 : VR7 on/off is con tro lled by VDD_ FCH_S 5_EN State.
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APW8855
14.8 Thermal Report Register Table
Address
0x2C
Field Name
THE RMAL RE PORT[7:0 ]
Da ta B it
D7
D6
D5
D4
D3
R
R
-
-
Bit Name
D2
D1
D0
R
R
R
-
-
-
D2
D1
D0
THE RMAL REPORT
Re ad/Write
Reser ved
Power On Defaul t
Bit Na me
Bit De finition
00 000 : - 10℃
00 001 : - 5℃
Th ermal Repo rt
00 010 : 0 ℃
…
01 000 : 3 0℃
…
11110 : 1 40℃
11111 : 145℃
14.9 POK BLANKING Time Register Table
Address
0x 26
Field Name
POK BLANKING TIME [7 :0]
Da ta B it
D7
D6
D5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
1
0
1
D2
D1
D0
Bit Name
D4
D3
PO K BLANK ING TIME
Re ad/Write
Power On Defaul t
Bit Nam e
Bit De finition
00 h : 320 us
01 h : 328 us
02 h : 336 us
POK B lanking Time
…
7d h : 132 0us ( De fau lt)
….
ffh : 2 360u s
14.10 Version ID Register
Address
0x F0
Field Name
V ERSION ID [7:0]
Da ta B it
D7
D6
D5
Bit Name
D4
D3
VERSION ID [7:0]
Re ad/Write
R
R
R
Ve rsion A Defa ult
0
0
0
Bit Na me
VERSION ID
R
R
R
R
R
0
0
0
0
0
Bit De finition
V ERSION ID
00 h:Ve rson A
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APW8855
15.Function Description
15.1 VR Function Description
Soft-Start
All VRs are equipped soft-start function, when enable signal of each VR is activated, an internal soft start ramps the
output voltage at a rate of 10mV/usec. This allows the output voltage to ramp up gradually, eliminating overshoot and
excessive in rush current.
Over Voltage Protection (OVP) for VR3 and VR4
The over voltage protection circuitry monitors the feedback voltage to prevent the output from accidently exceeding the
desired set point. Once the feedback voltage exceeds typically 130% of the set point voltage, the high side MOSFET
turn off, Low side MOSFET turns off and internal latch circuitry is activated. This insures protection of the load damage
and circuit reset is only achieved either by internal reset via the I2C, CTL or by cycling the power.
Over Current Protection (OCP) and Under Voltage Protection (UVP) for VR3 and VR4
The switching converter is protected against gradual over current or sudden short on its output. When inductor current
peak value exceeds the set threshold an internal over-current protection is activated which turns off the high side and
low side MOSFETs.
Once the output voltage drops below a typical threshold of 70% of the output set point value, both high side and low
side MOSFETs turn off and an internal latch circuit is initiated.
When any of OCP or UVP is activated, the IC will be latch off, need reset via the I2C, CTL or by cycling the power.
Over Voltage Protection (OVP) and Under Voltage Protection (UVP) for VR1, VR2 and VR5
Once the output voltage drops below a typical threshold of 70% of set point value or the output voltage exceeds typically
130% of the set point voltage, the PWM signal will be latched low to turn off the converter and discharge the output
voltage.
When any of UVP or OVP is activated, need reset via CTL or by cycling the power.
Soft-Stop
When VR3 or VR4 is shut down by CTL or I2C, both Upper and Lower MOSFETs will be turned off and an internal
MOSFET with about 10ohm (Typ.) Rds-on discharges the output via the FBP pin. The VR7 also discharges the output
via the output pin.
When VR1, VR2, VR5 is shut down by CTL or I2C, the PWM signal pin will be low level to discharge the output voltage
via the low-side MOSFET of APW8703.
VDD_FCH_S5 Output Voltage
The VDD_FCH_S5 output voltage level will be changed between internal fixed LDO regulator and external REFIN input
voltage, and it depends on S5_MUX signal and the REFIN voltage level. When MUX_S5 is high, the FCH_S5 output
voltage will follow the REFIN input voltage. When MUX_S5 is low, REFIN input voltage is below 0.78mV, FCH_S5
output voltage will change to internal LDO regulator. When MUX_S5 is low, and REFIN input voltage is above 0.78mV,
FCH_S5 output voltage will follow the REFIN input voltage. Below table shows the FCH_S5 output voltage operation.
MUX_S5
REFIN
VDD_FCH_S5 Output
H
X
L
<0.78V
Internal LDO regulator Output
L
≧0.78V
Track REFIN Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
Track REFIN Voltage
31
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APW8855
15.1 VR Function Description(Cont.)
POK Output
The POK circuitry monitors the VR1-VR5 via the FB pins of each regulator to make sure that the output of each
regulator has reached its desired set point during the start up. When all these voltages have reached 90% of their set
point, then POK will switch from a low state to high after a 1 ms delay time. The POK pin is an open drain output that
will switch high via an external pull up resistor. It can be pulled up to a maximum voltage of up to 5.5V.
The POK also monitors the FB voltage for any over voltage that may happen during the operation. This threshold is
typically set at 130% of the desired set point. If any of the voltages exceeds this threshold and satisfied the blanking
time the POK switches low and after a short delay of about 2usec or so, the outputs latch off and system returns to G3
state.
During the power down or at any point either of these VR1-VR5, output voltages drop below 90% typical set point and
continue over blanking time, the POK pin switches to low state again.
15.2 I2C Function Description
I2C Overview
APW8855 is a slave-only device that is mastered by the SoC. It resides off the SoC’s I2C. The slave device implemented on APW8855 side is an asynchronous implementation and will support the high speed mode (3.4MHz).
Some of the main features for the I2C slave are:
•
APW8855 is accessed using a 7-bit addressing scheme.
•
I2C slave is not allowed to stretch the clock, and must be capable of being multi-mastered in a debug
environment.
•
The interface draws as minimum power when not actively reading/writing registers.
•
The slave adapts to the incoming frequency without any communication as the protocol for fast mode and
high speed mode is the same.
•
Interface implementation is asynchronous.
Slave Address
APW8855 supports the standard I2C read and write functions. The configuration register space is divided to 59-byte
partitions. APW8855 supports five 7-bit device addresses to access each of the 59 byte partitions.
Slave Address
11 0111 0
Table 5. I2C Slave Addresses
The slave addresses need to be locked in order to avoid that software can overwrite them and disable the
communication.
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APW8855
15.2 I2C Function Description(Cont.)
Protocol
Reads from PMIC registers follow the “combined protocol” as described in the I2C specification, in which the first byte
written is the register offset to be read, and the first byte read (after a repeat START condition) is the data from that
register offset. See the figures below for details. The following diagrams capture the different high-speed and fastspeed transaction format/protocol.
S
7bit Slave
Address
R/W
7'h6E
‘0’
A
8bit Address
8bit Data
A
Reg. Address
A
P
Reg. Data
A=
Master to Slave
Slave to Master
Acknowledge
( SDA LOW
A=
Not Acknowledge
S=
START Condition
P=
STOP Condition
)
( SDA HIGH
)
Figure 1. I2C Fast Speed / Fast Speed Plus Single Byte Write
7bit Slave
Address
S
7'h 6E
R/W
A
8bit Reg.
Address
8bit Data
A
‘0’
A
8bit Data
Reg. First Byte
Data
Master to Slave
A=
Slave to Master
P
A
P
Reg. Last Byte
Data
Acknowledge
A=
A
( SDA LOW
Not Acknowledge
S=
START Condition
P=
STOP Condition
)
( SDA HIGH
)
Figure 2. I2C Fast Speed / Fast Speed Plus Multiple Byte Write
S
7bit Slave
Address
R/W
7'h 6E
‘0’
A
8bit Address
A
Sr
Reg. Address
7bit Slave
Address
R/W
7'h 6E
‘1’
A=
Master to Slave
Slave to Master
Acknowledge
Reg. Data
( SDA LOW
A=
Not Acknowledge
S=
START Condition
Sr =
P=
8bit Data
A
)
( SDA HIGH
)
Repeated START Condition
STOP Condition
Figure 3. I2C Fast Speed / Fast Speed Plus Single Byte Read
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APW8855
15.2 I2C Function Description(Cont.)
S
7bit Slave
Address
R/W
7'h6E
‘0’
A
8bit
Address
A
Sr
Reg . Address
7bit Slave
Address
R/W
7'h6E
‘1’
Master to Slave
8bit Data
A
8bit Data
Acknowledge
( SDA LOW
A=
Not Acknowledge
S=
START Condition
Sr =
P
A
Reg. Last
Byte Data
Reg. First
Byte Data
A=
Slave to Master
A
)
( SDA HIGH
)
Repeated START Condition
P=
STOP Condition
Figure 4. I2C Fast Speed / Fast Speed Plus Multiple Byte Read
S
Fast Speed
(400kHz)
8bit Master Code
“0000 1XXX”
High Speed
(3.4MHz)
A
Sr
7bit Slave
Address
R/W
7'h6E
‘0’
A
8bit
Address
A
Reg. Address
A=
Master to Slave
Slave to Master
8bit
Data
A
Reg. Data
Acknowledge
( SDA LOW
A=
Not Acknowledge
S=
START Condition
Sr =
P
)
( SDA HIGH
)
Repeated START Condition
P=
STOP Condition
Figure 5. I2C High Speed Single Byte Write
Fast Speed
(400kHz)
8bit Master Code
7bit Slave
R/W A
S
A Sr
“0000 1XXX”
Address
7'h 6E
‘0’
High Speed
(3.4MHz)
8bit
Address
Reg.
.
Address
A
8bit
Data
A
Reg. First
Byte Data
8bit
Data
A
P
Reg. Last
Byte Data
A= Acknowledge ( SDA LOW )
Master to Slave
A= Not Acknowledge ( SDA HIGH )
Slave to Master
S= START Condition
Sr=Repeated Start Condition
P= STOP Condition
Figure 6. I2C High Speed Multiple Byte Write
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APW8855
15.2 I2C Function Description(Cont.)
S
Fast Speed
(400kHz)
8bit Master Code
“0000 1XXX”
High Speed
(3.4MHz)
A
Sr
7bit Slave
Address
R/W
7'h6E
‘0’
A
8bit
Address
A
Sr
7bit Slave
Address
R/W
7'h6E
‘1’
Reg. Address
A=
Master to Slave
Slave to Master
Acknowledge
Not Acknowledge
S=
START Condition
P=
A
P
Reg. Data
( SDA LOW
A=
Sr =
8bit
Data
A
)
( SDA HIGH
)
Repeated START Condition
STOP Condition
Figure 7. I2C High Speed Single Byte Read
Fast Speed
(400kHz)
S
High Speed
(3.4MHz)
8bit Master Code
7bit Slave
A Sr
R/W A
“0000 1XXX”
Address
7'h 6E
‘0’
8bit
Address
A Sr
Reg.
.
Address
7bit Slave
R/W A
Address
7'h 6E
‘1’
8bit
Data
8bit
Data
A
Reg. First
Byte Data
A
P
Reg. Last
Byte Data
A= Acknowledge ( SDA LOW )
Master to Slave
A= Not Acknowledge ( SDA HIGH )
Slave to Master
S= START Condition
Sr=Repeated Start Condition
P= STOP Condition
Figure 8. I2CHigh Speed Multiple Byte Read
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APW8855
16.Application Information
Output Voltage Selection
The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage is
fixed, it can be written as:
D=
VOUT
VIN
For PWM converter, the inductor value (L) determines the sum of the inductor ripple currents Δ IP-P, and affects the load
d
transient response. Higher inductor value reduces the output capacitors¡¦ ripple current and induces lower output
ripple voltage. The ripple current can be approximated by:
ΔIP - P =
VIN − VOUT
FSw × L
×
VOUT
VIN
Where FSW is the switching frequency of the regulator, although the inductor value and frequency are increased and the
ripple current and voltage are reduced, a tradeoff exists between the inductor¡¦s ripple current and the regulator load
transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of
higher ripple current. Increasing the switching frequency (FSW ) also reduces the ripple current and voltage, but it will
increase the switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current
occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of
the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of
carrying the required peak current without going into saturation. In some types of inductors, especially core that is
made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage.
Output Capacitor Selection
Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when
selecting output capacitors. Higher capacitor value and lower ESR reduce the output ripple and the load transient drop.
Therefore, selecting high performance low ESR capacitors is recommended for switching regulator applications. In
addition to high frequency noise related to MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop ΔVCOUT and ESR voltage drop ΔVESR caused by the AC peak-to-peak sum of the inductor’s current. The
ripple voltage of output capacitors can be represented by:
ΔV COUT =
ΔIP − P
8 × COUT × FSw
ΔVESR = ΔIP − P × RESR
These two components constitute a large portion of the total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support another
load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR and suppress the
voltage ripple to a tolerable level. A small decoupling capacitor in parallel for bypassing the noise is also recommended,
and the voltage rating of the output capacitors are also must be considered. To support a load transient that is faster
than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change.
For getting same load transient response, another aspect of the capacitor selection is that the total AC current going
through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the
capacitor from overheating.
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APW8855
16.Application Information(Cont.)
Input Capacitor Selection
Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed
each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and
between the drain of high-side MOSFET and the source of low-side MOSFET. The important parameters for the bulk
input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with
voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The
capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of
1.5 times is a conservative guideline. The maximum RMS current rating requirement is approximately I OUT/2, where IOUT
is the load current.
Layout Consideration
S ignal Nam e
De scription
La yout G uidelines
GND
IC’s analog ground.
Connect the GND pin to GND plane through
several vias directly.
1V5_ALW_PGND,and
1V8_ALW_PGND
IC’s power ground pins of VR3
and VR4.
Use a ground plane or a short and wide trace
to connect the ground terminals of input
capacitors and output capacitors, and
1Vx_ALW_PGND pins on top layer.
Each of VR’s Input Pins
All VR’s input voltage pins.
Place the input capacitors on each of the VR’s
input pins with low impedance to GND and low
impedance to the each of VR’s input pins.
These are the connections to the
mid point of the power stage
consisting of the high- and
low-side switch. The output
inductor is connected here.
Connect to the output inductor with a short
wire. For higher efficiency requirement, the
inductor and LX pins should be as close as
possible, and the trace resistance from LX pin
to inductor should be less than 10mOhm is
recommended.
(VSYS, 1V8_ALW_IN...)
Each of PWM VR’s LX pins
(5V_ALW_LX1,
1V8_ALW_LX…)
Ideally, route the high current path like LX pins
to inductors and inductors to output capacitors
on the top layer is recommended.
Each of PWM VR’s output
voltage feedback pins
Voltage feedback pin for each of
VR.
(5V_ALW_FBP,
1V8_ALW_FBP…)
The pins are high impedance and sensible to
noise from the switch node. The positive
feedback signal should be tied to the V+ pad
of the output capacitor directly.
The feedback pin could be routed to the input
capacitor on the load side for remote sense.
Coupling from fast switching signals must be
avoided.
VSYS
APW8855 input supply voltage
Connect the input capacitors from VSYS to
GND for noise decoupling. The capacitors and
VSYS pins should be as close as possible.
5V_ALW_PWM,
3V3_ALW_PWM,
VDDP_ALW_PWM
The gate driver outputs of
5V_ALW,
3V3_ALW
and
VDDP_ALW
The traces of PWM signal from the gate driver
output pins to the APW8703 should be short to
eliminate the parasitical capacitance; the
parasitical capacitance less than 80pF is
recommended.
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APW8855
17.Revision History
Version
Date
Revision History
A1
-
Chapter
-
Description
Initial description
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APW8855
18.Package Information
D
A
b
E
TQFN4x4-32A
Pin 1
D1
A1
A3
NX
aaa C
E1
SEATING PLANE
L
K1
Pin 1 Corner
e
K
S
Y
M
B
O
L
TQFN4*4-32A
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.15
0.25
0.006
0.010
D
3.90
4.10
0.154
0.161
D1
1.20
1.50
0.047
0.059
E
3.90
4.10
0.154
0.161
E1
1.30
1.60
0.051
0.063
e
L
0.40 BSC
0.25
0.016 BSC
0.010
0.45
0.018
K
1.02 REF
0.040 REF
K1
0.93 REF
0.037 REF
aaa
0.08
0.003
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APW8855
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
T1
C
d
D
330.0±2.00
50 MIN.
12.4+2.00
-0.00
1 3.0+0 .50
-0.20
1.5 MIN.
20 .2 MIN.
P0
P1
P2
D0
D1
4.0±0.10
8 .0 ±0 .1 0
2.0±0.05
1.5+0.10
-0 .00
1.5 MIN.
TQFN4x4
T
0.6+0.00
-0.40
W
E1
1 2.0 ±0 .3 0 1 .7 5±0.10
F
5.5±0.05
A0
B0
K0
4 .30 ±0 .2 0
4.30±0.20
1 .3 0±0.2 0
( mm)
Devices Per Unit
P acka ge Type
Unit
Quantity
TQ FN4 x4
Ta pe & Reel
30 00
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APW8855
Taping Direction Information
TQFN4x4-32
USER DIRECTION OF FEED
Classification Profile
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APW8855
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
20** seconds
30** seconds
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax )
Time (T smin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time (tP)** within 5°C of the specified
classification temperature (Tc )
Average ramp-down rate (T p to Tsma x)
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm3
≥350
220 °C
220 °C
Volume mm3
<350
235 °C
220 °C
Package
Thickness
<2.5 mm
≥2.5 mm
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm3
<350
260 °C
260 °C
250 °C
Volume mm3
350-2000
260 °C
250 °C
245 °C
Volume mm3
>2000
260 °C
245 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW8855
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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