IDT IDT23S08-2HDC

IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
FEATURES:
IDT23S08
DESCRIPTION:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT23S08-1 1x
– IDT23S08-2 1x, 2x
– IDT23S08-3 2x, 4x
– IDT23S08-4 2x
– IDT23S08-1H, -2H, and -5H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Spread spectrum compatible
• Available in SOIC and TSSOP packages
The IDT23S08 is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT23S08 has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08 enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than 25µA
for Industrial temperature range, and the outputs are tri-stated.
The IDT23S08 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08 is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
FBK
16
2
2
CLKA1
PLL
1
2
(-5)
REF
3
CLKA2
14
CLKA3
15
CLKA4
S2
S1
8
9
Control
Logic
(-2, -3)
2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OCTOBER 2003
1
c
2003
Integrated Device Technology, Inc.
DSC 6394/8
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Rating
Supply Voltage Range
–0.5 to +4.6
V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5
V
VI
Input Voltage Range
–0.5 to
V
IIK (VI < 0)
Input Clamp Current
–50
mA
IO
Continuous Output Current
±50
mA
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
–65 to +150
°C
0 to +70
°C
-40 to +85
°C
1
16
FBK
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
6
11
CLKB4
CLKB3
TSTG
Storage Temperature Range
S1
Operating
Commercial Temperature
Temperature
Range
Operating
Industrial Temperature
Temperature
Range
7
10
S2
8
9
(except REF)
(in still air)(3)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
PIN DESCRIPTION
1
Input Reference Clock, 5 Volt Tolerant Input
CLKA1(2)
2
Clock Output for Bank A
CLKA2
3
Clock Output for Bank A
4
3.3V Supply
(2)
VDD
GND
5
Ground
(2)
6
Clock Output for Bank B
CLKB2(2)
7
Clock Output for Bank B
S2(3)
8
Select Input, Bit 2
CLKB1
S1(3)
of 150°C and a board trace length of 750 mils.
Functional Description
REF (1)
9
Select Input, Bit 1
CLKB3
(2)
10
Clock Output for Bank B
CLKB4
(2)
11
Clock Output for Bank B
GND
12
Ground
VDD
13
3.3V Supply
CLKA3(2)
14
Clock Output for Bank A
CLKA4(2)
15
Clock Output for Bank A
FBK
16
PLL Feedback Input
VDD+0.5
(VO = 0 to VDD)
SOIC/ TSSOP
TOP VIEW
Pin Number
Unit
VDD
REF
CLKB2
Max.
APPLICATIONS:
•
•
•
•
•
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
2
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1) SELECT INPUT DECODING
S2
S1
CLK A
CLK B
Output Source
PLL Shut Down
L
L
Tri-State
Tri-State
PLL
Y
L
H
Driven
Tri-State
PLL
N
H
L
Driven
Driven
REF
Y
H
H
Driven
Driven
PLL
N
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
AVAILABLE OPTIONS FOR IDT23S08
Device
Feedback From
Bank A Frequency
Bank B Frequency
IDT23S08-1
Bank A or Bank B
Reference
Reference
IDT23S08-1H
Bank A or Bank B
Reference
Reference
IDT23S08-2
Bank A
Reference
Reference/2
IDT23S08-2
Bank B
2 x Reference
Reference
IDT23S08-2H(1)
Bank A
Reference
Reference/2
IDT23S08-2H(1)
Bank B
2 x Reference
Reference
IDT23S08-3(1)
Bank A
2 x Reference
Reference or Reference(2)
IDT23S08-3(1)
Bank B
4 x Reference
2 x Reference
IDT23S08-4
Bank A or Bank B
2 x Reference
2 x Reference
IDT23S08-5H
Bank A or Bank B
Reference/2
Reference/2
NOTES:
1. Contact factory for availability.
2. Output phase is indeterminant (0° or 180° from input clock).
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
3
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT23S08, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
OPERATING CONDITIONS- COMMERCIAL
Symbol
Parameter
Min.
Max.
Unit
3
3.6
V
Operating Temperature (Ambient Temperature)
0
70
°C
Load Capacitance below 100MHz
—
30
pF
Load Capacitance from 100MHz to 133MHz
—
15
pF
Input Capacitance
—
7
pF
VDD
Supply Voltage
TA
CL
CIN
Test Conditions
(1)
NOTE:
1. Applies to both REF and FBK.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
Min.
Typ.(1)
Max.
Unit
VIL
Input LOW Voltage Level
—
—
0.8
V
VIH
Input HIGH Voltage Level
2
—
—
V
IIL
Input LOW Current
—
—
50
µA
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
—
—
100
µA
VOL
Output LOW Voltage
IOL = 8mA (-1, -2, -3, -4)
—
—
0.4
V
VOH
Output HIGH Voltage
IOH = -8mA (-1, -2, -3, -4)
2.4
—
—
V
µA
IOL = 12mA (-1H, -2H, -5H)
IOH = -12mA (-1H, -2H, -5H)
IDD_PD
IDD
Power Down Current
Supply Current
REF = 0MHz (S2 = S1 = H)
—
—
12
100MHz CLKA (-1, -2, -3, -4)
—
—
45
100MHz CLKA (-1H, -2H, -5H)
—
—
70
Unloaded Outputs
66MHz CLKA (-1, -2, -3, -4)
—
—
32
Select Inputs at VDD or GND
66MHz CLKA (-1H, -2H, -5H)
—
—
50
4
33MHz CLKA (-1, -2, -3, -4)
—
—
18
33MHz CLKA (-1H, -2H, -5H)
—
—
30
mA
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
t1
Output Frequency
30pF Load, all devices
Min.
Typ.
Max.
Unit
10
—
100
MHz
t1
Output Frequency
20pF Load, -1H, -2H, -5H Devices(1)
10
—
133.3
MHz
t1
Output Frequency
15pF Load, -1, -2, -3, -4 devices
10
—
133.3
MHz
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
(-1, -2, -3, -4, -1H, -2H, -5H)
30pF Load
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 50MHz
45
50
55
%
(-1, -2, -3, -4, -1H, -2H, -5H)
15pF Load
t3
Rise Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 30pF Load
—
—
2.2
ns
t3
Rise Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 15pF Load
—
—
1.5
ns
t3
Rise Time (-1H, -2H, -5H)
Measured between 0.8V and 2V, 30pF Load
—
—
1.5
ns
t4
Fall Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 30pF Load
—
—
2.2
ns
t4
Fall Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 15pF Load
—
—
1.5
ns
t4
Fall Time (-1H, -5H)
Measured between 0.8V and 2V, 30pF Load
—
—
1.25
ns
t5
Output to Output Skew on same Bank
All outputs equally loaded
—
—
200
ps
Output to Output Skew (-1H, -2H, -5H)
All outputs equally loaded
—
—
200
ps
Output Bank A to Output Bank B (-1, -4, -2H, -5H)
All outputs equally loaded
—
—
200
ps
Output Bank A to Output Bank B Skew (-2, -3)
All outputs equally loaded
—
—
400
ps
t6
Delay, REF Rising Edge to FBK Rising Edge
Measured at VDD/2
—
0
±250
ps
t7
Device to Device Skew
Measured at VDD/2 on the FBK pins of devices
—
0
700
ps
t8
Output Slew Rate
Measured between 0.8V and 2V on -1H, -2H, -5H
1
—
—
V/ns
tJ
Cycle to Cycle Jitter
Measured at 66.67 MHz, loaded outputs, 15pF Load
—
—
200
(-1, -1H, -4, -5H)
Measured at 66.67 MHz, loaded outputs, 30pF Load
—
—
200
Measured at 133.3 MHz, loaded outputs, 15pF Load
—
—
100
Measured at 66.67 MHz, loaded outputs, 30pF Load
—
—
400
(-1, -2, -3, -4)
device using Test Circuit 2
tJ
tLOCK
Cycle to Cycle Jitter
(-2, -2H, -3)
Measured at 66.67 MHz, loaded outputs, 15pF Load
—
—
400
PLL Lock Time
Stable Power Supply, valid clocks presented
—
—
1
on REF and FBK pins
NOTE:
1. IDT23S08-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67MHz.
5
ps
ps
ms
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS- INDUSTRIAL
Symbol
Parameter
Min.
Max.
Unit
3
3.6
V
Operating Temperature (Ambient Temperature)
-40
+85
°C
Load Capacitance below 100MHz
—
30
pF
Load Capacitance from 100MHz to 133MHz
—
15
pF
Input Capacitance
—
7
pF
VDD
Supply Voltage
TA
CL
CIN
Test Conditions
(1)
NOTE:
1. Applies to both REF and FBK.
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol
Parameter
Conditions
Min.
Typ.(1)
Max.
Unit
—
—
0.8
V
VIL
Input LOW Voltage Level
VIH
Input HIGH Voltage Level
2
—
—
V
IIL
Input LOW Current
VIN = 0V
—
—
50
µA
IIH
Input HIGH Current
VIN = VDD
—
—
100
µA
VOL
Output LOW Voltage
IOL = 8mA (-1, -2, -3, -4)
—
—
0.4
V
2.4
—
—
V
—
—
25
µA
100MHz CLKA (-1, -2, -3, -4)
—
—
45
100MHz CLKA (-1H, -2H, -5H)
—
—
70
IOL = 12mA (-1H, -2H, -5H)
VOH
Output HIGH Voltage
IOH = -8mA (-1, -2, -3, -4)
IOH = -12mA (-1H, -2H, -5H)
IDD_PD
IDD
Power Down Current
Supply Current
REF = 0MHz (S2 = S1 = H)
Unloaded Outputs
66MHz CLKA (-1, -2, -3, -4)
—
—
32
Select Inputs at VDD or GND
66MHz CLKA (-1H, -2H, -5H)
—
—
50
33MHz CLKA (-1, -2, -3, -4)
—
—
18
33MHz CLKA (-1H, -2H, -5H)
—
—
30
6
mA
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS - INDUSTRIAL
Symbol
Parameter
Conditions
t1
Output Frequency
30pF Load, all devices
t1
Output Frequency
20pF Load, -1H, -2H, -5H Devices
t1
Output Frequency
15pF Load, -1, -2, -3, -4 devices
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
(-1, -2, -3, -4, -1H, -2H, -5H)
30pF Load
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 50MHz
(1)
Min.
Typ.
Max.
Unit
10

100
MHz
10

133.3
MHz
10

133.3
MHz
40
50
60
%
45
50
55
%
(-1, -2, -3, -4, -1H, -2H, -5H)
15pF Load
t3
Rise Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 30pF Load


2.2
ns
t3
Rise Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 15pF Load


1.5
ns
t3
Rise Time (-1H, -2H, -5H)
Measured between 0.8V and 2V, 30pF Load


1.5
ns
t4
Fall Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 30pF Load


2.2
ns
t4
Fall Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 15pF Load


1.5
ns
t4
Fall Time (-1H, -5H)
Measured between 0.8V and 2V, 30pF Load


1.25
ns
t5
Output to Output Skew on same Bank
All outputs equally loaded


200
ps
Output to Output Skew (-1H, -2H, -5H)
All outputs equally loaded


200
ps
Output Bank A to Output Bank B (-1, -4, -2H, -5H)
All outputs equally loaded


200
ps
Output Bank A to Output Bank B Skew (-2, -3)
All outputs equally loaded


400
ps
t6
Delay, REF Rising Edge to FBK Rising Edge
Measured at VDD/2

0
±250
ps
t7
Device to Device Skew
Measured at VDD/2 on the FBK pins of devices

0
700
ps
t8
Output Slew Rate
Measured between 0.8V and 2V on -1H, -2H, -5H
1


V/ns


200
(-1, -2, -3, -4)
device using Test Circuit 2
tJ
tJ
tLOCK
Cycle to Cycle Jitter
Measured at 66.67 MHz, loaded outputs, 15pF Load
(-1, -1H, -4, -5H)
Measured at 66.67 MHz, loaded outputs, 30pF Load


200
Measured at 133.3 MHz, loaded outputs, 15pF Load


100
Cycle to Cycle Jitter
Measured at 66.67 MHz, loaded outputs, 30pF Load


400
(-2, -2H, -3)
Measured at 66.67 MHz, loaded outputs, 15pF Load


400
PLL Lock Time
Stable Power Supply, valid clocks presented


1
on REF and FBK pins
NOTE:
1. IDT23S08-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67MHz.
7
ps
ps
ms
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING WAVEFORMS
t1
t2
1.4V
1.4V
1.4V
Duty Cycle Timing
Output
0.8V
2V
0.8V
2V
0V
t4
t3
All Outputs Rise/Fall Time
1.4V
Output
3.3V
1.4V
Output
t5
Output to Output Skew
VDD/2
Input
VDD/2
FBK
t6
Input to Output Propagation Delay
VDD/2
FBK, Device 1
VDD/2
FBK, Device 2
t7
Device to Device Skew
8
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS
TEST CIRCUIT 1
VDD
VDD
0.1µF
TEST CIRCUIT 2
OUTPUTS
CLKOUT
0.1µF
1KΩ
CLKOUT
OUTPUTS
CLOAD
1KΩ
10pF
VDD
VDD
0.1µF
0.1µF
GND
GND
GND
GND
Test Circuit for t8, Output Slew Rate On -1H, -2H, and -5H Device
Test Circuit for all Parameters Except t8
9
IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device Type
XX
Package
X
Process
Blank
I
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
DC
DCG
PG
Small Outline
SOIC - Green
Thin Shrink Small Outline Package
23S08-1
23S08-2
23S08-3
23S08-4
23S08-1H
23S08-2H
23S08-5H
}
}
Ordering Code
Zero Delay Clock Buffer with Standard Drive,
Spread Spectrum Compatible
Zero Delay Clock Buffer with High Drive,
Spread Spectrum Compatible
Package Type
Operating Range
IDT23S08-1DC
16-Pin SOIC
Commercial
IDT23S08-1DCG
16-Pin SOIC
Commercial
IDT23S08-1DCI
16-Pin SOIC
Industrial
IDT23S08-1HDC
16-Pin SOIC
Commercial
IDT23S08-1HDCG
16-Pin SOIC
Commercial
IDT23S08-1HDCI
16-Pin SOIC
Industrial
IDT23S08-1HPG
16-Pin TSSOP
Commercial
IDT23S08-1HPGI
16-Pin TSSOP
Industrial
IDT23S08-2DC
16-Pin SOIC
Commercial
IDT23S08-2DCG
16-Pin SOIC
Commercial
IDT23S08-2DCGI
16-Pin SOIC
Industrial
IDT23S08-2DCI
16-Pin SOIC
Industrial
16-Pin SOIC
Commercial
IDT23S08-2HDCI
16-Pin SOIC
Industrial
IDT23S08-3DC(1)
16-Pin SOIC
Commercial
IDT23S08-3DCI
16-Pin SOIC
Industrial
IDT23S08-4DC
16-Pin SOIC
Commercial
IDT23S08-4DCI
16-Pin SOIC
Industrial
IDT23S08-5HDC
16-Pin SOIC
Commercial
IDT23S08-5HDCI
16-Pin SOIC
Industrial
IDT23S08-2HDC
(1)
(1)
(1)
IDT23S08-5HPG
16-Pin TSSOP
Commercial
IDT23S08-5HPGI
16-Pin TSSOP
Industrial
NOTE:
1. Contact factory for availability.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
10
for Tech Support:
[email protected]
(408) 654-6459