Advance Information IDT71P72204 IDT71P72104 IDT71P72804 IDT71P72604 18Mb Pipelined QDR™II SRAM Burst of 2 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description The IDT QDRIITM Burst of two SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with two data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate (QDR) performance. Comparing this with standard SRAM common I/O (CIO), single data rate (SDR) devices, a four to one increase in data access is achieved at equivalent clock speeds. Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The QDRII has a single DDR address bus with multiplexed read and write addresses. All read addresses are received on the first half of the clock cycle and all write addresses are received on the second half of the clock cycle. The read and write enables are received on the first half of the clock cycle. The byte and nibble write signals are received on both halves of the clock cycle simultaneously with the data they are controlling on the data input bus. The QDRII has echo clocks, which provide the user with a clock 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output 2-Word Burst on all SRAM accesses DDR (Double Data Rate) Multiplexed Address Bus One Read and One Write request per clock cycle DDR (Double Data Rate) Data Buses Two word burst data per clock on each port Four word transfers per clock cycle (2 word bursts on 2 ports) Depth expansion through Control Logic HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. Output Impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package JTAG Interface Functional Block Diagram (Note1) D (Note1) DATA REG DATA REG (Note1) K K C CTRL LOGIC (Note2) 18M MEMORY ARRAY CLK GEN (Note4) (Note4) OUTPUT SELECT (Note3) ADD REG OUTPUT REG R W BWx (Note2) SENSE AMPS SA WRITE/READ DECODE WRITE DRIVER (Note1) Q CQ CQ SELECT OUTPUT CONTROL C Notes 6109 drw 16 1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36. 3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2 signal lines. 4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36. MAY 2004 1 ©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ DSC-6109/0C IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range that is precisely timed to the data output, and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. The device is capable of sustaining full bandwidth on both the input and output ports simultaneously. All data is in two word bursts, with addressing capability to the burst level. Clocking The QDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the QDRII has an output “echo” clock, CQ, CQ. The K and K clocks are the primary device input clocks. The K clock is, used to clock in the control signals (R, W and BWx or NWx), the read address, and the first word of the data burst during a write operation. The K clock is used to clock in the control signals (BWx or NWx), write address and the second word of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will also be used to clock the data out of the output register and generate the echo clocks. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the QDRII will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the QDRII SRAM, the DLL will have already internally clocked the first data word to arrive at the device output simultaneously with the arrival of the C clock. The C and second data word of the burst will also correspond. Single Clock Mode The QDRII SRAM may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks. DLL Operation The DLL in the output structure of the QDRII SRAM can be used to closely align the incoming clocks C and C with the output of the data, generating very tight tolerances between the two. The user may disable the DLL by holding Doff low. With the DLL off, the C and C (or K and K if C and C are not used) will directly clock the output register of the SRAM. With the DLL off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. Echo Clock The echo clocks, CQ and CQ, are generated by the C and C clocks (or K, K if C, C are disabled). The rising edge of C generates the rising edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. The echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. Read and Write Operations QDRII devices internally store the two words of the burst as a single, wide word and will retain their order in the burst. There is no ability to address to the single word level or reverse the burst order; however, the byte and nibble write signals can be used to prevent writing any individual bytes, or combined to prevent writing one word of the burst. Read operations are initiated by holding the read port select (R) low, and presenting the read address to the address port during the rising edge of K which will latch the address. The data will then be read and will appear at the device output at the designated time in correspondence with the C and C clocks. Write operations are initiated by holding the write port select (W) low and designating with the Byte Write inputs (BWx) which bytes are to be written (or NWx on x8 devices). The first word of the data must also be present on the data input bus D[X:0]. Upon the rising edge of K the first word of the burst will be latched into the input register. After K has risen, and the designated hold times observed, the second half of the clock cycle is initiated by presenting the write address to the address bus SA[X:0], the BWx (or NWx) inputs for the second data word of the burst, and the second data item of the burst to the data bus D[X:0]. Upon the rising edge of K, the second word of the burst will be latched, along with the designated address. Both the first and second words of the burst will then be written into memory as designated by the address and byte write enables. Output Enables The QDRII SRAM automatically enables and disables the Q[X:0] outputs. When a valid read is in progress, and data is present at the output, the output will be enabled. If no valid data is present at the output (read not active), the output will be disabled (high impedance). The echo clocks will remain valid at all times and cannot be disabled or turned off. During power-up the Q outputs will come up in a high impedance state. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive impedance of the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM to it’s lowest value, the ZQ pin may be tied to VDDQ. 6.42 2 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Pin Definitions Symbol Pin Function D[X:0] Input Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations 2M x 8 -- D[7:0] 2M x 9 -- D[8:0] 1M x 18 -- D[17:0] 512K x 36 -- D[35:0] BW 0, BW 1 BW2, BW 3 Input Synchronous Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks d uring write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding b yte of data to be ignored and not written in to the device. 2M x 9 -- BW 0 controls D[8:0] 1M x 18 -- BW 0 controls D[8:0] and BW 1 controls D[17:9] 512K x 36 -- BW 0 controls D[8:0], BW 1 controls D[17:9], BW 2 controls D[26:18] and BW 3 controls D[35:27] NW0, NW1 Input Synchronous Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the device. SA Input Synchronous Q[X:0] Output Synchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the Read port is deselected, Q[X:0] are automatically three-stated. W Input Synchronous Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[X:0] to be ignored. R Input Synchronous Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfer. C Input Clock Description Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of K clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs are ignored when the appropriate port is deselected. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Input Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K. Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data thro ugh Q[X:0] when in single clock mode. K CQ, CQ Output Clock ZQ Input Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running and do not stop when the output data is tri-stated. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. 6109 tbl 02a 6.42 3 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Pin Definitions continued Symbol Pin Function Description DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured. The propagation delay is not a tested parameter, but will be similar to the propagation delay of other SRAM devices in this speed grade. Doff Input TDO Output TDO pin for JTAG TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. An internal resistor will pull TDI to V DD when the pin is unconnected. TMS Input TMS pin for JTAG. An internal resistor will pull TMS to V DD when the pin is unconnected. NC No Connect No connects inside the package. Can be tied to any voltage level VREF Input Reference Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. VDD Power Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply. VSS Ground Ground for the device. Should be connected to ground of the system. VDDQ Power Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage. 6109 tbl 02b 6.42 4 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Pin Configuration 2M x 8 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/ SA (2) SA W NW 1 K NC R SA VSS/ SA (1) CQ B NC NC NC SA NC K NW 0 SA NC NC Q3 C NC NC NC VSS SA SA SA V SS NC NC D3 D NC D4 NC VSS VSS VSS VSS V SS NC NC NC E NC NC Q4 V DDQ VSS VSS VSS VDDQ NC D2 Q2 F NC NC NC V DDQ VDD VSS VDD VDDQ NC NC NC G NC D5 Q5 V DDQ VDD VSS VDD VDDQ NC NC NC H Doff V REF VDDQ V DDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC V DDQ VDD VSS VDD VDDQ NC Q1 D1 K NC NC NC V DDQ VDD VSS VDD VDDQ NC NC NC L NC Q6 D6 V DDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS V SS NC NC D0 N NC D7 NC VSS SA SA SA V SS NC NC NC P NC NC Q7 SA SA C SA SA NC NC NC R TDO TCK SA SA SA C SA SA SA TMS TDI 6109 tbl 12 165-ball FBGA Pinout TOP VIEW NOTES: 1. A10 is reserved for the 36Mb expansion address. 2. A2 is reserved for the 72Mb expansion address. 6.42 5 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Pin Configuration 2M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/ SA (2) SA W NC K NC R SA VSS/ SA (1) CQ B NC NC NC SA NC K BW SA NC NC Q3 C NC NC NC VSS SA SA SA VSS NC NC D3 D NC D4 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS SA SA SA VSS NC NC NC P NC NC Q7 SA SA C SA SA NC D8 Q8 R TDO TCK SA SA SA C SA SA SA TMS TDI 6109 tb l 12a 165-ball FBGA Pinout TOP VIEW NOTES: 1. A10 is reserved for the 36Mb expansion address. 2. A2 is reserved for the 72Mb expansion address. 6.42 6 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Pin Configuration 1M x 18 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/ SA (3) NC/ SA (1) W BW1 K NC R SA VSS/ SA (2) CQ B NC Q9 D9 SA NC K BW0 SA NC NC Q8 C NC NC D10 VSS SA SA SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 6109 tbl 12b 165-ball FBGA Pinout TOP VIEW NOTES: 1. A3 is reserved for the 36Mb expansion address. 2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices. 3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 2 (71P72804) devices. 6.42 7 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Pin Configuration 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/ SA (4) NC/ SA (2) W BW2 K BW1 R NC/ SA (1) VSS/ SA (3) CQ B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 6109 tb l 12c 165-ball FBGA Pinout TOP VIEW NOTES: 1. A9 is reserved for the 36Mb expansion address. 2. A3 is reserved for the 72Mb expansion address. 3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604) devices. 4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 2 (71P72604) devices. 6.42 8 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Absolute Maximum Ratings (1) Sym bol Value Unit Symbol S up p ly Vo ltag e o n V D D with Re s p e ct to G ND –0.5 to + 2.9 V CIN V TE R M S up p ly Vo ltag e o n V D DQ with Re s p e ct to G ND –0.5 to V D D + 0.3 V V TE R M Vo lta g e o n Inp ut te rm inals with re s p e c t to GND . –0.5 to V D D + 0.3 V V TE R M Vo ltag e o n Outp ut and I/O te rm inals with re s p e c t to G ND. -0.5 to V DD Q + 0.3 V T B IA S Te m p e rature Und e r B ias –55 to + 125 °C T S TG S to rag e Te m p e rature –65 to + 150 °C IO U T Co ntinuo us Curre nt into Outp uts + 20 mA V TE R M Rating Capacitance (TA = +25°C, f = 1.0MHz)(1) (2) CCLK CO Conditions Input Capacitance V DD = 1.8V VDDQ = 1.5V Clock Input Capacitance Output Capacitance Max. Unit 5 pF 6 pF 7 pF 6109 tbl 06 NOTE: 1. Tested at characterization and retested after any design or process change that may affect these parameters. 610 9 t b l 0 5 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation. Recommended DC Operating and Temperature Conditions Symbol Parameter Min. Typ. Max. Unit V DD Power Supply Voltage 1.7 1.8 1.9 V V DDQ I/O Supply Voltage 1.4 1.5 1.9 V V SS Ground 0 0 0 V VREF Input Reference Voltage 0.68 VDDQ /2 0.95 V 0 25 +70 o TA Ambient Temperature (1) NOTE: 1. During production testing, the case temperature equals the ambient temperature. Write Descriptions (1,2) BW0 BW1 BW2 BW3 NW 0 NW 1 Write Byte 0 L X X X X X Write Byte 1 X L X X X X Write Byte 2 X X L X X X Write Byte 3 X X X L X X Write Nibble 0 X X X X L X Write Nibble 1 X X X X X L Signal Parameter 6109 tbl 09 NOTES: 1) All byte write (BWx) and nibble write (NWx) signals are sampled on the rising edge of K and again on K. The data that is present on the data bus in the designated byte/nibble will be latched into the input if the corresponding BWx or NWx is held low. The rising edge of K will sample the first byte/nibble of the two word burst and the rising edge of K will sample the second byte/nibble of the two word burst. 2) The availability of the BWx or NWx on designated devices is described in the pin description table. 3) The QDRII Burst of two SRAM has data forwarding. A read request that is initiated on the same cycle as a write request to the same address will produce the newly written data in response to the read request. 6.42 9 c 6109 tbl 04 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Application Example W SRAM #1 ZQ Q D VT SA R W B W 0 B W 1 C C R SRAM #4 KK 250 Ω D SA R W BW 0 BW 1 C C ZQ Q KK Data In Data Out Address R W BWx/NWx MEMORY CONTROLLER 250 Ω R R R R R VT VT R R Return CLK Source CLK Return CLK Source CLK R = 50Ω VT = VREF 6109 drw 20 6.42 10 VT IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current IIL VDD = Max VIN = VSS to VDDQ -10 +10 µA Output Leakage Current IOL Output Disabled -10 +10 µA - TBD IDD VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min 250MHZ Operating Current (x36,x18,x9,x8): DDR 200MHZ - TBD 167MHZ - TBD 250MHZ - TBD ISB1 Device Deselected (in NOP state), Iout = 0mA (outputs open), f=Max, All Inputs <0.2V or > VDD -0.2V 200MHZ - TBD Standby Current: NOP mA 1 mA 2 - TBD VOH1 RQ = 250Ω, IOH = -15mA VDDQ/2-0.12 VDDQ/2+0.12 V 3,7 Output Low Voltage VOL1 RQ = 250Ω, IOL = 15mA VDDQ/2-0.12 VDDQ/2+0.12 V 4,7 Output High Voltage VOH2 IOH = -0.1mA VDDQ-0.2 VDDQ V 5 Output Low Voltage VOL2 IOL = 0.1mA VSS 0.2 V Output High Voltage 167MHZ Note NOTES: 1. Operating Current is measured at 100% bus utilization. 2. Standby Current is only after all pending read and write burst operations are completed. 3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance. 4. Outputs are impedance-controlled. IOL = (V DDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance. 5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an impedance measurement point. 6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance measurement point. 7. Programmable Impedance Mode. 6.42 11 6 6109 tbl 10c IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V) PARAMETER SYMBOL MIN MAX UNIT NOTES Input High Voltage, DC V IH (DC ) VREF +0.1 V DDQ +0.3 V 1,2 Input Low Voltage, DC VIL (DC) -0.3 VREF -0.1 V 1,3 Input High Voltage, AC VIH (AC) VREF +0.2 - V 4,5 Input Low Voltage, AC VIL (AC) - VREF -0.2 V 4,5 6109 tbl 10d NOTES: 1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min)) 3. V IL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min)) 4. This conditon is for AC function test only, not for AC parameter test. 5. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC) b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, V IL(DC) or VIH(DC) Overshoot Timing Undershoot Timing 20% tKHKH (MIN) VIH VDD +0.5 VDD +0.25 VSS VDD VSS-0.25V VSS-0.5V VIL 6109 drw 22 6109 drw 21 20% tKHKH (MIN) AC Test Conditions AC Test Load Parameter Core Power Supply Voltage VR EF VD DQ /2 OUTPUT Device Under Test ZQ Z0 =50Ω RL = 50Ω Symbol Value Unit VDD 1.7-1.9 V Output Power Supply Voltage V DDQ 1.4-1.9 V Input High/Low Level VIH/VIL 1.25/0.25 V Input Reference Level VREF VDDQ/2 V Input Rise/Fall Time TR/TF 0.6/0.6 ns VDDQ/2 V Output Timing Reference Level RQ = 250 Ω VDD Q /2 6109tbl 11a NOTE: 1. Parameters are tested with RQ=250Ω 6109 drw 04 1.25V 0.75V 0.25V 6109 drw 06 6.42 12 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, TA =0 to 70°C) (3,8) 250MHz Symbol Param eter 200MHz 167MHz Min. Max Min. Max Min. Max Unit 4.00 6.30 5.00 7.88 6.00 8.40 ns - 0.20 - 0.20 - 0.20 ns 1,5 Notes Clock Parameters tKHKH A ve rag e c lo ck c yc le tim e (K , K,C ,C ) tKC v a r C y cle to C yc le P e rio d J itte r (K , K,C , C) tK HKL C lo ck Hig h Tim e (K , K,C , C) 1.60 - 2.00 - 2.40 - ns 9 tK LKH C lo ck LO W Tim e (K , K,C , C) 1.60 - 2.00 - 2.40 - ns 9 tKH KH C lo ck to clock (K →K,C →C) 1.80 - 2.20 - 2.70 - ns 10 tKH KH Clock to clo ck (K→K , C→C ) 1.80 - 2.20 - 2.70 - ns 10 tKHCH C lo ck to d ata clo c k (K →C , K→C) 0.00 1.80 0.00 2.30 0.00 2.80 ns tKC loc k D LL lo c k tim e (K , C ) 1024 - 1024 - 1024 - c yc le s tKC re s e t K s tatic to D LL re s e t 30 - 30 - 30 - ns 0.45 - 0.45 - 0.50 ns 3 2 Output Parameters tC HQV C , C H IG H to o utp ut v alid - tCHQX C , C H IGH to o utp ut ho ld -0.45 - -0.45 - -0.50 - ns 3 tC H CQV C , C HIG H to e c ho clo c k v alid - 0.45 - 0.45 - 0.50 ns 3 tC HC QX C , C HIG H to e c ho clo c k ho ld -0.45 - -0.45 - -0.50 - ns 3 tCQ HQV C Q , CQ H IGH to o utp ut valid - 0.30 - 0.35 - 0.40 ns tCQH QX C Q , CQ H IGH to o utp ut ho ld -0.30 - -0.35 - -0.40 - ns tCHQZ C H IG H to o utp ut Hig h-Z - 0.45 - 0.45 - 0.50 ns 3,4,5 tC HQX1 C H IGH to o utp ut Lo w -Z -0.45 - -0.45 - -0.50 - ns 3,4,5 Set-Up Times tAV KH A d d re s s v alid to K , K ris ing e d g e 0.35 - 0.40 - 0.50 - ns 6 tIV KH C o ntro l inp uts valid to K , K ris ing e d g e 0.35 - 0.40 - 0.50 - ns 7 tDV KH D ate -in v alid to K , K ris ing e d g e 0.35 - 0.40 - 0.50 - ns Hold Times tKHAX K , K ris ing e d g e to ad d re ss ho ld 0.35 - 0.40 - 0.50 - ns 6 tKHIX K , K ris ing e d g e to c o ntro l inp uts ho ld 0.35 - 0.40 - 0.50 - ns 7 tKHDX K , K ris ing e d g e to d ata-in ho ld 0.35 - 0.40 - 0.50 - ns 6109 tb l 11 NOTES: 1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65 (EIA/JESD65) pg.10 2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 3. If C,C are tied High, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX 1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 5. This parameter is guaranteed by device characterization, but not production tested. 6. All address inputs must meet the specified setup and hold times for all latching clock edges. 7. Control signals are R, W,BW0,BW 1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36) 8. During production testing, the case temperature equals TA. 9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH). 10. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH). 6.42 13 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Timing Waveform of Combined Read and Write Cycles Read A0 1 Write A1 2 Read A2 3 Write A3 4 Read A4 5 Write A5 6 NOP 7 Write A6 8 NOP 9 NOP 10 Q40 Q41 K tKHKL tKLKH tKHK H tKHKH K R tIVKH tKHIX W SA D A0 D10 A1 A2 tAVKH tKHAX tAVKH tKHAX D11 D30 A3 A4 A5 D31 D50 D51 tDVKH tKHDX D60 D61 tDVKH tKHDX Q00 Q A6 Q01 Q20 Q21 tCHQX1 tCHQX tKHCH tKLKH tCHQX tCHQV tCQHQV tCQHQX tCHQZ tCHQV C tKHKL tKHCH tKHKH tKHKH C tCHCQV tCHCQX CQ tCHCQV tCHCQX CQ 6109 drw 09a 6.42 14 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram SA,D K,K C,C JTAG Instruction Coding IR2 IR1 IR0 0 0 0 EXTEST Boundary Scan Register 0 0 1 IDCODE Identification register 2 0 1 0 SAMPLE-Z Boundary Scan Register 1 0 1 1 RESERVED Do Not Use 5 1 0 0 1 0 1 RESERVED Do Not Use 5 1 1 0 RESERVED Do Not Use 5 1 1 1 BYPASS SR AM CO RE Q CQ CQ TDI BYPA SS Reg. TDO Id entificatio n Reg. Instruction TDO Output SAMPLE/PRELOAD Boundary Scan register Bypass Register Notes 4 3 Instructio n Reg. 6109tbl 13 NOTES: Con trol Sign als TMS TCK 1. Places Qs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initialized to Vss when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction does not place output pins in Hi-Z. 5. This instruction is reserved for future use. TA P Controller 6109 drw 18 TAP Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 1 1 Capture DR 0 1 1 Exit 2 DR 1 Update DR 0 1 1 Exit 1 DR Pause DR Shift IR 0 0 1 Capture IR 0 Shift DR 1 1 0 0 Exit 1 IR 0 0 0 Pause IR 1 Exit 2 IR 0 0 1 Update IR 0 1 6109 drw 17 6.42 15 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Scan Register Definition Part Instruction Register Bypass Register ID Register Boundary Scan 512Kx36 3 bits 1 bit 32 bits 107 bits 1Mx18 3 bits 1 bit 32 bits 107 bits 2Mx8/x9 3 bits 1 bit 32 bits 107 bits 6109 tbl 14 Identification Register Definitions INSTRUCTION FIELD Revision Number (31:29) Device ID (28:12) IDT JEDEC ID CODE (11:1) ID Register Presence Indicator (0) ALL DEVICES 000 0 0000 0010 0100 0100 0 0000 0010 0100 0101 0 0000 0010 0100 0110 0 0000 0010 0100 0111 000 0011 0011 1 DESCRIPTION PART NUMBER Revision Number 512Kx36 1Mx18 2Mx9 2Mx8 QDRII Burst of 2 71P72604S 71P72804S 71P72104S 71P72204S Allows unique identification of SRAM vendor. Indicates the presence of an ID register. 6109 tbl 15 6.42 16 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Boundary Scan Exit Order (2M x 8-Bit, 2M x 9-Bit) ORDER PIN ID ORDER PIN ID ORDER PIN ID 1 6R 37 10D 73 3E 2 6P 38 9E 74 2C 3 6N 39 10C 75 1D 4 7P 40 11D 76 2E 5 7N 41 9C 77 1E 6 7R 42 9D 78 2F 7 8R 43 11B 79 3F 8 8P 44 11C 80 2G 3G 9 9R 45 9B 81 10 11P 46 10B 82 1F 11 10P 47 11A 83 1G 12 10N 48 Internal 84 1J 13 9P 49 9A 85 2J 14 10M 50 8B 86 3K 15 11N 51 7C 87 3J 16 9M 52 6C 88 3L 17 9N 53 8A 89 2L 11L 54 7A 90 1K 19 11M 55 7B 91 2K 20 9L 56 6B 92 1M 18 21 10L 57 6A 93 1L 22 11K 58 5B 94 3N 23 10K 59 5A 95 3M 9J 60 4A 96 2N 25 9K 61 5C 97 3P 26 10J 62 4B 98 2M 27 11J 63 3A 99 1N 28 11H 64 2A 100 2P 29 10G 65 1A 101 1P 30 9G 66 2B 102 3R 3B 24 31 11F 67 103 4R 32 11G 68 1C 104 4P 33 9F 69 1B 105 5P 34 10F 70 3D 106 5N 35 11E 71 3C 107 5R 36 10E 72 2D 6109 tbl 18a 6109 tbl 17a 6109 tbl 16a 6.42 17 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Boundary Scan Exit Order (1M x 18-Bit, 512K x 36 -Bit) ORDER PIN ID ORDER PIN ID ORDER PIN ID 1 6R 37 10D 73 2C 2 6P 38 9E 74 3E 3 6N 39 10C 75 2D 4 7P 40 11D 76 2E 5 7N 41 9C 77 1E 6 7R 42 9D 78 2F 7 8R 43 11B 79 3F 8 8P 44 11C 80 1G 9 9R 45 9B 81 1F 10 11P 46 10B 82 3G 2G 11 10P 47 11A 83 12 10N 48 Internal 84 1J 13 9P 49 9A 85 2J 14 10M 50 8B 86 3K 15 11N 51 7C 87 3J 16 9M 52 6C 88 2K 17 9N 53 8A 89 1K 18 11L 54 7A 90 2L 19 11M 55 7B 91 3L 20 9L 56 6B 92 1M 21 10L 57 6A 93 1L 22 11K 58 5B 94 3N 23 10K 59 5A 95 3M 24 9J 60 4A 96 1N 25 9K 61 5C 97 2M 26 10J 62 4B 98 3P 27 11J 63 3A 99 2N 28 11H 64 1H 100 2P 29 10G 65 1A 101 1P 30 9G 66 2B 102 3R 31 11F 67 3B 103 4R 11G 68 1C 104 4P 9F 69 1B 105 5P 10F 70 3D 106 5N 107 5R 32 33 34 35 11E 71 3C 36 10E 72 1D 6109 tbl 18 6109 tbl 17 6109 tbl 16 6.42 18 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range JTAG DC Operating Conditions P aram e te r Symbol M in Ty p M ax Unit No te Outp ut P o w e r S up p ly V DD Q 1.4 - 1.9 V P o we r S up p ly Vo ltag e V DD 1.7 1.8 1.9 V Inp ut H ig h Le v e l V IH 1.3 - V DD + 0.3 V Inp ut Lo w Le v e l V IL -0.3 - 0.5 V Outp ut Hig h Vo ltag e (IO H = -1m A ) V OH V D DQ - 0.2 - V DD Q V 1 Outp ut Lo w Vo ltag e (I O L = 1m A ) VOL VSS - 0.2 V 1 NOTE: 6109 tbl 19 1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ. JTAG AC Test Conditions Parameter Symbol Min Unit Input High/Low Level VIH/VIL 1.3/0.5 V Input Rise/Fall Time TR/TF 1.0/1.0 ns VDDQ/2 V Input and Output Timing Reference Level Note 1 NOTE: 1. See AC test load on page 12. 6109 tbl 20 JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note 6109 tbl.21 JTAG Timing Diagram TC K tC H C L tC H C H tM V C H tC H M X tDV CH tC H D X tS VC H tC H S X tC L C H TM S TD I/ SRAM In p u ts SRAM O u tp uts tC L Q V TDO 6 1 0 9 d rw 1 9 6.42 19 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Package Diagram Outline for 165-Ball Fine Pitch Grid Array 6.42 20 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Ordering Information IDT 71P72XXX Device Type S Power XXX Speed BQ X Package Process Temperature Range Blank Commercial (0oC to +70oC) BQ 165 Fine Pitch Ball Grid Array (fBGA) 250 200 167 Clock Frequency in MegaHertz IDT71P72204 IDT71P72104 IDT71P72804 IDT71P72604 2M x 8 QDR II SRAM Burst of 2 2M x 9 QDR II SRAM Burst of 2 1M x 18 QDR II SRAM Burst of 2 512K x 36 QDR II SRAM Burst of 2 6109 drw 15 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: [email protected] 800-544-7726 “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ 6.42 21 IDT71P72204 (2M x 8-Bit), 71P72104 (2M x 9-Bit), 71P72804 (1M x 18 x -Bit) 71P72604 (512K x 36-Bit) Advance Information 18 Mb QDR II SRAM Burst of 2 Commercial Temperature Range Revision History REVISION 0 A DATE 8/01/03 11/14/03 PAGES 1-21 11,12,19 15 B 3/30/04 16 1,3,5-8,14-15 5-8 9 9,11,12 10 11 13 14 17,18 19 C 5/18/04 1 2 12 15 DESCRIPTION Initial Advance Information Data Sheet Release Updated tKHKH (max) for 167-250 MHz and set-up & hold times for 250MHz. Incorporated 133 MHz speed grade in S167 speed bin. Changed number of Boundary Scan bits from 109 to 107. Specified ID bits [28:24] and IDT JEDEC ID bits [11:1] in binary. Updated Boundary Scan Pin IDs for order #48, #64 and #84 through 107. Renamed address inputs from A to SA. Identified 36Mb to 288Mb address expansion pins and requirements. Updated absolute maximum V TERM on input terminals, added VDDQ requirement note 2 and VREF min/max specifications Consolidated DC and AC input specifications by add ing new pg.12, including new Input Electrical Characteristics table, notes 1-5 and overshoot/undershoot timing diagrams. Updated application example showing HSTL terminations (R and VT) on control inputs. Clarified VOH, VOL, IDD and ISB1 test conditions and notes. Clarified tKHKL,tKLKH,tKHKH, tKHKH as a percentage of the cycle time; updated tKC var cycle to cycle period jitter and notes for AC Electrical Characteristics. Added tCQHQX to timing diagram. Modified Boundary Scan order for x8 and x9 options, adding new page 17 with new pin IDs for order#64, #72-75, #80-83, #88-91 and #96-99; changed order #48 from 10A to Internal for x8/9 and x18/36 options. Updated JTAG DC Operating Conditions note 1 and V OH (max) specification from VDD to VDDQ. Added tCLQV to JTAG Timing Diagram. Corrected package size to 13mm x 17mm fBGA. Clarified data word order. Updated AC Test Load and Test Conditions to V REF = VDDQ/2. Clarified pull up resistor to VDD for the unused JTAG inputs.