Die Datasheet Normally – OFF Silicon Carbide Junction Transistor GA50JT06-CAL VDS RDS(ON) o = 600 V = 25 mΩ ID @ 25 C = 100 A hFE = 105 Features • • • • • • • • 210°C maximum operating temperature Gate Oxide Free SiC switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Co-efficient of RDS,ON Suitable for connecting an anti-parallel diode Die Size = 4.35 mm x 4.35 mm Advantages Applications • • • • • • • • • • • • • • Compatible with Si MOSFET/IGBT gate-drivers > 20 µs Short-Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives o Absolute Maximum Ratings (TC = 25 C unless otherwise specified) Parameter Drain – Source Voltage Continuous Drain Current Continuous Drain Current Gate Peak Current Symbol VDS ID ID IGM Turn-Off Safe Operating Area RBSOA Short Circuit Safe Operating Area SCSOA Reverse Gate – Source Voltage Reverse Drain – Source Voltage Operating Junction and Storage Temperature Maximum Processing Temperature VGS VDS Tj, Tstg TProc Conditions VGS = 0 V TC = 25°C TC > 125°C, assumes RthJC < 0.26 oC/W TVJ = 210 oC, Clamped Inductive Load TVJ = 210 oC, IG = 1 A, VDS = 400 V, Non Repetitive 10 min. maximum Values 600 100 50 3.5 ID,max = 50 @ VDS ≤ VDSmax Unit V A A A 20 µs 30 25 -55 to 210 325 V V °C °C A Electrical Characteristics Parameter Symbol Conditions min. Values typ. max. Unit On Characteristics Drain – Source On Resistance RDS(ON) ID = 50 A, IG = 1000 mA, Tj = 25 °C ID = 50 A, IG = 1000 mA, Tj = 125 °C ID = 50 A, IG = 2000 mA, Tj = 175 °C ID = 50 A, IG = 2000 mA, Tj = 210 °C Gate – Source Saturation Voltage VGS,SAT ID = 50 A, ID/IG = 40, Tj = 25 °C ID = 50 A, ID/IG = 30, Tj = 175 °C β VDS = 5 V, ID = 50 A, Tj = 25 °C VDS = 5 V, ID = 50 A, Tj = 125 °C VDS = 5 V, ID = 50 A, Tj = 175 °C VDS = 5 V, ID = 50 A, Tj = 210 °C 25 39 43 62 3.42 3.23 105 77 71 69 VR = 600 V, VGS = 0 V, Tj = 25 °C VR = 600 V, VGS = 0 V, Tj = 210 °C VGS = -20 V, Tj = 25 °C 10 100 20 DC Current Gain mΩ V Off Characteristics Drain Leakage Current IDSS Gate – Source Leakage Current IGSS Feb 2015 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ µA nA Pg1 of 9 Die Datasheet GA50JT06-CAL Electrical Characteristics Parameter Symbol Conditions Ciss Crss/Coss VGS = 0 V, VD = 100 V, f = 1 MHz VD = 100 V, f = 1 MHz min. Values typ. max. Unit Capacitance Characteristics Input Capacitance Reverse Transfer/Output Capacitance 6440 420 pF pF Figures Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 125 °C Figure 3: Typical Output Characteristics at 175 °C Figure 4: Typical Output Characteristics at 210 °C Feb 2015 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg2 of 9 Die Datasheet GA50JT06-CAL Figure 5: Typical Gate – Source Saturation Voltage Figure 6: Normalized On-Resistance and Current Gain vs. Temperature Figure 7: Typical Blocking Characteristics Figure 8: Capacitance Characteristics Feb 2015 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg3 of 9 Die Datasheet GA50JT06-CAL Driving the GA50JT06-CAL Drive Topology TTL Logic Constant Current High Speed – Boost Capacitor High Speed – Boost Inductor Proportional Pulsed Power Gate Drive Power Consumption High Medium Medium Low Lowest Medium Switching Frequency Low Medium High High High N/A Application Emphasis Availability Wide Temperature Range Wide Temperature Range Fast Switching Ultra Fast Switching Wide Drain Current Range Pulse Power Coming Soon Coming Soon Production Coming Soon Coming Soon Coming Soon A: Static TTL Logic Driving The GA50JT06-CAL may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must meet or exceed the steady state gate current (IG,steady) required to operate the GA50JT06-CAL. The power level of the supply can be estimated from the target duty cycle of the particular application. IG,steady is dependent on the anticipated drain current ID through the SJT and the DC current gain hFE, it may be calculated from the following equation. An accurate value of the hFE may be read from Figure 6. 𝐼𝐼𝐺𝐺,𝑠𝑠𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 ≈ 𝐼𝐼𝐷𝐷 ∗ 1.5 ℎ𝐹𝐹𝐹𝐹 (𝑇𝑇, 𝐼𝐼𝐷𝐷 ) 5V SiC SJT TTL Gate Signal D G 5/0V TTL i/p IG,steady S Figure 9: TTL Gate Drive Schematic B: High Speed Driving The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 10 which features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on. Figure 10: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. 𝑄𝑄𝑜𝑜𝑜𝑜 = 𝐼𝐼𝐺𝐺,𝑜𝑜𝑜𝑜 ∗ 𝑡𝑡1 Feb 2015 𝑄𝑄𝑜𝑜𝑜𝑜 ≥ 𝑄𝑄𝑔𝑔𝑔𝑔 + 𝑄𝑄𝑔𝑔𝑔𝑔 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg4 of 9 Die Datasheet GA50JT06-CAL Ideally, IG,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady onstate. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the VGS,sat (see Figure 5) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with VGS = 0 V, a negative gate voltage VGS may be used in order to speed up the turn-off transition. Two high-speed drive topologies for the SiC SJTs are presented below. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA15IDDJT22-FR4 The GA50JT17-CAL may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in on-state. An evaluation gate drive board (GA15IDDJT22-FR4) utilizing this topology is commercially available for low-side driving, its datasheet provides additional details. Gate Driver Board CG1 VGL VGL Signal R2 R1 U4 D VGH U1 CG2 C6 VEE VCC High +12 V C2 X2 R6 C5 VCC Low RTN SJT S RG1 U3 R4 D1 RG2 VGH VCC Low C1 R5 VEE C8 VCC High RTN +12 V G C7 VGL R3 VGL IG U2 Signal RTN VEE C9 VEE C10 Gate X1 C21 Source C4 VEE Figure 1: Topology of the GA15IDDJT22-FR4 Two Voltage Source gate driver. The GA15IDDJT22-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective gate resistance3 of RG = 0.7 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe operation of the GA50JT17-CAL. The steady state current supplied to the gate pin of the GA50JT17-CAL with on-board RG = 0.7 Ω, is shown in Figure 25. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 26. For the GA50JT17-CAL, RG must be reduced for ID ≥ ~60 A for safe operation with the GA15IDDJT22-FR4. For operation at ID ≥ ~60 A, RG may be calculated from the following equation, which contains the DC current gain hFE (Figure 4) and the gatesource saturation voltage VGS,sat (Figure 7). 𝑅𝑅𝐺𝐺,𝑚𝑚𝑚𝑚𝑚𝑚 = Feb 2015 �4.7𝑉𝑉 − 𝑉𝑉𝐺𝐺𝐺𝐺,𝑠𝑠𝑠𝑠𝑠𝑠 � ∗ ℎ𝐹𝐹𝐹𝐹 (𝑇𝑇, 𝐼𝐼𝐷𝐷 ) − 0.1Ω 𝐼𝐼𝐷𝐷 ∗ 1.5 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg5 of 9 Die Datasheet Figure 2: Typical steady state gate current supplied by the GA15IDDJT22-FR4 board for the GA50JT17-CAL with the on board resistance of 0.7 Ω GA50JT06-CAL Figure 3: Maximum gate resistance for safe operation of the GA50JT17-CAL at different drain currents using the GA15IDDJT22-FR4 board. B:2: High Speed, Low Loss Drive with Boost Inductor A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA50JT06-CAL at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a specified IG,on current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 14. After turn on, while the device remains on the necessary steady state gate current IG,steady is supplied from source VCC through RG. Please refer to the article “A current-source concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional information on this driving topology.4 VCC S1 VCC S2 L VEE S3 SiC SJT D G RG S4 S VEE Figure 14: Simplified Inductive Pulsed Drive Topology 3 – RG = (1/RG1 +1/RG2)-1. Driver is pre-installed with RG1 = RG2 = 7.5 Ω 4 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013 Feb 2015 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg6 of 9 Die Datasheet GA50JT06-CAL C: Proportional Gate Current Driving For applications in which the GA50JT06-CAL will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain current ID feedback to vary the steady state gate current IG,steady supplied to the GA50JT06-CAL C:1: Voltage Controlled Proportional Driver The voltage controlled proportional driver relies on a gate drive IC to detect the GA50JT06-CAL drain-source voltage VDS during on-state to sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connected between the drain and sense protects the IC from high-voltage when the driver and GA50JT06-CAL are in off-state. A simplified version of this topology is shown in Figure 15, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ HV Diode Sense Gate Signal Proportional Gate Current Driver Signal D G Output IG,steady SiC SJT S Figure 15: Simplified Voltage Controlled Proportional Driver C:2: Current Controlled Proportional Driver The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback ID of the GA50JT06CAL during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to ID at a fixed forced current gain which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA50JT06-CAL is initially tuned-on using a gate current pulse supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 16, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/. N2 SiC SJT Gate Signal D G S N3 N1 N2 Figure 16: Simplified Current Controlled Proportional Driver Feb 2015 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg7 of 9 Die Datasheet GA50JT06-CAL Mechanical Parameters Die Dimensions 4.35 x 4.35 mm2 171 x 171 mil2 Die Area total / active 18.92/16.56 mm2 29330/25677 mil2 Die Thickness 360 µm 14 mil Wafer Size 100 mm 3937 mil 0 deg 0 deg Flat Position Die Frontside Passivation Polyimide Gate/Source Pad Metallization 4000 nm Al Bottom Drain Pad Metallization 400 nm Ni + 200 nm Au Die Attach Electrically conductive glue or solder Wire Bond Al ≤ 12 mil (Source) Al ≤ 5 mil (Gate) Φ ≥ 0.3 mm Reject ink dot size Store in original container, in dry nitrogen, Recommended storage environment < 6 months at an ambient temperature of 23 °C Chip Dimensions: A C D DIE F B E SOURCE WIREBONDABLE G D Feb 2015 GATE WIREBONDABLE http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ mm mil A 4.35 171 B 4.35 171 C 3.30 130 D 1.75 69 E 0.24 9 F 0.46 18 G 0.57 22 Pg8 of 9 Die Datasheet GA50JT06-CAL Revision History Date 2015/02/09 2014/08/26 Revision 3 2 Comments Updated Electrical Characteristics Updated Electrical Characteristics 2014/03/03 2013/12/04 1 0 Updated Electrical Characteristics Initial release Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Feb 2015 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg9 of 9 Die Datasheet GA50JT06-CAL SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website http://www.genesicsemi.com/images/hit_sic/baredie/sjt/GA50JT06-CAL_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA50JT06-CAL. * MODEL OF GeneSiC Semiconductor Inc. * * $Revision: 1.1 $ * $Date: 03-Mar-2014 $ * * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * * COPYRIGHT (C) 2013 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * .model GA50JT06 NPN + IS 5.00E-47 + ISE 1.26E-28 + EG 3.23 + BF 106 + BR 0.55 + IKF 9000 + NF 1 + NE 2 + RB 0.26 + RE 0.01 + RC 0.013 + CJC 2.3989E-9 + VJC 2.8346223 + MJC 0.4846 + CJE 6.026E-09 + VJE 3.17915435 + MJE 0.52951635 + XTI 3 + XTB -1.2 + TRC1 7.00E-3 + VCEO 600 + ICRATING 50 + MFG GeneSiC_Semiconductor * End of GA50JT06-CAL SPICE Model Mar 2014 http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/ Pg1 of 1