IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT BUFFER/ DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: IDT74ALVCH162827 DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package This 20-bit buffer/driver is built using advanced dual metal CMOS technology. The ALVCH162827 device provides high-performance bus interface buffering for wide data/address paths or busses carrying parity. Two pairs of NAND-ed output enable controls offer maximum control flexibility and are organized to operate the device as two 10-bit buffers or one 20-bit buffer. Flow-through organization of signal pins facilitates ease of layout. All inputs are designed with hysteresis for improved noise margin. The ALVCH162827 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCH162827 has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. DRIVE FEATURES: • Balanced Output Drivers: ±12mA • Low switching noise APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1 OE 1 1 OE 2 1A 1 1 2 OE 1 56 2 OE 2 55 2 2A 1 1Y 1 TO NINE OTHER CHANNELS 28 29 42 15 2Y 1 TO NINE OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE OCTOBER 2003 1 ©2003 Integrated Device Technology, Inc. DSC-4567/3 IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION 1 OE 1 1 56 1 OE 2 1Y 1 2 55 1A 1 1Y 2 3 54 1A 2 GND 4 53 GND 1Y 3 5 52 1A 3 Symbol Description VTERM(2) Max Unit Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C –50 to +50 mA ±50 mA IOUT DC Output Current IIK Continuous Clamp Current, VI < 0 or VI > VCC IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA 1Y 4 6 51 1A 4 V CC 7 50 V CC 1Y 5 8 49 1A 5 1Y 6 9 48 1A 6 1Y 7 10 47 1A 7 GND 11 46 GND 1Y 8 12 45 1A 8 1Y 9 13 44 1A 9 1 Y 10 14 43 1 A 10 CIN Input Capacitance VIN = 0V 5 7 pF 2Y 1 15 42 2A 1 COUT Output Capacitance VOUT = 0V 7 9 pF 2Y 2 16 41 2A 2 COUT I/O Port Capacitance VIN = 0V 7 9 pF 2Y 3 17 40 2A 3 GND 18 39 GND 2Y 4 19 38 2A 4 2Y 5 20 37 2A 5 2Y 6 21 36 2A 6 xOEx Output Enable Inputs (Active LOW) V CC 22 35 V CC xAx Data Inputs(1) 2Y 7 23 34 2A 7 xYx 3-State Outputs 2Y 8 24 33 2A 8 GND 25 32 GND 2Y 9 26 31 2A 9 2 Y 10 27 30 2 A 10 2 OE 1 28 29 2 OE 2 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. Unit NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (EACH 10-BIT SECTION)(1) Inputs TSSOP TOP VIEW xOE2 L L L L L L H H H X X Z X H X Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2 Output xOE1 xAx xYx IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V – 45 — — 45 — — — ±500 NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO VI = 0.7V VI = 0 to 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 — µA µA IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.7V VOL Output LOW Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — IOH = – 4mA 2.2 — IOH = – 8mA 2 — VCC = 3V IOH = – 6mA 2.4 — IOH = – 12mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V VCC = 2.7V VCC = 3V IOL = 4mA — 0.4 IOL = 6mA — 0.55 IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 16 18 pF 4 6 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter tPLH Propagation Delay tPHL xAx to xYx tPZH Output Enable Time tPZL xOEx to xYx tPHZ Output Disable Time tPLZ xOEx to xYx tSK(O) Output Skew(2) VCC = 3.3V ± 0.3V Max. Min. Max. Min. Max. Unit 1 4.4 — 4.4 1.5 3.8 ns 1.4 6.3 — 6.2 1.6 5.1 ns 1.7 5.9 — 5.2 1.8 4.7 ns — — — — — 500 ps NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 4 VCC = 2.7V Min. IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) VIN tPHL VIH VT 0V ALVC Link DISABLE ENABLE CONTROL INPUT GND tPZL D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL ALVC Link Test Circuit for All Outputs tPLH Propagation Delay VOUT RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC Pulse Generator VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION tPLZ VLOAD/2 VT VIH VT 0V VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Test GND All Other Tests Open INPUT OUTPUT 1 tPLH1 SYNCHRONOUS CONTROL VIH VT 0V VOH VT VOL tSK (x) OUTPUT 2 LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT ALVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tH Set-up, Hold, and Release Times VOH VT VOL tPLH2 tSU ALVC Link tPHL1 tSK (x) tREM ASYNCHRONOUS CONTROL VLOAD Disable High Enable High tH TIMING INPUT Switch Open Drain Disable Low Enable Low tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVCH162827 3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT ALVC X XX Bus-Hold Temp. Range XXX Family XX XXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PA Thin Shrink Small Outline Package 827 20-Bit Buffer/Driver with 3-State Outputs 162 Double-Density with Resistors, ±12mA H Bus-Hold 74 – 40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459