BIOS and Kernel Developer Guide (BKDG)

48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Cover Page
Preliminary
BIOS and Kernel
Developer’s Guide
(BKDG)
for AMD Family 16h
Models 00h-0Fh
(Kabini) Processors
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48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
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Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.2 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.1 Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.2 Arithmetic And Logical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.3 Operator Precedence and Associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5 Changes Between Revisions and Product Variations . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.1 Revision Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.2 Major Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.2.1 Major Changes to Core/NB Performance Counters . . . . . . . . . . . . . . . . . 28
2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1 Processor Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3 Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.1 BSC Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.2 AP Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.3 Using L2 Cache as General Storage During Boot . . . . . . . . . . . . . . . . . . . . 30
2.3.4 Instruction Cache Configuration Register Usage Requirements . . . . . . . . . 32
2.4 Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4.1 L2 complex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4.2 Caches and TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4.2.1 Registers Shared by Cores in a L2 complex . . . . . . . . . . . . . . . . . . . . . . . 33
2.4.3 Virtual Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4.4 Processor Cores and Downcoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.4.4.1 Software Downcoring using D18F3x190[DisCore] . . . . . . . . . . . . . . . . . 34
2.4.5 Physical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4.6 System Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4.6.1 Memory Access to the Physical Address Space . . . . . . . . . . . . . . . . . . . . 35
2.4.6.1.1 Determining Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4.6.1.2 Determining The Access Destination for Core Accesses . . . . . . . . . . . . 35
2.4.7 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4.8.1 Local APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4.8.1.1 Detecting and Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4.8.1.2 APIC Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.8.1.3 ApicId Enumeration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.8.1.4 Physical Destination Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.8.1.5 Logical Destination Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.8.1.6 Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.8.1.7 Vectored Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.8.1.8 Interrupt Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.8.1.9 Spurious Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.8.1.10 Spurious Interrupts Caused by Timer Tick Interrupt . . . . . . . . . . . . . . . 39
2.4.8.1.11 Lowest-Priority Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4.8.1.12 Inter-Processor Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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2.4.8.1.13 APIC Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.8.1.14 Generalized Local Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.8.1.15 State at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.8.2 System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.8.2.1 SMM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.8.2.2 Operating Mode and Default Register Values . . . . . . . . . . . . . . . . . . . . 41
2.4.8.2.3 SMI Sources And Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4.8.2.4 SMM Initial State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4.8.2.5 SMM Save State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.4.8.2.6 Exceptions and Interrupts in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.4.8.2.7 The Protected ASeg and TSeg Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.4.8.2.8 SMM Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.4.8.2.9 Locking SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.4.8.2.10 Synchronizing SMM Entry (Spring-Boarding) . . . . . . . . . . . . . . . . . . . 48
2.4.9 Secure Virtual Machine Mode (SVM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.4.9.1 BIOS support for SVM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.4.10 CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.4.10.1 Multi-Core Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.5.1 Processor Power Planes And Voltage Control. . . . . . . . . . . . . . . . . . . . . . . 51
2.5.1.1 Serial VID Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.5.1.1.1 SVI2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.1.2 Internal VID Registers and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.1.2.1 MinVid and MaxVid Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.1.3 Low Power Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.1.3.1 PSIx_L Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.1.3.1.1 BIOS Requirements for PSI0_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.5.1.3.2 Low Power Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.5.1.4 Voltage Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.5.1.4.1 Hardware-Initiated Voltage Transitions . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.5.1.4.2 Software-Initiated Voltage Transitions . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.5.1.4.2.1 Software-Initiated NB Voltage Transitions . . . . . . . . . . . . . . . . . . . . 55
2.5.2 Frequency and Voltage Domain Dependencies. . . . . . . . . . . . . . . . . . . . . . 55
2.5.2.1 Dependencies Between Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.5.2.2 Dependencies Between Subcomponents on VDDNB . . . . . . . . . . . . . . . . 55
2.5.2.3 BIOS Requirements for Power Plane Initialization . . . . . . . . . . . . . . . . . . 56
2.5.3 CPU Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.5.3.1 Core P-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.5.3.1.1 Core P-state Naming and Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.5.3.1.1.1 Software P-state Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.5.3.1.1.2 Hardware P-state Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.5.3.1.2 Core P-state Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.5.3.1.3 Core P-state Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.5.3.1.4 Core P-state Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.5.3.1.5 Core P-state Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.5.3.1.6 BIOS Requirements for Core P-state Initialization and Transitions . . . 59
2.5.3.1.7 Processor-Systemboard Power Delivery Compatibility Check . . . . . . . 60
2.5.3.1.8 BIOS COF and VID Requirements After Warm Reset . . . . . . . . . . . . . 62
2.5.3.1.8.1 Core Maximum P-state Transition Sequence After Warm Reset . . . . 62
2.5.3.1.8.2 Core Minimum P-state Transition Sequence After Warm Reset . . . . 62
2.5.3.1.8.3 ACPI Processor P-state Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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2.5.3.1.8.4 Fixed ACPI Description Table (FADT) Entries . . . . . . . . . . . . . . . . . 64
2.5.3.1.8.5 XPSS (Microsoft Extended PSS) Object . . . . . . . . . . . . . . . . . . . . . . 64
2.5.3.2 Core C-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.5.3.2.1 C-state Names and Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.5.3.2.2 C-state Request Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.5.3.2.3 C-state Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.5.3.2.3.1 C-state Probes and Cache Flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.5.3.2.3.2 Core C1 (CC1) State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.5.3.2.3.3 Core C6 (CC6) State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.5.3.2.3.4 Package C6 (PC6) State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.5.3.2.4 C-state Request Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.5.3.2.4.1 FCH Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.5.3.2.4.2 Cache Flush On Halt Saturation Counter . . . . . . . . . . . . . . . . . . . . . . 67
2.5.3.2.5 Exiting C-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.5.3.2.6 ACPI Processor C-state Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.5.3.2.6.1 _CST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.5.3.2.6.2 _CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.5.3.2.6.3 Fixed ACPI Description Table (FADT) Entries . . . . . . . . . . . . . . . . . 68
2.5.3.2.7 BIOS Requirements for Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.5.3.3 Effective Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.5.4 NB Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.5.4.1 NB P-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.5.4.1.1 NB P-state Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.5.4.1.2 BIOS NB P-state Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.5.4.1.2.1 NB P-state COF and VID Synchronization After Warm Reset . . . . . 70
2.5.4.1.2.2 NB P-state Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.5.4.1.2.3 NB P-state Configuration for Runtime . . . . . . . . . . . . . . . . . . . . . . . . 71
2.5.4.2 NB C-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.5.5 Bandwidth Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.5.6 GPU and Root Complex Power Management . . . . . . . . . . . . . . . . . . . . . . . 72
2.5.6.1 Dynamic Power Management (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.5.6.1.1 Activity Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.5.6.1.2 SCLK DPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.5.6.1.3 LCLK DPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.5.6.2 GPU and Root Complex Power Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.5.7 DRAM Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.5.7.1 Memory P-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.5.7.2 DRAM Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.5.7.3 Stutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.5.7.3.1 System BIOS Requirements for Stutter Mode Operation During POST 75
2.5.7.4 EVENT_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.5.8 System Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.5.8.1 S-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.5.8.1.1 ACPI Suspend to RAM State (S3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.5.9 Application Power Management (APM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.5.9.1 Core Performance Boost (CPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.5.9.1.1 C-state Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.5.9.2 TDP Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.5.9.3 Bidirectional Application Power Management (BAPM) . . . . . . . . . . . . . 77
Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.6.1 Performance Monitor Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5
48751 Rev 3.00 - May 30, 2013
2.7
2.8
2.9
BKDG for AMD Family 16h Models 00h-0Fh Processors
2.6.1.1 Core Performance Monitor Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.6.1.2 L2I Performance Monitor Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.6.1.3 NB Performance Monitor Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.6.2 Instruction Based Sampling (IBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.7.1 MMIO Configuration Coding Requirements. . . . . . . . . . . . . . . . . . . . . . . . 80
2.7.2 MMIO Configuration Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.7.3 Processor Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Northbridge (NB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.8.1 NB Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.8.2 NB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.8.2.1 Address Space Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.8.2.1.1 DRAM and MMIO Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.8.2.1.2 IO Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.8.2.1.3 Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.8.2.1.3.1 Recommended Buffer Count Settings Overview . . . . . . . . . . . . . . . . 83
2.8.3 Memory Scrubbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DRAM Controllers (DCTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.9.1 Common DCT Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.9.2 DCT Frequency Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.9.3 DCT Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.9.4 DDR Pad to Processor Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.9.4.1 DDR Chip to Pad Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.9.5 DRAM Controller Direct Response Mode . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.9.6 DRAM Data Burst Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.9.7 DCT/DRAM Initialization and Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.9.7.1 Low Voltage DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.9.7.2 NB P-state Specific Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.9.7.3 Memory P-state Specific Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.9.7.4 DDR Phy Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.9.7.4.1 Phy Voltage Level Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.9.7.4.2 DRAM Channel Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.9.7.4.2.1 Requirements for DRAM Frequency Change During Training . . . . . 95
2.9.7.4.3 Phy Fence Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.9.7.4.3.1 Phy Fence Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.9.7.4.4 Phy Compensation Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.9.7.5 SPD ROM-Based Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.9.7.6 Non-SPD ROM-Based Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2.9.7.6.1 TrdrdSdSc, TrdrdSdDc, and TrdrdDd (Read to Read Timing) . . . . . . 102
2.9.7.6.2 TwrwrSdSc, TwrwrSdDc, TwrwrDd (Write to Write Timing) . . . . . . 102
2.9.7.6.3 Twrrd (Write to Read DIMM Termination Turn-around) . . . . . . . . . . 102
2.9.7.6.4 TrwtTO (Read-to-Write Turnaround for Data, DQS Contention) . . . . 103
2.9.7.6.5 DRAM ODT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2.9.7.6.5.1 DRAM ODT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.9.7.6.6 DRAM Address Timing and Output Driver Compensation Control . . 106
2.9.7.7 DCT Training Specific Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2.9.7.8 DRAM Device and Controller Initialization . . . . . . . . . . . . . . . . . . . . . . 114
2.9.7.8.1 Software DDR3 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.9.7.8.1.1 DDR3 MR Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.9.7.9 DRAM Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.9.7.9.1 Write Levelization Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
2.9.7.9.1.1 Write Leveling Seed Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.9.7.9.2 DQS Receiver Enable Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2.9.7.9.2.1 DQS Receiver Enable Training Seed Value . . . . . . . . . . . . . . . . . . . 122
2.9.7.9.3 DQS Receiver Enable Cycle Training . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.9.7.9.4 DQS Position Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.9.7.9.5 Calculating MaxRdLatency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.9.7.9.5.1 MaxRdLatency Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.9.7.10 DRAM Phy Power Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
2.9.8 Continuous Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
2.9.8.1 DCT Training Pattern Generation (Reliable Read Write Mode) . . . . . . . 129
2.9.8.1.1 Activate and Precharge Command Generation . . . . . . . . . . . . . . . . . . 129
2.9.8.1.2 Read and Write Command Generation . . . . . . . . . . . . . . . . . . . . . . . . 130
2.9.8.1.3 Configurable Data Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2.9.8.1.3.1 Static Data Pattern Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
2.9.8.1.3.2 Xor Data Pattern Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
2.9.8.1.4 Data Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
2.9.8.1.4.1 Activate and Precharge Traffic Generation . . . . . . . . . . . . . . . . . . . 134
2.9.8.1.5 BubbleCnt and CmdStreamLen Programming . . . . . . . . . . . . . . . . . . . 135
2.9.9 Memory Interleaving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
2.9.9.1 Chip Select Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
2.9.10 Memory Hoisting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
2.9.10.1 DramHoleOffset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
2.9.11 DRAM CC6/PC6 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
2.9.11.1 Fixed Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
2.9.12 DRAM On DIMM Thermal Management and Power Capping . . . . . . . . 140
2.10 Thermal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
2.10.1 The Tctl Temperature Scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
2.10.2 Temperature Slew Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.10.3 Temperature-Driven Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2.10.3.1 PROCHOT_L and Hardware Thermal Control (HTC) . . . . . . . . . . . . . . 143
2.10.3.2 Local Hardware Thermal Control (LHTC) . . . . . . . . . . . . . . . . . . . . . . . 144
2.10.3.3 Software P-state Limit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
2.10.3.4 THERMTRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
2.11 Root Complex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
2.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
2.11.2 Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
2.11.2.1 IOAPIC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.11.3 Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.11.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
2.11.3.2 Link Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
2.11.4 Root Complex Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
2.11.4.1 LPC MMIO Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
2.11.4.2 Configuration for non-FCH Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
2.11.4.3 Link Configuration and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
2.11.4.3.1 Link Configuration and Core Initialization . . . . . . . . . . . . . . . . . . . . . 149
2.11.4.3.2 Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2.11.4.4 Miscellaneous Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2.11.4.4.1 Lane Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2.11.4.4.2 Link Speed Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.11.4.4.2.1 Autonomous Link Speed Changes . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.11.4.4.3 Deemphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7
48751 Rev 3.00 - May 30, 2013
2.12
2.13
2.14
2.15
BKDG for AMD Family 16h Models 00h-0Fh Processors
2.11.4.5 Link Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.11.4.5.1 Link States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.11.4.5.2 Dynamic Link-width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.11.4.6 Link Test and Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.11.4.6.1 Compliance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
2.11.5 BIOS Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
2.11.6 PCIe Client Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
System Management Unit (SMU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
2.12.1 Software Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Graphics Processor (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
2.13.1 Graphics Memory Controller (GMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
2.13.2 Frame Buffer (FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
RAS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
2.14.1 Machine Check Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
2.14.1.1 Machine Check Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
2.14.1.2 Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
2.14.1.3 Error Detection, Action, Logging, and Reporting . . . . . . . . . . . . . . . . . . 156
2.14.1.3.1 MCA conditions that cause Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 157
2.14.1.3.2 Error Logging During Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
2.14.1.4 MCA Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
2.14.1.5 Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
2.14.1.6 Handling Machine Check Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
2.14.1.6.1 Differentiation Between System-Fatal and Process-Fatal Errors . . . . . 162
2.14.1.7 Error Thresholding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
2.14.1.8 Scrub Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
2.14.1.9 Error Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
2.14.1.9.1 Common Diagnosis Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
2.14.2 DRAM ECC Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
2.14.2.1 ECC Syndromes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
2.14.2.1.1 x4 ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
2.14.3 Error Injection and Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
2.14.3.1 DRAM Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Fusion Controller Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
2.15.1 MMIO Programming for Legacy Devices. . . . . . . . . . . . . . . . . . . . . . . . . 171
2.15.2 USB Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
2.15.2.1 USB Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
2.15.2.2 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
2.15.2.3 BIOS Programming Requirements For USB Reset During S3 Resume . 172
2.15.2.4 Enabling the xHCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
2.15.2.5 OHCI Arbiter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
2.15.2.6 USB2.0 Controller PHY Configuration and Calibration . . . . . . . . . . . . . 173
2.15.2.7 USB2.0 Controller ISO Device CRC False Error Detection . . . . . . . . . . 173
2.15.2.8 xHC USB2.0 Common PHY Calibration . . . . . . . . . . . . . . . . . . . . . . . . 174
2.15.2.9 USB3.0 PHY Auto-Calibration Enablement . . . . . . . . . . . . . . . . . . . . . . 174
2.15.2.10 xHCI ISO Device CRC False Error Detection . . . . . . . . . . . . . . . . . . . . 174
2.15.2.11 xHCI PHY Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
2.15.2.12 xHCI Firmware Preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
2.15.2.13 xHCI Clear Pending PME on Sx State Entry . . . . . . . . . . . . . . . . . . . . . 175
2.15.2.14 xHCI Enable OHCI3/EHCI3 on S4/S5 State Entry . . . . . . . . . . . . . . . . . 176
2.15.3 SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
2.15.3.1 SATA Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
8
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
2.15.3.2 SATA Drive Detection in IDE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
2.15.3.3 SATA PHY Auto-Calibration Enablement . . . . . . . . . . . . . . . . . . . . . . . 176
2.15.3.4 SATA PHY Fine Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
2.15.3.5 SATA PHY Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . 177
2.15.3.6 SATA Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
2.15.3.6.1 SATA PHY Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
2.15.3.7 Enable Shadow Register Reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
2.15.3.8 SATA Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
2.15.3.8.1 Line Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
2.15.3.8.2 MSI Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
2.15.3.9 Clear status of SATA PERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
2.15.4 LPC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
2.15.4.1 Enabling LPC DMA function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
2.15.4.2 Enabling SPI 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
2.15.5 SD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
2.15.6 HD Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
2.15.6.1 HD Audio AF and MSI Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
2.15.7 ASF Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
2.15.8 Integrated Micro-Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
2.15.9 On-Chip Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
2.15.9.1 Power Saving In Internal Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 181
2.15.9.2 Global A-Link / B-Link Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . 181
2.15.9.3 CG_PLL CMOS Clock Driver Setting for Power Saving . . . . . . . . . . . . 181
2.15.10 Scallion Gasket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
2.15.11 A-Link Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
2.15.11.1 Detection of Upstream Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
2.15.11.2 AB Memory Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
2.15.11.3 AB Internal Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
2.15.11.4 AB 32/64 Byte DMA Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
3.1 Register Descriptions and Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
3.1.1 Northbridge MSRs In Multi-Core Products. . . . . . . . . . . . . . . . . . . . . . . . 187
3.1.2 Software Recommendation (BIOS, SBIOS, IBIOS) . . . . . . . . . . . . . . . . . 187
3.1.3 See Keyword (See:) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.1.4 Mapping Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.1.4.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.1.4.2 Index Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.1.4.3 Field Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.1.4.4 Broadcast Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3.1.4.5 Reset Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
3.1.4.6 Valid Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
3.1.4.7 BIOS Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
3.2 IO Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
3.3 Device 0 Function 0 (Root Complex) Configuration Registers . . . . . . . . . . . . . . . 191
3.4 Device 0 Function 2 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
3.5 Device 1 Function 0 (Internal Graphics) Configuration Registers . . . . . . . . . . . . . 231
3.6 Device 1 Function 1 (Audio Controller) Configuration Registers . . . . . . . . . . . . . 243
3.7 Device 2 Function 0 (Host Bridge) Configuration Registers . . . . . . . . . . . . . . . . . 254
3.8 Device 2 Function [5:1] (Root Port) Configuration Registers . . . . . . . . . . . . . . . . 255
3.9 Device 18h Function 0 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 286
9
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
Device 18h Function 1 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Device 18h Function 2 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Device 18h Function 3 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Device 18h Function 4 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Device 18h Function 5 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 447
GPU Memory Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Northbridge IOAPIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
APIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
CPUID Instruction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
MSRs - MSR0000_xxxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
MSRs - MSRC000_0xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
MSRs - MSRC001_0xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
MSRs - MSRC001_1xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Core Performance Counter Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
3.23.1 PMCx0[1F:00] Events (FP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
3.23.2 PMCx0[3F:20] Events (LS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
3.23.3 PMCx0[5F:40] Events (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
3.23.4 PMCx[8,1:0][7F:60] Events (BU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
3.23.5 PMCx[1:0][9F:80] Events (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
3.23.6 PMCx[1,0][DF:C0] Events (EX, DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
3.24 L2I Performance Counter Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
3.25 NB Performance Counter Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
3.25.1 PMCx0E[7:4] Events (Memory Controller) . . . . . . . . . . . . . . . . . . . . . . . 602
3.25.2 PMCx0E[F:8] Events (Crossbar). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
3.25.3 PMCx0F[F:0] Events (ONION, Crossbar) . . . . . . . . . . . . . . . . . . . . . . . . 605
3.25.4 NBPMCx1E[F:0] Events (Crossbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
3.25.5 NBPMCx1F[F:0] Events (Memory Controller, Crossbar) . . . . . . . . . . . . 608
3.26 Fusion Controller Hub Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
3.26.1 Legacy Block Configuration Registers (IO) . . . . . . . . . . . . . . . . . . . . . . . 611
3.26.2 AB Configuration Registers (Scallion) . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
3.26.3 SATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
3.26.3.1 Device 11h Function 0 (SATA) Configuration Registers . . . . . . . . . . . . 634
3.26.3.2 SATA IO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
3.26.3.2.1 IDE Compatibility Mode and Native Mode (BAR0, BAR1, BAR2,
BAR3)Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
3.26.3.2.2 IDE Bus Master (BAR4) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
3.26.3.3 SATA Memory Mapped AHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . 654
3.26.3.3.1 Generic Host Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
3.26.3.3.2 Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
3.26.3.3.3 Enclosure Buffer Management Registers . . . . . . . . . . . . . . . . . . . . . . . 676
3.26.4 USB Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
3.26.4.1 USB 1.1 (OHCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
3.26.4.1.1 Devices 16h, 13h, 12h Function 0 (OHCI) Configuration Registers . . 679
3.26.4.1.2 OHCI Memory Mapped IO Registers . . . . . . . . . . . . . . . . . . . . . . . . . 686
3.26.4.2 USB 2.0 (EHCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
3.26.4.2.1 Devices 16h, 13h, 12h Function 2 (EHCI) Configuration Registers . . 700
3.26.4.2.2 EHCI Memory Mapped IO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 709
3.26.4.3 USB 3.0 (xHCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
3.26.4.3.1 Device 10h Function 0 (xHCI) Configuration Registers . . . . . . . . . . . 725
3.26.4.3.1.1 USB xHCI Capability Registers (XHCI_CAP) . . . . . . . . . . . . . . . . 744
3.26.4.3.2 xHCI Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 744
10
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
3.26.5 HD Audio Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
3.26.5.1 Device 14h Function 2 (Audio Controller) Configuration Registers . . . 750
3.26.6 Secure Digital (SD) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
3.26.6.1 Device 14h Function 7 Configuration Registers (SD) . . . . . . . . . . . . . . . 757
3.26.6.2 SD Host Controller Configuration Registers (SDHC) . . . . . . . . . . . . . . 762
3.26.7 SMBus Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
3.26.7.1 Device 14h Function 0 (SMBus) Configuration Registers . . . . . . . . . . . 777
3.26.7.2 ASF (Alert Standard Format) Registers . . . . . . . . . . . . . . . . . . . . . . . . . 780
3.26.7.3 SMBus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
3.26.8 IOAPIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
3.26.9 LPC-ISA Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
3.26.9.1 Device 14h Function 3 (LPC Bridge) Configuration Registers . . . . . . . 794
3.26.9.2 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
3.26.10 High Precision Event Timer (HPET) Registers . . . . . . . . . . . . . . . . . . . . . 817
3.26.11 Miscellaneous (MISC) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
3.26.12 GPIO Pin control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
3.26.12.1 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
3.26.12.2 IOMux Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
3.26.13 Power Management (PM) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
3.26.14 Power Management Block 2 (PM2) Registers. . . . . . . . . . . . . . . . . . . . . . 876
3.26.15 Standard ACPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
3.26.15.1 AcpiPmEvtBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
3.26.15.2 AcpiPm1CntBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
3.26.15.3 AcpiPm2CntBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
3.26.15.4 AcpiPmTmrBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
3.26.15.5 CpuCntBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
3.26.15.6 AcpiGpe0Blk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
3.26.15.7 SmiCmdBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
3.26.16 SMI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
3.26.17 Watchdog Timer (WDT) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
3.26.18 Wake Alarm Device (AcDcTimer) Registers . . . . . . . . . . . . . . . . . . . . . . 919
4
Register List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
11
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
A L2 Complex............................................................................................................................. 29
DQS Position Training Example Results.................................................................................. 125
DQS Position Training Insertion Delay Recovery Example Results........................................ 126
Memory Configuration with Memory Hole inside of Region .................................................. 138
Memory Configuration with Memory Hole outside of Region ................................................ 139
Tctl scale ................................................................................................................................... 143
Root complex topology............................................................................................................. 146
Address/Command Timing at the Processor Pins..................................................................... 327
12
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
List of Tables
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Table 29:
Table 30:
Table 31:
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Table 33:
Table 34:
Table 35:
Table 36:
Arithmetic and Logical Operators............................................................................................... 21
Functions..................................................................................................................................... 21
Operator Precedence and Associativity ...................................................................................... 22
Definitions................................................................................................................................... 22
Processor revision conventions................................................................................................... 28
SMM Initial State........................................................................................................................ 42
SMM Save State.......................................................................................................................... 42
Power Management Support....................................................................................................... 51
Software P-state Naming ............................................................................................................ 57
Software P-state Control ............................................................................................................. 58
ONION Link Definitions ............................................................................................................ 83
DCT Definitions.......................................................................................................................... 84
DDR3 UDIMM Maximum Frequency Support with 6-layer Motherboard
Design FT3 package......................................................................................................................85
DDR3 UDIMM Maximum Frequency Support with 6-layer Motherboard
Design FT3 package Microserver.................................................................................................86
DDR3 SODIMM Maximum Frequency Support with 6-layer Motherboard
Design FT3 package ...................................................................................................................86
DDR3 UDIMM Maximum Frequency Support with 4-layer Motherboard
Design FT3 package ....................................................................................................................86
DDR3 SODIMM Maximum Frequency Support with 4-layer Motherboard
Design FT3 package ...................................................................................................................87
DDR3 SODIMM plus Solder-down DRAM Maximum Frequency with
6-layer Motherboard FT3 package ..............................................................................................87
DDR3 SODIMM plus Solder-down DRAM Maximum Frequency with
4-layer Motherboard FT3 package...............................................................................................87
DDR3 Solder-down DRAM Maximum Frequency Support FT3 package................................. 88
DDR3 UDIMM Maximum Frequency Support FS1b package .................................................. 88
DDR3 Population Support .......................................................................................................... 88
Package pin mapping ................................................................................................................. 89
Pad (from chiplet) pin mapping .................................................................................................. 90
DDR PLL Lock Time................................................................................................................. 95
Phy predriver calibration codes for Data/DQS at 1.5V .............................................................. 97
Phy predriver calibration codes for Data/DQS at 1.35V ............................................................ 98
Phy Predriver Calibration Codes for Data/DQS at 1.25V .......................................................... 98
Phy predriver calibration codes for Cmd/Addr at 1.5V .............................................................. 98
Phy predriver calibration codes for Cmd/Addr at 1.35V ............................................................ 99
Phy Predriver Calibration Codes for Cmd/Addr at 1.25V .......................................................... 99
Phy predriver calibration codes for Clock at 1.5V...................................................................... 99
Phy predriver calibration codes for Clock at 1.35V.................................................................. 100
Phy Predriver Calibration Codes for Clock at 1.25V................................................................ 100
DDR3 ODT Pattern NumDimmSlots=1 ................................................................................... 103
DDR3 ODT Pattern NumDimmSlots=2 ................................................................................... 103
13
48751 Rev 3.00 - May 30, 2013
Table 37:
Table 38:
Table 39:
Table 40:
Table 41:
Table 42:
Table 43:
Table 44:
Table 45:
Table 46:
Table 47:
Table 48:
Table 49:
Table 50:
Table 51:
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61:
Table 62:
Table 63:
Table 64:
Table 65:
Table 66:
Table 67:
Table 68:
Table 69:
Table 70:
Table 71:
Table 72:
Table 73:
Table 74:
BKDG for AMD Family 16h Models 00h-0Fh Processors
BIOS recommendations for MR1[RttNom] and MR2[RttWr] UDIMM FT3 package ............ 104
BIOS recommendations for MR1[RttNom] and MR2[RttWr] SODIMM FT3 package .......... 104
BIOS recommendations for MR1[RttNom] and MR2[RttWr] SODIMM plus
Solder-down DRAM FT3 package............................................................................................105
BIOS recommendations for MR1[RttNom] and MR2[RttWr] Solder-down
DRAM FT3 package.................................................................................................................105
BIOS recommendations for MR1[RttNom] and MR2[RttWr] UDIMM FS1b package .......... 105
BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and
Output Driver Control UDIMM FT3 package...........................................................................107
BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and
Output Driver Control SODIMM FT3 package........................................................................109
BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and
Output Driver Control SODIMM plus Solder-down DRAM FT3 package..............................111
BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and
Output Driver Control Solder-down DRAM FT3 package...................................................... 112
BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and
Output Driver Control UDIMM FS1b package........................................................................ 113
DCT Training Specific Register Values.....................................................................................114
BIOS Recommendations for MR0[WR]....................................................................................116
BIOS Recommendations for MR0[CL[3:0]] .............................................................................116
BIOS Recommendations for MR2[ASR, SRT] .........................................................................118
DDR3 Write Leveling Seed Values........................................................................................... 121
DDR3 DQS Receiver Enable Training Seed Values................................................................. 123
Configurable Data Pattern Example with 1 Address Target ..................................................... 131
Configurable Data Pattern Circular Shift Example with 1 Address Target .............................. 132
Data Pattern Override Example with 1 Address Target ........................................................... 133
Command Generation and Data Comparison ........................................................................... 134
DDR3 Command Generation and BubbleCnt Programming.................................................... 135
Recommended Interleave Configurations................................................................................. 136
DDR3 Swapped Normalized Address Lines for CS Interleaving............................................. 137
Example storage region configuration ...................................................................................... 140
Recommended Interrupt Routing and Swizzling Configuration............................................... 147
Supported General Purpose (GPP) Link Configurations .......................................................... 148
SMU Software Interrupts .......................................................................................................... 152
Recommended Frame Buffer Configurations ........................................................................... 153
MCA register cross-reference table .......................................................................................... 155
Overwrite Priorities for All Banks ............................................................................................ 158
Error Code Types ...................................................................................................................... 159
Error codes: transaction type (TT) ............................................................................................ 159
Error codes: cache level (LL).................................................................................................... 159
Error codes: memory transaction type (RRRR)........................................................................ 159
Error codes: participation processor (PP) ................................................................................. 160
Error codes: memory or IO (II)................................................................................................. 160
Error codes: Internal Error Type (UU)...................................................................................... 160
Error Scope Hierarchy .............................................................................................................. 162
14
48751 Rev 3.00 - May 30, 2013
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Table 81:
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Table 83:
Table 84:
Table 85:
Table 86:
Table 87:
Table 88:
Table 89:
Table 90:
Table 91:
Table 92:
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Table 95:
Table 96:
Table 97:
Table 98:
Table 99:
Table 100:
Table 101:
Table 102:
Table 103:
Table 104:
Table 105:
Table 106:
Table 107:
Table 108:
Table 109:
Table 110:
Table 111:
Table 112:
Table 113:
Table 114:
Table 115:
Table 116:
Table 117:
Table 118:
BKDG for AMD Family 16h Models 00h-0Fh Processors
Recommended Scrub Rates per Node....................................................................................... 164
Registers Commonly Used for Diagnosis................................................................................. 166
x4 ECC Correctable Syndromes ............................................................................................... 168
USB Port Mapping.................................................................................................................... 171
USB Port to EHCI[3:1]xB4[PortNumber] Mapping ................................................................ 173
USB Port to D10F0x4C_x4000_0000[PortNumber] Mapping ................................................ 175
HD Audio AF and MSI Capability Settings ............................................................................. 180
ASF Remote Control Commands ............................................................................................. 180
Terminology in Register Descriptions ...................................................................................... 185
Reset values for D0F0x64_x3[4:0] ........................................................................................... 196
Register Mapping for D0F0xBC_x3FD[8C:00:step14]............................................................ 206
Register Mapping for D0F0xBC_x3FD[94:08:step14] ............................................................ 207
Register Mapping for D0F0xBC_x3FD[9C:10:step14]............................................................ 207
Index addresses for D0F0xE4_x0110_001[8:7,3:2] ................................................................. 214
Index address mapping for D0F0xE4_x0130_0[C:8]00........................................................... 216
Index address mapping for D0F0xE4_x0130_0[C:8]03........................................................... 217
Index address mapping for D0F0xE4_x0130_0[C:8]05........................................................... 217
Lane index addresses for D0F0xE4_x0130_802[4:1] .............................................................. 221
Reset Mapping for D0F0xE4_x0130_802[4:1] ........................................................................ 221
Field mapping for D0F0xE4_x0130_802[4:1] ......................................................................... 221
Lane index addresses for D0F0xE4_x0130_802[8:5] .............................................................. 222
Reset Mapping for D0F0xE4_x0130_802[8:5] ........................................................................ 222
Field mapping for D0F0xE4_x0130_802[8:5] ......................................................................... 222
Register Mapping for D2F[5:1]x00 .......................................................................................... 255
Link controller state encodings ................................................................................................. 276
Register Mapping for D18F0x[5C:40]...................................................................................... 287
Register Mapping for D18F0x[E4,C4,A4,84] .......................................................................... 291
Register Mapping for D18F0x[EC,CC,AC,8C]........................................................................ 291
Register Mapping for D18F0x[F0,D0,B0,90]........................................................................... 292
Link Buffer Definitions............................................................................................................. 293
Register Mapping for D18F0x[F4,D4,B4,94]........................................................................... 294
Register Mapping for D18F0x[F8,D8,B8,98]........................................................................... 295
Register Mapping for D18F0x[11C,118,114,110].................................................................... 296
Register Mapping for D18F0x[18C:170].................................................................................. 297
Onion Definitions...................................................................................................................... 297
Register Mapping for D18F1x[17C:140,7C:40]....................................................................... 299
Register Mapping for D18F1x[7:4][8,0]................................................................................... 300
Register Mapping for D18F1x[7:4][C,4] .................................................................................. 300
Register Mapping for D18F1x[2CC:2A0,1CC:180,BC:80] ..................................................... 301
Register Mapping for D18F1x[2B:1A,B:8][8,0] ...................................................................... 302
Register Mapping for D18F1x[2B:1A,B:8][C,4]...................................................................... 302
Register Mapping for D18F1x[1F:1E,D:C][8,0] ...................................................................... 304
Register Mapping for D18F1x[1F:1E,D:C][C,4]...................................................................... 305
Register Mapping for D18F1x[1DC:1D0,EC:E0] .................................................................... 305
15
48751 Rev 3.00 - May 30, 2013
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Table 125:
Table 126:
Table 127:
Table 128:
Table 129:
Table 130:
Table 131:
Table 132:
Table 133:
Table 134:
Table 135:
Table 136:
Table 137:
Table 138:
Table 139:
Table 140:
Table 141:
Table 142:
Table 143:
Table 144:
Table 145:
Table 146:
Table 147:
Table 148:
Table 149:
Table 150:
Table 151:
Table 152:
Table 153:
Table 154:
Table 155:
Table 156:
Table 157:
Table 158:
Table 159:
Table 160:
Table 161:
Table 162:
BKDG for AMD Family 16h Models 00h-0Fh Processors
Register Mapping for D18F1x2[1C:00].................................................................................... 309
Register Mapping for D18F1x2[1,0][8,0]................................................................................. 309
Register Mapping for D18F1x2[1,0][C,4] ................................................................................ 310
DIMM, Chip Select, and Register Mapping ..............................................................................311
DDR3 DRAM Address Mapping.............................................................................................. 315
Valid Values for Memory Clock Frequency Value Definition ................................................. 322
Index Mapping for D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0]...................................... 326
Byte Lane Mapping for D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0] .............................. 326
Index Mapping for D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0]...................................... 328
Byte Lane Mapping for D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0] .............................. 329
Index Mapping for D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0]......................................... 333
Byte Lane Mapping for D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0] ................................. 334
Index Mapping for D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0]......................................... 335
Byte Lane Mapping for D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0] ................................. 336
Index Mapping for D18F2x9C_x0000_00[52:50]_dct[0] ........................................................ 336
Byte Lane Mapping for D18F2x9C_x0000_00[52:50]_dct[0]................................................. 337
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]02_dct[0] ...................................................... 337
Broadcast Mapping for D18F2x9C_x0D0F_0[F,8:0]02_dct[0] ............................................... 338
Valid Values for D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]........................................... 338
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]0[B,7,3]_dct[0]............................................. 339
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0] ....................................... 339
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]06_dct[0] ...................................................... 340
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]0A_dct[0] ..................................................... 340
Broadcast Mapping for D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0]......................................... 340
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]10_dct[0]_mp[1:0] ....................................... 340
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0] ....................................... 341
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1C_dct[0]_mp[1:0] ...................................... 342
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1E_dct[0]_mp[1:0]....................................... 343
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0]....................................... 343
Index Mapping for D18F2x9C_x0D0F_0[F,8:0]2[3:0]_dct[0]_mp[1:0] ................................. 344
Index Addresses for D18F2x9C_x0D0F_0[F,8:0]30_dct[0] .................................................... 346
Broadcast Write Index Address for D18F2x9C_x0D0F_0[F,8:0]30_dct[0] ............................ 346
Index addresses for D18F2x9C_x0D0F_0[F,8:0]31_dct[0] ..................................................... 346
Broadcast write index address for D18F2x9C_x0D0F_0[F,8:0]31_dct[0] .............................. 347
Index addresses for D18F2x9C_x0D0F_0[F,8:0]38_dct[0] ..................................................... 347
Broadcast write index address for D18F2x9C_x0D0F_0[F,8:0]38_dct[0] .............................. 347
Broadcast write index address for D18F2x9C_x0D0F_1C00_dct[0]....................................... 348
Index Mapping for D18F2x9C_x0D0F_2[2:0]02_dct[0] ......................................................... 348
Index address mapping for D18F2x9C_x0D0F_[C,8,2][2:0]1E_dct[0]_mp[1:0] .................... 349
Index address mapping for D18F2x9C_x0D0F_[C,8,2][2:0]1F_dct[0] ................................... 349
Index Addresses for D18F2x9C_x0D0F_[C,8,2][2:0]20_dct[0]_mp[1:0] ............................... 350
Index Addresses for D18F2x9C_x0D0F_2[F,2:0]30_dct[0] .................................................... 350
Index Mapping for D18F2x9C_x0D0F_[C,8][1:0]02_dct[0]................................................... 352
Index Mapping for D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0]................................ 353
16
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Table 164:
Table 165:
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Table 167:
Table 168:
Table 169:
Table 170:
Table 171:
Table 172:
Table 173:
Table 174:
Table 175:
Table 176:
Table 177:
Table 178:
Table 179:
Table 180:
Table 181:
Table 182:
Table 183:
Table 184:
Table 185:
Table 186:
Table 187:
Table 188:
Table 189:
Table 190:
Table 191:
Table 192:
Table 193:
Table 194:
Table 195:
Table 196:
Table 197:
Table 198:
Table 199:
Table 200:
Table 201:
Table 202:
Table 203:
Table 204:
Table 205:
Table 206:
BKDG for AMD Family 16h Models 00h-0Fh Processors
Index Mapping for D18F2x9C_x0D0F_[C,8][F:0]30_dct[0]................................................... 353
BIOS Recommendations for D18F2x1B[4:0]........................................................................... 366
Field Mapping for D18F2x1BC_dct[0] .................................................................................... 370
BIOS Recommendations for D18F2x1BC_dct[0] .................................................................... 370
BIOS Recommendations for RdPtrInit ..................................................................................... 374
Register Mapping for D18F2x25[8,4]_dct[0]........................................................................... 386
Register Mapping for D18F2x2[B4,B0,AC,A8]_dct[0] ........................................................... 393
Field Mapping for D18F2x2[B4,B0,AC,A8]_dct[0] ................................................................ 394
Field Mappings for D18F2x2[C0,BC]_dct[0] .......................................................................... 395
Buffer Definitions ......................................................................................................................411
SMAF Action Definition .......................................................................................................... 414
Register Mapping for D18F3x1[54:48] .................................................................................... 428
D18F5x80[Enabled, DualCore, TripleCore, QuadCore] Definition......................................... 448
Register Mapping for D18F5x16[C:0]...................................................................................... 453
NB P-state Definitions .............................................................................................................. 454
Register Mapping for APIC[170:100] ...................................................................................... 466
Register Mapping for APIC[1F0:180] ...................................................................................... 467
Register Mapping for APIC[270:200] ...................................................................................... 467
ICR valid combinations ............................................................................................................ 468
Register Mapping for APIC3[60:50] ........................................................................................ 471
Div[3,1:0] Value Table .............................................................................................................. 472
Register Mapping for APIC[4F0:480] ...................................................................................... 473
Register Mapping for APIC[530:500] ...................................................................................... 474
Reset Mapping for CPUID Fn8000_0000_E[D,C,B]X ............................................................ 475
CPUID Fn8000_0000_E[B,C,D]X Value ................................................................................. 483
Valid Values for CPUID Fn8000_000[4:2]_E[D,C,B,A]X...................................................... 486
ECX mapping to Cache Type for CPUID Fn8000_001D_E[D,C,B,A]X................................. 496
Register Mapping for MSR0000_020[E,C,A,8,6,4,2,0] ........................................................... 507
Valid Values for Memory Type Definition............................................................................... 508
Register Mapping for MSR0000_020[F,D,B,9,7,5,3,1] ........................................................... 508
Register Mapping for MSR0000_02[6F:68,59:58,50].............................................................. 509
Field Mapping for MSR0000_02[6F:68,59:58,50]................................................................... 509
MC0 Error Descriptions............................................................................................................ 514
MC0 Error Signatures ............................................................................................................... 515
MC0 Address Register .............................................................................................................. 515
MC1 Error Descriptions............................................................................................................ 517
MC1 Error Signatures ............................................................................................................... 518
MC1 Address Register .............................................................................................................. 518
MC2 Error Descriptions............................................................................................................ 521
MC2 Error Signatures ............................................................................................................... 522
MC2 Address Register .............................................................................................................. 523
MC4 Error Descriptions............................................................................................................ 526
MC4 Error Signatures, Part 1.................................................................................................... 527
MC4 Error Signatures, Part 2.................................................................................................... 528
17
48751 Rev 3.00 - May 30, 2013
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Table 208:
Table 209:
Table 210:
Table 211:
Table 212:
Table 213:
Table 214:
Table 215:
Table 216:
Table 217:
Table 218:
Table 219:
Table 220:
Table 221:
Table 222:
Table 223:
Table 224:
Table 225:
Table 226:
Table 227:
Table 228:
Table 229:
Table 230:
Table 231:
Table 232:
Table 233:
Table 234:
Table 235:
Table 236:
Table 237:
Table 238:
BKDG for AMD Family 16h Models 00h-0Fh Processors
Format of MSR0000_0412[ErrAddr[47:1]] for All Other Errors............................................. 529
Format of MSR0000_0412[ErrAddr[47:1]] for Protocol Errors .............................................. 529
Valid Values for ProtocolErrorType ......................................................................................... 529
Format of MSR0000_0412[ErrAddr[47:1]] for NB Array Errors ............................................ 530
Valid Values for ArrayErrorType ............................................................................................. 530
Format of MSR0000_0412[ErrAddr[47:1]] for Watchdog Timer Errors ................................. 531
MC5 Error Descriptions............................................................................................................ 534
MC5 Error Signatures ............................................................................................................... 534
MC5 Address Register .............................................................................................................. 534
Register Mapping for MSRC001_00[03:00] ............................................................................ 542
Register Mapping for MSRC001_00[07:04] ............................................................................ 544
Register Mapping for MSRC001_00[35:30] ............................................................................ 550
BIOS Recommendations for MSRC001_00[35:30] ................................................................. 550
Register Mapping for MSRC001_00[53:50] ............................................................................ 554
Register Mapping for MSRC001_00[6B:64]............................................................................ 558
P-state Definitions..................................................................................................................... 558
Register Mapping for MSRC001_023[6,4,2,0] ........................................................................ 568
Register Mapping for MSRC001_023[7,5,3,1] ........................................................................ 570
Register Mapping for MSRC001_024[6,4,2,0] ........................................................................ 570
Register Mapping for MSRC001_024[7,5,3,1] ........................................................................ 571
Register Mapping for MSRC001_101[B:9].............................................................................. 575
Field Mapping for MSRC001_101[B:9]................................................................................... 575
Register Mapping for PMCx0D[F:C] ....................................................................................... 599
SATA Controller Subclass Code and ProgramIF Settings ........................................................ 635
IDE Compatibility Mode and Native Mode Address Mapping ................................................ 651
OHCI[3:1]x48 reset values ....................................................................................................... 693
Reset mapping for EHCI[3:1]x04 ............................................................................................. 710
Register Mapping for SDHCx6[C:0:step4]............................................................................... 774
Field Mapping for SDHCx6[C:0:step4].................................................................................... 774
Reset Mapping for IOMUXx[E4:00]........................................................................................ 844
BIOS Recommendations for KbRstEn ..................................................................................... 868
BIOS Recommendations for UsbPhyS5PwrDwnEnable.......................................................... 875
18
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Revision History
KB BKDG Revision 3.00 initial release.
19
48751 Rev 3.00 - May 30, 2013
1
BKDG for AMD Family 16h Models 00h-0Fh Processors
Overview
This document defines AMD Family 16h Models 00h-0Fh Processors, henceforth referred to as the processor.
• The processor overview is located at 2.1 [Processor Overview].
• The processor is distinguished by the combined ExtFamily and BaseFamily fields of the CPUID instruction (see CPUID Fn8000_0001_EAX in 3.18 [CPUID Instruction Registers]).
1.1
Intended Audience
This document provides the processor behavioral definition and associated design notes. It is intended for platform designers and for programmers involved in the development of low-level BIOS (basic input/output system) functions, drivers, and operating system kernel modules. It assumes prior experience in personal
computer platform design, microprocessor programming, and legacy x86 and AMD64 microprocessor architecture. The reader should also have familiarity with various platform technologies, such as DDR DRAM.
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Reference Documents
Advanced Configuration and Power Interface (ACPI) Specification. www.acpi.info.
AMD64 Architecture Programmer's Manual Volume 1: Application Programming, #24592.
AMD64 Architecture Programmer's Manual Volume 2: System Programming, #24593.
AMD64 Architecture Programmer's Manual Volume 3: Instruction-Set Reference, #24594.
AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, #26568.
AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions,
#26569.
Software Optimization Guide for AMD Family 16h Processors, #52128.
Revision Guide for AMD Family 16h Models 00h-0Fh Processors, #51810
JEDEC standards. www.jedec.org.
PCI local bus specification. (www.pcisig.org).
PCI Express® specification. (www.pcisig.org).
Universal Serial Bus Specification (http://www.usb.org)
Serial ATA Specification (http://www.sata-io.org)
AT Attachment with Packet Interface (http://www.t13.org)
SD Host Controller Standard Specification (https://www.sdcard.org)
Alert Standard Format Specification (http://dmtf.org/standards/asf)
1.3
1.3.1
Conventions
Numbering
• Binary numbers. Binary numbers are indicated by appending a “b” at the end, e.g., 0110b.
• Decimal numbers. Unless specified otherwise, all numbers are decimal. This rule does not apply to the register mnemonics described in 3.1 [Register Descriptions and Mnemonics]; register mnemonics all utilize
hexadecimal numbering.
• Hexadecimal numbers. hexadecimal numbers are indicated by appending an “h” to the end, e.g., 45f8h.
• Underscores in numbers. Underscores are used to break up numbers to make them more readable. They do
not imply any operation. E.g., 0110_1100b.
20
48751 Rev 3.00 - May 30, 2013
1.3.2
BKDG for AMD Family 16h Models 00h-0Fh Processors
Arithmetic And Logical Operators
In this document, formulas generally follow Verilog conventions for logic equations.
Table 1: Arithmetic and Logical Operators
Operator
{}
|
||
&
&&
^
~
!
<, <=, >, >=, ==, !=
+, -, *, /, %
<<
>>
?:
Definition
Concatenation. Curly brackets are used to indicate a group of bits that are concatenated
together. Each set of bits is separated by a comma. E.g., {Addr[3:2], Xlate[3:0]} represents a 6-bit value; the two MSBs are Addr[3:2] and the four LSB’s are Xlate[3:0].
Bitwise OR. E.g. (01b | 10b == 11b).
Logical OR. E.g. (01b || 10b == 1b); treats multibit operand as 1 if >=1 and produces a
1-bit result.
Bitwise AND. E.g. (01b & 10b == 00b).
Logical AND. E.g. (01b && 10b == 1b); logical treats multibit operand as 1 if >=1 and
produces a 1-bit result.
Bitwise exclusive-OR. E.g. (01b ^ 10b == 11b). Sometimes used as “raised to the
power of” as well, as indicated by the context in which it is used. E.g. (2^2 == 4).
Bitwise NOT. (also known as one’s complement). E.g. (~10b == 01b).
Logical NOT. E.g. (!10b == 0b); treats multibit operand as 1 if >=1 and produces a 1bit result.
Relational. Less than, Less than or equal, greater, greater than or equal, equal, and not
equal.
Arithmetic. Addition, subtraction, multiplication, division, and modulus.
Bitwise left shift. Shift left first operand by the number of bits specified by the 2nd
operand. E.g. (01b << 01b == 10b).
Bitwise right shift. Shift right first operand by the number of bits specified by the 2nd
operand. E.g. (10b >> 01b == 01b).
Ternary conditional. E.g. condition ? value if true : value if false. Equivalent to IF condition THEN value if true ELSE value if false.
Table 2: Functions
Function
ABS
FLOOR
CEIL
MIN
MAX
COUNT
Definition
ABS(integer-expression): Remove sign from signed value.
FLOOR(integer-expression): Rounds real number down to nearest integer.
CEIL(real-expression): Rounds real number up to nearest integer.
MIN(integer-expression-list): Picks minimum integer or real value of comma separated list.
MAX(integer-expression-list): Picks maximum integer or real value of comma separated list.
COUNT(integer-expression): Returns the number of binary 1’s in the integer.
21
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 2: Functions
Function
ROUND
Definition
ROUND(real-expression): Rounds to the nearest integer; halfway rounds away from
zero.
UNIT(fieldName UnitOfMeasure): Input operand is a register field name that defines
all values with the same unit of measure. Returns the value expressed in the unit of
measure for the current value of the register field.
POW(base, exponent): POW(x,y) returns the value x to the power of y.
UNIT
POW
1.3.3
Operator Precedence and Associativity
This document follows C operator precedence and associativity. The following table lists operator precedence
(highest to lowest). Their associativity indicates in what order operators of equal precedence in an expression
are applied. Parentheses are also used to group sub-expressions to force a different precedence; such parenthetical expressions can be nested and are evaluated from inner to outer. E.g. “X = A | ~B & C” is the same as “X=
A | ((~B) & C)”.
Table 3: Operator Precedence and Associativity
Operator Description
!, ~
*, /, %
+, <<, >>
Logical negation/bitwise complement
right-to-left
Multiplication/division/modulus
left-to-right
Addition/subtraction
left-to-right
Bitwise shift left, Bitwise shift right
left-to-right
< , <=, >, Relational operators
>=, ==, !=
left-to-right
&
Bitwise AND
left-to-right
^
Bitwise exclusive OR
left-to-right
|
Bitwise inclusive OR
left-to-right
Logical AND
left-to-right
||
Logical OR
left-to-right
?:
Ternary conditional
right-to-left
&&
1.4
Associativity
Definitions
Table 4: Definitions
Term
AP
BAPM
BatteryPower
BCS
Definition
Application processor. See 2.3 [Processor Initialization].
Bidirectional Application Power Management. See 2.5.9.3 [Bidirectional Application Power
Management (BAPM)].
The system is running from a battery power source or otherwise undocked from a continuous
power supply. Setting using this definition may be required to change during runtime.
Base configuration space. See 2.7 [Configuration Space].
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Table 4: Definitions
Term
BERT
Definition
Bit error rate tester. A piece of test equipment that generates arbitrary test patterns and checks
that a device under test returns them without errors.
BIST
Built-in self-test. Hardware within the processor that generates test patterns and verifies that
they are stored correctly (in the case of memories) or received without error (in the case of
links).
Boot VID
Boot voltage ID. This is the VDD and VDDNB voltage level that the processor requests from
the external voltage regulator during the initial phase of the cold boot sequence. See 2.5.1.2
[Internal VID Registers and Encodings].
BCD
Binary coded decimal number format.
BSC
Boot strap core. Core 0 of the BSP. Specified by MSR0000_001B[BSC].
BSP
Boot strap processor. See 2.3 [Processor Initialization].
CAR
Use of the L2 cache as RAM during boot. See 2.3.3 [Using L2 Cache as General Storage During Boot].
C-states
These are ACPI-defined core power states. C0 is operational. All other C-states are low-power
states in which the processor is not executing code. See 2.5.3.2 [Core C-states].
Canonical
An address in which the state of the most-significant implemented bit is duplicated in all the
address
remaining higher-order bits, up to bit 63.
Channel
See DRAM channel.
CMP
Chip multi-processing. Refers to processors that include multiple cores. See 2.1 [Processor
Overview].
COF
Current operating frequency of a given clock domain. See 2.5.3 [CPU Power Management].
Cold reset
PWROK is deasserted and RESET_L is asserted. See 2.3 [Processor Initialization].
Core Cluster Four JG Cores that share L2 resources. See L2 complex.
L2 complex Four Cores that share L2 resources. See 2.1 [Processor Overview].
Core
CPB
CpuCoreNum
CPUID
function X
CS
DCT
DCQ
DDR3
DID
The instruction execution unit of the processor. See 2.1 [Processor Overview].
Core performance boost. See 2.5.9.1 [Core Performance Boost (CPB)].
Specifies the core number. See 2.4.4 [Processor Cores and Downcoring].
Refers to the CPUID instruction when EAX is preloaded with X. See 3.18 [CPUID Instruction
Registers].
Chip select. See D18F2x[5C:40]_dct[0] [DRAM CS Base Address].
DRAM controller. See 2.9 [DRAM Controllers (DCTs)].
DRAM controller queue.
DDR3 memory technology. See 2.9 [DRAM Controllers (DCTs)].
Divisor identifier. Specifies the post-PLL divisor used to reduce the COF. See 2.5.3 [CPU
Power Management].
Doubleword A 32-bit value.
Downcoring Removal of cores. See 2.4.4 [Processor Cores and Downcoring].
DRAM
The part of the DRAM interface that connects to a DIMM. See 2.9 [DRAM Controllers
channel
(DCTs)].
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Table 4: Definitions
Term
Dual-Plane
DW
ECS
EDS
FCH
FDS
FID
FreeRunSampleTimer
GB
#GP
#GP(0)
GpuEnabled
GT/s
HCD
HTC
Definition
Refers to a processor or systemboard where VDD and VDDNB are separate and may operate at
independent voltage levels. Refer to 2.5.1 [Processor Power Planes And Voltage Control].
Doubleword. A 32-bit value.
Extended configuration space. See 2.7 [Configuration Space].
Electrical data sheet. See 1.2 [Reference Documents].
Fusion Controller Hub. The integrated platform device that contains the IO subsystem and the
bridge to system BIOS. See 2.15 [Fusion Controller Hub].
Functional data sheet; there is one FDS for each package type.
Frequency identifier. Specifies the PLL frequency multiplier for a given clock domain. See
2.5.3 [CPU Power Management].
An internal free running timer used by many power management features. The timer increments at the rate specified by D18F4x110[CSampleTimer].
Gbyte or Gigabyte; 1,073,741,824 bytes.
A general-protection exception.
Notation indicating a general-protection exception (#GP) with error code of 0.
GpuEnabled = (D1F0x00!=FFFF_FFFFh).
Giga-transfers per second.
Host Controller Driver. A software component.
Hardware thermal control. See 2.10.3.1 [PROCHOT_L and Hardware Thermal Control
(HTC)].
HTC-active Hardware-controlled lower-power, lower-performance state used to reduce temperature. See
state
2.10.3.1 [PROCHOT_L and Hardware Thermal Control (HTC)].
IBS
Instruction based sampling. See 2.6.2 [Instruction Based Sampling (IBS)].
IFCM
Isochronous flow-control mode, as defined in the link specification.
ILM
Internal loopback mode. Mode in which the link receive lanes are connected directly to the
transmit lanes of the same link for testing and characterization. See D18F0x[18C:170] [Link
Extended Control].
IO configu- Access to configuration space through IO ports CF8h and CFCh. See 2.7 [Configuration
ration
Space].
IORR
IO range register. See MSRC001_00[18,16] [IO Range Base (IORR_BASE[1:0])].
KB
Kbyte or Kilobyte; 1024 bytes.
L1 cache
The level 1 caches (instruction cache and the data cache) and the level 2 caches. See 2.1 [Processor Overview].
L2 cache
L2I
The L2 Interface complex common to a set of cores.
L2BC
L2I Base Core. The lowest numbered core for a L2I instance.
Linear (vir- The address generated by a core after the segment is applied.
tual) address
Link
Generic term that refers to a refer to PCIe® link.
LINT
Local interrupt.
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Table 4: Definitions
Term
Logical
address
LVT
Definition
The address generated by a core before the segment is applied.
Local vector table. A collection of APIC registers that define interrupts for local events. E.g.,
APIC[530:500] [Extended Interrupt [3:0] Local Vector Table].
Master
This is a PCI-defined term that is applied to transactions on other than PCI buses. It indicates
abort
that the transaction is terminated without affecting the intended target; reads return all 1’s;
writes are discarded; the master abort error code is returned in the response, if applicable; master abort error bits are set if applicable.
MB
Megabyte; 1024 KB.
MCT
Memory controller. See 2.8 [Northbridge (NB)].
MCQ
Memory controller queue. See 2.8 [Northbridge (NB)].
Micro-op
Micro-op. Instructions have variable-length encoding and many perform multiple primitive
operations. The processor does not execute these complex instructions directly, but, instead,
decodes them internally into simpler fixed-length instructions called macro-ops. Processor
schedulers subsequently break down macro-ops into sequences of even simpler instructions
called micro-ops, each of which specifies a single primitive operation. See Software Optimization Guide for AMD Family 16h Processors.
MEMCLK Refers to the clock signals, M[B, A][3:0]_CLK, that are driven from the processor to DDR
DIMMs.
MMIO
Memory-mapped input-output range. This is physical address space that is mapped to the IO
functions such as the IO links or MMIO configuration. The IO link MMIO ranges are specified
by D18F1x[2CC:2A0,1CC:180,BC:80] [MMIO Base/Limit].
MMIO con- Access to configuration space through memory space. See 2.7 [Configuration Space].
figuration
MSR
Model-specific register. The core includes several MSRs for general configuration and control.
See 3.19 [MSRs - MSR0000_xxxx] for the beginning of the MSR register definitions.
MTRR
Memory-type range register. The MTRRs specify the type of memory associated with various
memory ranges. See MSR0000_00FE, MSR0000_020[F:0], MSR0000_02[6F:68,59:58,50],
and MSR0000_02FF.
NB
Northbridge. The transaction routing block of the node. See 2.1 [Processor Overview].
NBC
NBC = (CPUID Fn0000_0001_EBX[LocalApicId[3:0]]==0). Node Base Core. The lowest
numbered core in the node.
NBPMC
Performance monitor counter. See 2.6.1.3 [NB Performance Monitor Counters].
The main northbridge clock. The NCLK frequency is the NB COF.
NCLK
Node
See 2.1 [Processor Overview].
Normalized Addresses used by DCTs. See 2.8 [Northbridge (NB)].
address
OW
Octword. An 128-bit value.
ODM
On-DIMM mirroring. See D18F2x[5C:40]_dct[0][OnDimmMirror].
ODT
On-die termination, which is applied DRAM interface signals.
ODTS
DRAM On-die thermal sensor.
Operational The frequency at which the processor operates. See 2.5 [Power Management].
frequency
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Table 4: Definitions
Term
®
PCIe
PDS
Physical
address
PMC
PRBS
Processor
PSI
P-state
PTE
QW
RAS
Definition
PCI Express®.
Product data sheet.
Addresses used by cores in transactions sent to the NB.
Performance monitor counter. See 2.6.1.1 [Core Performance Monitor Counters].
Pseudo-random bit sequence.
See 2.1 [Processor Overview].
Power Status Indicator. See 2.5.1.3.1 [PSIx_L Bit].
Performance state. See 2.5 [Power Management].
Page table entry.
Quadword. A 64-bit value.
Reliability, availability and serviceability (industry term). See 2.14.1 [Machine Check Architecture].
RDQ
Read data queue.
REFCLK
Reference Clock, refers to the clock frequency (100 MHz) or the clock period (10 ns) depending on the context used.
RX
Receiver.
RevA0
RevA0 = ((D18F3xFC[BaseModel] == 0h) && (D18F3xFC[Stepping] == 0h))
RevA1
RevA1 = ((D18F3xFC[BaseModel] == 0h) && (D18F3xFC[Stepping] == 1h)).
Scrubber
Background memory checking logic. See 2.8.3 [Memory Scrubbers].
Shutdown
A state in which the affected core waits for either INIT, RESET, or NMI. When shutdown state
is entered, a shutdown special cycle is sent on the IO links.
Single-Plane Refers to a processor or systemboard where VDD and VDDNB are tied together and operate at
the same voltage level. Refer to 2.5.1 [Processor Power Planes And Voltage Control].
Slam
Refers to changing the voltage to a new value in one step (as opposed to stepping). See
2.5.1.4.1 [Hardware-Initiated Voltage Transitions].
SMAF
System management action field. This is the code passed from the SMC to the processors in
STPCLK assertion messages. The action taken by the processors in response to this message is
specified by D18F3x[84:80] [ACPI Power State Control].
SMBus
System management bus.
Refers to the protocol on which the serial VID interface (SVI) commands are based. See 2.5.1
[Processor Power Planes And Voltage Control], and 1.2 [Reference Documents].
System management controller. This is the platform device that communicates system management state information to the processor through an IO link, typically the system IO hub.
SMI
System management interrupt. See 2.4.8.2.1 [SMM Overview].
SMM
System management mode. See 2.4.8.2 [System Management Mode (SMM)].
Speculative A performance monitor event counter that counts all occurrences of the event even if the event
event
occurs during speculative code execution.
SVI2
Serial VID 2.0 interface. See 2.5.1.1 [Serial VID Interface]
SVM
Secure virtual machine. See 2.4.9 [Secure Virtual Machine Mode (SVM)].
SMC
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Table 4: Definitions
Term
Sync flood
TX
UI
UMI
VDD
Definition
The propagation of continuous sync packets to all links. This is used to quickly stop the transmission of potentially bad data when there are no other means to do so. See the link specification for additional information.
Temperature calculation circuit. See 2.10 [Thermal Functions].
Processor temperature control value. See 2.10.3 [Temperature-Driven Logic].
Thermal design current. See the AMD Infrastructure Roadmap, #41482.
Thermal design power. A power consumption parameter that is used in conjunction with thermal specifications to design appropriate cooling solutions for the processor. See 2.5.9.2 [TDP
Limiting].
A scheduler entry used in various northbridge queues to track outstanding requests. See
D18F3x140 [SRI to XCS Token Count] on Page 461.
Transmitter.
Unit interval. This is the amount of time equal to one half of a clock cycle.
Unified Media Interface. The link between the processor and the FCH.
Main power supply to the processor core logic.
VDDNB
Main power supply to the processor NB logic.
TCC
Tctl
TDC
TDP
Token
VID
Voltage level identifier. See 2.5.1 [Processor Power Planes And Voltage Control].
Virtual CAS The clock in which CAS is asserted for the burst, N, plus the burst length (in MEMCLKs),
minus 1; so the last clock of virtual CAS = N + (BL/2) - 1.
VRM
Voltage regulator module.
W
Word. A 16-bit value.
Warm reset RESET_L is asserted only (while PWROK stays high). See 2.3 [Processor Initialization].
WDT
Watchdog timer. A timer that detects activity and triggers an error if a specified period of time
expires without the activity. For example, see MSRC001_0074 [CPU Watchdog Timer (CpuWdtCfg)] or the NB watchdog timer in D18F3x40 [MCA NB Control].
WDQ
Write data queue.
XBAR
Cross bar; command packet switch. See 2.8 [Northbridge (NB)].
1.5
1.5.1
Changes Between Revisions and Product Variations
Revision Conventions
The processor revision is specified by CPUID Fn0000_0001_EAX [Family, Model, Stepping Identifiers] or
CPUID Fn8000_0001_EAX [Family, Model, Stepping Identifiers]. This document uses a revision letter
instead of specific model numbers. The following table contains the definitions based on model and stepping
used in this document. Where applicable, the processor stepping is indicated after the revision letter. All behavior marked with a revision letter apply to future revisions unless they are superseded by a change in a later revision. See the revision guide for additional information about revision determination. See 1.2 [Reference
Documents].
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Table 5: Processor revision conventions
Term
PROC
KB_A1
1.5.2
Definition
Processor. PROC = {CPUID Fn0000_0001_EAX[ExtFamily], {CPUID
Fn0000_0001_EAX[ExtModel], CPUID Fn0000_0001_EAX[BaseModel]},
CPUID Fn0000_0001_EAX[Stepping]}.
KB_A1 = {07h,00h,1h}.
Major Changes
This section describes the major changes relative to Family 14h Models 00h-0Fh (ON) Processors.
• CPU core (JG) changes, with respect to BT:
• Architectural changes:
• Shared L2 Cache.
• MSRC001_023[6,4,2,0], MSRC001_023[7,5,3,1] L2I Performance counters indicated by CPUID
Fn8000_0001_ECX[PerfCtrExtL2I].
• MSRC001_024[6,4,2,0], MSRC001_024[7,5,3,1]: NB Performance counters indicated by CPUID
Fn8000_0001_ECX[PerfCtrExtNB].
• CPUID Fn8000_0008_EAX[PhysAddrSize]: Physical Address Extended to 40 bits.
• CPUID Fn8000_0001_ECX[DataBreakpointExtension]: Debug Breakpoint Extension.
• Instruction set changes:
• CPUID Fn0000_0001_ECX[AVX]: Added AVX instruction support.
• CPUID Fn0000_0001_ECX[XSAVE,OSXSAVE]: CPUID Fn0000_000D: Added XSAVE support.
• CPUID Fn0000_0001_ECX[AES]: Added AES instruction support.
• CPUID Fn0000_0001_ECX[SSE41, SSE42]: Added SSE4.1 and SSE4.2 instruction support.
• CPUID Fn0000_0001_ECX[PCLMULQDQ]: Added PCLMULQDQ instruction support.
• CPUID Fn0000_000D_EAX_x0-CPUID Fn0000_000D_EDX_x2: Added XSAVE/XRSTOR.
• CPUID Fn0000_0001_ECX[MOVBE]: Added MOVBE instruction support.
• CPUID Fn0000_0001_ECX[F16C]: Added F16C instruction support.
• CPUID Fn0000_0007_EBX_x0[BMI1]: Added BMI1 instruction support.
• Virtualization Support
• CPUID Fn8000_000A_EDX[TscRateMsr]: Added TSC Scaling.
• CPUID Fn8000_000A_EDX[FlushByAsid]: Added Flush by ASID.
• CPUID Fn8000_000A_EDX[DecodeAssists]: Added Decode Assist.
• CPUID Fn8000_000A_EDX[PauseFilterThreshold]: Added Enhanced Pause Filter.
1.5.2.1
Major Changes to Core/NB Performance Counters
Major Changes to Core/NB Performance Counters:
PerfMon Changes: Added L2I PerfMon group. See MSRC001_023[6,4,2,0] and MSRC001_023[7,5,3,1].
2
Functional Description
2.1
Processor Overview
The processor is defined as follows:
• The processor is a package that contains one node.
• Supports x86-based instruction sets.
• Packages:
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• FT3: Notebook BGA Package.
• FS1b: Desktop uPGA Package.
• See CPUID Fn8000_0001_EBX[PkgType].
• L2 complex
L 2 C o m p le x
2MB
S h a r e d L2 C A C H E
L 2 I In te rfa c e ( In c lu d e s L 2 T a g s)
CPU CORE
32 KB I CACHE
32 KB DCACHE
CPU CORE
32 KB I CACHE
32 KB DCACHE
CPU CORE
32 KB I CACHE
32 KB D C AC H E
CPU CORE
32 KB I CACHE
32 KB DCACHE
Figure 1: A L2 Complex
•
•
•
•
•
• 1 L2 complex (4 cores)
• 2 MB L2
• See 2.4.1 [L2 complex].
DRAM:
• One 64-bit DDR3 memory channel (A). See Figure 16 [System Diagram].
Northbridge (UNB):
• One communication packet routing block referred to as the northbridge (NB). The NB routes transactions between the cores, the link, and the DRAM interfaces. It includes the configuration register space
for the device.
Graphics northbridge/GNB:
• Link:
• PCIe® Gen2
• One x4 Gfx link, four x1 GPP links.
• See 2.11.3 [Links].
Power Management:
• See 2.5 [Power Management].
RAS:
• See 2.14 [RAS Features].
2.2
System Overview
2.3
Processor Initialization
This section describes the initialization sequence after a cold reset (2.6.1 [Cold Boot Sequence (S4/S5 to S0)]).
Core 0 of the processor, the bootstrap core (BSC), begins executing code from the reset vector. The remaining
cores do not fetch code until their enable bits are set (D18F0x1DC[CpuEn]).
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BSC Initialization
The BSC must perform the following tasks as part of boot.
• Store BIST information from the EAX register into an unused processor register.
• D18F0x6C[InitDet] may be used by BIOS to differentiate between INIT and cold/warm reset.
• Determine type of startup using D18F0x6C[ColdRstDet].
• If this is a warm reset then BIOS may check for valid MCA errors and if present save the status for later
use. See 2.14.1.6 [Handling Machine Check Exceptions].
• Enable the cache, program the MTRRs for CAR and initialize CAR. See 2.3.3 [Using L2 Cache as General
Storage During Boot].
• Setup the SMU.
• Setup of APIC (2.4.8.1.3 [ApicId Enumeration Requirements]).
• Setup the link configuration 2.11.3.2 [Link Configurations].
• Setup the root complex and initialize the I/O links 2.11.4.3 [Link Configuration and Initialization].
• If required, reallocate data and flow control buffers of the links (see D18F0x[F0,D0,B0,90] [Link Base
Channel Buffer Count] and D18F0x[F4,D4,B4,94] [Link Isochronous Channel Buffer Count]).
• Issue system warm reset. See 2.6.2 [Warm Reset Sequence].
• Configure the DRAM controllers.
• Configure processor power management. See 2.5 [Power Management].
• Allow other cores to begin fetching instructions by setting D18F0x1DC[CpuEn] in the PCI configuration
space of all nodes. See 2.4.4 [Processor Cores and Downcoring].
2.3.2
AP Initialization
All other processor cores other than core 0 begin executing code from the reset vector. They must perform the
following tasks as part of boot.
• Store BIST information from the eax register into an unused processor register.
• D18F0x6C[InitDet] may be used by BIOS to differentiate between INIT and cold/warm reset.
• Determine the history of this reset using the D18F0x6C [Link Initialization Control] [ColdRstDet] bit:
• If this is a warm reset then BIOS may check for valid MCA errors and if present save the status for use
later. See 2.14.1.6 [Handling Machine Check Exceptions].
• Set up the local APIC. See 2.4.8.1.3 [ApicId Enumeration Requirements].
• Configure processor power management. See 2.4 [Core].
2.3.3
Using L2 Cache as General Storage During Boot
Prior to initializing the DRAM controller for system memory, BIOS may use the L2 cache as general storage.
If BIOS is not using L2 cache as general storage during boot, program MSRC001_102A[ClLinesToL2Dis]=0.
The L2 cache as general storage is described as follows:
• Each L2 complex has its own L2 cache.
• BIOS manages the mapping of the L2 storage such that cacheable accesses do not cause L2 victims.
• The L2 size, L2 associativity, and L2 line size is determined by reading CPUID Fn8000_0006_ECX[L2Size,
L2Assoc, L2LineSize]. L2WayNum is defined to be the number of ways indicated by the L2Assoc code.
• The L2 cache is viewed as (L2Size/L2LineSize) cache lines of storage, organized as L2WayNum ways,
each way being (L2Size/L2WayNum) in size.
• E.g. L2Assoc=8 so L2WayNum=16 (there are 16 ways). If (L2Size=2MB) then there are 16 blocks
of cache, each 2MB/16 in size, or 128KB each.
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• For each of the following values of L2Size, the following values are defined:
• L2Size=1 MB: L2Tag=PhysAddr[39:16], L2WayIndex=PhysAddr[15:6].
• L2Size=2 MB: L2Tag=PhysAddr[39:17], L2WayIndex=PhysAddr[16:6].
• PhysAddr[5:0] addresses the L2LineSize number of bytes of storage associated with the cache line.
• The L2 cache, when allocating a line at L2WayIndex:
• Picks an invalid way before picking a valid way.
• Prioritizes the picking of invalid ways such that way 0 is the highest priority and L2WayNum-1 is
the lowest priority.
• It is recommended that BIOS assume a simpler allocation of L2 cache memory, being L2WayNum sizealigned blocks of memory, each being L2Size/L2WayNum bytes.
• BIOS can rely on a minimum L2Size of 1 MB and can rely on being able to use all 16 ways for general
storage. See CPUID Fn8000_0006_ECX[L2Size].
The following memory types are supported:
• WP-IO: BIOS ROM may be assigned the write-protect IO memory type and may be accessed read-only
as data and fetched as instructions.
• WP-IO accesses, both read and write, do not get allocated into the L2 and therefore do not need to be
considered for allocation into the L2.
• WB-DRAM: General storage may be assigned the write-back DRAM memory type and may be accessed
as read-write data, but not accessed by instruction fetch.
• BIOS initializes an L2LineSize sized and aligned location in the L2 cache, mapped as write-back
DRAM, with 1 read to at least 1 byte of the L2LineSize sized and aligned WB-DRAM address.
BIOS may store to a line only after it has been allocated by a load.
• Fills, sent to the disabled memory controller, return undefined data.
• All of memory space that is not accessed as WP-IO or WB-DRAM space must be marked as UC memory type.
• In order to prevent victimizing L2 data, no more than L2WayNum cache lines accessed as WB-DRAM may
have the same L2WayIndex.
• Software does not need to know which ways the L2WayNum lines are allocated to for any given value of
L2WayIndex, only that invalid ways will be selected for allocation before valid ways will be selected for
allocation.
• Software is not allowed to deallocate a line in the L2 by using CLFLUSH.
Performance monitor event L2IPMCx060[3:2], titled “write victim block“, can be used to indicate whether L2
dirty data was lost by being victimized and sent to the disabled memory controller.
The following requirements must be satisfied prior to using the cache as general storage:
• Paging must be disabled. Reason: The caching of TLB entries will displace L2 cache entries.
• MSRC001_0015[INVDWBINVD]=0. Reason: INVD’s must be prevented from pushing dirty data to
uninitialized DRAM.
• MSRC001_1021[DisSpecTlbRld]=1. Disable speculative ITLB reloads. Reason: Prevent misinterpreted
speculative IFetch from accessing WB-DRAM dirty lines as code and evicting them from the L2.
• MSRC001_1022[DisSpecTlbWalk]=1. Disable speculative DTLB reloads. Reason: BIOS has been
known to map more memory as WB-DRAM than the size of the L2. Setting this bit will prevent mispredicted speculative data accesses from accessing a region outside of the CAR region that may be mapped
as WB-DRAM and cause an L2 eviction.
• MSRC001_1022[DisHwPf]=1.
• MSRC001_10A0[L2RinserDis]=1. Reason: Disable background removal of stored data.
• MSRC001_10A0[PrefetcherDis]=1. Disable L2 hardware prefetcher.
• MSRC001_10A0[CacheIcAttrDis]=1. Reason: If there is data access to an instruction line whose attri-
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butes were written into that the L2 cache, we would get an L2 eviction so the line could be reloaded from
the NB with ECC.
CLFLUSH, INVD, and WBINVD must not be used during CAR but may be used when tearing down
CAR for all compute units on a node. Reason: In order to ensure that data L2 data for a compute unit is
not evicted when another compute unit completes use of CAR.
The BIOS must not use SSE, or MMX™ instructions, with the exception of the following list: MOVD,
MOVQ, MOVDQA, MOVQ2DQ, MOVDQ2Q.
The BIOS must not enable exceptions, page-faults, and other interrupts.
BIOS must not use software prefetches.
UC-DRAM: All of DRAM that is not accessed as WB-DRAM space must be marked as UC memory
type. Reason: This prevents speculative accesses that fall outside of the CAR region from getting to the
caches and DRAM controller.
When BIOS has completed using the cache for general storage the following steps are followed:
1. Prior to issuing an INVD instruction, BIOS must ensure that no other source of coherent traffic, such as a
DMA engine, is operating in the system. This condition must hold true until the INVD instruction for teardown has been executed on all CPUs.
2. An INVD instruction is executed on each core that used cache as general storage; an INVD is issued when
all cores on all nodes have completed using the cache for general storage.
3. If DRAM is initialized and there is data in the cache that needs to get moved to main memory, CLFLUSH
or WBINVD may be used instead of INVD, but software must ensure that needed data in main memory is
not overwritten.
4. Program the following configuration state (Order is unimportant):
• MSRC001_0015[INVDWBINVD]=1.
• MSRC001_1021[DisSpecTlbRld]=0.
• MSRC001_1022[DisSpecTlbWalk]=0.
• MSRC001_1022[DisHwPf]=0.
• MSRC001_10A0[PrefetcherDis]=0.
• MSRC001_10A0[CacheIcAttrDis]=0.
• MSRC001_102A[ClLinesToL2Dis]=0.
2.3.4
Instruction Cache Configuration Register Usage Requirements
Modification of MSRC001_1021 [Instruction Cache Configuration (IC_CFG)] requires the following steps for
all cores within the L2 complex:
• Synchronize all cores.
• Modify MSRC001_1021 observing the Same-for-all requirement.
• Flush all caches using WBINVD for all cores within the L2 complex.
• Resume all cores.
2.4
Core
The majority of the behavioral definition of the core is specified in the AMD64 Architecture Programmer’s
Manual. See 1.2 [Reference Documents].
2.4.1
L2 complex
Each L2 complex or cluster includes 4 cores each having an x86 instruction execution logic and first-level (L1)
data cache and first-level (L1) instruction cache. The second level (L2) general-purpose cache is shared
between all cores of the L2 complex.
There is a set of MSRs and APIC registers associated with each core. Processors that include multiple cores are
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said to incorporate chip multi-processing or CMP. Unless otherwise specified the processor configuration interface hides the L2 complex implementation and presents software with homogenous cores, each independent of
the other.
Software may use D18F5x80[Enabled, DualCore, TripleCore, QuadCore] in order to associate a core with a L2
complex. This information can be useful because some configuration settings are determined based on active
L2 complexes and core performance may vary based on resource sharing within a L2 complex.
2.4.2
Caches and TLBs
Cache and TLBstorage available to a core is reported by:
• CPUID Fn8000_0005_EAX-CPUID Fn8000_0006_EDX.
• CPUID Fn8000_0019_EAX-CPUID Fn8000_0019_E[D,C]X.
• CPUID Fn8000_001D_EAX_x0-CPUID Fn8000_001E_EDX.
Cache and TLB storage available to a core is summarized as follows:
• L1 and L2 Caches:
• DC: 32 KB, 8-way, write-back, per-core.
• IC: 32 KB, 2-way, per-core.
• L2: 1 MB or 2 MB (Product-specific), 16-way associative, shared between all cores of a L2 complex.
• TLBs:
• D, L1TLB:
• 4 KB: 40 entries, fully associative.
• 2 MB: 8 entries, fully associative.
• D, L2TLB:
• 4 KB: 512 entries, 4 way associative
• 2 MB: 256 entries, hashed 2 way associative.
• I, L1TLB:
• 4 KB: 32 entries, fully associative.
• 2 MB, 8 entries, fully associative.
• I, L2TLB:
• 4 KB: 512 entries, 4-way associative.
2.4.2.1
Registers Shared by Cores in a L2 complex
Some registers are implemented one instance per L2 complex instead of per core; these registers are designated
as Per-L2. The absence of Per-L2 implies the normal per-core instance programming model.
Programing rules for Per-L2 registers:
• Software must ensure that a shared MSR written by one core on a L2 complex will not cause a problem
for software that is running on the other core of the L2 complex.
• Per-L2: A write to a Per-L2 MSR does not have to be written to the other cores of the L2 complex in
order for the other cores to see the updated value.
• A read-modify-write of a shared MSR register is not atomic. Software must ensure atomicity between
the cores that could simultaneously read-modify-write the shared register.
2.4.3
Virtual Address Space
The processor supports 48 address bits of virtual memory space (256 TB) as indicated by CPUID
Fn8000_0008_EAX.
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Processor Cores and Downcoring
Each L2 Complex supports downcoring as follows:
• The number of fuse enabled cores supported is specified by D18F5x84[CmpCap].
• The cores of a L2 complex may be software downcored by D18F3x190[DisCore]. See 2.4.4.1 [Software
Downcoring using D18F3x190[DisCore]].
• Clocks are turned off and power is gated to software or fuse downcored L2 complexes. The power savings is the same as CC6.
• There must be at least 1 L2 complex enabled.
• D18F3x190[DisCore] affects the value of CPUID Fn0000_0001_EBX[LogicalProcessorCount], CPUID
Fn0000_0001_EDX[HTT], CPUID Fn8000_0001_ECX[CmpLegacy], CPUID
Fn8000_0008_ECX[NC], D18F3x12C[CpuNum], D18F5x80[Enabled, DualCore, TripleCore, QuadCore]. D18F3x190[DisCore] does not affect the value of D18F5x84[CmpCap].
• An implemented (physical) core that is downcored is not visible to software. Cores that are not downcored
are numbered logically in a contiguous manner. The physical to logical mapping is described as follows:
• D18F5x80 [Compute Unit Status 1] reports core topology information to software.
• The number of cores specified in CPUID Fn8000_0008_ECX[NC] must be the same as the number of cores
enabled in D18F0x1DC[CpuEn].
• The core number, CpuCoreNum, is provided to SW running on each core through CPUID
Fn0000_0001_EBX[LocalApicId] and APIC20[ApicId]; CpuCoreNum also affects D18F0x1DC[CpuEn].
CpuCoreNum, varies as the lowest integers from 0 to D18F5x84[CmpCap], based on the number of enabled
cores; e.g., a 4-core node with 1 core disabled results in cores reporting CpuCoreNum values of 0, 1, and 2
regardless of which core is disabled. The boot core is always the core reporting CpuCoreNum=0.
Some legacy operating systems do not support processors with a non-power-of-2 number of cores. The BIOS is
recommended to support a user configurable option to disable cores down to a power-of-2 number of cores for
legacy operating system support.
2.4.4.1
Software Downcoring using D18F3x190[DisCore]
Cores may be downcored by D18F3x190[DisCore].
Software is required to use D18F3x190[DisCore] as follows:
• Setting bits corresponding to cores that are not present results in undefined behavior.
• Once a core has been removed by D18F3x190[DisCore]=1, it cannot be added back without a cold reset.
E.g. Software may only set DisCore bits, never clear them.
• For enabled L2 complexs where (L2 complex>=1) software may not disable logical Core 0 of the L2
complex.
• The most significant bit N, affected by Fuse[CoreDis], is (the number of cores)-1 at cold reset; the number of cores at cold reset is (CPUID Fn8000_0008_ECX[NC]+1).
• The most significant bit N and the logical core ID significance of DisCore is not affected by the value of
DisCore followed by a warm-reset.
• E.g. If logical core 2 is disabled by DisCore[3:0]=0100b followed by a warm reset, then the new logical core 2 is the old logical core 3. If the new logical core 2 needs to then be disabled then DisCore[3:0]=1100b followed by a warm reset.
• All bits greater than bit N are reserved. Bits greater than N associated with a fuse disabled core are readwrite. Bits greater than N associated with a non-existent core are read-only.
• If D18F3x190[DisCore] is changed, then the following need to be updated:
• D18F0x60[CpuCnt[4:0]].
• D18F5x170[NbPstateThreshold]
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Physical Address Space
The processor supports a 40 bit physical address space, as indicated by CPUID Fn8000_0008_EAX [Long
Mode Address Size Identifiers].
The processor master aborts the following upper-address transactions (to address PhysAddr):
• Link or core requests with non-zero PhysAddr[63:40].
2.4.6
System Address Map
The processor defines a reserved memory address region starting at 0000_00FD_0000_0000h and extending
up to 0000_0100_0000_0000h. System software must not map memory into this region. Downstream host
accesses to the reserved address region results in a page fault. Upstream system device accesses to the reserved
address region results in an undefined operation.
2.4.6.1
Memory Access to the Physical Address Space
All memory accesses to the physical address space from a core are sent to its associated northbridge (NB). All
memory accesses from a link are routed through the NB. An IO link access to physical address space indicates
to the NB the cache attribute (Coherent or Non-coherent, based on bit[0] of the Sized Read and Write commands).
A core access to physical address space has two important attributes that must be determined before issuing the
access to the NB: the memory type (e.g., WB, WC, UC; as described in the MTRRs) and the access destination
(DRAM or MMIO).
This mechanism is managed by the BIOS and does not require any setup or changes by system software.
2.4.6.1.1
Determining Memory Type
The memory type for a core access is determined by the highest priority of the following ranges that the access
falls in: 1==Lowest priority.
1. The memory type as determined by architectural mechanisms.
• See the APM2 chapter titled “Memory System”, sections “Memory-Type Range Registers”and “PageAttribute Table Mechanism”.
• See the APM2 chapter titled “Nested Paging”, section “Combining Memory Types, MTRRs”.
• See MSR0000_02FF [MTRR Default Memory Type (MTRRdefType)], MSR0000_020[F:0] [VariableSize MTRRs Base/Mask], MSR0000_02[6F:68,59:58,50] [Fixed-Size MTRRs].
2. TSeg & ASeg SMM mechanism. (see MSRC001_0112 and MSRC001_0113)
3. CR0[CD]: If (CR0[CD]==1) then MemType=CD.
4. MMIO config space, APIC space.
• MMIO APIC space and MMIO config space must not overlap.
• MemType=UC.
• See 2.4.8.1.2 [APIC Register Space] and 2.7 [Configuration Space].
5. SmmATValNoMchFrcCD: If (“In SMM Mode” && (MSRC001_102A[SmmATValNoMchFrcCDDis]==0) && ~((MSRC001_0113[AValid] && “The address falls within the ASeg region”) ||
(MSRC001_0113[TValid] && “The address falls within the TSeg region”))) then MemType=CD.
2.4.6.1.2
Determining The Access Destination for Core Accesses
The access destination, DRAM or MMIO, is based on the highest priority of the following ranges that the
access falls in: 1==Lowest priority.
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1. RdDram/WrDram as determined by MSRC001_001A [Top Of Memory (TOP_MEM)] and
MSRC001_001D [Top Of Memory 2 (TOM2)].
2. The IORRs. (see MSRC001_00[18,16] and MSRC001_00[19,17]).
3. The fixed MTRRs. (see MSR0000_02[6F:68,59:58,50] [Fixed-Size MTRRs])
4. TSeg & ASeg SMM mechanism. (see MSRC001_0112 and MSRC001_0113)
5. MMIO config space, APIC space.
• MMIO APIC space and MMIO config space must not overlap.
• RdDram=IO, WrDram=IO.
• See 2.4.8.1.2 [APIC Register Space] and 2.7 [Configuration Space].
6. NB address space routing. See 2.8.2.1.1 [DRAM and MMIO Memory Space].
2.4.7
Timers
Each core includes the following timers. These timers do not vary in frequency regardless of the current P-state
or C-state.
• MSR0000_0010 [Time Stamp Counter (TSC)]; the TSC increments at the rate specified by the P0 Pstate.
• See 2.5.3.1.1.1 [Software P-state Numbering].
• See MSRC001_00[6B:64] [P-state [7:0]].
• The APIC timer (APIC380 and APIC390), which increments at the rate of 2xCLKIN; the APIC timer
may increment in units of between 1 and 8.
2.4.8
2.4.8.1
Interrupts
Local APIC
The local APIC contains logic to receive interrupts from a variety of sources and to send interrupts to other
local APICs, as well as registers to control its behavior and report status. Interrupts can be received from:
• IO devices including the IO hub (IO APICs)
• Other local APICs (inter-processor interrupts)
• APIC timer
• Thermal events
• Performance counters
• Legacy local interrupts from the IO hub (INTR and NMI)
• APIC internal errors
The APIC timer, thermal events, performance counters, local interrupts, and internal errors are all considered
local interrupt sources, and their routing is controlled by local vector table entries. These entries assign a message type and vector to each interrupt, allow them to be masked, and track the status of the interrupt.
IO and inter-processor interrupts have their message type and vector assigned at the source and are unaltered
by the local APIC. They carry a destination field and a mode bit that together determine which local APIC(s)
accepts them. The destination mode (DM) bit specifies if the interrupt request packet should be handled in
physical or logical destination mode. If the destination field matches the broadcast value specified by
D18F0x68[ApicExtBrdCst], then the interrupt is a broadcast interrupt and is accepted by all local APICs
regardless of destination mode.
2.4.8.1.1
Detecting and Enabling
APIC is detected and enabled via CPUID Fn0000_0001_EDX[APIC].
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The local APIC is enabled via MSR0000_001B[ApicEn]. Reset forces APIC disabled.
2.4.8.1.2
APIC Register Space
MMIO APIC space:
• Memory mapped to a 4 KB range. The memory type of this space is the UC memory type; also, hardware
forces the 4 KB page mapped by ApicBar to UC. The base address of this range is specified by
{MSR0000_001B[ApicBar[47:12]], 000h}.
• The mnemonic is defined to be APICXX; XX is the byte address offset from the base address.
• MMIO APIC registers in xAPIC mode is defined by the register from APIC20 to APIC[530:500].
• Treated as normal memory space when APIC is disabled, as specified by MSR0000_001B[ApicEn].
2.4.8.1.3
ApicId Enumeration Requirements
System hardware and BIOS must ensure that the number of cores per processor (NC) exposed to the operating
system by all tables, registers, and instructions across all cores in the processor is identical. See 2.4.10.1
[Multi-Core Support] to derive NC.
Operating systems are expected to use CPUID Fn8000_0008_ECX[ApicIdCoreIdSize], the number of least
significant bits in the Initial APIC ID that indicate core ID within a processor, in constructing per-core CPUID
masks. (ApicIdCoreIdSize[3:0] determines the maximum number of cores (MNC) that the processor could theoretically support, not the actual number of cores that are actually implemented or enabled on the processor, as
indicated by CPUID Fn8000_0008_ECX[NC].) MNC = (2 ^ CPUID Fn8000_0008_ECX[ApicIdCoreIdSize]).
BIOS must use the ApicId MNC rule when assigning APIC20[ApicId] values as described below.
ApicId MNC rule: The ApicId of core j on processor i must be enumerated/assigned as:
• ApicId[proc=i, core=j] = (OFFSET_IDX + i) * MNC + j
• Where OFFSET_IDX is an integer offset (0 to N) used to shift up the core ApicId values to allow room
for IOAPIC devices.
It is recommended that BIOS use the following APIC ID assignments for the broadest operating system support. Given N = (Number_Of_Processors * MNC) and M = Number_Of_IOAPICs:
• If (N+M) < 16, then assign the local (core) ApicIds first from 0 to N-1, and the IOAPIC IDs from N to
N+(M-1). APIC ID 15 is reserved for broadcast when APIC410[ExtApicIdEn]==0.
• If (N+M) >= 16, then assign the IOAPIC IDs first from 0 to M-1, and the local (core) ApicIds from K to
K+(N-1), where K is an integer multiple of MNC greater than M-1.
2.4.8.1.4
Physical Destination Mode
The interrupt is only accepted by the local APIC whose APIC20[ApicId] matches the destination field of the
interrupt. Physical mode allows up to 255 APICs to be addressed individually.
2.4.8.1.5
Logical Destination Mode
A local APIC accepts interrupts selected by APICD0 [Logical Destination (LDR)] and the destination field of
the interrupt using either cluster or flat format as configured by APICE0[Format].
If flat destinations are in use, bits 7-0 of APICD0[Destination] are checked against bits 7-0 of the arriving
interrupt’s destination field. If any bit position is set in both fields, the local APIC is a valid destination. Flat
format allows up to 8 APICs to be addressed individually.
If cluster destinations are in use, bits 7-4 of APICD0[Destination] are checked against bits 7-4 of the arriving
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interrupt’s destination field to identify the cluster. If all of bits 7-4 match, then bits 3-0 of APICD0[Destination]
and the interrupt destination are checked for any bit positions that are set in both fields to identify processors
within the cluster. If both conditions are met, the local APIC is a valid destination. Cluster format allows 15
clusters of 4 APICs each to be addressed.
2.4.8.1.6
Interrupt Delivery
SMI, NMI, INIT, Startup, and External interrupts are classified as non-vectored interrupts.
When an APIC accepts a non-vectored interrupt, it is handled directly by the processor instead of being queued
in the APIC. When an APIC accepts a fixed or lowest-priority interrupt, it sets the bit in APIC[270:200] [Interrupt Request (IRR)] corresponding to the vector in the interrupt. For local interrupt sources, this comes from
the vector field in that interrupt’s local vector table entry. The corresponding bit in APIC[1F0:180] [Trigger
Mode (TMR)] is set if the interrupt is level-triggered and cleared if edge-triggered. If a subsequent interrupt
with the same vector arrives when the corresponding bit in APIC[270:200][RequestBits] is already set, the two
interrupts are collapsed into one. Vectors 15-0 are reserved.
2.4.8.1.7
Vectored Interrupt Handling
APIC80 [Task Priority (TPR)] and APICA0 [Processor Priority (PPR)] each contain an 8-bit priority divided
into a main priority (bits 7-4) and a priority sub-class (bits 3-0). The task priority is assigned by software to set
a threshold priority at which the processor is interrupted.
The processor priority is calculated by comparing the main priority (bits 7-4) of APIC80[Priority] to bits 7-4 of
the 8-bit encoded value of the highest bit set in APIC[170:100] [In-Service (ISR)]. The processor priority is the
higher of the two main priorities.
The processor priority is used to determine if any accepted interrupts (indicated by APIC[270:200][RequestBits]) are high enough priority to be serviced by the processor. When the processor is ready to service an interrupt, the highest bit in APIC[270:200][RequestBits] is cleared, and the corresponding bit is set in
APIC[170:100][InServiceBits].
When the processor has completed service for an interrupt, it performs a write to APICB0 [End of Interrupt],
clearing the highest bit in APIC[170:100][InServiceBits] and causing the next-highest interrupt to be serviced.
If the corresponding bit in APIC[1F0:180][TriggerModeBits] is set, a write to APICB0 is performed on all
APICs to complete service of the interrupt at the source.
2.4.8.1.8
Interrupt Masking
Interrupt masking is controlled by the APIC410 [Extended APIC Control]. If APIC410[IerEn] is set,
APIC[4F0:480] [Interrupt Enable] are used to mask interrupts. Any bit in APIC[4F0:480][InterruptEnableBits]
that is clear indicates the corresponding interrupt is masked. A masked interrupt is not serviced and the corresponding bit in APIC[270:200][RequestBits] remains set.
2.4.8.1.9
Spurious Interrupts
In the event that the task priority is set to or above the level of the interrupt to be serviced, the local APIC
delivers a spurious interrupt vector to the processor, as specified by APICF0 [Spurious-Interrupt Vector
(SVR)]. APIC[170:100] is not changed and no write to APICB0 occurs.
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Spurious Interrupts Caused by Timer Tick Interrupt
A typical interrupt is asserted until it is serviced. An interrupt is deasserted when software clears the interrupt
status bit within the interrupt service routine. Timer tick interrupt is an exception, since it is deasserted regardless of whether it is serviced or not.
The processor is not always able to service interrupts immediately (i.e. when interrupts are masked by clearing
EFLAGS.IM or when the processor is in PDM).
If the processor is not able to service the timer tick interrupt for an extended period of time, the INTR caused
by the first timer tick interrupt asserted during that time is delivered to the local APIC in ExtInt mode and
latched, and the subsequent timer tick interrupts are lost. The following cases are possible when the processor
is ready to service interrupts:
• An ExtInt interrupt is pending, and INTR is asserted. This results in timer tick interrupt servicing. This
occurs 50 percent of the time.
• An ExtInt interrupt is pending, and INTR is deasserted. The processor sends the interrupt acknowledge
cycle, but when the PIC receives it, INTR is deasserted, and the PIC sends a spurious interrupt vector.
This occurs 50 percent of the time.
There is a 50 percent probability of spurious interrupts to the processor.
2.4.8.1.11
Lowest-Priority Interrupt Arbitration
Fixed, remote read, and non-vectored interrupts are accepted by their destination APICs without arbitration.
Delivery of lowest-priority interrupts requires all APICs to arbitrate to determine which one accepts the interrupt. If APICF0[FocusDisable] is clear, then the focus processor for an interrupt always accepts the interrupt.
A processor is the focus of an interrupt if it is already servicing that interrupt (corresponding bit in
APIC[170:100][InServiceBits] is set) or if it already has a pending request for that interrupt (corresponding bit
in APIC[270:200][RequestBits] is set). If APIC410[IerEn] is set the interrupt must also be enabled in
APIC[4F0:480][InterruptEnableBits] for a processor to be the focus processor. If there is no focus processor
for an interrupt, or focus processor checking is disabled, then each APIC calculates an arbitration priority
value, stored in APIC90 [Arbitration Priority (APR)], and the one with the lowest result accepts the interrupt.
The arbitration priority value is calculated by comparing APIC80[Priority] with the 8-bit encoded value of the
highest bit set in APIC[270:200][RequestBits] (IRRVec) and the 8-bit encoded value of the highest bit set
APIC[170:100][InServiceBits] (ISRVec). If APIC410[IerEn] is set the IRRVec and ISRVec are based off the
highest enabled interrupt. The main priority bits 7-4 are compared as follows:
IF ((APIC80[Priority[7:4]] >= IRRVec[7:4]) && (APIC80[Priority[7:4]] > ISRVec[7:4])) THEN
APIC90[Priority] = APIC80[Priority]
ELSEIF (IRRVec[7:4] > ISRVec[7:4]) THEN
APIC90[Priority] = {IRRVec[7:4],0h}
ELSE
APIC90[Priority] = {ISRVect[7:4],0h}
ENDIF.
2.4.8.1.12
Inter-Processor Interrupts
APIC300 [Interrupt Command Low (ICR Low)] and APIC310 [Interrupt Command High (ICR High)] provide
a mechanism for generating interrupts in order to redirect an interrupt to another processor, originate an interrupt to another processor, or allow a processor to interrupt itself. A write to register APIC300 causes an inter-
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rupt to be generated with the properties specified by the APIC300 and APIC310 fields.
2.4.8.1.13
APIC Timer Operation
The local APIC contains a 32-bit timer, controlled by APIC320 [LVT Timer], APIC380 [Timer Initial Count],
and APIC3E0 [Timer Divide Configuration]. The processor bus clock is divided by the value in APIC3E0[Div]
to obtain a time base for the timer. When APIC380[Count] is written, the value is copied into APIC390 [Timer
Current Count]. APIC390[Count] is decremented at the rate of the divided clock. When the count reaches 0, a
timer interrupt is generated with the vector specified in APIC320[Vector]. If APIC320[Mode] specifies periodic operation, APIC390[Count] is reloaded with the APIC380[Count] value, and it continues to decrement at
the rate of the divided clock. If APIC320[Mask] is set, timer interrupts are not generated.
2.4.8.1.14
Generalized Local Vector Table
All LVTs (APIC330 to APIC3[60:50], and APIC[530:500]) support a generalized message type as follows:
• 000b=Fixed
• 010b=SMI
• 100b=NMI
• 111b=ExtINT
• All other messages types are reserved.
2.4.8.1.15
State at Reset
At power-up or reset, the APIC is hardware disabled (MSR0000_001B[ApicEn]=0) so only SMI, NMI, INIT,
and ExtInt interrupts may be accepted.
The APIC can be software disabled through APICF0[APICSWEn]. The software disable has no effect when
the APIC is hardware disabled.
When a processor accepts an INIT interrupt, the APIC is reset as at power-up, with the exception that:
• APIC20[ApicId] is unaffected.
• Pending APIC register writes complete.
2.4.8.2
System Management Mode (SMM)
System management mode (SMM) is typically used for system control activities such as power management.
These activities are typically transparent to the operating system.
2.4.8.2.1
SMM Overview
SMM is entered by a core on the next instruction boundary after a system management interrupt (SMI) is
received and recognized. A core may be programmed to broadcast a special cycle to the system, indicating that
it is entering SMM mode. The core then saves its state into the SMM memory state save area and jumps to the
SMI service routine (or SMI handler). The pointer to the SMI handler is specified by MSRs. The code and data
for the SMI handler are stored in the SMM memory area, which may be isolated from the main memory
accesses.
The core returns from SMM by executing the RSM instruction from the SMI handler. The core restores its state
from the SMM state save area and resumes execution of the instruction following the point where it entered
SMM. The core may be programmed to broadcast a special bus cycle to the system, indicating that it is exiting
SMM mode.
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Operating Mode and Default Register Values
The software environment after entering SMM has the following characteristics:
• Addressing and operation is in Real mode.
• A far jump, call or return in the SMI handler can only address the lower 1M of memory, unless the
SMI handler first switches to protected mode.
• If (MSRC001_0111[SmmBase]>=0010_0000h) then:
• The value of the CS selector is undefined upon SMM entry.
• The undefined CS selector value should not be used as the target of a far jump, call, or return.
• 4-Gbyte segment limits.
• Default 16-bit operand, address, and stack sizes (instruction prefixes can override these defaults).
• Control transfers that do not override the default operand size truncate the EIP to 16 bits.
• Far jumps or calls cannot transfer control to a segment with a base address requiring more than 20 bits,
as in Real mode segment-base addressing, unless a change is made into protected mode.
• A20M# is disabled. A20M# assertion or deassertion have no affect during SMM.
• Interrupt vectors use the Real mode interrupt vector table.
• The IF flag in EFLAGS is cleared (INTR is not recognized).
• The TF flag in EFLAGS is cleared.
• The NMI and INIT interrupts are masked.
• Debug register DR7 is cleared (debug traps are disabled).
The SMM base address is specified by MSRC001_0111[SmmBase]. Important offsets to the base address
pointer are:
• MSRC001_0111[SmmBase] + 8000h: SMI handler entry point.
• MSRC001_0111[SmmBase] + FE00h - FFFFh: SMM state save area.
2.4.8.2.3
SMI Sources And Delivery
The processor accepts SMIs as link-defined interrupt messages only. The core/node destination of these SMIs
is a function of the destination field of these messages. However, the expectation is that all such SMI messages
are specified to be delivered globally (to all cores of all nodes).
There are also several local events that can trigger SMIs. However, these local events do not generate SMIs
directly. Each of them triggers a programmable IO cycle that is expected to target the SMI command port in the
IO hub and trigger a global SMI interrupt message back to the coherent fabric.
Local sources of SMI events that generate the IO cycle specified in MSRC001_0056 [SMI Trigger IO Cycle]
are:
• In the core, as specified by:
• MSRC001_0022 [Machine Check Exception Redirection].
• MSRC001_00[53:50] [IO Trap (SMI_ON_IO_TRAP_[3:0])].
• All local APIC LVT registers programmed to generate SMIs.
The status for these is stored in SMMFEC4.
2.4.8.2.4
SMM Initial State
After storing the save state, execution starts at MSRC001_0111[SmmBase] + 08000h. The SMM initial state is
specified in the following table.
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Table 6: SMM Initial State
Register
CS
DS
ES
FS
GS
SS
General-Purpose Registers
EFLAGS
RIP
CR0
CR4
GDTR
LDTR
IDTR
TR
DR6
DR7
EFER
2.4.8.2.5
SMM Initial State
SmmBase[19:4]
0000h
0000h
0000h
0000h
0000h
Unmodified (including CR2, CR3, CR8)
0000_0002h
0000_0000_0000_8000h
Bits 0, 2, 3, and 31 cleared (PE, EM, TS, and PG); remainder is unmodified
0000_0000_0000_0000h
Unmodified
Unmodified
Unmodified
Unmodified
Unmodified
0000_0000_0000_0400h
All bits are cleared except bit 12 (SVME) which is unmodified.
SMM Save State
In the following table, the offset field provides the offset from the SMM base address specified by
MSRC001_0111 [SMM Base Address (SMM_BASE)].
Table 7: SMM Save State
Offset
FE00h
FE02h
FE08h
FE10h
FE12h
FE18h
FE20h
FE22h
FE28h
FE30h
FE32h
FE38h
Size
Word
6 Bytes
Quadword
Word
6 Bytes
Quadword
Word
6 Bytes
Quadword
Word
6 Bytes
Quadword
Contents
ES
Selector
Reserved
Descriptor in memory format
CS
Selector
Reserved
Descriptor in memory format
SS
Selector
Reserved
Descriptor in memory format
DS
Selector
Reserved
Descriptor in memory format
Access
Read-only
Read-only
Read-only
Read-only
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Table 7: SMM Save State
Offset
FE40h
FE42h
FE44h
Size
Word
2 Bytes
Doubleword
FE48h
FE50h
FE52h
FE54h
Quadword
Word
2 Bytes
Doubleword
FE58h
FE60h
FE64h
FE66h
FE68h
FE70h
FE72h
FE74h
FE78h
FE80h
FE84h
FEB6h
FE88h
FE90h
FE92h
FE94h
FE98h
FEA0h
FEA8h
FEB0h
FEB8h
FEC0h
FEC4
FEC8h
Quadword
4 Bytes
Word
2 Bytes
Quadword
Word
Word
Doubleword
Quadword
4 Bytes
Word
2 Bytes
Quadword
Word
Word
Doubleword
Quadword
Quadword
Quadword
Quadword
Quadword
Doubleword
Doubleword
Byte
FEC9h
Byte
FECAh
FECCh
FED0h
FED8h
FEE0h
Byte
4 Bytes
Quadword
Quadword
Quadword
Contents
FS
Selector
Reserved
GS
FS Base {16'b[47], 47:32}1
Descriptor in memory format
Selector
Reserved
GS Base {16'b[47], 47:32}1
Descriptor in memory format
GDTR Reserved
Limit
Reserved
Descriptor in memory format
LDTR Selector
Attributes
Limit
Base
IDTR Reserved
Limit
Reserved
Base
TR
Selector
Attributes
Limit
Base
IO_RESTART_RIP
IO_RESTART_RCX
IO_RESTART_RSI
IO_RESTART_RDI
SMMFEC0 [SMM IO Trap Offset]
SMMFEC4 [Local SMI Status]
SMMFEC8 [SMM IO Restart Byte] (no if zero; yes
if non-zero)
SMMFEC9 [Auto Halt Restart Offset] (no if zero;
yes if non-zero)
SMMFECA [NMI Mask]
Reserved
EFER
SMMFED8 [SMM SVM State]
Guest VMCB physical address
Access
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
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Table 7: SMM Save State
Offset
FEE8h
FEF0h
FEFCh
FF00h
FF20h
FF28h
Size
Quadword
8 Bytes
Doubleword
Quadword
Quadword
Quadword
Contents
SVM Virtual Interrupt Control
Reserved
SMMFEFC [SMM-Revision Identifier]
SMMFF00 [SMM Base Address (SMM_BASE)]
Guest PAT
FF30h
Quadword
Host CR42
FF38h
Quadword
Nested CR32
FF40h
Quadword
FF48h
FF50h
FF58h
FF60h
FF68h
FF70h
FF78h
FF80h
FF88h
FF90h
FF98h
FFA0h
FFA8h
FFB0h
FFB8h
FFC0h
FFC8h
FFD0h
FFD8h
FFE0h
FFE8h
FFF0h
FFF8h
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Quadword
Host Cr02
CR4
CR3
CR0
DR7
DR6
RFLAGS
RIP
R15
R14
R13
R12
R11
R10
R9
R8
RDI
RSI
RBP
RSP
RBX
RDX
RCX
RAX
Access
Read-only
Read-only
Read-write
Read-only
Host EFER2
Read-only
Read-write
Read-write
Read-write
Notes:
1. This notation specifies that bit[47] is replicated in each of the 16 MSBs of the DW (sometimes called sign
extended). The 16 LSB’s contain bits[47:32].
2. Only used for an SMI in guest mode with nested paging enabled. Used to control the table walker.
The SMI save state includes most of the integer execution unit. Not included in the save state are: the floating
point state, MSRs, and CR2. In order to be used by the SMI handler, these must be saved and restored. The
save state is the same, regardless of the operating mode (32-bit or 64-bit).
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The following are some offsets in the SMM save state area. The mnemonic for each offset is in the form
SMMxxxx, where xxxx is the offset in the save state.
SMMFEC0 SMM IO Trap Offset
If the assertion of SMI is recognized on the boundary of an IO instruction, SMMFEC0 [SMM IO Trap Offset]
contains information about that IO instruction. For example, if an IO access targets an unavailable device, the
system can assert SMI and trap the IO instruction. SMMFEC0 then provides the SMI handler with information
about the IO instruction that caused the trap. After the SMI handler takes the appropriate action, it can reconstruct and then re-execute the IO instruction from SMM. Or, more likely, it can use SMMFEC8 [SMM IO
Restart Byte], to cause the core to re-execute the IO instruction immediately after resuming from SMM.
Bits Description
31:16 Port: trapped IO port address. Read-only. This provides the address of the IO instruction.
15:12 BPR: IO breakpoint match. Read-only.
11
TF: EFLAGS TF value. Read-only.
10:7 Reserved.
6
SZ32: size 32 bits. Read-only. 1=Port access was 32 bits.
5
SZ16: size 16 bits. Read-only. 1= Port access was 16 bits.
4
SZ8: size 8 bits. Read-only. 1=Port access was 8 bits.
3
REP: repeated port access. Read-only.
2
STR: string-based port access. Read-only.
1
V: IO trap word valid. Read-only. 1=The core entered SMM on an IO instruction boundary; all information in this offset is valid. 0=The other fields of this offset are not valid.
0
RW: port access type. Read-only. 0=IO write (OUT instruction). 1=IO read (IN instruction).
SMMFEC4 Local SMI Status
This offset stores status bits associated with SMI sources local to the core. For each of these bits, 1=The associated mechanism generated an SMI.
Bits
Description
17
SmiSrcLvtExt: SMI source LVT extended entry. Read-only. This bit is associated with the SMI
sources specified in APIC[530:500] [Extended Interrupt [3:0] Local Vector Table].
16
SmiSrcLvtLcy: SMI source LVT legacy entry. Read-only. This bit is associated with the SMI
sources specified by the non-extended LVT entries of the APIC.
15:9 Reserved.
8
3:0
MceRedirSts: machine check exception redirection status. Read-only. This bit is associated with
the SMI source specified in MSRC001_0022[RedirSmiEn].
IoTrapSts: IO trap status. Read-only. Each of these bits is associated with each of the respective
SMI sources specified in MSRC001_00[53:50] [IO Trap (SMI_ON_IO_TRAP_[3:0])].
SMMFEC8 SMM IO Restart Byte
00h on entry into SMM.
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If the core entered SMM on an IO instruction boundary, the SMI handler may write this to FFh. This causes the
core to re-execute the trapped IO instruction immediately after resuming from SMM. The SMI handler should
only write to this byte if SMMFEC0 field V==1; otherwise, the behavior is undefined.
If a second SMI is asserted while a valid IO instruction is trapped by the first SMI handler, the core services the
second SMI prior to re-executing the trapped IO instruction. SMMFEC0 field V==0 during the second entry
into SMM, and the second SMI handler must not rewrite this byte.
If there is a simultaneous SMI IO instruction trap and debug breakpoint trap, the processor first responds to the
SMI and postpones recognizing the debug exception until after resuming from SMM. If debug registers other
than DR6 and DR7 are used while in SMM, they must be saved and restored by the SMI handler. If SMMFEC8
[SMM IO Restart Byte], is set to FFh when the RSM instruction is executed, the debug trap does not occur
until after the IO instruction is re-executed.
Bits Description
7:0
RST: SMM IO Restart Byte. Read-write.
SMMFEC9 Auto Halt Restart Offset
Bits Description
7:1
0
Reserved.
HLT: halt restart. Read-write. Upon SMM entry, this bit indicates whether SMM was entered from
the Halt state. 0=Entered SMM on a normal x86 instruction boundary. 1=Entered SMM from the Halt
state. Before returning from SMM, this bit can be written by the SMI handler to specify whether the
return from SMM should take the processor back to the Halt state or to the instruction-execution state
specified by the SMM state save area (normally, the instruction after the halt). 0=Return to the instruction specified in the SMM save state. 1=Return to the halt state. If the return from SMM takes the processor back to the Halt state, the HLT instruction is not refetched and re-executed. However, the Halt
special bus cycle is broadcast and the processor enters the Halt state.
SMMFECA NMI Mask
Bits Description
7:1
0
Reserved.
NmiMask. Read-write. Specifies whether NMI was masked upon entry to SMM. 0=NMI not masked.
1=NMI masked.
SMMFED8 SMM SVM State
Read-only. This offset stores the SVM state of the processor upon entry into SMM.
Bits Description
63:4 Reserved.
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HostEflagsIf: host Eflags IF.
SvmState.
Bits
000b
001b
010b
101b-011b
110b
111b
Definition
SMM entered from a non-guest state.
Reserved.
SMM entered from a guest state.
Reserved.
SMM entered from a guest state with nested paging enabled.
Reserved.
SMMFEFC SMM-Revision Identifier
SMM entry state: 0003_0064h
Bits Description
31:18 Reserved.
17
BRL. Read-only. Base relocation supported.
16
IOTrap. Read-only. IO trap supported.
15:0 Revision. Read-only.
SMMFF00 SMM Base Address (SMM_BASE)
Bits Description
31:0 See: MSRC001_0111[SmmBase].
2.4.8.2.6
Exceptions and Interrupts in SMM
When SMM is entered, the core masks INTR, NMI, SMI, INIT, and A20M interrupts. The core clears the IF
flag to disable INTR interrupts. To enable INTR interrupts within SMM, the SMM handler must set the IF flag
to 1. A20M is disabled so that address bit 20 is never masked when in SMM.
Generating an INTR interrupt can be used for unmasking NMI interrupts in SMM. The core recognizes the
assertion of NMI within SMM immediately after the completion of an IRET instruction. Once NMI is recognized within SMM, NMI recognition remains enabled until SMM is exited, at which point NMI masking is
restored to the state it was in before entering SMM.
While in SMM, the core responds to the DBREQ and STPCLK interrupts, as well as to all exceptions that may
be caused by the SMI handler.
2.4.8.2.7
The Protected ASeg and TSeg Areas
These ranges are controlled by MSRC001_0112 and MSRC001_0113; see those registers for details.
2.4.8.2.8
SMM Special Cycles
Special cycles can be initiated on entry and exit from SMM to acknowledge to the system that these transitions
are occurring. These are controlled by MSRC001_0015[RsmSpCycDis, SmiSpCycDis].
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Locking SMM
The SMM registers (MSRC001_0112 and MSRC001_0113) can be locked from being altered by setting
MSRC001_0015[SmmLock]. SBIOS must lock the SMM registers after initialization to prevent unexpected
changes to these registers.
2.4.8.2.10
Synchronizing SMM Entry (Spring-Boarding)
The BIOS must take special care to ensure that all cores have entered SMM prior to accessing shared IO
resources and all core SMI interrupt status bits are synchronized. This generally requires that BIOS waits for
all cores to enter SMM.
The following conditions can cause one or more cores to enter SMM without all cores entering SMM:
• More than one IO device in the system is enabled to signal an SMI without hardware synchronization
(e.g. using an end of SMI gate).
• A single device may signal multiple SMI messages without hardware synchronization (e.g. using an end
of SMI gate).
• An SMI is received while one or more AP cores are in the INIT state. This may occur either during BIOS
or secure boot.
• A hardware error prevents a core from entering SMM.
The act of synchronizing cores into SMM is called spring-boarding. Because not all of the above conditions
can be avoided, it is recommended that all systems support spring-boarding.
An ACPI-compliant IO hub is required for spring-boarding. Depending on the IO hub design, BIOS may have
to set additional end-of-SMI bits to trigger an SMI from within SMM.
The software requirements for the suggested spring-boarding implementation are listed as follows.
• A binary semaphore located in SMRAM, accessible by all cores. For the purpose of this discussion, the
semaphore is called CheckSpringBoard. CheckSpringBoard is initialized to zero.
• Two semaphores located in SMRAM, accessible by all cores. For the purpose of this discussion, the
semaphores are called NotInSMM and WaitInSMM. NotInSMM and WaitInSMM are initialized to a
value equal to the number of cores in the system (NumCPUs).
The following BIOS algorithm describes spring-boarding and is optimized to reduce unnecessary SMI activity.
This algorithm must be made part of the SMM instruction sequence for each core in the system.
1. Attempt to obtain ownership of the CheckSpringBoard semaphore with a read-modify-write instruction. If
ownership was obtained then do the following, else proceed to step 2:
• Check all enabled SMI status bits in the IO hub.
Let Status=enable1&status1 | enable2&status2 | enable3&status3 … enable n & status n.
• If (Status==0) then perform the following sub-actions.
• Trigger an SMI broadcast assertion from the IO hub by writing to the software SMI command port.
• Resume from SMM with the RSM instruction.
//Example:
InLineASM{
BTS CheckSpringBoard,0; Try to obtain ownership of semaphore
JC Step_2:
CALL CheckIOHUB_SMIEVT; proc returns ZF=1 for no events
JNZ Step_2:
CALL Do_SpringBoard;Trigger SMI and then RSM
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3.
4.
5.
6.
7.
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Step_2:
}
Decrement the NotInSMM variable. Wait for (NotInSMM==0). See Note 1.
Execute the core-local event SMI handler. Using a third semaphore (not described here), synchronize core
execution at the end of the task. After all cores have executed, proceed to step 4. The following is a brief
description of the task for each core:
• Check all enabled core-local SMI status bits in the core’s private or MSR address space. Handle the
event if possible, or pass information necessary to handle the event to a mailbox for the BSC to handle.
• An exclusive mailbox must exist for each core for each core local event.
• Wait for all cores to complete this task at least once.
If the current core executing instructions is not the BSC then jump to step 5. If the core executing instructions is the BSC then jump to the modified main SMI handler task, described below.
• Check all enabled SMI status bits in the IO hub. Check mailboxes for event status.
• For each event, handle the event and clear the corresponding status bit.
• Repeat until all enabled SMI status bits are clear and no mailbox events remain.
• Set NotInSMM=NumCPUs. (Jump to step 5.)
Decrement the WaitInSMM variable. Wait for WaitInSMM=0. See Note 2.
Increment the WaitInSMM variable. Wait for WaitInSMM=NumCPUs.
If the current processor core executing instructions is the BSC then reset CheckSpringBoard to zero.
Resume from SMM with the RSM instruction.
Notes:
1. To support a secure startup by the secure loader the BIOS must provide a timeout escape from the otherwise endless loop. The timeout value should be large enough to account for the latency of all cores entering
SMM. The maximum SMM entrance latency is defined by the platform’s IO sub-system, not the processor.
A value of twice the watchdog timer count is recommended. See D18F3x44 [MCA NB Configuration] for
more information on the watchdog time-out value. If a time-out occurs in the wait loop, the BIOS (the last
core to decrement NotInSMM) should record the number of cores that have not entered SMM and all cores
must fall out of the loop.
2. If a time-out occurs in the wait loop in step 2, the BIOS must not wait for WaitInSMM=0. Instead it must
wait for WaitInSMM=(the number of cores recorded in step 2).
3. If BIOS places APs in the INIT state during any part of the boot process when SMIs may be generated, or
may generate SMIs before taking all APs out of their initial microcode reset loop (i.e., before
D18F0x1DC[CpuEn] is set), then it is recommended that BIOS keep a record of how many APs are in
these two states and exclude these cores from the wait loops. SMIs are not recognized by a processor in
these states. AMD does not recommend enabling SMI sources prior to bringing all APs out of these states.
2.4.9
Secure Virtual Machine Mode (SVM)
Support for SVM mode is indicated by CPUID Fn8000_0001_ECX[SVM].
2.4.9.1
BIOS support for SVM Disable
The BIOS should include the following user setup options to enable and disable AMD Virtualization™ technology.
• Enable AMD Virtualization™.
• MSRC001_0114[SvmeDisable] = 0.
• MSRC001_0114[Lock] = 1.
• MSRC001_0118[SvmLockKey] = 0000_0000_0000_0000h.
• Disable AMD Virtualization™.
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• MSRC001_0114[SvmeDisable]=1.
• MSRC001_0114[Lock]=1.
• MSRC001_0118[SvmLockKey] = 0000_0000_0000_0000h.
The BIOS may also include the following user setup options to disable AMD Virtualization™ technology.
• Disable AMD Virtualization™, with a user supplied key.
• MSRC001_0114[SvmeDisable]=1.
• MSRC001_0114[Lock]=1.
• MSRC001_0118[SvmLockKey] programmed with value supplied by user. This value should be stored
in NVRAM.
2.4.10
CPUID Instruction
The CPUID instruction provides data about the features supported by the processor. See 3.18 [CPUID Instruction Registers].
2.4.10.1
Multi-Core Support
There are two methods for determining multi-core support. A recommended mechanism is provided and a legacy method is also available for existing operating systems. System software should use the correct architectural mechanism to detect the number of physical cores by observing CPUID Fn8000_0008_ECX[NC]. The
legacy method utilizes the CPUID Fn0000_0001_EBX[LogicalProcessorCount].
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Power Management
The processor supports many power management features in a variety of systems. Table 8 provides a summary
of ACPI states and power management features and indicates whether they are supported.
Table 8: Power Management Support
ACPI/Power Management State
Supported
Description
G0/S0/C0: Working
Yes
G0/S0/C0: Core P-state transitions
Yes
G0/S0/C0: NB P-state transitions
Yes
2.5.4.1 [NB P-states]
G0/S0/C0: Hardware thermal control (HTC)
Yes
2.10.3.1 [PROCHOT_L and Hardware
Thermal Control (HTC)]
G0/S0/Per-core IO-based C-states
Yes
G0/S0/C1: Halt
Yes
2.5.3.2 [Core C-states] and 2.5.1.3.2
[Low Power Voltages]
G0/S0/CC6: Per-core Power gating
Yes
2.5.3.2 [Core C-states]
G0/S0/XC6: CPC-L2 power gating
Yes
2.5.3.2 [Core C-states] and 2.5.5.2.3.5
[XC6 State]
G0/S0/PC6: 0V support (VDD power plane).
Yes
2.5.3.2 [Core C-states] and 2.5.1.3.2
[Low Power Voltages]
G0/S0/Cx: Cache flushing support
Yes
2.5.3.2.3.1 [C-state Probes and Cache
Flushing]
G0/S0: Northbridge C-states (DRAM self-refresh, NB clock-gating)
Yes
2.5.4.2 [NB C-states]
G1/S1: Stand By (Powered On Suspend)
No
G1/S3: Stand By (Suspend to RAM)
Yes
G1/S4: Hibernate (Suspend to Disk)
Yes
G1/S5: Shut Down (Soft Off)
Yes
G3 Mechanical Off
Yes
Parallel VID Interface
No
Serial VID Interface 1
Yes
Serial VID Interface 2
Yes
Single-plane systems
No
Number of voltage planes
APM: Application Power Management
2.5.1
2.5.3.1 [Core P-states]
2.5.8.1 [S-states]
2.5.1 [Processor Power Planes And
Voltage Control]
2
2.5.1 [Processor Power Planes And
Voltage Control]
Yes
2.5.9 [Application Power Management (APM)]
Processor Power Planes And Voltage Control
Refer to the Electrical Data Sheet and the AMD Infrastructure Roadmap for power plane definitions. See 1.2
[Reference Documents].
2.5.1.1
Serial VID Interface
The processor includes an interface to control external voltage regulators, called the serial VID interface (SVI).
Both SVI1 and SVI2 are supported. On PWROK assertion, the SVT pin is sampled by the processor to
determine the SVI mode supported by the voltage regulator. If SVT is high the processor uses SVI2 mode,
otherwise the processor uses SVI1 mode. The default frequency for SVI1 is 3.4MHz. The frequency of SVC
for SVI2 is controlled by D18F3xA0[Svi2HighFreqSel]. See the AMD Voltage Regulator Specification and the
AMD Serial VID Interface 2.0 (SVI2) Specification for additional details.
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SVI2 Features
The processor supports the following SVI2 features:
• Voltage offsets:
• VDD: D18F5x12C[CoreOffsetTrim], D0F0xBC_x3F9F8[SviLoadLineOffsetVdd]. Changes to
either register must be reflected in both locations.
• VDDNB: D18F5x188[NbOffsetTrim], D0F0xBC_x3F9F8[SviLoadLineOffsetVddNB]. Changes to
either register must be reflected in both locations.
• Load line trim:
• VDD: D18F5x12C[CoreLoadLineTrim], D0F0xBC_x3F9F4[SviTrimValueVdd]. Changes to either
register must be reflected in both locations.
• VDDNB: D18F5x188[NbLoadLineTrim], D0F0xBC_x3F9F4[SviTrimValueVddNB]. Changes to
either register must be reflected in both locations.
2.5.1.2
Internal VID Registers and Encodings
All VID register fields within the processor are 8-bits wide. When using SVI1, VID encodings are 7-bits wide
and the least significant bit is ignored. In SVI2 all 8 bits are used. The VID encodings to voltage translation for
all VID codes are defined by the SVI mode. See the AMD Voltage Regulator Specification and the AMD Serial
VID Interface 2.0 (SVI2) Specification for additional details.
The boot VID is 1.0 volts.
2.5.1.2.1
MinVid and MaxVid Check
Hardware limits the minimum and maximum VID code that is sent to the voltage regulator. The allowed limits
are specified in D18F5x17C[MinVid, MaxVid]. Prior to generating VID-change commands to SVI, the
processor filters the InputVid value to the OutputVid as follows (higher VID codes correspond to lower
voltages and lower VID codes correspond to higher voltages):
• If InputVid < MaxVid, OutputVid=MaxVid.
• Else if (InputVid > MinVid) & (MinVid!=00h), OutputVid=MinVid.
• Else OutputVid=InputVid.
This filtering is applied regardless of the source of the VID-change command, except for THERMTRIP which
applies Fuse[ThermVid] irrespective of MinVid.
2.5.1.3
2.5.1.3.1
Low Power Features
PSIx_L Bit
The processor can indicate whether or not it’s in a low-voltage state via the PSIx_L bit. This indicator may be
used by the voltage regulator to place itself into a more power efficient mode. PSIx_L is controlled
independently for VDD and VDDNB. Support for PSIx_L varies with the SVI mode as follows:
• SVI2: The processor supports the PSI0_L and the PSI1_L bits in the data fields of the SVI2 command.
• PSI0_L: PSI0_L for VDD and VDDNB is enabled using D18F3xA0[PsiVidEn] and
D18F5x17C[NbPsi0VidEn], respectively. Once enabled, the state of PSI0_L is controlled by
D18F3xA0[PsiVid[7:0]] and D18F5x17C[NbPsi0Vid]. Changes to the state of PSI0_L can only occur on
VID changes.
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• PSI1_L: The PSI1_L bit for VDD and VDDNB is specified by D18F5x12C[CorePsi1En] and
D0F0xBC_x3F9EC[EnableNbPsi1], respectively. See also D18F5x188[NbPsi1]. Changes to the state of
PSI1_L can occur at any time.
2.5.1.3.1.1
BIOS Requirements for PSI0_L
Enabling PSI0_L for the VDD and VDDNB planes depends on support from the voltage regulator and is
therefore system specific. The voltage regulator must be able to supply the current required for the processor to
operate at the VID code specified in D18F3xA0[PsiVid[7:0]] and D18F5x17C[NbPsi0Vid[7:0]]. Depending on
the regulator used, AMD recommends one of the following methods:
• PSI0_L disabled:
• VDD: To set PSI0_L for the VDD plane, program D18F3xA0[PsiVidEn]=0.
• VDDNB: To set PSI0_L for the VDDNB plane, program D18F5x17C[NbPsi0VidEn]=0.
• PSI0_L set/clear based on current requirements:
• VDD: The following algorithm describes how to program PSI0_L on VDD:
PSI_vrm_current = current at which the regulator allows PSI0_L. Refer to parameter
BLDCFG_VRM_LOW_POWER_THRESHOLD in AMD Generic Encapsulated Software Architecture (AGESA)
Interface Specification, order #44065.
previous_voltage = FFh
for (each P-state from P0 to D18F3xDC[HwPstateMaxVal]) {
pstate_current = ProcIddMax for the current P-state,
see 2.5.3.1.7 [Processor-Systemboard Power Delivery Compatibility Check];
pstate_voltage = MSRC001_00[6B:64][CpuVid] of the current P-state;
if (current P-state == D18F3xDC[HwPstateMaxVal]) {
next_pstate_current = 0;
} else {
next_pstate_current = ProcIddMax for the next P-state,
see 2.5.3.1.7 [Processor-Systemboard Power Delivery Compatibility Check];
}
if ((pstate_current <= PSI_vrm_current) &&
(next_pstate_current <= PSI_vrm_current) &&
(pstate_voltage != previous_voltage)) {
Program D18F3xA0[PsiVid] = pstate_voltage;
Program D18F3xA0[PsiVidEn] = 1;
break;
}
previous_voltage = pstate_voltage;
}
• VDDNB: The following algorithm describes how to program PSI0_L on VDDNB:
NbIddMax = D18F5x16[C:0][NbIddDiv] current.
PSI_vrm_current = current at which the VDDNB regulator allows PSI0_L. Refer to
parameter BLDCFG_VRM_NB_LOW_POWER_THRESHOLD in AMD Generic Encapsulated Software
Architecture (AGESA) Interface Specification, order #44065.
previous_voltage = FFh
for (each valid NB P-state starting with NBP0) {
pstate_current = NbIddMax of the current NB P-state;
pstate_voltage = D18F5x16[C:0][NbVid] of the current NB P-state;
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if (current P-state is the last valid P-state) {
next_pstate_current = 0;
} else {
next_pstate_current = NbIddMax for the next P-state;
}
if ((pstate_current <= PSI_vrm_current) &&
(next_pstate_current <= PSI_vrm_current) &&
(pstate_voltage != previous_voltage)) {
Program D18F5x17C[NbPsi0Vid] = pstate_voltage;
Program D18F5x17C[NbPsi0VidEn] = 1;
break;
}
previous_voltage = pstate_voltage;
}
2.5.1.3.2
Low Power Voltages
In order to save power, voltages lower than those normally needed for operation may be applied to the VDD
power plane while the processor is in a C-state or S-state. The lower voltages are defined as follows:
• PC6Vid: D18F5x128[PC6Vid] specifies a voltage that does not retain the CPU caches or the core
microarchitectural state. PC6Vid does not allow execution and is only applied to the cores. See 2.5.3.2.3.4
[Package C6 (PC6) State].
2.5.1.4
Voltage Transitions
The processor supports dynamic voltage transitions on the VDD and VDDNB planes. These transitions are
requested by either hardware or software during state changes such as reset, P-state changes, and C-state
changes. In all cases the VID code passed to the voltage regulator changes from the old value to the new value
without stepping through intermediate values. The voltage regulator ramps the voltage directly from the
starting voltage to the final voltage, no stepping occurs. See the AMD Voltage Regulator Specification and the
AMD Serial VID Interface 2.0 (SVI2) Specification for additional details.
• If a voltage increase is requested in SVI2, the processor waits the amount of time specified by
D18F5x12C[WaitVidCompDis] before sending any additional voltage change requests to the voltage
regulator or before beginning a frequency transition.
• If a voltage decrease is requested, the processor waits the amount of time specified by
D18F5x128[FastSlamTimeDown] before sending any additional voltage change requests to the voltage
regulator. For voltage decreases, the processor does not wait any time before beginning frequency
changes.
The processor continues code execution during voltage changes when in the C0 state.
2.5.1.4.1
Hardware-Initiated Voltage Transitions
When software requests any of the following state changes, or hardware determines that any of the following
state changes are necessary, hardware coordinates the necessary voltage changes:
• VDD:
• Core P-state transition. See 2.5.3.1 [Core P-states].
• Package C-state transition. D18F5x128[PC6Vid] specifies a voltage that does not retain the CPU caches
or the core microarchitectural state. PC6Vid does not allow execution and is only applied to the cores.
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See 2.5.3.2.3.4 [Package C6 (PC6) State].
• S-state transition. See 2.5.8.1 [S-states].
• VDDNB:
• NB P-state transition. See 2.5.4.1 [NB P-states].
• S-state transition. See 2.5.8.1 [S-states].
2.5.1.4.2
Software-Initiated Voltage Transitions
2.5.1.4.2.1
Software-Initiated NB Voltage Transitions
Software can request voltage changes on the VDDNB power plane using the
BIOSSMC_MSG_VDDNB_REQUEST software interrupt. To make a voltage change request, software uses
the sequence described in 2.12.1 [Software Interrupts] with Service Index 3Ah. This request is evaluated with
other VDDNB requests within GNB as mentioned below.
Software voltage requests are considered by hardware when taking voltage plane dependencies into account
(see 2.5.2.2 [Dependencies Between Subcomponents on VDDNB]).
2.5.2
2.5.2.1
Frequency and Voltage Domain Dependencies
Dependencies Between Cores
Whenever a P-state or C-state is requested on a core (see 2.5.3.1 [Core P-states] and 2.5.3.2 [Core C-states]),
hardware must take the following frequency and voltage domain dependencies into account when deciding
whether to make the requested change:
• Cores within a compute unit share a common frequency and voltage domain.
• Compute units within a processor share a common voltage domain, but have independent frequency
domains. The voltage is determined by the highest-performance P-state requested on any core.
As a result, the P-state and C-state change requests have the following results:
• If different compute units request different voltages, the VDD voltage is determined by the highest voltage
(lowest VID) requested.
• If the cores within a compute unit request different P-states while in C0, frequency and voltage are
determined by the highest-performance P-state requested.
• If both cores request non-C0 states, the behavior is specified by D18F4x128[CoreCstatePolicy].
• If one core within a compute unit requests a CC6 while the other core is in C0, the frequency and voltage of
the compute unit is determined by the core in C0.
• If one core within a compute unit requests a CC6 while the other core is in C0, the core could independently
enter CC6.
2.5.2.2
Dependencies Between Subcomponents on VDDNB
Many subcomponents of the processor reside on the VDDNB power plane. Hardware must take voltage
domain dependencies into account when determining whether to make a voltage change requested by one of
the subcomponents. Whenever a state transition occurs that causes a voltage change request (see 2.5.1.4.1
[Hardware-Initiated Voltage Transitions]), or software makes a voltage change request (see 2.5.1.4.2 [Software-Initiated Voltage Transitions]), the VDDNB voltage requested by the processor is determined by the
highest voltage (lowest VID) request made by any of the subcomponents or by software. GNB voltage requests
can be ignored by NB voltage controller via D18F5x178[GnbVidReqDis].
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BIOS Requirements for Power Plane Initialization
• Ensure the following fields are configured to their BIOS recommendations:
• D18F3xA0[Svi2HighFreqSel, SviHighFreqSel].
• D18F3xD8[VSRampSlamTime].
• Optionally configure PSIx_L. Refer to 2.5.1.3.1 [PSIx_L Bit] for additional details.
2.5.3
2.5.3.1
CPU Power Management
Core P-states
Core P-states are operational performance states characterized by a unique combination of core frequency and
voltage. The processor supports up to 8 core P-states (P0 through P7), specified in MSRC001_00[6B:64]. Out
of cold reset, the voltage and frequency of the compute units is specified by MSRC001_0071[StartupPstate]
and D18F3xA0[CofVidProg].
Support for dynamic core P-state changes is indicated by more than one enabled selection in
MSRC001_00[6B:64][PstateEn]. At least one enabled P-state (P0) is specified for all processors.
Software requests core P-state changes for each core independently using the hardware P-state control
mechanism (a.k.a. fire and forget). Support for hardware P-state control is indicated by CPUID
Fn8000_0007_EDX[HwPstate]=1b. Software may not request any P-state transitions using the hardware Pstate control mechanism until the P-state initialization requirements defined in 2.5.3.1.6 [BIOS Requirements
for Core P-state Initialization and Transitions] are complete.
The processor supports independently-controllable frequency planes for each compute unit and the NB; and
independently-controllable voltage planes. See 2.5.1 [Processor Power Planes And Voltage Control] for
voltage plane definitions and 1.5.4 [Supported Feature Variations] for package/socket-specific information on
voltage plane compatibility.
The following terms may be applied to each of these planes:
• FID: frequency ID. Specifies the PLL frequency multiplier, relative to the reference clock, for a given
domain.
• DID: divisor ID. Specifies the post-PLL power-of-two divisor that can be used to reduce the operating
frequency.
• COF: current operating frequency. Specifies the operating frequency as a function of the FID and DID. Refer
to CoreCOF for the CPU COF formula and NBCOF for the NB COF formula.
• VID: voltage ID. Specifies the voltage level for a given domain. Refer to 2.5.1.2.1 [MinVid and MaxVid
Check] for encodings.
All FID and DID parameters for software P-states must be programmed to equivalent values for all cores and
NBs in the coherent fabric. See 2.5.3.1.1.1 [Software P-state Numbering]. Refer to MSRC001_00[6B:64] and
D18F5x16[C:0] for further details on programming requirements.
2.5.3.1.1
Core P-state Naming and Numbering
Since the number of boosted P-states may vary from product to product, the mapping between
MSRC001_00[6B:64] and the indices used to request P-state changes or status also varies. In order to clarify
this, two different numbering schemes are used.
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Software P-state Numbering
When referring to software P-state numbering, the following naming convention is used:
• Non-boosted P-states are referred to as P0, P1, etc.
• P0 is the highest power, highest performance, non-boosted P-state.
• Each ascending P-state number represents a lower-power, lower performance non-boosted P-state than
the prior P-state number.
• Boosted P-states are referred to as Pb0, Pb1, etc.
• Pb0 is the highest-performance, highest-power boosted P-state.
• Each higher numbered boosted P-state represents a lower-power, lower-performance boosted P-state.
For example, if D18F4x15C[NumBoostStates] contains the values shown below, then the P-states would be
named as follows:
Table 9: Software P-state Naming
D18F4x15C[NumBoostD18F4x15C[NumBoostStates]=1
States]=3
P-state Name Corresponding P-state Name Corresponding
MSR Address
MSR Address
Pb0
MSRC001_0064
Pb0
MSRC001_0064
P0
MSRC001_0065
Pb1
MSRC001_0065
P1
MSRC001_0066
Pb2
MSRC001_0066
P2
MSRC001_0067
P0
MSRC001_0067
P3
MSRC001_0068
P1
MSRC001_0068
P4
MSRC001_0069
P2
MSRC001_0069
P5
MSRC001_006A
P3
MSRC001_006A
P6
MSRC001_006B
P4
MSRC001_006B
All sections and register definitions use software P-state numbering unless otherwise specified.
2.5.3.1.1.2
Hardware P-state Numbering
When referring to hardware P-state numbering, the following naming convention is used:
• All P-states are referred to as P0, P1, etc.
• P0 is the highest power, highest-performance P-state, regardless of whether it is a boosted P-state or a
non-boosted P-state.
• Each ascending P-state number represents a lower-power, lower-performance P-state, regardless of
whether it is a boosted P-state or not.
2.5.3.1.2
Core P-state Control
Core P-states are dynamically controlled by software and are exposed through ACPI objects (refer to
2.5.3.1.8.3 [ACPI Processor P-state Objects]). Software requests a core P-state change by writing a 3 bit index
corresponding to the desired P-state number to MSRC001_0062[PstateCmd] of the appropriate core. For
example, to request P3 for core 0 software would write 011b to core 0’s MSRC001_0062[PstateCmd].
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Boosted P-states may not be directly requested by software. Whenever software requests the P0 state on a
processor that supports APM (i.e. writes 000b to MSRC001_0062[PstateCmd]), hardware dynamically places
the core into the highest-performance P-state possible as determined by APM. See 2.5.9 [Application Power
Management (APM)].
Hardware sequences the frequency and voltage changes necessary to complete a P-state transition as specified
by 2.5.3.1.5 [Core P-state Transition Behavior] with no additional software interaction required. Hardware also
coordinates frequency and voltage changes when differing P-state requests are made on cores that share a
frequency or voltage plane. See 2.5.2 [Frequency and Voltage Domain Dependencies] for details about
hardware coordination.
Table 10: Software P-state Control
D18F4x15C[NumBoostStates]=1
D18F4x15C[NumBoostStates]=3
P-state Name Index Used for Corresponding P-state Name Index Used for Corresponding
Requests/Status MSR Address
Requests/Status MSR Address
Pb0
n/a
MSRC001_0064
Pb0
n/a
MSRC001_0064
P0
0
MSRC001_0065
Pb1
n/a
MSRC001_0065
P1
1
MSRC001_0066
Pb2
n/a
MSRC001_0066
P2
2
MSRC001_0067
P0
0
MSRC001_0067
P3
3
MSRC001_0068
P1
1
MSRC001_0068
P4
4
MSRC001_0069
P2
2
MSRC001_0069
P5
5
MSRC001_006A
P3
3
MSRC001_006A
P6
6
MSRC001_006B
P4
4
MSRC001_006B
Hardware controls the VID for each voltage domain according to the highest requirement of the frequency
domain(s) on each plane. For example, the VID for a 4 compute unit dual-plane system must be maintained at
the highest level required for all 4 frequency domains. The number of frequency domains in a voltage domain
is package/platform specific. Refer to 2.5.3.1.5 [Core P-state Transition Behavior] for details on hardware Pstate voltage control. 2.5.2.3 [BIOS Requirements for Power Plane Initialization] specifies the processor
initialization requirements for voltage plane control.
2.5.3.1.3
Core P-state Visibility
MSRC001_0063[CurPstate] reflects the current non-boosted P-state number for each compute unit. For
example, if MSRC001_0063[CurPstate]=010b on compute unit 1, then compute unit 1 is in the P2 state. If a
compute unit is in a boosted P-state, MSRC001_0063[CurPstate] reads back as 0.
The voltage on a compute unit may not correspond to the VID code specified by the current P-state of the
compute unit due to voltage plane dependencies. See 2.5.2 [Frequency and Voltage Domain Dependencies]. If
a compute unit is in the P0 state (i.e. if MSRC001_0063[CurPstate]=0), the frequency of the compute unit
could be the frequency specified by P0 or any boosted P-state. To determine the frequency of a compute unit,
see 2.5.3.3 [Effective Frequency].
2.5.3.1.4
Core P-state Limits
Core P-states may be limited to lower-performance values under certain conditions, including:
• HTC. See D18F3x64[HtcPstateLimit].
• Software. See D18F3x68[SwPstateLimit].
• Core Performance Boost. See 2.5.9 [Application Power Management (APM)].
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• PROCHOT_L assertion. See 2.10.3.1 [PROCHOT_L and Hardware Thermal Control (HTC)].
• SMU. See D18F4x13C[SmuPstateLimit].
P-state limits are applied to all cores on the processor. The current P-state limit is provided in
MSRC001_0061[CurPstateLimit]. Changes to the MSRC001_0061[CurPstateLimit] can be programmed to
trigger interrupts through D18F3x64[PslApicLoEn, PslApicHiEn]. In addition, the maximum P-state value,
regardless of the source, is limited as specified in MSRC001_0061[PstateMaxVal].
2.5.3.1.5
Core P-state Transition Behavior
The following rules specify how P-states changes function and interact with other system or processor states:
• If the P-state number is increasing (the compute unit is moving to a lower-performance state), then the COF
is changed first, followed by the VID change. If the P-state number is decreasing, then the VID is changed
first followed by the COF.
• When the processor initiates a VID change that increases voltage for a voltage domain, no new voltage or
frequency changes occur until D18F3xD8[VSRampSlamTime] has expired, regardless of whether any new
requests are received. When the processor initiates a VID change that decreases voltage for a voltage
domain, new voltage or frequency changes are allowed to occur immediately.
• This is true regardless of whether the frequency or voltages changes occur as a result of P-state or C-state
changes.
• If multiple commands are issued that affect the P-state of a domain prior to when the processor initiates the
change of the P-state of that domain, then the processor operates on the last one issued.
• Once a P-state change starts, the P-state state machine (PSSM) continues through completion unless
interrupted by a PWROK deassertion. If multiple P-state changes are requested concurrently, the PSSM may
group the associated VID changes separately from the associated COF changes.
• Behavior during RESET_L assertions:
• All cores are transitioned to C0.
• VDD VID is transitioned to HWP0 VID. See MSRC001_0064[CpuVid].
• If there is no P-state transition activity, then the compute units and NB remain in the current P-state. If
there is an altvid applied:
• If a RESET_L assertion interrupts a P-state transition, then the COF remains in it’s current state at the
time RESET_L is asserted (either the value of the old or the new P-state). BIOS is required to transition
to valid COF and VID settings after a warm reset according to the sequence defined in 2.5.3.1.8 [BIOS
COF and VID Requirements After Warm Reset].
• After a warm reset MSRC001_0063 [P-state Status] is consistent with MSRC001_0071[CurPstate].
MSRC001_0062 [P-state Control] may not be consistent with MSRC001_0071[CurPstate].
• The OS controls the P-state through MSRC001_0062 [P-state Control], independent of P-state limits
described in D18F3x64[HtcPstateLimit], D18F3x68[SwPstateLimit], and D18F3xC4 [SBI P-state
Limit]. P-state limits interact with OS-directed P-state transitions as follows:
• Of all the active P-state limits, the one that represents the lowest-performance P-state number, at any
given time, is treated as an upper limit on performance.
• As the limit becomes active or inactive, or if it changes, the P-state for each compute unit is placed in
either the last OS-requested P-state or the new limit P-state, whichever is a lower performance P-state
number.
• If the resulting P-state number exceeds MSRC001_0061[PstateMaxVal], regardless of whether it is a
limit or OS-requested, then the PstateMaxVal is used instead.
2.5.3.1.6
BIOS Requirements for Core P-state Initialization and Transitions
1. Check that CPUID Fn8000_0007_EDX[HwPstate]=1. If not, P-states are not supported, no P-state related
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3.
4.
5.
6.
7.
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ACPI objects should be generated, and BIOS must skip the rest of these steps.
Complete the 2.5.2.3 [BIOS Requirements for Power Plane Initialization].
Ensure the following fields are configured to their BIOS recommendations:
• D18F3xA0[PllLockTime].
• D18F3xD4[PowerStepUp, PowerStepDown].
Transition all cores to the minimum performance P-state using the algorithm detailed in 2.5.3.1.8.2 [Core
Minimum P-state Transition Sequence After Warm Reset].
Complete the 2.5.4.1.2.1 [NB P-state COF and VID Synchronization After Warm Reset]. All cores on a
processor must be in the minimum performance P-state prior to executing this sequence.
Complete the 2.5.3.1.7 [Processor-Systemboard Power Delivery Compatibility Check].
Perform the following steps in any order:
A. Enable 2.5.9 [Application Power Management (APM)] as follows:
• Ensure the following fields are configured to their BIOS recommendations:
• D18F4x110[CSampleTimer].
• D18F4x15C[ApmMasterEn].
• D18F5xE0[RunAvgRange].
• If D18F4x15C[NumBoostStates]!=0, program D18F4x15C[BoostSrc]=1.
B. Transition all cores to the maximum performance P-state by writing 0 to MSRC001_0062[PstateCmd].
This is done to enable faster boot times.
C. Create ACPI objects if neccessary:
• Determine the valid set of P-states as indicated by MSRC001_00[6B:64][PstateEn].
• If P-states are not supported, as indicated by only one enabled selection in
MSRC001_00[6B:64][PstateEn], then BIOS must not generate ACPI-defined P-state objects
described in 2.5.3.1.8.3 [ACPI Processor P-state Objects]. Otherwise, the ACPI objects should be
generated to enable P-state support.
D. Configure the COF and VID for each processor appropriately based on the sequence described in
2.5.4.1.2 [BIOS NB P-state Configuration].
Configure PSIx_L. Refer to 2.5.1.3.1 [PSIx_L Bit] for additional details.
2.5.3.1.7
Processor-Systemboard Power Delivery Compatibility Check
BIOS must disable processor P-states that require higher power delivery than the systemboard can support.
This power delivery compatibility check is designed to prevent system failures caused by exceeding the power
delivery capability of the systemboard for the power plane(s) that contain the core(s). Refer to 2.5.1 [Processor
Power Planes And Voltage Control] for power plane definitions and configuration information. BIOS can
optionally notify the user if P-states are detected that exceed the systemboard power delivery capability.
Modifications to MSRC001_00[6B:64] [P-state [7:0]] must be applied equally to all cores on the same node.
This check does not ensure functionality for all package/socket compatible processor/systemboard
combinations.
MSRC001_00[6B:64][PstateEn] must be set to 0 for any P-state MSR where PstateEn=1 and the processor
current requirement (ProcIddMax), defined by the following equation, is greater than the systemboard current
delivery capability. ProcIddMax is reported in amps per core power plane.
ProcIddMax = MSRC001_00[6B:64][IddValue] current * 1/10^MSRC001_00[6B:64][IddDiv] *
(D18F5x84[CmpCap]+1) * 1/2^D18F3xD8[PwrPlanes]
The power delivery check should be applied starting with hardware P0 and continue with increasing P-state
indexes (1, 2, 3, and 4) for all enabled P-states. Once a compatible P-state is found using the ProcIddMax
equation the check is complete. All processor P-states with higher indexes are defined to be lower power and
performance, and are therefore compatible with the systemboard.
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Example:
• MSRC001_0065[IddValue] = 32d
• MSRC001_0065[IddDiv] = 0d
• D18F5x84[CmpCap] = 1d
• ProcIddMax = 32 * 1 * 2 * 1 = 64A per plane
The systemboard must be able to supply >= 64A for the unified core power plane in order to support P1 for this
processor. If the systemboard current delivery capability is < 64A per plane then BIOS must set
MSRC001_0065[PstateEn]=0 for all cores on this node, and continue by checking P2 in the same fashion.
If no P-states are disabled while performing the power delivery compatibility check then BIOS does not need
to take any action.
If at least one P-state is disabled by performing the power delivery compatibility check and at least one P-state
remains enabled, then BIOS must perform the following steps:
1. If the P-state pointed to by MSRC001_0063[CurPstate] is disabled by the power delivery compatibility
check, then BIOS must request a transition to an enabled P-state using MSRC001_0062[PstateCmd] and
wait for MSRC001_0063[CurPstate] to reflect the new value.
2. Copy the contents of the enabled P-state MSRs (MSRC001_00[6B:64]) to the highest performance P-state
locations. E.g. if P0 and P1 are disabled by the power delivery compatibility check and P2 - P4 remain
enabled, then the contents of P2 - P4 should be copied to P0 - P2 and P3 and P4 should be disabled
(PstateEn=0). This step uses software P-state numbering. See 2.5.3.1.1.1 [Software P-state Numbering].
3. Request a P-state transition to the P-state MSR containing the COF/VID values currently applied. E.g. If
MSRC001_0063[CurPstate]=100b and P4 P-state MSR information is copied to P2 in step 2, then BIOS
should write 010b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] to reflect the
new value.
4. If a subset of boosted P-states are disabled, then copy the contents of the P-state MSR pointed to by the
highest performance boosted P-state that is enabled to the P-state MSRs pointed to by the boosted P-states
that are disabled.
5. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc]=0.
6. Adjust the following P-state parameters affected by the P-state MSR copy by subtracting the number of
software P-states that are disabled by the power delivery compatibility check. This calculation should not
wrap, but saturate at 0. E.g. if P0 and P1 are disabled, then each of the following register fields should have
2 subtracted from them:
• D18F3x64[HtcPstateLimit]
• D18F3x68[SwPstateLimit]
• D18F3xDC[HwPstateMaxVal]
If any node has all P-states disabled after performing the power delivery compatibility check, then BIOS must
perform the following steps. This does not ensure operation and BIOS should notify the user of the
incompatibility between the processor and systemboard if possible.
1. If MSRC001_0063[CurPstate]!=MSRC001_0061[PstateMaxVal], then write
MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
to reflect the new value.
2. If MSRC001_0061[PstateMaxVal]!=000b copy the contents of the P-state MSR pointed to by
MSRC001_0061[PstateMaxVal] to MSRC001_0064 and set MSRC001_0064[PstateEn]; Write 000b to
MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] to reflect the new value. This step
uses software P-state numbering. See 2.5.3.1.1.1 [Software P-state Numbering].
3. Adjust the following fields to 000b.
• D18F3x64[HtcPstateLimit]
• D18F3x68[SwPstateLimit]
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• D18F3xDC[HwPstateMaxVal]
4. Program D18F4x15C[BoostSrc]=0.
2.5.3.1.8
BIOS COF and VID Requirements After Warm Reset
Warm reset is asynchronous and can interrupt P-state transitions leaving the processor in a VID state that does
not correspond to MSRC001_0063[CurPstate] on any core. The processor frequency after warm reset
corresponds to MSRC001_0063[CurPstate]. See 2.5.3.1.5 [Core P-state Transition Behavior] for P-state
transition behavior when RESET_L is asserted. BIOS is required to transition the processor to valid COF and
VID settings corresponding to an enabled P-state following warm reset. The cores may be transitioned to either
the maximum or minimum P-state COF and VID settings using the sequences defined in 2.5.3.1.8.1 [Core
Maximum P-state Transition Sequence After Warm Reset] and 2.5.3.1.8.2 [Core Minimum P-state Transition
Sequence After Warm Reset]. Transitioning to the minimum P-state after warm reset is recommended to
prevent undesired system behavior if a warm reset occurs before the 2.5.3.1.7 [Processor-Systemboard Power
Delivery Compatibility Check] is complete. BIOS must also transition NB COF and VID settings after warm
reset for processors that support NB P-states (as indicated by NbDid=1 in any of MSRC001_00[6B:64] [Pstate [7:0]]) using the sequence defined in 2.5.4.1.2.1 [NB P-state COF and VID Synchronization After Warm
Reset]. BIOS is not required to manipulate NB COF and VID settings following warm reset if the warm reset
was issued by BIOS to update D18F5x16[C:0][NbFid].
2.5.3.1.8.1
Core Maximum P-state Transition Sequence After Warm Reset
1. If MSRC001_0071[CurPstate] = D18F3xDC[HwPstateMaxVal], then skip step 3 for that core.
2. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all cores in the processor. This
step is required to ensure VDD is set to a non-boosted P-state voltage level since no cores should be in
boost at this point. This step is not required for 2.5.3.1.8.2 [Core Minimum P-state Transition Sequence
After Warm Reset] since P-state down transitions are not gated by a boost voltage on VDD. See 2.5.3.1.5
[Core P-state Transition Behavior].
3. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from MSRC001_00[6B:64]
indexed by D18F3xDC[HwPstateMaxVal].
4. Wait for MSRC001_0071[CurCpuVid] = [CurCpuVid] from MSRC001_00[6B:64] indexed by
D18F3xDC[HwPstateMaxVal].
5. All previous steps must be completed on all cores prior to continuing the sequence since a compute unit
transitions to the highest performance P-state requested on either core.
6. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
7. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from MSRC001_00[6B:64]
indexed by MSRC001_0071[CurPstateLimit]. The check against MSRC001_0071[CurPstateLimit] is
required since MSRC001_0071[CurPstateLimit] affects the resultant P-state.
8. If MSRC001_0071[CurPstateLimit] != D18F3xDC[HwPstateMaxVal], wait for
MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
MSRC001_0071[CurPstateLimit]. See 2.5.3.1.8.2 [Core Minimum P-state Transition Sequence After
Warm Reset].
9. Wait for MSRC001_0063[CurPstate] = MSRC001_0061[CurPstateLimit].
2.5.3.1.8.2
Core Minimum P-state Transition Sequence After Warm Reset
1. If MSRC001_0071[CurPstate] = MSRC001_0071[CurPstateLimit], then skip step 3 for that core.
2. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
3. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from MSRC001_00[6B:64]
indexed by MSRC001_0071[CurPstateLimit].
4. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all cores in the processor.
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5. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from MSRC001_00[6B:64]
indexed by D18F3xDC[HwPstateMaxVal].
6. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
D18F3xDC[HwPstateMaxVal]. If MSRC001_0071[CurPstateLimit] = MSRC001_0071[CurPstate], do not
perform a voltage check. On multi-node processors, there is a corner case where all core frequencies are in
PstateMaxVal, but the voltage may not be.
7. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
2.5.3.1.8.3
ACPI Processor P-state Objects
Processor performance control is implemented through the _PCT, _PSS and _PSD objects in ACPI 2.0 and
later revisions. The presence of these objects indicates to the OS that the platform and processor are capable of
supporting multiple performance states. Processor performance states are not supported with ACPI 1.0b. BIOS
must provide the _PCT, _PSS, and _PSD objects, and define other ACPI parameters to support operating
systems that provide native support for processor P-state transitions.
The following rules apply to BIOS generated ACPI objects in multi-core systems. Refer to the appropriate
ACPI specification for additional details:
• All cores must expose the same number of performance states to the OS.
• The respective performance states displayed to the OS for each core must have identical performance and
power-consumption parameters (e.g. P0 on core 0 must have the same performance and power-consumptions
parameters as P0 on core 1, P1 on core 0 must have the same parameters as P1 on core 1, however P0 can be
different than P1).
• Performance state objects must be present under each processor object in the system.
2.5.3.1.8.3.1
_PCT (Performance Control)
BIOS must declare the performance control object parameters as functional fixed hardware. This definition
indicates the processor driver understands the architectural definition of the P-state interface associated with
CPUID Fn8000_0007_EDX[HwPstate]=1.
• Perf_Ctrl_Register = Functional Fixed Hardware
• Perf_Status_Register = Functional Fixed Hardware
2.5.3.1.8.3.2
_PSS (Performance Supported States)
A unique _PSS entry is created for each non-boosted P-state. The value contained in the _PSS Control field is
written to MSRC001_0062 [P-state Control] to request a P-state change to the CoreFreq of the associated _PSS
object. The value contained in MSRC001_0063 [P-state Status] can be used to identify the _PSS object of the
current P-state request by equating MSRC001_0063[CurPstate] to the value of the Status field. See 2.5.3.1
[Core P-states].
BIOS loops through each of MSRC001_00[6B:64] applying the following formulas to create the fields for the
_PSS object for for each valid P-state (see MSRC001_00[6B:64][PstateEn]). BIOS skips over any P-state
MSRs that specify boost P-states (see D18F4x15C[NumBoostStates]).
• CoreFreq (MHz) = Calculated using the formula for CoreCOF.
• Power (mW) =MSRC001_00[6B:64][CpuVid] voltage * MSRC001_00[6B:64][IddValue] current * 1000.
• TransitionLatency (us) and BusMasterLatency (us):
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• If MSRC001_00[6B:64][CpuFid] is the same for all enabled P-states (see
MSRC001_00[6B:64][PstateEn]) and all boosted P-states:
• TransitionLatency = BusMasterLatency = (15 steps * D18F3xD4[PowerStepDown] time * 1000
us/ns) + (15 steps * D18F3xD4[PowerStepUp] time * 1000 us/ns)
• Else if MSRC001_00[6B:64][CpuFid] is different for any enabled (see MSRC001_00[6B:64][PstateEn])
or boost P-states:
• TransitionLatency = BusMasterLatency = (15 steps * D18F3xD4[PowerStepDown] time * 1000
us/ns) + D18F3xA0[PllLockTime] time + (15 steps * D18F3xD4[PowerStepUp] time * 1000 us/ns)
• Example:
• MSRC001_00[6B:64][CpuFid] is not the same for all P-states
• D18F3xD4[PowerStepDown] = D18F3xD4[PowerStepUp] = 8h (50 ns/step)
• D18F3xA0[PllLockTime] = 001b (2 us)
• TransitionLatency = BusMasterLatency = (15 steps * 50 ns/step / 1000 us/ns) + 2us + (15 steps * 50
ns/step / 1000 us/ns) = 3.5 us (round up to 4 us)
• Control/Status:
• The highest performance non-boosted P-state must have the _PSS control and status fields programmed
to 0.
• Any lower performance non-boosted P-states must have the _PSS control and status fields programmed
in ascending order.
2.5.3.1.8.3.3
_PPC (Performance Present Capabilities)
The _PPC object is optional. Refer to the ACPI specification for details on use and content.
2.5.3.1.8.3.4
_PSD (P-state Dependency)
AMD recommends the ACPI 3.0 _PSD object be generated for each core as follows to cause the cores to
transition between P-states independently:
•
•
•
•
•
NumberOfEntries = 5.
Revision = 0.
Domain = CPUID Fn0000_0001_EBX[LocalApicId[7:2]].
CoordType = FEh. (HW_ALL)
NumProcessors = 4. Indicates the P-state dependency for the number of cores within a compute unit.
2.5.3.1.8.4
Fixed ACPI Description Table (FADT) Entries
Declare the following FADT entries:
• PSTATE_CNT = 00h.
• DUTY_WIDTH = 00h.
2.5.3.1.8.5
XPSS (Microsoft® Extended PSS) Object
Some Microsoft® operating systems require an XPSS object to make P-state changes function properly. A
BIOS that implements an XPSS object has special requirements for the _PCT object. See the Microsoft
Extended PSS ACPI Method Specification for the detailed requirements to implement these objects.
2.5.3.2
Core C-states
C-states are processor power states. C0 is the operational state in which instructions are executed. All other Cstates are low-power states in which instructions are not executed. When coming out of warm and cold reset,
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the processor is transitioned to the C0 state.
2.5.3.2.1
C-state Names and Numbers
C-states are often referred to by an alphanumeric naming convention, C1, C2, C3, etc. The mapping between
ACPI defined C-states and AMD specified C-states is not direct. AMD specified C-states are referred to as IObased C-states. Up to three IO-based C-states are supported, IO-based C-state 0, 1, and 2. The IO-based C-state
index corresponds to the offset added to MSRC001_0073[CstateAddr] to initiate a C-state request. See
2.5.3.2.2 [C-state Request Interface]. The actions taken by the processor when entering a low-power C-state
are configured by software. See 2.5.3.2.3 [C-state Actions] for information about AMD specific actions.
2.5.3.2.2
C-state Request Interface
C-states are dynamically requested by software and are exposed through ACPI objects (see 2.5.3.2.6 [ACPI
Processor C-state Objects]). C-states can be requested on a per-core basis. Software requests a C-state change
in one of two ways:
• Reading from an IO address: The IO address must be the address specified by MSRC001_0073[CstateAddr]
plus an offset of 0 through 7. The processor always returns 0 for this IO read. Offsets 2 through 7 result in an
offset of 2. The IO read is trapped by core microcode and does not leave the processor.
• Executing the HLT instruction. This is equivalent to reading from the IO address specified by
D18F4x128[HaltCstateIndex].
Microcode communicates the C-state request to the NB by writing to D18F4x114[CstateIndex]. When
software requests a C-state transition, hardware evaluates any frequency and voltage domain dependencies and
determines which C-state actions to execute. See 2.5.2 [Frequency and Voltage Domain Dependencies] and
2.5.3.2.3 [C-state Actions].
2.5.3.2.3
C-state Actions
A core takes one of several different possible actions based upon a C-state change request from software. The
C-state action fields are defined in D18F4x11[C:8].
2.5.3.2.3.1
C-state Probes and Cache Flushing
If probes occur after a core enters a non-C0 state, and the caches are not flushed by hardware, the core clock
may be ramped back up to the C0 frequency to service the probes, as specified by
D18F4x118/D18F4x11C[CpuPrbEn].
If a core enters a non-C0 state and cache flush is enabled (see D18F3xDC[CacheFlushOnHaltCtl] and
D18F4x118/D18F4x11C[CacheFlushEn]), a timer counts down for a programmable period of time as specified
by D18F3xDC[CacheFlushOnHaltTmr] or D18F4x118/D18F4x11C[CacheFlushTmrSel]. When the timer
expires, the core flushes its L1 cache to L2 cache and the core clocks are ramped down to a divisor specified by
D18F3xDC[CacheFlushOnHaltCtl]. If the core is the last core within a CPC to enter CC6 (see 2.5.5.2.3.5
[XC6 State]), then L2 cache is flushed to DRAM. The core checks for interrupts after each sector of the cache
is flushed and exits the C-state if an interrupt occurs. The timer is reset if the core exits the C-state for any reason. See 2.5.3.2.4.2 [Cache Flush On Halt Saturation Counter].
As a core enters a non-C0 state, probes are blocked on all cores within a CPC until all probes to the CPC are
drained. When all responses are returned from L2 cache, the core may enter non-C0 state. Once a core flushes
its caches and performs the stpclk handshake with the L2I, probes are no longer sent to that core. This
improves probing performance for cores that are in C0.
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Core C1 (CC1) State
When a core enters the CC1 state, its clock ramps down to the frequency specified by
D18F4x118/D18F4x11C[ClkDivisorCstAct].
2.5.3.2.3.3
Core C6 (CC6) State
A core can gate off power to its internal logic when it enters any non-C0 state. This power gated state is known
as CC6. In order to enter CC6, hardware first enters CC1 then checks
D18F4x118/D18F4x11C[PwrGateEnCstAct]. Power gating reduces the amount of power consumed by the
core. VDD voltage is not reduced when a core is in CC6. The following sequence occurs when a core enters the
CC6 state:
8. If MSRC001_10A0[CacheC6StateDis]=0, Internal core state is saved to L1 cache (microcode). Else,
internal core state is saved to DRAM.
9. L1 cache is flushed to L2 cache (microcode). See 2.5.3.2.3.1 [C-state Probes and Cache Flushing].
10. Power is removed from the core and the core PLL/voltage regulator is powered down as specified by
D18F5x128[CC6PwrDwnRegEn and CC6PwrDwnVcoEn].
All of the following must be true in order for a core to be placed into CC6:
• D18F4x118/D18F4x11C[CacheFlushEn]=1 for the corresponding C-state action field.
• D18F4x118/D18F4x11C[CacheFlushTmrSel] != 11b for the corresponding C-state action field.
• D18F4x118/D18F4x11C[PwrGateEnCstAct]=1 for the corresponding C-state action field.
• D18F2x118[CC6SaveEn]=1.
• D18F2x118[LockDramCfg]=1 or D18F3x12C[OverrideLockDramCfg]=1.
• The CC6 storage area in DRAM is configured. See 2.9.11 [DRAM CC6/PC6 Storage].
The events which cause a core to exit the CC6 state are specified in 2.5.3.2.5 [Exiting C-states]. When a core
exits the CC6 state, it executes the following sequence:
If a warm reset occurs while a core is in CC6, all MCA registers in the core shown in Table 65 are cleared to 0.
See 2.14.1 [Machine Check Architecture]. Since the core was in CC6, the core was not the cause of the warm
reset. As a result, no information pertinent to the reset is lost. Correctable error information logged prior to
CC6 entry may be lost, but this is not critical to system operation.
The time required to enter and exit CC6 is directly proportional to the core P-state frequency. Slower core
frequencies require longer entry and exit times. Latency issues may occur with core P-state frequencies less
than 800MHz.
2.5.3.2.3.4
Package C6 (PC6) State
When all cores enter a non-C0 state, VDD can be reduced to a non-operational voltage that does not retain core
state. This state is known as PC6 and reduces the amount of static and dynamic power consumed by all cores.
The following actions are taken by hardware prior to PC6 entry:
1. If D18F3xA8[CC6PopDownEn]=1 and MSRC001_0071[CurPstate] < D18F3xA8[PopDownPstate],
transition the core P-state to D18F3xA8[PopDownPstate].
2. If MSRC001_10A0[CacheC6StateDis]=0, For all cores not in CC6, internal core state is saved to L1 cache
(microcode). Else, internal core state is saved to DRAM.
3. For all cores not in CC6, L1 cache is flushed to L2 cache (microcode). See 2.5.3.2.3.1 [C-state Probes and
Cache Flushing].
4. VDD is transitioned to the VID specified by D18F5x128[PC6Vid].
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5. If the core PLLs are not powered down during CC6 entry (see 2.5.3.2.3.3 [Core C6 (CC6) State]), then they
are powered down as specified by D18F5x128[PC6PwrDwnRegEn].
All of the following must be true on all cores in order for a package to be placed into PC6:
• D18F4x118/D18F4x11C[CacheFlushEn]=1 for the corresponding C-state action field
• D18F4x118/D18F4x11C[CacheFlushTmrSel] != 11b for the corresponding C-state action field.
• D18F4x118/D18F4x11C[PwrOffEnCstAct]=1 for the corresponding C-state action field.
• D18F2x118[CC6SaveEn]=1.
• D18F2x118[LockDramCfg]=1 or D18F3x12C[OverrideLockDramCfg]=1.
2.5.3.2.4
C-state Request Monitors
Deeper C-states have higher entry and exit latencies but provide greater power savings than shallower C-states.
To help balance the performance and power needs of the system, the processor can limit access to specific Cstates in certain scenarios.
2.5.3.2.4.1
FCH Messaging
The FCH can be notified when the processor transitions package C-states. See the following:
• D18F4x128[CstateMsgDis].
• D18F5x178[CstateFusionDis].
2.5.3.2.4.2
Cache Flush On Halt Saturation Counter
A cache flush success monitor tracks the success rate of cache flush timer expirations relative to the core
exiting a C-state. Based on the success rate, caches may be flushed immediately without waiting for the cache
flush timer to expire. See D18F4x130[CacheFlushSuccessMonitor] and
D18F4x128[CacheFlushSucMonThreshold]. When the core resumes normal execution, the caches refill as
normal.
2.5.3.2.5
Exiting C-states
The following events may cause the processor to exit a non-C0 C-state and return to C0:
• INTR
• NMI
• SMI
• INIT
• RESET_L assertion
If an INTR is received while a core is in a non-C0 C-state, the state of EFLAGS[IF] and the mechanism used to
enter the non-C0 C-state determine the actions taken by the processor.
• Entry via HLT, EFLAGS[IF]==0: The interrupt does not wake up the core.
• Entry via HLT, EFLAGS[IF]==1: The interrupt wakes the core and the core begins execution at the
interrupt service routine.
• Entry via IO read, EFLAGS[IF]==0: The interrupt wakes the core and the core begins execution at the
instruction after the IN instruction that was used to enter the non-C0 C-state.
• Entry via IO read, EFLAGS[IF]==1: The interrupt wakes the core and the core begins execution at the
interrupt service routine.
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ACPI Processor C-state Objects
Processor power control is implemented through the _CST object in ACPI 2.0 and later revisions. The
presence of the _CST object indicates to the OS that the platform and processor are capable of supporting
multiple power states. BIOS must provide the _CST object and define other ACPI parameters to support
operating systems that provide native support for processor C-state transitions. See 2.5.3.2.6.1 [_CST].
The _CST object is not supported with ACPI 1.0b. BIOS should provide FADT entries to support operating
systems that are not compatible with ACPI 2.0 and later revisions. See 2.5.3.2.6.2 [_CRS].
2.5.3.2.6.1
_CST
The _CST object should be generated for each core as follows:
• Count = 1.
• Register = MSRC001_0073[CstateAddr] + 1.
• Type =2.
• Latency = 400. From CC6 Latency Calculations.
• Power = 0. This field is set to 0 since it’s not used by Linux, Win7, or Vista.
2.5.3.2.6.2
_CRS
BIOS must declare in the root host bridge _CRS object that the IO address range from
MSRC001_0073[CstateAddr] to MSRC001_0073[CstateAddr]+7 is consumed by the host bridge.
2.5.3.2.6.3
Fixed ACPI Description Table (FADT) Entries
Declare the following FADT entries:
• P_LVL2_LAT = 100.
• P_LVL3_LAT = 1001.
• FLAGS.PROC_C1 = 1.
• FLAGS.P_LVL2_UP = 1.
Declare the following P_BLK entries:
• P_LVL2 =MSRC001_0073[CstateAddr] + 1.
• P_LVL3 = 0.
BIOS must declare the PSTATE_CNT entry as 00h.
2.5.3.2.7
BIOS Requirements for Initialization
1. Initialize MSRC001_0073[CstateAddr] with an available IO address. See 2.5.3.2.6.2 [_CRS].
2. Initialize D18F4x11[C:8].
3. Generate ACPI objects as described in 2.5.3.2.6 [ACPI Processor C-state Objects].
2.5.3.3
Effective Frequency
The effective frequency interface allows software to discern the average, or effective, frequency of a given core
over a configurable window of time. This provides software a measure of actual performance rather than
forcing software to assume the current frequency of the core is the frequency of the last P-state requested. This
can be useful when the P-state is limited by:
• HTC
• D18F3x68[SwPstateLimit]
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• SBI
• CPB
The following procedure calculates effective frequency using MSR0000_00E7 [Max Performance Frequency
Clock Count (MPERF)] and MSR0000_00E8 [Actual Performance Frequency Clock Count (APERF)]:
1. At some point in time, write 0 to both MSRs.
2. At some later point in time, read both MSRs.
3. Effective frequency = (value read from MSR0000_00E8 / value read from MSR0000_00E7) * P0 frequency using software P-state numbering.
Additional notes:
• The amount of time that elapses between steps 1 and 2 is determined by software.
• It is software’s responsibility to disable interrupts or any other events that may occur in between the write of
MSR0000_00E7 and the write of MSR0000_00E8 in step 1 or between the read of MSR0000_00E7 and the
read of MSR0000_00E8 in step 2.
• The behavior of MSR0000_00E7 and MSR0000_00E8 may be modified by MSRC001_0015[EffFreqCntMwait].
• The effective frequency interface provides +/- 50MHz accuracy if the following constraints are met:
• Effective frequency is read at most one time per millisecond.
• When reading or writing MSR0000_00E7 and MSR0000_00E8 software executes only MOV instructions,
and no more than 3 MOV instructions, between the two RDMSR or WRMSR instructions.
• MSR0000_00E7 and MSR0000_00E8 are invalid if an overflow occurs. Intel defines each counter to reset to
0 on overflow. AMD counters simply wrap.
2.5.4
2.5.4.1
NB Power Management
NB P-states
The processor supports up to four NB P-states (NBP0 through NBP3), specified in D18F5x16[C:0]. Each NB
P-state consists of the following:
•
•
•
•
Enable: D18F5x16[C:0][NbPstateEn].
NCLK frequency: D18F5x16[C:0][NbFid, NbDid].
VDDNB voltage: D18F5x16[C:0][NbVid].
Memory P-state: D18F5x16[C:0][MemPstate]. See 2.5.7.1 [Memory P-states].
Out of cold reset, the NB P-state is specified by D18F5x174[StartupNbPstate] and D18F3xA0[CofVidProg].
The current NB P-state is specified by D18F5x174[CurNbFid, CurNbDid, CurNbVid].
Although four NB P-states are defined, only two NB P-states are used at any given time, specified by
D18F5x170[NbPstateHi, NbPstateLo]. See 2.5.6.1.5.2 [NB P-state Pointer Configuration].
2.5.4.1.1
NB P-state Transitions
Hardware selects whether to use the high or low NB P-state based on several criteria as follows:
• Core P-state:
• MSRC001_00[6B:64][NbPstate].
• D18F5x170[NbPstateThreshold].
• GPU activity (current SCLK DPM state):
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• The GPU driver selects levels of GPU activity that force the NB P-state to either the high or low
state or allow either NB P-state.
• Hysteresis timer:
• D18F5x170[NbPstateHiRes, NbPstateLoRes].
• The following configuration registers:
• D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateGnbSlowDis].
• MSRC001_0071[NbPstateDis].
Once the UNB determines that an NB P-state transition is necessary, the UNB executes the following
sequence:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
If transitioning from the low NB P-state to the high NB P-state, transition VDDNB voltage.
If the GPU is enabled as specified by D18F5x178[SwGfxDis], wait for display buffer to fill.
Quiesce all active cores.
If the internal GPU is enabled as specified by D18F5x178[SwGfxDis], wait for display buffer to fill (see
D18F5x178[Dis2ndGnbAllowPsWait]).
Stop memory traffic and place DRAM into self-refresh.
Transition NCLK frequency.
Update NB P-state specific DRAM settings within hardware, see D18F2x210_dct[0]_nbp[3:0].
Take DRAM out of self-refresh and allow memory traffic.
Wake up cores.
If transitioning from the high NB P-state to the low NB P-state, transition VDDNB voltage.
2.5.4.1.2
2.5.4.1.2.1
BIOS NB P-state Configuration
NB P-state COF and VID Synchronization After Warm Reset
BIOS performs the following sequence on one core. This is done after any warm reset and before 2.9.7
[DCT/DRAM Initialization and Resume]. The sequence must always be performed to ensure the NB VID
request matches the NB P-state request.
1. Temp1=D18F5x170[SwNbPstateLoDis].
2. Temp2=D18F5x170[NbPstateDisOnP0].
3. Temp3=D18F5x170[NbPstateThreshold].
4. Temp4=D18F5x170[NbPstateGnbSlowDis].
5. If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11.
6. Write 1 to D18F5x170[NbPstateGnbSlowDis].
7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
CurNbDid]=[NbFid, NbDid] from D18F5x16[C:0] indexed by D18F5x170[NbPstateLo].
9. Set D18F5x170[SwNbPstateLoDis]=1.
10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
CurNbDid]=[NbFid, NbDid] from D18F5x16[C:0] indexed by D18F5x170[NbPstateHi]. Go to step 15.
11. Write 1 to D18F5x170[SwNbPstateLoDis].
12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
CurNbDid]=[NbFid, NbDid] from D18F5x16[C:0] indexed by D18F5x170[NbPstateHi].
13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
CurNbDid]=[NbFid, NbDid] from D18F5x16[C:0] indexed by D18F5x170[NbPstateLo].
15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, and
D18F5x170[NbPstateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
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NB P-state Transitions
During boot when D18F5x174[NbPstateDis]=0, BIOS forces the processor to the desired NB P-states using
the following steps:
1. Save the values in D18F5x170 for later restoration to unforce the NB P-state.
2. Set the desired NB P-state pointers, D18F5x170[NbPstateHi, NbPstateLo]. See 2.5.6.1.5.2 [NB P-state
Pointer Configuration].
3. Transition to the desired state as follows:
• In order to transition to D18F5x170[NbPstateHi], program D18F5x170 as follows:
• SwNbPstateLoDis = 1.
• Wait for D18F5x174[CurNbPstate] to equal NbPstateHi.
• In order to transition to D18F5x170[NbPstateLo], program D18F5x170 as follows:
• SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0.
• Wait for D18F5x174[CurNbPstate] to equal NbPstateLo.
BIOS performs the following to release the NB P-state force:
4. Release the NB P-state force by restoring initial D18F5x170 values.
• Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateLo] values.
• Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values.
2.5.4.1.2.3
NB P-state Configuration for Runtime
Please see the SMU programming guide (see 1.2 [Reference Documents]) for details.
2.5.4.2
NB C-states
NB C-states are package-level actions that occur only when all cores enter a non-C0 state (see 2.5.3.2 [Core Cstates]). See also 2.20.5.1 [Trace Mode Active/Inactive]. The NB C-state actions are:
• DRAM self-refresh (see 2.5.7.2 [DRAM Self-Refresh]):
• Enable bits: D18F4x118/D18F4x11C[SelfRefr] and D18F5x128[SelfRefrDis].
• Entry requirements (all of the following must be true):
• No outstanding GPU traffic or traffic from a link. (GPU->UNB traffic)
• Exit conditions (any of the following must be true):
• The local APIC timer expires. See 2.4.8.1 [Local APIC].
• New GPU traffic or traffic from a link. (GPU->UNB traffic)
• A P-state limit update (see 2.5.3.1.4 [Core P-state Limits]) causes the most restrictive P-state
limit to become a higher number than the current P-state for any core in CC1.
• NB clock gating:
• Enable bits: D18F4x118/D18F4x11C[NbClkGate] and D18F5x128[ClkGateDis].
• Entry requirements:
• No outstanding GPU traffic or traffic from a link.
• Exit conditions (any of the following must be true):
• The local APIC timer expires. See 2.4.8.1 [Local APIC].
• New GPU traffic or traffic from a link.
• A P-state limit update (see 2.5.3.1.4 [Core P-state Limits]) causes the most restrictive P-state
limit to become a higher number than the current P-state for any core in CC1.
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When entering NB C-states, the actions are taken in the following order:
1. DRAM self-refresh.
2. NB clock gating.
When exiting NB C-states, the actions are taken in the following order:
1. NB clock gating.
2. DRAM self-refresh.
2.5.5
Bandwidth Requirements
• The frequency relationship of (core COF / NB COF) <= 6 && (core COF / NB COF) >=1 must be
maintained for all supported P-state combinations. E.g., a core P0 COF of 4.0 GHz could not be combined
with a NB P0 COF of 0.6 GHz; the NB P0 COF would have to be 0.8 GHz or greater; if the NB P0 COF is
1.2 GHz, then the NB P1 COF of 0.6 GHz may only be supported if the corresponding core P-state specify a
COF of 3.0 GHz or less. This limit is only a bound for verification.
• All core P-states are required to be defined such that (NB COF/core COF) <= 32, for all NB/core P-state
combinations. E.g., if the NB COF is 4.8 GHz then the core COF must be no less than 150 MHz; support for
an NB P-state that brings the NB COF down to 2.4 GHz would not change the core COF requirement, since
all NB/core P-state combinations must meet this requirement.
• All core P-states must be defined such that CoreCOF >= 600 MHz.
• NBCOF >= MEMCLK frequency.
• 400MHz <= NBCOF <= 1600MHz.
• NBCOF <= 2*MEMCLK frequency.
2.5.6
2.5.6.1
GPU and Root Complex Power Management
Dynamic Power Management (DPM)
The processor supports dynamic GPU frequency changes along with VDDNB voltage change requests, known
as Dynamic Power Management (DPM). Once initialized, hardware dynamically monitors processor
utilization and adjusts the frequencies and voltage based on that utilization. For DPM, higher numbered states
represent higher performance and lower numbered states represent lower performance.
2.5.6.1.1
Activity Monitors
The processor contains activity monitors which track the usage level of different processor subcomponents. A
binary signal from each subcomponent is used to determine whether that subcomponent is busy. On each clock
cycle, the activity monitor samples the signal from each unmasked subcomponent. If any given subcomponent
reports that it is busy, an accumulator is incremented.
See D0F0xBC_xC020_0110 and D0F0xBC_xC0200118 for LCLK DPM activity monitor.
The output of the activity monitor is then used to determine whether the DPM state should be changed.
2.5.6.1.2
SCLK DPM
SCLK DPM consists of up to 8 states. Any number of states up through 8 may be used and there is no
requirement that the states be contiguous.
During runtime, SCLK DPM parameters are programmed by the graphics driver. To support the driver, BIOS
creates a data structure in memory containing information about the processor. Please see your AMD
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representative for more information.
2.5.6.1.3
LCLK DPM
LCLK DPM consists of up to 8 states. Any number of states up through 8 may be used and there is no
requirement that the states be contiguous. Each state is made up of the following parameters.
•
•
•
•
Valid bit: D0F0xBC_x3FD[8C:00:step14][StateValid].
Voltage change hysteresis threshold: D0F0xBC_x3FD[8C:00:step14][LowVoltageReqThreshold].
Divisor: D0F0xBC_x3FD[8C:00:step14][LclkDivider].
VID: D0F0xBC_x3FD[8C:00:step14][VID].
• See 2.5.2.2 [Dependencies Between Subcomponents on VDDNB].
• State change hysteresis thresholds: D0F0xBC_x3FD[94:08:step14][HysteresisUp, HysteresisDown].
• Activity thresholds: D0F0xBC_x3FD[9C:10:step14][ActivityThreshold].
• Residency counter: See D0F0xBC_x3FD[94:08:step14][ResidencyCounter].
LCLK DPM is enabled by setting D0F0xBC_x3FDC8[LclkDpmEn] to 1 and interrupting the SMU with
Service Index 1Eh (see 2.12.1 [Software Interrupts]). LCLK DPM voltage changes are enabled using
D0F0xBC_x3FDC8[VoltageChgEn]. When LCLK DPM is first enabled, the DPM state is transitioned to
D0F0xBC_x3FDC8[LclkDpmBootState].
2.5.6.2
GPU and Root Complex Power Gating
Several subcomponents of the GPU and root complex can be power gated when not in use.
• GPU: GPU power gating is initialized and enabled by software (see GpuEnabled and
D0F0x7C[ForceIntGfxDisable]). Once initialized and enabled, the GPU is power gated by hardware when
inactive and is ungated by hardware when needed. When internal GPU is disabled by BIOS, BIOS is
responsible for power gating the GPU. When internal GPU is disable via fusing, hardware power gates the
GPU.
• UVD: UVD is power gated by software when not in use and is ungated by software when needed. UVD’s
internal state is not saved and UVD goes through an internal reset when power is restored.
• GMC: GMC power gating is initialized and enabled by software. Once initialized and enabled, GMC is
power gated by hardware when inactive and is ungated by hardware when needed. GMC’s state is saved
internally. If the internal GPU is disabled, either by hardware (fusing) or by software, software is repsonsible
for power gating GMC.
• VCE: VCE is power gated by software when not in use and is ungated by software when needed. VCE’s
internal state is not saved and VCE goes through an internal reset when power is restored.
• DCE: DCE is power gated by software when there is no display connected. DCE’s internal state is not saved
and DCE goes through an internal reset when power is restored.
• PCIe: The Gfx link core can be power gated when it is not in use. In addition, the individual phys on the TX
and RX sides of each link can be power gated when the links are not connected. During POST and runtime,
several software components inform the SMU whether the Gfx link core or the link phys are in use.
Hardware dynamically power gates or ungates the Gfx link core and the link phys as needed.
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DRAM Power Management
Memory P-states
The processor supports up to 2 memory P-states, M0 and M1. Each memory P-state consists of the following:
• MEMCLK frequency
• A set of frequency dependent DRAM timing and configuration registers
See 2.9 [DRAM Controllers (DCTs)] for DRAM technology specific information and requirements.
All valid memory P-states are associated with a specific NB P-state, as specified by
D18F5x16[C:0][MemPstate]. When hardware transitionsto a new NB P-state, the memory P-state is
transitioned to that specified by the new NB P-state.
Out of cold reset the current memory P-state is M0. The P-state value specified by
D18F5x16[C:0][MemPstate] of the NB P-state indexed by D18F5x174[StartupNbPstate] is invalid. Support
for dynamic memory P-state changes is indicated by D18F3xE8[MemPstateCap]=1 and one or more
D18F5x16[C:0][MemPstate]=1; otherwise M0 is used by hardware for configuration purposes.
During boot, and if D18F5x170[MemPstateDis]=0, the BIOS can disable memory P-states using the following
steps:
1. Program D18F5x170[MemPstateDis]=1.
2. Program D18F5x16[C:0][MemPstate]=0.
2.5.7.2
DRAM Self-Refresh
DRAM is placed into self-refresh on S3 entry (see 2.5.8.1.1 [ACPI Suspend to RAM State (S3)]).
D18F5x178[AllowSelfRefrS3Dis] controls whether the NB waits for the GPU to assert an internal
AllowSelfRefresh signal before transitioning into self-refresh. D18F5x178[InbWakeS3Dis] controls whether
the NB to GPU interface must be idle before this transition is started.
In addition to S3, DRAM is placed into self-refresh in S0 in the following two scenarios:
• NB P-state transitions (see 2.5.4.1 [NB P-states]).
• NB C-states (see 2.5.4.2 [NB C-states]).
The following requirements must be met before hardware places DRAM into self-refresh:
• No pending traffic.
• One of the following is true:
• The GPU is idle and the internal display buffer is full as specified by
GMMx63C[McAllowStop].
• The internal GPU is disabled.
Once the above requirements are met, the NB asserts an internal signal called PreSelfRefresh. In response, the
GNB asserts an internal signal called AllowSelfRefresh when the DMIF region representing its own display is
full or exceeds the high watermark (see 2.5.9.3 [Stutter Mode]), and hardware places DRAM into selfrefresh.
Early self-refresh occurs when DRAMs are placed in self-refresh before expiration of the cache flush timer.
See D18F4x118/D18F4x11C[SelfRefrEarly] and D18F5x128[SelfRefrEarlyDis]. If early self-refresh is
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enabled, the DRAMs are taken out of self-refresh to perform the flush operation when the cache flush timer
expires and then placed back into self-refresh.
The following are events that cause DRAM to transition out of self-refresh:
• Core transitioning to C0.
• Incoming request from any link or the GMC as indicated by the assertion of the internal signal InbWake.
• P-state limit update, only in the case when all cores are not in the power gated (CC6) state.
To save additional power, hardware always tristates MEMCLK when entering self-refresh.
2.5.7.3
Stutter Mode
DRAM is most commonly placed in self-refresh due to stutter mode when the internal GPU is in use. The
display buffer in the GPU is a combination of a large buffer known as the DMIF (Display Memory Interface
FIFO) and a smaller line buffer. The DMIF takes data originating from DRAM and sends it to the line buffer to
draw to the screen. When the data level in the DMIF is full, DRAM is placed in self-refresh, and incoming
DRAM requests are queued. As the DMIF drains, it eventually falls below a predefined watermark level, at
which point hardware pulls DRAM out of self-refresh and services all the requests in the queue. Once all the
requests are complete and the DMIF is full again, a transition back into self-refresh occurs if the stutter mode
conditions are still met.
2.5.7.3.1
System BIOS Requirements for Stutter Mode Operation During POST
BIOS creates a data structure in memory containing information about the processor for use by the driver.
Please see your AMD representative for more information.
2.5.7.4
EVENT_L
EVENT_L is a level sensitive input to the processor. When asserted, the actions specified by D18F2xA4 are
taken. EVENT_L is generally asserted to indicate that a DRAM high temperature condition exists. The
minimum assertion time for EVENT_L is 15 ns. The minimum deassertion time for EVENT_L is 15 ns.
• EVENT_L is pulled to VDDIO on the motherboard.
• EVENT_L is ignored while:
• PWROK is de-asserted.
• RESET_L is asserted.
• BIOS must ensure that throttling is disabled (see D18F2xA4[CmdThrottleMode]) until DRAM training is
complete.
See 2.9.12 [DRAM On DIMM Thermal Management and Power Capping].
2.5.8
2.5.8.1
System Power Management
S-states
S-states are ACPI defined sleep states. S0 is the operational state. All other S-states are low-power states in
which various voltage rails in the system may or may not be powered. See the ACPI specification for
descriptions of each S-state. The only other S-state supported is S5.
2.5.8.1.1
ACPI Suspend to RAM State (S3)
The processor supports the ACPI-defined S3 state. Software is responsible for restoring the state of the
processor’s registers when resuming from S3. All registers in the processor that BIOS initialized during the
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initial boot must be restored. The method used to restore the registers is system specific.
During S3 entry, software is responsible for transitioning the processor to Memory Pstate0. See 2.5.7.1 [Memory P-states].
During S3 entry, system memory enters self-refresh mode (see 2.5.7.2 [DRAM Self-Refresh]). Software is
responsible for bringing memory out of self-refresh mode when resuming from S3. To bring memory out of
self-refresh mode. See 2.9.7 [DCT/DRAM Initialization and Resume].
Many of the systemboard power planes for the processor are powered down during S3. Refer to the Electrical
Data Sheet and the AMD Infrastructure Roadmap for the following:
• Power plane electrical requirements during S3.
• Power plane sequencing requirements on S3 entry and exit.
• System signal states for both inputs (e.g. PWROK and RESET_L) and outputs (e.g. VID[*], PSI_L bit,
THERMTRIP_L, etc.) during S3.
• System signal sequencing requirements on S3 entry and exit.
• System management message sequencing on S3 entry and exit.
2.5.9
Application Power Management (APM)
Application Power Management (APM) allows the processor to deterministically provide maximum
performance while remaining within the specified power delivery and removal envelope. APM dynamically
monitors processor activity and generates an approximation of power consumption. If power consumption
exceeds a defined power limit, a P-state limit is applied by APM hardware to reduce power consumption. APM
ensures that average power consumption over a thermally significant time period remains at or below the
defined power limit. This allows P-states to be defined with higher frequencies and voltages than could be used
without APM.
2.5.9.1
Core Performance Boost (CPB)
These P-states are referred to as boosted P-states.
• Support for APM is specified by CPUID Fn8000_0007_EDX[CPB].
• APM is enabled if all of the following conditions are true:
• MSRC001_0015[CpbDis] = 0 for all cores.
• D18F4x15C[ApmMasterEn] = 1.
• D18F4x15C[BoostSrc] = 01b.
• D18F4x15C[NumBoostStates] != 0.
• APM can be dynamically enabled and disabled through MSRC001_0015[CpbDis]. If core performance
boost (CPB) is disabled on any core, a P-state limit is applied to all cores. The P-state limit restricts all cores
to the highest performance non-boosted P-state. See 2.5.5.1.6 [Modification of P-state Requests and Visibility].
• All P-states, both boosted and non-boosted, are specified in MSRC001_00[6B:64].
• The number of boosted P-states is specified by D18F4x15C[NumBoostStates].
• The number of boosted P-states may vary from product to product.
• Two levels of boosted P-states are supported. Compute units can be placed in the first level of boosted Pstates if the processor power consumption remains within the TDP limit. The second level of boosted Pstates is C-state Boost. See 2.5.9.1.1 [C-state Boost].
• All boosted P-states are always higher performance than non-boosted P-states.
• To ensure proper operation, boosted P-states should be hidden from the operating system. BIOS should not
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provide ACPI _PSS entries for boosted P-states. See 2.5.3.1.8.3.2 [_PSS (Performance Supported States)].
• The lowest-performance P-state CPB limits the processor to is the highest-performance non-boosted P-state.
2.5.9.1.1
C-state Boost
C-state Boost can only be achieved if a subset of compute units are in CC6 and the processor power
consumption remains within the TDP limit. See D18F4x16C[CstateCnt, CstateBoost].
2.5.9.2
TDP Limiting
TDP limiting is a mechanism for capping the power consumption of the processor through a TDP limit.
2.5.9.3
Bidirectional Application Power Management (BAPM)
Bidirectional Application Power Management (BAPM) is an algoirthm to enable fine grained power transfers
between the core and GPU. This algorithm tracks either power or temperature across the processor which
enables maximum performance within a defined limit.
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Performance Monitoring
The processor includes support for two methods of monitoring processor performance:
• 2.6.1 [Performance Monitor Counters].
• 2.6.2 [Instruction Based Sampling (IBS)].
2.6.1
Performance Monitor Counters
The following types of performance counters are supported:
• 2.6.1.1 [Core Performance Monitor Counters], consisting of one set located in each core of each compute
unit.
• 2.6.1.2 [L2I Performance Monitor Counters], consisting of one set located in each compute unit.
• 2.6.1.3 [NB Performance Monitor Counters], consisting of one set located in each node.
The accuracy of the performance counters is not ensured. The performance counters are not assured of producing identical measurements each time they are used to measure a particular instruction sequence, and they
should not be used to take measurements of very small instruction sequences. The RDPMC instruction is not
serializing, and it can be executed out-of-order with respect to other instructions around it. Even when bound
by serializing instructions, the system environment at the time the instruction is executed can cause events to
be counted before the counter value is loaded into EDX:EAX.
To accurately start counting with the write that enables the counter, disable the counter when changing the
event and then enable the counter with a second MSR write.
Writing the performance counters can be useful if there is an intention for software to count a specific number
of events, and then trigger an interrupt when that count is reached. An interrupt can be triggered when a performance counter overflows. Software should use the WRMSR instruction to load the count as a two’s-complement negative number into the performance counter. This causes the counter to overflow after counting the
appropriate number of times.
In addition to the RDMSR instruction, the performance counter registers can be read using a special read performance-monitoring counter instruction, RDPMC. The RDPMC instruction loads the contents of the performance counter register specified by the ECX register, into the EDX register and the EAX register. See Table 36
[RDPMC ECX Definition].
2.6.1.1
Core Performance Monitor Counters
The core performance monitor counters are used by software to count specific non L2 events that occur in a
core of the compute unit. Each core of each compute unit provides four 48-bit performance counters. Unless
otherwise specified, the events count only the activity of the core, not activity caused by the other core of the
compute unit.
MSRC001_00[03:00] specify the events to be monitored and how they are monitored. All of the events are
specified in 3.23 [Core Performance Counter Events]. MSRC001_00[07:04] are the counters.
All of the events are specified in 3.23 [Core Performance Counter Events].
2.6.1.2
L2I Performance Monitor Counters
The L2I performance monitor counters are used by software to count specific L2 events that occur in a core of
the compute unit. Unless otherwise specified using the thread masks, the events count the activity of all cores.
Each compute unit provides four 48-bit performance counters.
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MSRC001_023[6,4,2,0] [L2I Performance Event Select (L2I_PERF_CTL[3:0])] specify the events to be monitored and how they are monitored. MSRC001_023[7,5,3,1] [L2I Performance Event Counter
(L2I_PERF_CTR[3:0]] are the counters. Support for MSRC001_023[7:0] is indicated by CPUID
Fn8000_0001_ECX[PerfCtrExtL2I].
All of the events are specified in 3.24 [L2I Performance Counter Events].
All L2I performance monitor events can be counted on all counters.
All L2I performance events are one event per clock.
2.6.1.3
NB Performance Monitor Counters
The NB performance monitor counters are used by software to count specific events that occur in the NB. Each
node provides four 48-bit performance counters. Since the northbridge performance counter register are shared
by all cores on a node, monitoring of northbridge events should only be performed by one core on a node.
MSRC001_024[6,4,2,0] [Northbridge Performance Event Select (NB_PERF_CTL[3:0])] and
MSRC001_024[7,5,3,1] [Northbridge Performance Event Counter (NB_PERF_CTR[3:0])] specify the events
to be monitored and how they are monitored. Support for MSRC001_024[7:0] is indicated by CPUID
Fn8000_0001_ECX[PerfCtrExtNB].
All of the events are specified in 3.25 [NB Performance Counter Events].
All NB performance monitor events can be counted on all counters.
All NB performance events are one event per clock.
NB performance counters do not support APIC interrupt capability.
2.6.2
Instruction Based Sampling (IBS)
IBS is a code profiling mechanism that enables the processor to select a random instruction fetch or micro-op
after a programmed time interval has expired and record specific performance information about the operation.
An interrupt is generated when the operation is complete as specified by MSRC001_103A [IBS Control]. An
interrupt handler can then read the performance information that was logged for the operation.
The IBS mechanism is split into two parts: instruction fetch performance controlled by MSRC001_1030 [IBS
Fetch Control (IbsFetchCtl)]; and instruction execution performance controlled by MSRC001_1033 [IBS Execution Control (IbsOpCtl)]. Instruction fetch sampling provides information about instruction TLB and instruction cache behavior for fetched instructions. Instruction execution sampling provides information about microop execution behavior. The data collected for instruction fetch performance is independent from the data collected for instruction execution performance. Support for the IBS feature is indicated by the CPUID
Fn8000_0001_ECX[IBS].
Instruction fetch performance is profiled by recording the following performance information for the tagged
instruction fetch:
• If the instruction fetch completed or was aborted. See MSRC001_1030.
• The number of clock cycles spent on the instruction fetch. See MSRC001_1030.
• If the instruction fetch hit or missed the IC, hit/missed in the L1 and L2 TLBs, and page size. See
MSRC001_1030.
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• The linear address, physical address associated with the fetch. See MSRC001_1031, MSRC001_1032.
Instruction execution performance is profiled by tagging one micro-op associated with an instruction. Instructions that decode to more than one micro-op return different performance data depending upon which micro-op
associated with the instruction is tagged. These micro-ops are associated with the RIP of the next instruction to
retire. The following performance information is returned for the tagged micro-op:
• Branch and execution status for micro-ops. See MSRC001_1035.
• Branch target address for branch micro-ops. See MSRC001_103B.
• The logical address associated with the micro-op. See MSRC001_1034.
• The linear and physical address associated with a load or store micro-op. See MSRC001_1038,
MSRC001_1039.
• The data cache access status associated with the micro-op: DC hit/miss, DC miss latency, TLB hit/miss,
TLB page size. See MSRC001_1037.
• The number clocks from when the micro-op was tagged until the micro-op retires. See MSRC001_1035.
• The number clocks from when the micro-op completes execution until the micro-op retires. See
MSRC001_1035.
• Source information for DRAM and MMIO. See MSRC001_1036.
2.7
Configuration Space
PCI-defined configuration space was originally defined to allow up to 256 bytes of register space for each
function of each device; these first 256 bytes are called base configuration space (BCS). It was expanded to
support up to 4096 bytes per function; bytes 256 through 4095 are called extended configuration space (ECS).
The processor includes configuration space registers located in both BCS and ECS. Processor configuration
space is accessed through bus 0, devices 18h to 1Fh, where device 18h corresponds to node 0 and device 1Fh
corresponds to node 7. See 2.7.3 [Processor Configuration Space].
Configuration space is accessed by the processor through two methods:
• IO-space configuration: IO instructions to addresses CF8h and CFCh.
• Enabled through IOCF8[ConfigEn], which allows access to BCS.
• Access to ECS enabled through MSRC001_001F[EnableCf8ExtCfg].
• Use of IO-space configuration can be programmed to generate GP faults through MSRC001_0015[IoCfgGpFault].
• SMI trapping for these accesses is specified by MSRC001_0054 [IO Trap Control
(SMI_ON_IO_TRAP_CTL_STS)] and MSRC001_00[53:50] [IO Trap (SMI_ON_IO_TRAP_[3:0])].
• MMIO configuration: configuration space is a region of memory space.
• The base address and size of this range is specified by MSRC001_0058 [MMIO Configuration Base
Address]. The size is controlled by the number of configuration-space bus numbers supported by the system. Accesses to this range are converted configuration space as follows:
• Address[31:0] = {0h, bus[7:0], device[4:0], function[2:0], offset[11:0]}.
The BIOS may use either configuration space access mechanism during boot. Before booting the OS, BIOS
must disable IO access to ECS, enable MMIO configuration and build an ACPI defined MCFG table. BIOS
ACPI code must use MMIO to access configuration space.
Per the link specification, BCS accesses utilize link addresses starting at FD_FE00_0000h and ECS accesses
utilize link addresses starting at FE_0000_0000h.
2.7.1
MMIO Configuration Coding Requirements
MMIO configuration space accesses must use the uncacheable (UC) memory type.
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Instructions used to read MMIO configuration space are required to take the following form:
mov eax/ax/al, any_address_mode;
Instructions used to write MMIO configuration space are required to take the following form:
mov any_address_mode, eax/ax/al;
No other source/target registers may be used other than eax/ax/al.
In addition, all such accesses are required not to cross any naturally aligned DW boundary. Access to MMIO
configuration space registers that do not meet these requirements result in undefined behavior.
2.7.2
MMIO Configuration Ordering
Since MMIO configuration cycles are not serializing in the way that IO configuration cycles are, their ordering
rules relative to posted may result in unexpected behavior.
Therefore, processor MMIO configuration space is designed to match the following ordering relationship that
exists naturally with IO-space configuration: if a core generates a configuration cycle followed by a postedwrite cycle, then the posted write is held in the processor until the configuration cycle completes. As a result,
any unexpected behavior that might have resulted if the posted-write cycle were to pass MMIO configuration
cycle is avoided.
2.7.3
Processor Configuration Space
The processor includes configuration space as described in 3 [Registers]. Accesses to unimplemented registers
of implemented functions are ignored: writes dropped; reads return 0. Accesses to unimplemented functions
also ignored: writes are dropped; however, reads return all F’s. The processor does not log any master abort
events for accesses to unimplemented registers or functions.
Accesses to device numbers of devices not implemented in the processor are routed based on the configuration
map registers. If such requests are master aborted, then the processor can log the event.
2.8
Northbridge (NB)
Each node includes a single northbridge that provides the interface to the local core(s), the interface to system
memory, and the interface to system IO devices. The NB includes all power planes except VDD; see 2.5.1
[Processor Power Planes And Voltage Control].
The NB is responsible for routing transactions sourced from cores and link to the appropriate core, cache,
DRAM, or link. See 2.4.6 [System Address Map].
2.8.1
NB Architecture
Major NB blocks are: System Request Interface (SRI), Memory Controller (MCT), DRAM Controllers
(DCTs), and crossbar (XBAR). SRI interfaces with the core(s). MCT maintains cache coherency and interfaces
with the DCTs; MCT maintains a queue of incoming requests called MCQ. XBAR is a switch that routes packets between SRI, MCT, and the link.
The MCT operates on physical addresses. Before passing transactions to the DCTs, the MCT converts physical
addresses into normalized addresses that correspond to the values programmed into D18F2x[5C:40]_dct[0]
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[DRAM CS Base Address]. Normalized addresses include only address bits within the DCTs’ range.
2.8.2
2.8.2.1
NB Routing
Address Space Routing
There are four main types of address space routed by the NB:
1. Memory space targeting system DRAM
2. Memory space targeting IO (MMIO)
3. IO space
4. Configuration space.
2.8.2.1.1
DRAM and MMIO Memory Space
Memory space transactions provide the NB with the physical address, cacheability type, access type, and
DRAM/MMIO destination type as specified in section 2.4.6.1.2 [Determining The Access Destination for Core
Accesses].
Memory-space transactions are handled by the NB as follows:
• IO-device accesses are compared against:
• If the access matches D18F1x[2CC:2A0,1CC:180,BC:80] [MMIO Base/Limit], then the transaction is
routed to the root complex;
• Else, if the access matches D18F1x[17C:140,7C:40] [DRAM Base/Limit], then the access is routed to
the DCT;
• Else, the access is routed to the UMI.
• For core accesses the routing is determined based on the DRAM/MMIO destination:
• If the destination is DRAM:
• Else, if the access matches D18F1x[17C:140,7C:40] [DRAM Base/Limit], then the transaction is
routed to the DCT;
• Else, the access is routed to the UMI.
• If the destination is MMIO:
• If the access matches the VGA-compatible MMIO address space and D18F1xF4[VE]=1 then
D18F1xF4 describes how the access is routed and controlled;
• Else, If the access matches D18F1x[2CC:2A0,1CC:180,BC:80] [MMIO Base/Limit], then the transaction is routed to the root complex;
• Else, the access is routed to the UMI.
2.8.2.1.2
IO Space
IO-space transactions from IO links or cores are routed as follows:
• If the access matches D18F1x[DC:C0] [IO-Space Base/Limit], then the transaction is routed to the root complex;
• Else, If the access matches the VGA-compatible IO address space and D18F1xF4[VE]=1 then D18F1xF4
describes how the access is routed and controlled.
• Else, the access is routed to the UMI.
2.8.2.1.3
Configuration Space
Configuration-space transactions from IO links are master aborted. Configuration-space transactions from
cores are routed as follows:
• If the access matches D18F1x[1DC:1D0,EC:E0] [Configuration Map], then the transaction is routed to the
specified link;
• Else, the access is routed to link that contains compatibility (subtractive) address space.
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Recommended Buffer Count Settings Overview
When changing from the recommended settings, see the register programming requirements in the definition of
each register. Some chipsets may further optimize these settings for their platform. If values other than the recommended settings are used, see the register requirements in the definition of each register. Table 11 defines
commonly used terms for the following tables.
Table 11: ONION Link Definitions
Term
LinkGanged
2.8.3
Definition
Ganged = 0.
Memory Scrubbers
The processor includes memory scrubbers specified in MSRC001_10A0, D18F3x58, D18F3x5C, and
D18F3x60. The scrubbers ensure that all cachelines in memory within or connected to the processor are periodically read and, if correctable errors are discovered, they are corrected.
For recommendations on scrub rates, see 2.14.1.8 [Scrub Rate Considerations].
The scrub rate is specified as the time between successive scrub events. A scrub event occurs when a line of
memory is checked for errors; the amount of memory that is checked varies based on the memory block (see
field descriptions).
The time required to fully scrub the memory of a node is determined as:
• Time = ((memory size in bytes)/64) * (Scrub Rate).
• E.g. If a node contains 1GB of system memory and DramScrub=5.24 ms, then all of the system memory
of the node is scrubbed about once every 23 hours.
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DRAM Controllers (DCTs)
The processor includes one DRAM controller (DCT). Each DCT controls one 64-bit DDR3 DRAM channel.
A DRAM channel consists of the group of DRAM interface pins connecting to one series of DIMMs.
BIOS reads D18F5x84[DctEn] to determine the DCT to DDR channel mapping as follows:
• DCT0 controls channel A.
The DCTs operate on normalized addresses corresponding to the values programmed into
D18F2x[5C:40]_dct[0]. Normalized addresses only include address bits within a DCT’s range. The physical to
normalized address translation varies based on various Northbridge settings. See 2.9.10 [Memory Hoisting]
and 2.9.11 [DRAM CC6/PC6 Storage].
The following restrictions limit the DIMM types and configurations supported by the DCT:
• All DIMMs connected to a node are required to operate at the same MEMCLK frequency, regardless of the
channel. All DCTs of a node must be programmed to the same frequency.
• Mixing of DIMM types within a system is not supported.
• RDIMM, LRDIMM, and stacked DRAM type DIMMs are not supported.
• Mixing of ECC and non-ECC DIMMs within a system is not supported
2.9.1
Common DCT Definitions
Table 12: DCT Definitions
Term
AutoSelfRefresh
DataMaskMbType
Definition
SPDByte[31][2] of the DIMM being configured.
Motherboard type for processor Data Mask pins.
Description
Bits
00b
No connect
01b
Pins are routed per DM rules
10b
Pins are routed per DQS rules
The DDR data rate (MT/s) as specified by D18F2x94_dct[0][MemClkFreq] and
D18F2x2E0_dct[0][M1MemClkFreq].
DeviceWidth
SPDByte[7][2:0] of the DIMM being configured.
DIMM
The DIMM being configured
DIMM0
DIMM slots 0-n. The DIMMs on each channel are numbered from 0 to n where
DIMM0 is the DIMM closest to the processor on that channel and DIMMn is the
DIMM1
DIMM farthest from the processor on that channel.
DimmsPopulated
The number of DIMMs populated per channel plus rows of Solder-down DRAM
devices.
DR
Dual Rank
DramCapacity
SPDByte[4][3:0] of the DIMM being configured.
ExtendedTemperature- SPDByte[31][0] of the DIMM being configured.
Range
MRS
JEDEC defined DRAM Mode Register Set.
NP
No DIMM populated
DdrRate
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Table 12: DCT Definitions
Term
NumDimmSlots
Definition
The number of motherboard DIMM slots per channel plus rows of Solder-down
DRAM devices
SPDByte[7][5:3] of the DIMM being configured, or the number of ranks soldered
down.
The rank being configured
SPDByte[63][0] of the DIMM being configured.
SPDByte[5][5:3] of the DIMM being configured.
DRAM devices soldered directly to the motherboard.
DCT is configured for SODIMM if (D18F2x90_dct[0][UnbuffDimm]==1) and
SODIMMs are populated.
Serial Presence Detect. In the case of DRAMs soldered on the platform, this refers
to a virtual representation of the DRAM vendors’ data sheets.
Single Rank
DCT is configured for UDIMM if (D18F2x90_dct[0][UnbuffDimm]==1) and
UDIMMs are populated.
DDR VDDIO in V.
NumRanks
Rank
RankMap
RowAddrBits
Solder-down DRAM
SODIMM
SPD
SR
UDIMM
VDDIO
2.9.2
DCT Frequency Support
The tables below list the maximum DIMM speeds supported by the processor for different configurations. The
motherboard should comply with the relevant AMD socket motherboard design guideline (MBDG) to achieve
the rated speeds. In cases where MBDG design options exist, lower-quality options may compromise the maximum achievable speed; motherboard designers should assess the tradeoffs.
Table 13: DDR3 UDIMM Maximum Frequency Support with 6-layer Motherboard Design FT3 package
Num- Dimms
DimmS- Populots
lated
1
1
DRAM
SR
DR
Frequency1 (MT/s)
1.5V
1.35V
1.25V
1
1600
1
1600
2
1
1
1600
1
1600
2
2
1600
1
1
1333
2
1333
1. Population restrictions (including the order for partially populated channels) may apply.
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Table 14: DDR3 UDIMM Maximum Frequency Support with 6-layer Motherboard Design FT3 package
Microserver
Num- Dimms
DimmS- Populots
lated
1
1
DRAM
SR
DR
Frequency1 (MT/s)
1.5V
1.35V
1.25V
1
1600
1600
1
1600
1600
2
1
1
1600
1600
1
1600
1600
2
2
1600
1600
1
1
1333
1333
2
1333
1333
1. Population restrictions (including the order for partially populated channels) may apply.
Table 15: DDR3 SODIMM Maximum Frequency Support with 6-layer Motherboard Design FT3 package
Num- Dimms
DimmS- Populots
lated
1
1
DRAM
SR
DR
Frequency1 (MT/s)
1.5V
1.35V
1.25V
1
1600
1600
1333
1
1600
1600
1333
2
1
1
1600
1600
1333
1
1600
1600
1333
2
2
1600
1600
1333
1
1
1600
1333
1333
2
1600
1333
1333
1. Population restrictions (including the order for partially populated channels) may apply.
Table 16: DDR3 UDIMM Maximum Frequency Support with 4-layer Motherboard Design FT3 package
Num- Dimms
DimmS- Populots
lated
1
1
DRAM
SR
DR
Frequency1 (MT/s)
1.5V
1.35V
1.25V
1
1600
1
1600
2
1
1
1600
1
1600
2
2
1600
1
1
1333
2
1333
1. Population restrictions (including the order for partially populated channels) may apply.
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Table 17: DDR3 SODIMM Maximum Frequency Support with 4-layer Motherboard Design FT3 package
Num- Dimms
DimmS- Populots
lated
1
1
2
1
2
DRAM
Frequency1 (MT/s)
SR
DR
1.5V
1.35V
1.25V
1
-
1600
1333-16002
1066-13332
-
1
1600
1333-16002
1
-
1333-16002
1333-16002
1066-13332
1066
-
1
1333-16002
2
-
1333-16002
1333
1066
1066
1333-16002
1
1
1333
1333
1066
2
1333
1333
1066
1. Population restrictions (including the order for partially populated channels) may apply.
Table 18: DDR3 SODIMM plus Solder-down DRAM Maximum Frequency with 6-layer Motherboard FT3
package
Num- Dimms
DimmS- Populots
lated
2
1
DRAM
SR
DR
Frequency1 (MT/s)
1.5V
1.35V
1.25V
1
1333
1333
1066
1
1333
1333
1066
2
2
1333
1333
1066
1
1
1333
1066
1066
2
1333
1066
1066
1. Population restrictions (including the order for partially populated channels) may apply.
Table 19: DDR3 SODIMM plus Solder-down DRAM Maximum Frequency with 4-layer Motherboard FT3
package
Num- Dimms
DimmS- Populots
lated
2
1
DRAM
SR
DR
Frequency1 (MT/s)
1.5V
1.35V
1.25V
1
1066
1066
1066
1
1066
1066
1066
2
2
1066
1066
1066
1
1
1066
1066
1066
2
1066
1066
1066
1. Population restrictions (including the order for partially populated channels) may apply.
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Table 20: DDR3 Solder-down DRAM Maximum Frequency Support FT3 package
Num- Dimms
DimmS- Populots
lated
1
1
DRAM
SR
DR
Frequency1 (MT/s)
1.5V
1.35V
1.25V
1
1600
1600
1333
1
1600
1600
1333
1. Population restrictions (including the order for partially populated channels) may apply.
Table 21: DDR3 UDIMM Maximum Frequency Support FS1b package
Num- Dimms
DimmS- Populots
lated
1
1
2
1
2
DRAM
Frequency1 (MT/s)
SR
DR
1.5V
1.35V
1.25V
1
-
1
1600
1600
1600
1600
1600
1
-
1
1600
1600
1600
1600
2
-
1600
1333-16002
1333-16002
1333
1
1
1600
1333-16002
1333
-
2
1600
2
1333-16002
1600
1333
1333-1600
1. Population restrictions (including the order for partially populated channels) may apply.
The tables below list the DIMM populations as supported by the processor. DIMMs must be populated from
farthest slot to closest slot to the processor on a per channel basis when a daisy chain topology is used.
Table 22: DDR3 Population Support
NumDimmSlots DIMM0 DIMM1
1
SR/DR N/A
2
NP
SR/DR
SR/DR SR/DR
2.9.3
DCT Configuration Registers
There are multiple types of DCT configuration registers:
• Registers for which there is one instance. E.g. D18F2xA4 or D18F2x78_dct[0].
• Registers for which there is one instance per NbPstate use D18F1x10C[NbPsSel] for software accesses.
• D18F2x210_dct[0]_nbp[3:0] refers to all instances of the D18F2x210 register.
• D18F2x210_dct[0]_nbp[1] refers to the register for Nb P-state 1 of any or all DCTs.
• Registers for which there is one instance per memory P-state use D18F1x10C[MemPsSel] for software
accesses. The syntax for this register type is described by example as follows:
• D18F2x2E8_dct[0]_mp[1:0] refers to all instances of the D18F2x2E8 register.
• D18F2x2E8_dct[0]_mp[1] refers to the register for memory P-state 1 of either or both DCTs.
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DDR Pad to Processor Pin Mapping
The relationship of pad drivers to processor pins varies by package as shown in the following table. The pad
names in the tables below may be prefixed with “BP_” to obtain the correct bump name.
Table 23: Package pin mapping
Pin1
FT3
MEMCLK0_H[0]
MA_CLK_H[0]
MEMCLK0_H[1]
MA_CLK_H[1]
MEMCLK0_H[2]
MA_CLK_H[2]
MEMCLK0_H[3]
MA_CLK_H[3]
MEMCLK0_H[4]
NC
MEMCLK0_H[5]
NC
MEMCS0_L[0]
MA0_CS_L[0]
MEMCS0_L[1]
MA0_CS_L[1]
MEMCS0_L[2]
MA1_CS_L[0]
MEMCS0_L[3]
MA1_CS_L[1]
MEMCS0_L[4]
NC
MEMCS0_L[5]
NC
MEMCS0_L[6]
NC
MEMCS0_L[7]
NC
MEMODT0[0]
MA0_ODT[0]
MEMODT0[1]
MA0_ODT[1]
MEMODT0[2]
MA1_ODT[0]
MEMODT0[3]
MA1_ODT[1]
MEMCKE0[0]
MA_CKE[0]
MEMCKE0[1]
MA_CKE[1]
MEMCKE0[2]
MA_CKE[2]
MEMCKE0[3]
MA_CKE[3]
1. For differential pins, only positive polarity pins are shown; negative polarity
pins have corresponding mapping and
are controlled by the same CSR field.
NC = Not connected. BIOS should tristate or disable the pad for maximum
power savings.
Pad
2.9.4.1
DDR Chip to Pad Mapping
The relationship of chip to pad drivers is shown in the following table. BIOS should disable or power down
unused chips for maximum power savings.
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Table 24: Pad (from chiplet) pin mapping
Chip
Group
Pad1
Clk chip 0
0
MEMCLK0_H[1:0]
Clk chip 1
0
MEMCLK0_H[3:2]
Cmd/Addr 0
0
MEMCS0_L[7,5,3,1]
1
MEMODT0[3:0]
2
MEMCS0_L[6,4,2,0]
Cmd/Addr 1
0
MEMRAS0_L
MEMCAS0_L
MEMWE0_L
MEMADD0[13]
1
MEMADD0[10,0]
MEMBANK0[1:0]
2
MEMPAR0
Address 2
0
MEMCKE0[3:0]
1
MEMADD0[0,1,8,9]
2
MEMADD0[2,3,10,11]
3
MEMADD0[4,5,12,13]
4
MEMADD0[6,7,14,15]
2
0
MEMDATA[5,4,1,0]
Data
1
MEMDQS_H[0], MEMDQSDM[0]
2
MEMDATA[7,6,3,2]
1. For differential pads, only positive polarity pads are shown; negative polarity pads have corresponding mapping and are controlled
by the same chip.
Only channel A map is shown. For multi-channel products the
other channels are similar.
2. Only Data chip 0 is shown. Remaining data chips are repeated
with sequential DQ/DQS/DM pin numbers.
2.9.5
DRAM Controller Direct Response Mode
The DCT supports direct response mode for responding to a cache line fill request before the DCT is initialized. In direct response mode, the target DCT responds to a cache line fill request by returning 64 bytes of all
ones without issuing a read transaction on the DRAM bus. The BIOS uses this feature, a.k.a dummy response
mode, or, graceful abort, to allocate cache lines for temporary data storage. The controller exits direct response
mode when D18F2x7C_dct[0][EnDramInit] or D18F2x90_dct[0][InitDram]|[ExitSelfRef] is set to 1. See
2.3.3 [Using L2 Cache as General Storage During Boot].
2.9.6
DRAM Data Burst Mapping
DRAM requests are mapped to data bursts on the DDR bus in the following order:
• When D18F2x110[DctDatIntLv] = 0, a 64 B request is mapped to each of the eight sequential data beats as
QW0, QW1...QW7.
• When D18F2x110[DctDatIntLv] = 1, the order of cache data to QW on the bus is the same except that even
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and odd bits are interleaved on the DRAM bus as follows:
• For every 8 bytes in the cache line, even bits map to QW0, QW2, QW4, and QW6 on the DRAM bus.
• For every 8 bytes in the cache line, odd bits map to QW1, QW3, QW5, and QW7 on the DRAM bus.
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DCT/DRAM Initialization and Resume
DRAM initialization involves several steps in order to configure the DRAM controllers and the DRAM, and to
tune the DRAM channel for optimal performance.
DRAM resume requires several steps to configure the DCTs to properly resume from the S3 state.
The following sequence describes the steps needed after a reset for initialization or resume:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Configure the DDR supply voltage regulator. See 2.9.7.1.
Force NB P-state to NBP0.
Force register accesses to M0. See 2.9.7.3 for further requirements used in steps below.
DDR phy initialization. See 2.9.7.4.
DRAM device and controller initialization.
• If BIOS is booting from an unpowered state (ACPI S4, S5 or G3), then it performs the following:
a. Program SPD configuration. See 2.9.7.5.
b. Program Non-SPD configuration. See 2.9.7.6.
c. Program DCT training specific configuration. See 2.9.7.7.
d. Program the remaining DCT registers not covered by an explicit sequence dependency.
e. DRAM device initialization. See 2.9.7.8.
• If BIOS is resuming the platform from S3 state, then it performs the following:
a. Restore all DCT and phy registers that were programmed during the first boot from non-volatile
storage. See 2.9.7.5 and 2.9.7.6 for a review of registers.
b. Program D18F2x90_dct[0][ExitSelfRef] = 1. Dct sends MR0.
c. Restore the trained delayed values (found during the initial boot in step 6 below) from nonvolatile
storage.
d. Continue at step 8.
DRAM data training.
A. Write levelization training. See 2.9.7.9.1.
B. DQS receiver enable training. See 2.9.7.9.2 and 2.9.7.9.3.
C. DQS position training. See 2.9.7.9.4.
NB P-state specific training. For each NB P-state to D18F5x170[NbPstateMaxVal]:
A. Force the NB P-state. See 2.9.7.2.
B. MaxRdLatency training. See 2.9.7.9.5.1. Programs NBPx version.
Release NB P-state force.
Program DRAM phy for power savings. See 2.9.7.10.
Program DCT for normal operation. See 2.9.7.7.
The DRAM subsystem is ready for use.
2.9.7.1
Low Voltage DDR3
The processor supports JEDEC defined DDR3L and DDR3U devices which operate at voltages lower than
1.5V.
Platforms supporting low voltage devices should power up VDDIO at 1.35V. BIOS should not indefinitely
operate DIMMs at voltages higher than supported as indicated by SPD Byte 6: Module Nominal Voltage,
VDD.
BIOS should consult vendor data sheets for the supply voltage regulator programming requirements. On supported platforms, BIOS must take steps to configure the supply voltage regulators as follows:
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1. Read the SPD of all DIMMs within the programmable VDDIO domain and check all of the defined bits
within the SPD byte to determine the common operating voltages. (SPD Byte 6, Bits [2:0] indicate support
for 1.25V, 1.35V, 1.5V operation. Refer to the JEDEC specification).
2. Configure VDDIO to match the lowest common supported voltage based on the SPD values.
• If the DIMMs do not specify a common operating voltage then BIOS must take platform vendor defined
action to notify the end user of the mismatch and to protect DIMMs from damage. AMD suggests the
following possible actions: Configure VDDIO for 1.35V; configure all DIMMs to run at the lowest frequency supported by the DIMMs and the processor; configure 1.5V-only DIMMs with F2x[1,
0][5C:40][TestFail] bit set prior to sending MRS commands and exclude those DIMMs from the system
address map; notify the user of the mismatch. The vendor retains all responsibility for operating mismatched DIMMs.
3. Additional derating of the DDR speed may be necessary for reliable operation at lower voltage. See 2.9.2
[DCT Frequency Support].
2.9.7.2
NB P-state Specific Configuration
A subset of DCT configuration and training must be repeated for each enabled NB P-state. To accomplish this,
BIOS forces the processor to the desired NB P-state and releases the force once DRAM initialization and training is complete. See 2.5.4.1 [NB P-states] and 2.5.4.1.2.2 [NB P-state Transitions].
2.9.7.3
Memory P-state Specific Configuration
A subset of DCT configuration and training must be repeated for each enabled memory P-state. See also
2.5.7.1 [Memory P-states].
To accomplish this, BIOS forces the processor to the NBP0 state and uses the M0 context to train for values
that are used by all memory P-states. For example, BIOS uses D18F2x94_dct[0][MemClkFreq] to specify the
dram frequency during each pass of training. BIOS saves the trained configuration values at each step and uses
them appropriately as outlined below:
1. Force NB P-state to NBP0. See 2.9.7.2.
2. Program D18F1x10C[MemPsSel]=0. Force memory P-state DCT CSR access context to M0. See 2.9.3.
3. Program D18F2x9C_x0D04_E008_dct[0][PStateToAccess]=0. Force memory P-state PHY CSR access
context to M0.
4. Using the M0 context, BIOS optimally configures the controller and trains at DDR667 according to 2.9.7
steps 4 thru 7. Tcl, Trcd, Trp configured per best practices, etc.
A. BIOS saves the trained values for use in M1 and for subsequent higher frequencies.
B. BIOS saves the controller configuration for use in M1.
C. BIOS optimally writes all the values to registers in step 6. It may optionally write the values as each is
computed or trained. If this is done then BIOS must ensure that D18F1x10C[MemPsSel] and
D18F2x9C_x0D04_E008_dct[0][PStateToAccess] are configured correctly before and after each register access.
5. BIOS increases the frequency and repeats step 4 until the target frequency is trained. The target frequency
is always associated with M0.
6. BIOS programs the M1 controller context with the DDR667 configuration and trained results. This step
may optionally be performed after the first pass of step 4 above. This must be done before the next subsequent NB P-state change.
a. Program D18F1x10C[MemPsSel]=1.
b. Program D18F2x9C_x0D04_E008_dct[0][PStateToAccess] = 1.
c. Program D18F2x2E0_dct[0][M1MemClkFreq] and
D18F2x9C_x0D0F_E000_dct[0]_mp[1][Rate, FreqValid] = {04h, 1}. 667 MT/s
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d. Program DCT configuration and trained delay values saved earlier.
Three groups of registers must be written in the same order as the initialization sequence so h/w
correctly computes fence bits:
• Fence values: D18F2x9C_x0000_000C_dct[0], D18F2x9C_x0D0F_0[F,8:0]31_dct[0],
D18F2x9C_x0D0F_E019_dct[0].
• Address/Command timing delays: D18F2x9C_x0000_0004_dct[0]_mp[1:0].
• All other Data/Dqs delays: See step 6 in section 2.9.7.
e. Program D18F2x9C_x0D04_E008_dct[0][PStateToAccess] = 0.
f. Program D18F1x10C[MemPsSel] = 0.
2.9.7.4
DDR Phy Initialization
The BIOS initializes the phy and the internal interface from the DCT to the phy, including the PLLs and the
fence value, after each reset and for each time a MEMCLK frequency change is made.
BIOS obtains size, loading, and frequency information about the DIMMs and channels using SPDs prior to phy
initialization. BIOS then performs the following actions:
1. Program D18F2x9C_x0D0F_E013_dct[0] = 0118h.
2. For each byte lane and each memory P-state: Program
D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0][RxSsbMntClkEn] = 0.
3. Program D18F2xA8_dct[0][MemPhyPllPdMode] = 00b.
4. Force the phy to M0 with the following sequence.
A. Program D18F2x9C_x0D0F_E006_dct[0][PllLockTime] = 190h. Restore the default PLL lock time.
B. Program D18F2x9C_x0000_000B_dct[0] = 80800000h. ESR
C. Program D18F2x9C_x0000_000D18F2x9C_x0000_000B_dct[0] = 40000000h. PhyPSR. Note: BIOS
performs the sequence only on DCTs with an enabled interface (D18F2x94_dct[0][DisDramInterface]==0).
D. For each DCT: Program D18F2x9C_x0000_000B_dct[0] = 80000000h. XSR
5. Phy Voltage Level Programming. See 2.9.7.4.1.
6. DRAM channel frequency change. See 2.9.7.4.2.
7. Phy fence programming. See 2.9.7.4.3.
8. Phy compensation initialization. See 2.9.7.4.4.
2.9.7.4.1
Phy Voltage Level Programming
BIOS programs the following according to the desired phy VDDIO voltage level:
• Program D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0][RxVioLvl].
• Program D18F2x9C_x0D0F_[C,8,2][2:0]1F_dct[0][RxVioLvl].
• Program D18F2x9C_x0D0F_4009_dct[0][CmpVioLvl,ComparatorAdjust].
• Program D18F2x9C_x0D0F_4006_dct[0][VrefSel] = 0.
• Program D18F2x9C_x0D0F_4007_dct[0] per platform requirements.
See 2.9.7.1 [Low Voltage DDR3].
2.9.7.4.2
DRAM Channel Frequency Change
The following sequence is used to change the DRAM frequency under all boot conditions, including restoring
the DCT state when resuming from the S3 state. BIOS performs the sequence only on DCTs with an enabled
interface (D18F2x94_dct[0][DisDramInterface]==0):
For each DCT:
1. Program D18F2x9C_x0D0F_E006_dct[0][PllLockTime] = 190h. Restore the default PLL lock time.
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2. Program D18F2x94_dct[0][MemClkFreqVal] = 0.
3. Program D18F2x94_dct[0][MemClkFreq] to the desired DRAM frequency.
4. Program the following parameters which must be configured prior to setting MemClkFreqVal:
• D18F2x94_dct[0][ProcOdtDis]
• D18F2x9C_x0000_0004_dct[0]_mp[1:0]
• D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0][ProcOdtAdv]
• D18F2x210_dct[0]_nbp[3:0][RdPtrInit, DataTxFifoWrDly] of the current NB P-state for the target
MEMCLK frequency. See also 2.9.7.2.
• IF (target DdrRate >= 1600) D18F2x9C_x0D0F_0[F,8:0]38_dct[0][ReducedLoop] = 10b ENDIF.
For each DCT:
5. Program D18F2x94_dct[0][MemClkFreqVal] = 1. Wait for D18F2x94_dct[0][FreqChgInProg] = 0.
For each DCT:
6. Program D18F2x9C_x0D0F_E006_dct[0][PllLockTime] according to Table 25.
BIOS must observe the following requirements:
• BIOS must not change the PLL frequency after DRAM has exited from self-refresh.
• BIOS must not change the PLL frequency after the DRAM training for DDR3 DIMMs is complete.
Table 25: DDR PLL Lock Time
D18F2xA8_dct[0][MemPhyPllPdMode]
00b
10b
2.9.7.4.2.1
PllLockTime
0Fh
190h
Requirements for DRAM Frequency Change During Training
During DRAM training, BIOS may be required to change the DRAM(MEMCLK) frequency. The steps below
describe what is required to prepare the processor and memory subsystem for the new MEMCLK frequency. It
is assumed that the memory subsystem has previously been initialized at the current MEMCLK frequency, and
this procedure describes only the steps that must be repeated at the new MEMCLK frequency. See 2.9.7.9.1
[Write Levelization Training] and 2.9.7.9.2 [DQS Receiver Enable Training].
1. Force the NB P-state. See 2.9.7.2.
2. Enter self-refresh:
A. Program D18F2x90_dct[0][DisDllShutdownSR] = 1.
B. Program D18F2x90_dct[0][EnterSelfRef] = 1.
C. Wait for D18F2x90_dct[0][EnterSelfRef] = 0.
3. DRAM channel frequency change. See 2.9.7.4.2.
4. Change NCLK frequency to meet NCLK-MEMCLK ratio requirements. See 2.5.3.1.5.
5. Phy fence programming. See 2.9.7.4.3.
6. Phy compensation initialization. See 2.9.7.4.4.
7. Program SPD configuration. See 2.9.7.5. Re-program frequency dependent parameters according to the
new frequency (Twr, Tcwl, Tcl, etc.).
8. Program Non-SPD configuration. See 2.9.7.6. Re-program frequency dependent parameters according to
the new frequency (ODT, addr/cmd timings, etc.).
9. Exit self-refresh:
A. Program D18F2x90_dct[0][ExitSelfRef] = 1.
B. Wait for D18F2x90_dct[0][ExitSelfRef] = 0.
C. Program D18F2x90_dct[0][DisDllShutdownSR] = 0.
10. Re-program devices with frequency dependent mode register field values. See 2.9.7.8. (Twr, Tcwl, Tcl,
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etc.).
2.9.7.4.3
Phy Fence Programming
The DDR phy fence logic is used to adjust the phase relationship between the data fifo and the data going to the
pad. After any MEMCLK frequency change and before any memory training, BIOS must perform phy fence
training for each channel using the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Program D18F2x9C_x0D0F_0[F,8:0]31_dct[0] = 0000_0000h.
Program D18F2x9C_x0D0F_E019_dct[0] = 0000_0000h.
Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][FenceTrSel]=10b.
Program D18F2x9C_x0000_00[52:50]_dct[0]=1313_1313h.
Perform phy fence training. See 2.9.7.4.3.1 [Phy Fence Training].
Write the calculated fence value to D18F2x9C_x0000_000C_dct[0][FenceThresholdTxDll].
Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][FenceTrSel]=01b.
Program D18F2x9C_x0000_00[52:50]_dct[0]=1313_1313h.
Perform phy fence training. See 2.9.7.4.3.1 [Phy Fence Training].
Write the calculated fence value to D18F2x9C_x0000_000C_dct[0][FenceThresholdRxDll].
Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][FenceTrSel]=11b.
Program D18F2x9C_x0000_00[52:50]_dct[0]=1313_1313h.
Perform phy fence training. See 2.9.7.4.3.1 [Phy Fence Training].
Write the calculated fence value to D18F2x9C_x0000_000C_dct[0][FenceThresholdTxPad].
Program Fence2 threshold for data as follows:
A. IF (D18F2x9C_x0000_000C_dct[0][FenceThresholdTxPad] < 16) THEN
Fence2_TxPad[4:0] = {1b, D18F2x9C_x0000_000C_dct[0][19:16]}
ELSE
Fence2_TxPad[4:0] = 00000b
ENDIF.
B. IF (D18F2x9C_x0000_000C_dct[0][FenceThresholdRxDll] < 16) THEN
Fence2_RxDll[4:0] = {1b, D18F2x9C_x0000_000C_dct[0][24:21]}
ELSE
Fence2_RxDll[4:0] = 00000b
ENDIF.
C. IF (D18F2x9C_x0000_000C_dct[0][FenceThresholdTxDll] < 16) THEN
Fence2_TxDll[4:0] = {1b, D18F2x9C_x0000_000C_dct[0][29:26]}
ELSE
Fence2_TxDll[4:0] = 00000b
ENDIF.
D. Program D18F2x9C_x0D0F_0[F,8:0]31_dct[0] = {000000b, Fence2_TxDll[4:0],
Fence2_TxPad[4:0]}.
E. Program D18F2x9C_x0D0F_E019_dct[0] = {0b, Fence2_RxDll[4:0], 00000b, Fence2_TxPad[4:0]}.
16. Reprogram D18F2x9C_x0000_0004_dct[0]_mp[1:0]. This forces the phy to recompute the fence.
When resuming from S3, BIOS reprograms D18F2x9C_x0000_000C_dct[0][FenceThresholdTxDll, FenceThresholdRxDll, FenceThresholdTxPad], and D18F2x9C_x0D0F_E019_dct[0] from values stored in non-volatile storage instead of training. BIOS reprograms D18F2x9C_x0D0F_0[F,8:0]31_dct[0] and
D18F2x9C_x0D0F_E019_dct[0] as indicated in the steps above.
BIOS may use D18F2x9C_x0000_000C_dct[0] and D18F2x9C_x0D0F_E01A_dct[0] for local storage of
fence values during the intermediate time between training and writing the values into non-volatile storage in
preparation for S3.
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Phy Fence Training
1. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][PhyFenceTrEn]=1. The PRE tracks phase sign using
coarse delay bits. For all lanes, the Tx insertion delay, the phase between PCLK and the DLL output clock,
is greater than 0 and less then 1 UI; therefore a seed value is not necessary.
2. Wait 2000 MEMCLKs.
3. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][PhyFenceTrEn]=0.
4. Read the phase recovery engine registers D18F2x9C_x0000_00[52:50]_dct[0].
5. Calculate the average of the fine delay values of all byte lanes. If FenceTrSel != 00b subtract 8. If the result
is negative then the fence value is zero.
2.9.7.4.4
Phy Compensation Initialization
Each DDR IO driver has a programmable slew rate controlled by the pre-driver calibration code. The recommended slew rate is a function of the DC drive strength. BIOS initializes the recommended nominal slew rate
values as follows:
1. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][DisAutoComp] = 1.
2. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][DisablePredriverCal]=1.
3. Program TxPreP/TxPreN for Data and DQS according to Table 26, Table 27, or Table 28.
A. Program D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0]={0000b, TxPreP, TxPreN}.
B. Program D18F2x9C_x0D0F_0[F,8:0]02_dct[0]={1000b, TxPreP, TxPreN}.
4. Program TxPreP/TxPreN for Cmd/Addr according to Table 29, Table 30, or Table 31.
A. Program D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0]={0000b, TxPreP, TxPreN}.
B. Program D18F2x9C_x0D0F_[C,8][1:0]02_dct[0]={1000b, TxPreP, TxPreN}.
5. Program TxPreP/TxPreN for Clock according to Table 32, Table 33, or Table 34.
A. Program D18F2x9C_x0D0F_2[2:0]02_dct[0]={1000b, TxPreP, TxPreN}.
6. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][DisAutoComp] = 0.
Table 26: Phy predriver calibration codes for Data/DQS at 1.5V
DDR Rate
667 - 2133
Drive Strength1
000b
{TxPreP, TxPreN}2
FFFh
001b
410h
010b
208h
011b
104h
1. IF (D18F2x9C_x0D0F_0[F,8:0]06) THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][DqsDrvStren]
ELSE
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][DataDrvStren]
ENDIF.
2. See D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0] and D18F2x9C_x0D0F_0[F,8:0]02_dct[0].
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Table 27: Phy predriver calibration codes for Data/DQS at 1.35V
DDR Rate
667 - 2133
Drive Strength1
000b
{TxPreP, TxPreN}2
FFFh
001b
FFFh
010b
820h
011b
410h
1. IF (D18F2x9C_x0D0F_0[F,8:0]06) THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][DqsDrvStren]
ELSE
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][DataDrvStren]
ENDIF.
2. See D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0] and D18F2x9C_x0D0F_0[F,8:0]02_dct[0].
Table 28: Phy Predriver Calibration Codes for Data/DQS at 1.25V
DDR Rate
667 - 2133
Drive Strength1
000b
{TxPreP, TxPreN}2
FFFh
001b
FFFh
010b
FFFh
011b
FFFh
1. IF (D18F2x9C_x0D0F_0[F,8:0]06) THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][DqsDrvStren]
ELSE
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][DataDrvStren]
ENDIF.
2. See D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0] and D18F2x9C_x0D0F_0[F,8:0]02_dct[0].
Table 29: Phy predriver calibration codes for Cmd/Addr at 1.5V
DDR Rate
667 - 2133
Drive Strength1
101b
{TxPreP, TxPreN}2
000b
082h
001b
010b
011b
041h
041h
041h
0C3h
1. IF (D18F2x9C_x0D0F_C002) THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][CkeDrvStren]
ELSEIF (D18F2x9C_x0D0F_800[A,6,2]) THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][CsOdtDrvStren]
ELSE
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][AddrCmdDrvStren]
ENDIF.
2. See D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0] and D18F2x9C_x0D0F_[C,8][1:0]02_dct[0].
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Table 30: Phy predriver calibration codes for Cmd/Addr at 1.35V
DDR Rate
667 - 2133
Drive Strength1
101b
{TxPreP, TxPreN}2
000b
186h
001b
010b
011b
104h
0C3h
082h
208h
1. IF (D18F2x9C_x0D0F_C002)THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][CkeDrvStren]
ELSEIF (D18F2x9C_x0D0F_800[A,6,2])THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][CsOdtDrvStren]
ELSE
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][AddrCmdDrvStren]
ENDIF.
2. See D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0] and D18F2x9C_x0D0F_[C,8][1:0]02_dct[0].
Table 31: Phy Predriver Calibration Codes for Cmd/Addr at 1.25V
DDR Rate
667- 2133
Drive Strength1
101b
{TxPreP, TxPreN}2
000b
30Ch
001b
28Ah
010b
208h
011b
186h
410h
1. IF (D18F2x9C_x0D0F_C002)THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][CkeDrvStren]
ELSEIF (D18F2x9C_x0D0F_800[A,6,2])THEN
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][CsOdtDrvStren]
ELSE
See D18F2x9C_x0000_0000_dct[0]_mp[1:0][AddrCmdDrvStren]
ENDIF.
2. See D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0] and D18F2x9C_x0D0F_[C,8][1:0]02_dct[0].
Table 32: Phy predriver calibration codes for Clock at 1.5V
DDR Rate
667 - 2133
Drive Strength1
101b
{TxPreP, TxPreN}2
000b
FFFh
001b
010b
011b
1. See D18F2x9C_x0000_0000_dct[0]_mp[1:0][ClkDrvStren].
2. See D18F2x9C_x0D0F_2[2:0]02_dct[0].
FFFh
FFFh
FFFh
820h
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Table 33: Phy predriver calibration codes for Clock at 1.35V
DDR Rate
667 - 2133
Drive Strength1
101b
{TxPreP, TxPreN}2
000b
FFFh
001b
010b
FFFh
FFFh
011b
FFFh
FFFh
1. See D18F2x9C_x0000_0000_dct[0]_mp[1:0][ClkDrvStren].
2. See D18F2x9C_x0D0F_2[2:0]02_dct[0].
Table 34: Phy Predriver Calibration Codes for Clock at 1.25V
DDR Rate
667 - 2133
Drive Strength1
101b
{TxPreP, TxPreN}2
000b
FFFh
001b
010b
011b
1. See D18F2x9C_x0000_0000_dct[0]_mp[1:0][ClkDrvStren].
2. See D18F2x9C_x0D0F_2[2:0]02_dct[0].
2.9.7.5
FFFh
FFFh
FFFh
FFFh
SPD ROM-Based Configuration
The Serial Presence Detect (SPD) ROM is a non-volatile memory device on the DIMM encoded by the DIMM
manufacturer. The description of the SPD is usually provided on a data sheet for the DIMM itself along with
data describing the memory devices used. The data describes configuration and speed characteristics of the
DIMM and the SDRAM components mounted on the DIMM. The associated data sheet also contains the
DIMM byte values that are encoded in the SPD on the DIMM.
BIOS reads the values encoded in the SPD ROM through a system-specific interface. BIOS acquires DIMM
configuration information, such as the amount of memory on each DIMM, from the SPD ROM on each DIMM
and uses this information to program the DRAM controller registers.
For solder-down DRAM, in the absence of an SPD ROM, BIOS provides the information necessary for
DRAM configuration. For convenience, this document may refer to solder-down DRAM as a DIMM, and to
DRAM data sheet or JEDEC DRAM specifications as SPD ROM based, unless otherwise noted.
The SPD ROM provides values for several DRAM timing parameters that are required by the DCT. In general,
BIOS should use the optimal value specified by the SPD ROM. These parameters are:
•
•
•
•
•
•
D18F2x8C_dct[0][Tref]: See SPD Byte 31: SDRAM Thermal and Refresh Options
D18F2x200_dct[0]_mp[1:0][Tras]: Active to precharge time
D18F2x200_dct[0]_mp[1:0][Trp]: Precharge time
D18F2x200_dct[0]_mp[1:0][Trcd]: RAS to CAS delay
D18F2x200_dct[0]_mp[1:0][Tcl]: CAS latency
D18F2x204_dct[0]_mp[1:0][Trtp]: Internal read to precharge command delay time
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•
•
•
•
•
•
BKDG for AMD Family 16h Models 00h-0Fh Processors
D18F2x204_dct[0]_mp[1:0][FourActWindow]: Four activate window delay time
D18F2x204_dct[0]_mp[1:0][Trrd]: Row active to row active delay
D18F2x204_dct[0]_mp[1:0][Trc]: Active to active/refresh time
D18F2x208_dct[0][Trfc3, Trfc2, Trfc1, Trfc0]: Refresh recovery delay time
D18F2x20C_dct[0]_mp[1:0][Twtr]: Internal write to read command delay time
D18F2x22C_dct[0]_mp[1:0][Twr]: Write recovery time
Optimal cycle time is specified for each DIMM and is used to limit or determine bus frequency. See 2.9.7.8
[DRAM Device and Controller Initialization].
The DRAM data sheet or the JEDEC DRAM specification provides values for some DRAM timing parameters
that are required by the DCT, regardless of whether the DRAMs are solder-down. Most of these parameters
have a fixed time component as part of their specification. If memory P-states are supported (See 2.5.7.1
[Memory P-states]) and a timing register does not have per memory P-state contexts, BIOS must evaluate the
minimum value for each frequency and choose the most pessimistic value for all frequencies to program into
the register. These parameters are:
•
•
•
•
•
•
•
•
•
•
•
D18F2x20C_dct[0]_mp[1:0][Tcwl]: CAS write latency
D18F2x220_dct[0][Tmrd]: MRS command cycle time
D18F2x220_dct[0][Tmod]: MRS command recovery time
D18F2x224_dct[0][Tzqcs]: Short calibration command recovery time
D18F2x224_dct[0][Tzqoper]: Long calibration command recovery time
D18F2x248_dct[0]_mp[1:0][Txpdll]: Exit precharge power down (with DLL frozen) to command delay.
D18F2x248_dct[0]_mp[1:0][Txp]: Exit precharge power down to command delay.
D18F2x24C_dct[0][Tcksrx]: Clock stable to self refresh exit delay
D18F2x24C_dct[0][Tcksre]: Self refresh entry to clock removal delay
D18F2x24C_dct[0][Tckesr]: Self refresh entry to command delay
D18F2x24C_dct[0][Tpd]: Power down entry to exit delay. BIOS may increase this value above the JEDEC
minimum for certain power down modes.
2.9.7.6
Non-SPD ROM-Based Configuration
There are several DRAM timing parameters and DCT configurations that need to be programmed for optimal
memory performance. These values are not derived from the SPD ROM. Several of these timing parameters
are functions of other configuration values. These interdependencies must be considered when programming
values into several DCT register timing fields. The factors to consider when specifying a value for a specific
non-SPD timing parameter are:
• Training delay values. See 2.9.7.9 [DRAM Training].
• Read and write latency differences.
• The phy's idle clock requirements on the data bus.
• DDR3 ODT timing requirements.
• NCLK frequency
• MEMCLK frequency
The following sub-sections describe how BIOS programs each non-SPD related timing field to a recommended
minimum timing value with respect to the above factors.
The following terms are defined to simplify calculations and are calculated in MEMCLKs:
• Latency Difference (LD) = D18F2x200_dct[0]_mp[1:0][Tcl] - D18F2x20C_dct[0]_mp[1:0][Tcwl].
• These equations assume D18F2x200_dct[0]_mp[1:0][Tcl] >= D18F2x20C_dct[0]_mp[1:0][Tcwl].
• Read ODT Delay (ROD) = MAX(0, D18F2x240_dct[0]_mp[1:0][RdOdtOnDuration] - 6).
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• Write ODT Delay (WOD) = MAX(0, D18F2x240_dct[0]_mp[1:0][WrOdtOnDuration] - 6).
• WrEarly =ABS(D18F2x20C_dct[0]_mp[1:0][WrDqDqsEarly]) /2
2.9.7.6.1
TrdrdSdSc, TrdrdSdDc, and TrdrdDd (Read to Read Timing)
The optimal values for D18F2x218_dct[0]_mp[1:0][TrdrdSdSc, TrdrdSdDc, TrdrdDd] are platform and configuration specific and should be characterized for best performance. Prior to DRAM training, BIOS should
program these parameters to the largest defined value. After DRAM training, BIOS should use the guidelines
below to configure the recommended platform generic timing values:
• TrdrdSdSc (in MEMCLKs) = 1.
• TrdrdSdDc (in MEMCLKs) = MAX(TrdrdSdSc, 3 + (IF (D18F2xA8_dct[0][PerRankTimingEn]) THEN
CEIL(CDDTrdrdSdDc / 2 + 0.5) ELSE 0 ENDIF)).
• TrdrdDd (in MEMCLKs) = MAX(TrdrdSdDc, ROD + 3, CEIL(CDDTrdrdDd/2 + 3.5)).
The Critical Delay Difference (CDD) is the largest delay difference of the channel.
• Each delay difference is D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay] minus
D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay].
• For CDDTrdrdSdDc, the subtraction terms are the delays of different chip selects within the same DIMM
within the same byte lane.
• For CDDTrdrdDd, the subtraction terms are the delays of different DIMMs within the same byte lane.
2.9.7.6.2
TwrwrSdSc, TwrwrSdDc, TwrwrDd (Write to Write Timing)
The optimal values for D18F2x214_dct[0]_mp[1:0][TwrwrSdSc, TwrwrSdDc, TwrwrDd] are platform and
configuration specific and should be characterized for best performance. Prior to DRAM training, BIOS should
program these parameters to the largest defined value. After DRAM training, BIOS should use the guidelines
below to configure the recommended platform generic timing values:
• TwrwrSdSc (in MEMCLKs) = 1.
• TwrwrSdDc (in MEMCLKs) = MAX(TwrwrSdSc, WOD + 3, 3 + (IF (D18F2xA8_dct[0][PerRankTimingEn]) THEN CEIL(CDDTwrwrSdDc / 2 + 0.5) ELSE 0 ENDIF)).
• TwrwrDd (in MEMCLKs) = MAX(TwrwrSdDc, WOD + 3, CEIL(CDDTwrwrDd / 2 + 3.5)).
The Critical Delay Difference (CDD) is the largest delay difference of the channel.
• Each delay difference is D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][WrDqsGrossDly] minus
D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][WrDqsGrossDly].
• For CDDTwrwrSdDc, the subtraction terms are the delays of different chip selects within the same DIMM
within the same byte lane.
• For CDDTwrwrDd, the subtraction terms are the delays of different DIMMs within the same byte lane.
2.9.7.6.3
Twrrd (Write to Read DIMM Termination Turn-around)
The optimal value for D18F2x218_dct[0]_mp[1:0][Twrrd] is platform and configuration specific and should be
characterized for best performance. Prior to DRAM training, BIOS should program these parameters to the
largest defined value. After DRAM training, BIOS should use the guidelines below to configure the recommended platform generic timing values:
• Twrrd (in MEMCLKs) = MAX(1, MAX(WOD, CEIL(CDDTwrrd / 2 + 2 - WrEarly)) - LD + 3).
The Critical Delay Difference (CDD) is the largest delay difference of the channel.
• Each delay difference is D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][WrDqsGrossDly] minus
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D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay].
• For CDDTwrrd, the subtraction terms are the delays of different chip selects within the same byte lane.
2.9.7.6.4
TrwtTO (Read-to-Write Turnaround for Data, DQS Contention)
The optimal value for D18F2x21C_dct[0]_mp[1:0][TrwtTO] is platform and configuration specific and should
be characterized for best performance. Prior to DRAM training, BIOS should program this parameter to the
largest defined value. After DRAM training, BIOS should use the guidelines below to configure the recommended platform generic timing values after DDR training is complete:
• TrwtTO (in MEMCLKs) = MAX(ROD, CEIL(CDDTrwtTO / 2 + WrEarly)) + LD + 3.
• If 1 DIMM/ch, substitute ROD = 0 in the above equation. Assumes no DIMM ODT switching
occurs.
The Critical Delay Difference (CDD) is the largest delay difference of the channel.
• Each delay difference is D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay] minus
D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][WrDqsGrossDly].
• For CDDTrwtTO, the subtraction terms are the delays of all chip selects within the same byte lane.
2.9.7.6.5
DRAM ODT Control
BIOS configures the DIMM ODT behavior per chip select according to the DIMM population. The ODT pin
patterns for reads and writes are programmed using D18F2x[234:230]_dct[0] and D18F2x[23C:238]_dct[0],
respectively.
BIOS also configures the ODT pin pattern used during write leveling by programming
D18F2x9C_x0000_0008_dct[0]_mp[1:0][WrLvOdtEn, WrLvOdt]. BIOS programs WrLvOdt with the
D18F2x[23C:238]_dct[0] value provided for writes to the rank targeted by training. See 2.9.7.9.1 [Write Levelization Training].
Table 35: DDR3 ODT Pattern NumDimmSlots=1
D18F2x[234:230]_dct[0]
D18F2x[23C:238]_dct[0]
D18F2x234
D18F2x230
D18F2x23C
D18F2x238
SR
0000_0000h
0000_0000h
0000_0000h
0000_0001h
DR
0000_0000h
0000_0000h
0000_0000h
0000_0201h
1. DIMM0: BP_MEMCSx[1:0], BP_MEMODTx[1,0].
DIMM01
Table 36: DDR3 ODT Pattern NumDimmSlots=2
D18F2x[234:230]_dct[0]
D18F2x234
D18F2x230
SR
0000_0000h
0000_0000h
DR
0000_0000h
0000_0000h
SR/DR SR/DR
0000_0000h
0101_0404h
1. DIMM0: BP_MEMCSx[1:0], BP_MEMODTx[1,0].
DIMM1: BP_MEMCSx[3:2], BP_MEMODTx[3,2].
DIMM01 DIMM11
D18F2x[23C:238]_dct[0]
D18F2x23C
D18F2x238
0000_0000h
0004_0000h
0000_0000h
0804_0000h
0000_0000h
0905_0605h
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DRAM ODT Configuration
These tables document the optimal settings for motherboards which meet the relevant AMD motherboard
design guidelines. See 2.9.2 [DCT Frequency Support] for an overview of the DIMM population and memory
bus speed support.
Table 37: BIOS recommendations for MR1[RttNom] and MR2[RttWr] UDIMM FT3 package
Condition
DdrRate
NumDimmSlots
VDDIO
1
1
2
2
2
2
2
667, 800, 1066
1333, 1600, 1866
667, 800, 1066
667, 800
1066, 1333
1333, 1600, 1866
1600
1.5
1.5
1.5
1.5
1.5
1.5
1.5
DIMM0
SR, DR
SR, DR
NP
SR, DR
SR, DR
NP
SR, DR
MR1
RttNom
DIMM1
SR, DR
SR, DR
SR, DR
SR, DR
SR, DR
010b
001b
010b
011b
101b
001b
100b
MR2
RttWr
00b
00b
00b
10b
10b
00b
01b
Table 38: BIOS recommendations for MR1[RttNom] and MR2[RttWr] SODIMM FT3 package
Condition
NumDimmSlots
DdrRate
VDDIO
DIMM0
DIMM1
MR1
MR2
RttNom
RttWr
1 667, 800, 1066
1.5, 1.35, 1.25
SR, DR
-
010b
00b
1 1333
1.5, 1.35, 1.25
SR, DR
-
001b
00b
1 1600
1.5, 1.35
SR, DR
-
001b
00b
2 667, 800, 1066
1.5, 1.35, 1.25
NP
SR, DR
010b
00b
2 667, 800
1.5, 1.35, 1.25
SR, DR
SR, DR
011b
10b
2 1066, 1333
1.5, 1.35, 1.25
SR, DR
SR, DR
101b
10b
2 1333
1.5, 1.35, 1.25
NP
SR, DR
001b
00b
2 1600
1.5, 1.35
NP
SR, DR
001b
00b
2 1600
1.5
SR, DR
SR, DR
100b
01b
2 1600
1.35
SR
SR
100b
01b
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Table 39: BIOS recommendations for MR1[RttNom] and MR2[RttWr] SODIMM plus Solder-down DRAM
FT3 package
Condition
NumDimmSlots
DdrRate
VDDIO
DIMM0
DIMM1
MR1
MR2
RttNom
RttWr
2 667, 800, 1066
1.5, 1.35, 1.25
NP
SR, DR
010b
00b
2 667, 800
1.5, 1.35, 1.25
SR, DR
SR, DR
011b
10b
2 1066
1.5, 1.35, 1.25
SR, DR
SR, DR
101b
10b
2 1333
1.5, 1.35
NP
SR, DR
001b
00b
2 1333
1.5
SR, DR
SR, DR
101b
10b
2 1333
1.35
SR
SR
101b
10b
Table 40: BIOS recommendations for MR1[RttNom] and MR2[RttWr] Solder-down DRAM FT3 package
Condition
NumDimmSlots
DdrRate
VDDIO
DIMM0
MR1
MR2
RttNom
RttWr
1 667
1.5, 1.35, 1.25
SR, DR
000b
00b
1 800, 1066
1.5, 1.35, 1.25
SR, DR
010b
00b
1 1333
1.5, 1.35, 1.25
SR, DR
001b
00b
1 1600
1.5, 1.35
SR, DR
001b
00b
1 1866
1.5
SR, DR
001b
00b
Table 41: BIOS recommendations for MR1[RttNom] and MR2[RttWr] UDIMM FS1b package
NumDimmSlots
Condition
DdrRate
1
1
2
2
667, 800, 1066
1333, 1600
667, 800, 1066
667, 800
VDDIO
1.5, 1.35, 1.25
1.5, 1.35, 1.25
1.5, 1.35, 1.25
1.5, 1.35, 1.25
DIMM0
SR, DR
SR, DR
NP
SR, DR
MR1
RttNom
DIMM1
SR, DR
SR, DR
010b
001b
010b
011b
MR2
RttWr
00b
00b
00b
10b
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Table 41: BIOS recommendations for MR1[RttNom] and MR2[RttWr] UDIMM FS1b package
NumDimmSlots
Condition
DdrRate
2 1066, 1333
2 1333, 1600
2 1600
2.9.7.6.6
VDDIO
1.5, 1.35, 1.25
1.5, 1.35, 1.25
1.5, 1.35
DIMM0
SR, DR
NP
SR, DR
MR1
RttNom
DIMM1
SR, DR
SR, DR
SR, DR
101b
001b
100b
MR2
RttWr
10b
00b
01b
DRAM Address Timing and Output Driver Compensation Control
This section describes the settings required for programming the timing on the address pins, the CS/ODT pins,
and the CKE pins. The following tables document the address timing and output driver settings on a per channel basis for DDR3. These tables document the optimal settings for motherboards which meet the relevant
AMD socket motherboard design guidelines. See 2.9.2 [DCT Frequency Support] for an overview of the
DIMM and memory bus speed support.
When POdtOff=0, in all cases the processor ODT is off for writes and is on for reads.
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Table 42: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver
Control UDIMM FT3 package
DIMM0
DIMM1
D18F2x9C_x0000_0000_dct[0]_mp[1:0]
VDDIO
D18F2x9C_x0000_0004_dct[0]_mp[1:0]
NumDimmSlots
DdrRate
D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0]
POdtOff
D18F2x94_dct[0]
SlowAccessMode
Condition
1 667, 800 1.5
SR, DR
-
0 0 00000000h
00002222h
1 1066
1.5
SR
-
0 0 003D3D3Dh
10002222h
1 1066
1.5
DR
-
0 0 00000000h
10002222h
1 1333
1.5
SR
-
0 0 003D3D3Dh
20112222h
1 1333
1.5
DR
-
0 0 00003D3Dh
20112222h
1 1600,
1866
1.5
SR
-
0 0 003C3C3Ch
30332222h
1 1600,
1866
1.5
DR
-
1 0 00003C3Ch
30332222h
2 667, 800 1.5
NP
SR, DR
0 0 00000000h
00002222h
2 667
1.5
SR, DR
SR, DR
1 0 00000000h
10222323h
2 800
1.5
SR, DR
SR, DR
1 0 00000000h
20222323h
2 1066
1.5
NP
SR
0 0 003D3D3Dh
10002222h
2 1066
1.5
NP
DR
0 0 00000000h
10002222h
2 1066,
1333,
1600
1.5
SR, DR
SR, DR
1 0 00000000h
30222323h
2 1333
1.5
NP
SR
0 0 003D3D3Dh
20112222h
2 1333
1.5
NP
DR
0 0 00003D3Dh
20112222h
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Table 42: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver
Control UDIMM FT3 package
DIMM0
DIMM1
D18F2x9C_x0000_0000_dct[0]_mp[1:0]
VDDIO
D18F2x9C_x0000_0004_dct[0]_mp[1:0]
NumDimmSlots
DdrRate
D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0]
POdtOff
D18F2x94_dct[0]
SlowAccessMode
Condition
2 1600,
1866
1.5
NP
SR
0 0 003C3C3Ch
30332222h
2 1600,
1866
1.5
NP
DR
1 0 00003C3Ch
30332222h
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Table 43: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver
Control SODIMM FT3 package
DIMM0
DIMM1
D18F2x9C_x0000_0000_dct[0]_mp[1:0]
VDDIO
D18F2x9C_x0000_0004_dct[0]_mp[1:0]
NumDimmSlots
DdrRate
D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0]
POdtOff
D18F2x94_dct[0]
SlowAccessMode
Condition
1 667, 800 1.5, 1.35, 1.25
SR, DR
-
0 0 00000000h
00002222h
1 1066
1.5, 1.35, 1.25
SR
-
0 0 003D3D3Dh
10002222h
1 1066
1.5, 1.35, 1.25
DR
-
0 0 00000000h
10002222h
1 1333
1.5, 1.35, 1.25
SR
-
0 0 003D3D3Dh
20112222h
1 1333
1.5, 1.35, 1.25
DR
-
0 0 00003D3Dh
20112222h
1 1600
1.5, 1.35
SR
-
0 0 003C3C3Ch
30332222h
1 1600
1.5, 1.35
DR
-
1 0 00003C3Ch
30332222h
2 667, 800 1.5, 1.35, 1.25
NP
SR, DR
0 0 00000000h
00002222h
2 667
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
10222323h
2 800
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
20222323h
2 1066
1.5, 1.35, 1.25
NP
SR
0 0 003D3D3Dh
10002222h
2 1066
1.5, 1.35, 1.25
NP
DR
0 0 00000000h
10002222h
2 1066,
1333
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
30222323h
2 1333
1.5, 1.35, 1.25
NP
SR
0 0 003D3D3Dh
20112222h
2 1333
1.5, 1.35, 1.25
NP
DR
0 0 00003D3Dh
20112222h
2 1600
1.5, 1.35
NP
SR
0 0 003C3C3Ch
30332222h
2 1600
1.5, 1.35
NP
DR
1 0 00003C3Ch
30332222h
2 1600
1.5
SR, DR
SR, DR
1 0 00000000h
30222323h
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Table 43: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver
Control SODIMM FT3 package
1.35
DIMM0
SR
DIMM1
SR
1 0 00000000h
D18F2x9C_x0000_0000_dct[0]_mp[1:0]
2 1600
VDDIO
D18F2x9C_x0000_0004_dct[0]_mp[1:0]
NumDimmSlots
DdrRate
D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0]
POdtOff
D18F2x94_dct[0]
SlowAccessMode
Condition
30222323h
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Table 44: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver
Control SODIMM plus Solder-down DRAM FT3 package
DIMM0
DIMM1
D18F2x9C_x0000_0000_dct[0]_mp[1:0]
VDDIO
D18F2x9C_x0000_0004_dct[0]_mp[1:0]
NumDimmSlots
DdrRate
D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0]
POdtOff
D18F2x94_dct[0]
SlowAccessMode
Condition
2 667, 800 1.5, 1.35, 1.25
NP
SR, DR
0 0 00000000h
00002222h
2 667
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
10222323h
2 800
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
20222323h
2 1066
1.5, 1.35, 1.25
NP
SR
0 0 003D3D3Dh
10002222h
2 1066
1.5, 1.35, 1.25
NP
DR
0 0 00000000h
10002222h
2 1066
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
30222323h
2 1333
1.5, 1.35
NP
SR
0 0 003D3D3Dh
20112222h
2 1333
1.5, 1.35
NP
DR
0 0 00003D3Dh
20112222h
2 1333
1.5
SR, DR
SR, DR
1 0 00000000h
30222323h
2 1333
1.35
SR
SR
1 0 00000000h
30222323h
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Table 45: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver
Control Solder-down DRAM FT3 package
DIMM0
D18F2x9C_x0000_0000_dct[0]_mp[1:0]
VDDIO
D18F2x9C_x0000_0004_dct[0]_mp[1:0]
NumDimmSlots
DdrRate
D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0]
POdtOff
D18F2x94_dct[0]
SlowAccessMode
Condition
1 667
1.5, 1.35, 1.25
SR, DR
0 1 00000000h
00000000h
1 800
1.5, 1.35, 1.25
SR, DR
0 0 00000000h
00000000h
1 1066
1.5, 1.35, 1.25
SR
0 0 003D3D3Dh
10000000h
1 1066
1.5, 1.35, 1.25
DR
0 0 00000000h
10000000h
1 1333
1.5, 1.35, 1.25
SR
0 0 003D3D3Dh
20000000h
1 1333
1.5, 1.35, 1.25
DR
0 0 00003D3Dh
20110000h
1 1600
1.5, 1.35
SR
0 0 003C3C3Ch
30110000h
1 1600
1.5, 1.35
DR
1 0 00003C3Ch
30110000h
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Table 46: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver
Control UDIMM FS1b package
DIMM0
DIMM1
D18F2x9C_x0000_0000_dct[0]_mp[1:0]
VDDIO
D18F2x9C_x0000_0004_dct[0]_mp[1:0]
NumDimmSlots
DdrRate
D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0]
POdtOff
D18F2x94_dct[0]
SlowAccessMode
Condition
1 667, 800 1.5, 1.35, 1.25
SR, DR
-
0 0 00000000h
00002222h
1 1066
1.5, 1.35, 1.25
SR
-
0 0 003D3D3Dh
10002222h
1 1066
1.5, 1.35, 1.25
DR
-
0 0 00000000h
10002222h
1 1333
1.5, 1.35, 1.25
SR
-
0 0 003D3D3Dh
20112222h
1 1333
1.5, 1.35, 1.25
DR
-
0 0 00003D3Dh
20112222h
1 1600
1.5, 1.35, 1.25
SR
-
0 0 003C3C3Ch
30332222h
1 1600
1.5, 1.35, 1.25
DR
-
1 0 00003C3Ch
30332222h
2 667, 800 1.5, 1.35, 1.25
NP
SR, DR
0 0 00000000h
00002222h
2 667
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
10222323h
2 800
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
20222323h
2 1066
1.5, 1.35, 1.25
NP
SR
0 0 003D3D3Dh
10002222h
2 1066
1.5, 1.35, 1.25
NP
DR
0 0 00000000h
10002222h
2 1066,
1333
1.5, 1.35, 1.25
SR, DR
SR, DR
1 0 00000000h
30222323h
2 1333
1.5, 1.35, 1.25
NP
SR
0 0 003D3D3Dh
20112222h
2 1333
1.5, 1.35, 1.25
NP
DR
0 0 00003D3Dh
20112222h
2 1600
1.5, 1.35, 1.25
NP
SR
0 0 003C3C3Ch
30332222h
2 1600
1.5, 1.35, 1.25
NP
DR
1 0 00003C3Ch
30332222h
2 1600
1.5, 1.35
SR, DR
SR, DR
1 0 00000000h
30222323h
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2.9.7.7
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DCT Training Specific Configuration
The DCT requires certain features be disabled during DRAM device initialization and training. BIOS should
program the registers in Table 47 before DRAM device initialization and training. For normal operation, BIOS
programs the recommended values if provided in Table 47. BIOS must quiesce all other forms of DRAM traffic on the channel being trained. See 2.9.7 [DCT/DRAM Initialization and Resume].
Table 47: DCT Training Specific Register Values
Register
D18F2x78_dct[0][AddrCmdTriEn]
D18F2x8C_dct[0][DisAutoRefresh]
D18F2x90_dct[0][ForceAutoPchg]
D18F2x90_dct[0][DynPageCloseEn]
D18F2x94_dct[0][BankSwizzleMode]
D18F2x94_dct[0][DcqBypassMax]
D18F2x94_dct[0][PowerDownEn]
D18F2x94_dct[0][ZqcsInterval]
D18F2x9C_x0000_000D_dct[0]_mp[1:0][RxMaxDurDllNoLock]
D18F2x9C_x0000_000D_dct[0]_mp[1:0][TxMaxDurDllNoLock]
D18F2x9C_x0D0F_0[F,8:0]10_dct[0]_mp[1:0][En
RxPadStandby]
D18F2xA4[CmdThrottleMode]
D18F2xA4[ODTSEn]
D18F2xA4[BwCapEn]
D18F2xA8_dct[0][BankSwap]
D18F3x58[DramScrub]2
D18F3x5C[ScrubReDirEn]2
Training
0
1
0
0
0
0
0
00b
000b
Normal Operation
1
0
0
0
1
1Fh
1
10b
See 2.9.7.10
000b
See 2.9.7.10
0
See 2.9.7.10
000b
000b
0
0
0
See 2.9.12
See 2.9.12
See 2.9.12
1
See 2.14.1.8
0
IF (D18F3x44[DramEccEn]==1) THEN 1
ELSE 0 ENDIF
1. Programmed specific to the current platform or memory configuration.
2. BIOS must quiesce all other forms of DRAM traffic on the channel when performing writes via
D18F2x98_dct[0]. See also D18F3x88[DisDramScrub].
2.9.7.8
DRAM Device and Controller Initialization
BIOS initializes the DRAM devices and the controller using either a hardware or a software controlled
sequence. Hardware init is supported for verification only. See 2.10.8.8.1 [Hardware DDR3 Device Initialization] and 2.9.7.8.1 [Software DDR3 Device Initialization].
BIOS must observe additional requirements for changing the PLL frequency when setting
D18F2x90_dct[0][InitDram] or D18F2x7C_dct[0][EnDramInit]. See 2.9.7.4.2 [DRAM Channel Frequency
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Change].
DRAM initialization is complete after the value of D18F2x90_dct[0][InitDram] transitions from 1 to 0 in the
hardware-controlled sequence or the value of D18F2x7C_dct[0][EnDramInit] is written by BIOS from 1 to 0
in the software-controlled sequence.
2.9.7.8.1
Software DDR3 Device Initialization
BIOS should apply the following procedure to each DCT to initialize the DDR3 DIMMs on the channel. This
procedure should be run only when booting from an unpowered state (ACPI S4, S5 or G3; not S3, suspend to
RAM).
1. Program D18F2x7C_dct[0][EnDramInit] = 1.
2. Wait 200 us.
3. Program D18F2x7C_dct[0][DeassertMemRstX] = 1.
4. Wait 500 us.
5. Program D18F2x7C_dct[0][AssertCke] = 1.
6. Wait 360 ns.
7. Send MRS(2).
8. Send MRS(3). Ordinarily at this time, MrsAddress[2:0] = 000b.
9. Send MRS(1) with MrsAddress[7] = 0 (write leveling disabled).
10. Send MRS(0) with MrsAddress[8] = 1 (reset the DLL).
11. Send two ZQCL commands.
• BIOS instructs the DCT to send a ZQCL command by programming D18F2x7C_dct[0] as follows:
• Program MrsAddress[10] = 1.
• Program SendZQCmd = 1.
• Wait for SendZQCmd = 0.
• Wait 512 MEMCLKs.
12. Program D18F2x7C_dct[0][EnDramInit] = 0.
13. Program D18F2x2E8_dct[0]_mp[1:0], D18F2x2EC_dct[0]_mp[1:0] with a copy of the mode register data
sent in the steps above, except with MR0[DLL] = 0 (Do not reset the DRAM DLL with a memory P-state
change).
2.9.7.8.1.1
DDR3 MR Initialization
BIOS instructs the DCT to send MRS commands by programming D18F2x7C_dct[0] as follows:
1.Program MrsBank and MrsAddress as specified below:
• MrsBank[2:0] = BA2:BA0.
• MrsAddress[15:0] = A15:A0.
• BIOS may need to remap bits, see also D18F2x[5C:40]_dct[0][OnDimmMirror].
• Set all other bits in MrsAddress to zero. BIOS should write reserved fields as 0.
2.Program MrsChipSel as appropriate.
3.Program SendMrsCmd = 1.
4.Wait for SendMrsCmd = 0.
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MR0 DDR3 MR0
Table 48: BIOS Recommendations for MR0[WR]
Condition
D18F2x22C_dct[0]_mp[1:0][Twr]
10h
5h
6h
7h
8h
Ah
Ch
Eh
12h
MR0
WR[3:0]
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1001b
Table 49: BIOS Recommendations for MR0[CL[3:0]]
Condition
D18F2x200_dct[0]_mp[1:0][Tcl]
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h
11h
Bits
MR0
CL[3:0]
2h
4h
6h
8h
Ah
Ch
Eh
1h
3h
5h
7h
9h
Bh
Description
15:14 Reserved.
13
WR[3]: write recovery for autoprecharge. See WR[2:0].
12
PPD: DLL control for precharge powerdown. BIOS: D18F2x84_dct[0][PchgPDModeSel].
11:9 WR[2:0]: write recovery for autoprecharge. WR[3:0] = {WR[3], WR[2:0]}. BIOS: Table 48.
8
DLL: DLL reset. BIOS: See 2.9.7.8.1.
7
TM: test mode. BIOS: 0.
6:4
CL[3:1]. CAS latency. See: CL[0].
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3
RBT: read burst type. BIOS: 1.
2
CL[0]. CAS latency. CL[3:0] = {CL[3:1], CL[0]}. BIOS: Table 49.
1:0
BL: burst length. BIOS: D18F2x84_dct[0][BurstCtrl].
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MR1 DDR3 MR1
Bits
Description
15:13 Reserved.
12
Qoff: Qoff. BIOS: See 2.9.7.9.1. See also D18F2x84_dct[0][Qoff].
11
TDQS: TDQS enable. BIOS: 0. See D18F2x94_dct[0][RDqsEn].
10
Reserved.
9
RttNom[2]: RttNom. See: RttNom[0].
8
Reserved.
7
Level: write leveling enable. BIOS: See 2.9.7.9.1.
6
RttNom[1]: RttNom. See: RttNom[0].
5
DIC[1]: output driver impedance control. See: DIC[0].
4:3
AL: additive latency. BIOS: 0.
2
RttNom[0]: RttNom. RttNom[2:0] = {RttNom[2], RttNom[1], RttNom[0]}. BIOS: See 2.9.7.6.5.1
1
DIC[0]: output driver impedance control. DIC[1:0] = {DIC[1], DIC[0]}. BIOS: 01b.
0
DLL: DLL enable. BIOS: 0.
MR2 DDR3 MR2
Table 50: BIOS Recommendations for MR2[ASR, SRT]
Condition
AutoSelfRefresh
0
0
1
Bits
ExtendedTemperatureRange
0
1
-
MR2
ASR
SRT
0
0
1
0
1
0
Description
15:11 Reserved.MR2
10:9 RttWr: RttWr. BIOS: See 2.9.7.6.5.1. See also D18F2x84_dct[0][DramTermDyn].
8
Reserved.
7
SRT: self refresh temperature range. BIOS: Table 50. See D18F2x84_dct[0][SRT].
6
ASR: auto self refresh. BIOS: Table 50. See D18F2x84_dct[0][ASR].
5:3
CWL: CAS write latency. BIOS: D18F2x20C_dct[0]_mp[1:0][Tcwl] - 5.
2:0
PASR: partial array self refresh. BIOS: 0.
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MR3 DDR3 MR3
Bits
Description
15:3 Reserved.
2
1:0
MPR: MPR operation. BIOS: 0.
MPRLoc: MPR location. BIOS: 0.
2.9.7.9
DRAM Training
This section describes detailed methods used to train the processor DDR interface to DRAM for optimal functionality and performance. DRAM training is performed by BIOS after initializing the DRAM controller. See
2.9.7.8 [DRAM Device and Controller Initialization].
Some of the DRAM training steps described in this section require two passes if the target MEMCLK frequency is greater than 333 MHz. For optimal software performance, software may defer the second pass (at
target MEMCLK frequency) for each training step until after the first pass (at lowest supported frequency) of
all other training steps are complete. See D18F2x94_dct[0][MemClkFreq].
Product specific training requirements are as follows:
• Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][TrNibbleSel]=0.
• Program D18F2xA8_dct[0][PerRankTimingEn]=1.
See 2.9.7.7 [DCT Training Specific Configuration] for additional training requirements.
In the following subsections, lane is used to describe an 8-bit wide data group, each with its own timing control.
2.9.7.9.1
Write Levelization Training
Write levelization involves using the phase recovery engine in the phy to detect the edge of DQS with respect
to the memory clock on the DIMM for write accesses to each lane.
Training is accomplished on a per channel, per rank basis. If the target frequency is greater than 333 MHz then
BIOS performs two passes; otherwise, only one pass is required. See 2.9.7.4.2 [DRAM Channel Frequency
Change].
• Pass 1: Configure the memory subsystem for 333 MHz MEMCLK frequency.
• Pass 2: Configure the memory subsystem for the target MEMCLK frequency. BIOS must reconfigure the
phy and the DRAM devices to the new target frequency.
The following describes the steps used for each pass of write levelization training for each channel:
For each rank:
1. Prepare the DIMMs for write levelization using DDR3-defined MR commands.
A. Configure the output driver and on-die termination of the target DIMM as follows:
• For the target rank of the target DIMM, enable write leveling mode and enable the output driver.
• For all other ranks of the target DIMM, enable write leveling mode and disable the output driver.
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2.
3.
4.
5.
6.
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• For two or more DIMMs per channel, program Rtt_Nom of the target rank to the corresponding
specified Rtt_Wr termination. Otherwise, configure Rtt_Nom of the target DIMM as normal. See
2.9.7.6.6 [DRAM Address Timing and Output Driver Compensation Control].
B. Configure Rtt_Nom on the non-target DIMMs as normal. See 2.9.7.6.6 [DRAM Address Timing and
Output Driver Compensation Control].
Wait 40 MEMCLKs to satisfy DDR3-defined internal DRAM timing parameters tWLMRD, tWLODEN,
and tWLDQSEN.
Configure the phy for write levelization training:
A. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][WrtLvTrEn]=0.
B. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][TrChipSel] to specify the target rank to be trained.
C. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][WrLvOdt] to the proper ODT settings for the current memory subsystem configuration. See 2.9.7.6.5 [DRAM ODT Control].
D. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][WrLvOdtEn]=1.
E. MFENCE.
F. Wait 10 MEMCLKs to allow for ODT signal settling.
G. For each lane program an initial value to registers D18F2x9C_x0000_00[52:50]_dct[0] to set the gross
and fine delay. See 2.9.7.9.1.1 [Write Leveling Seed Value].
Perform write leveling of the devices on the DIMM:
A. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][WrtLvTrEn]=1.
B. MFENCE.
C. Wait 200 MEMCLKs.
D. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][WrtLvTrEn]=0.
E. Read from registers D18F2x9C_x0000_00[52:50]_dct[0] to get the gross and fine delay settings for
the target DIMM and save these values.
Disable write levelization training so that the phy stops driving write levelization ODT.
A. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][WrLvOdtEn]=0.
B. MFENCE.
C. Wait 10 MEMCLKs to allow for ODT signal settling.
Program the target DIMM back to normal operation by configuring the following:
A. Configure all ranks of the target DIMM for normal operation.
B. Enable the output drivers of all ranks of the target DIMM.
C. For a two or more DIMM system, program the Rtt_Nom value for the target DIMM to the normal
operating termination.
For each rank:
• BIOS calculates and programs the final saved gross and fine delay values for each lane into
D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0] [DRAM DQS Write Timing].
• WrDqsFineDly = PhRecFineDly.
• GrossDly = SeedGross + PhRecGrossDly - SeedPreGross.
• The Critical Gross Delay (CGD) is the minimum GrossDly of all byte lanes and all DIMMs.
• If (CGD < 0) Then
• D18F2x20C_dct[0]_mp[1:0][WrDqDqsEarly] = ABS(CGD)
• WrDqsGrossDly = GrossDly + WrDqDqsEarly
• Else
• D18F2x20C_dct[0]_mp[1:0][WrDqDqsEarly] = 1.
• WrDqsGrossDly = GrossDly + 1.
2.9.7.9.1.1
Write Leveling Seed Value
The seed value for pass 1 of write leveling is design and platform specific. The seed value represents the actual
clock delay and is platform dependent. The platform vendor may need to characterize and adjust this value for
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proper write levelization training. The seed delay value must fall within +/- 1/2 MEMCLK, including silicon
PVT margin and jitter of the measured clock delay.
1. Calculate the total seed based on the following:
• Pass 1: SeedTotal = configuration specific seed value found in Table 51.
• Pass N:
• SeedTotalPreScaling = the total delay values obtained from the previous (N-1) pass of write levelization training.
• Write Leveling Total Delay = D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][WrDqsGrossDly,
WrDqsFineDly] - (0x20 * D18F2x20C_dct[0]_mp[1:0][WrDqDqsEarly])
• SeedTotal = SeedTotalPreScaling*(target frequency)/(frequency from previous pass).
2. SeedGross = SeedTotal DIV 32.
3. SeedFine = SeedTotal MOD 32.
4. If (SeedGross is odd)
then SeedPreGross = 1
else SeedPreGross = 2. Only LSB is used to effect starting PRE gross delay. Setting MSB allows the phase
recovery engine a positive and negative adjustment range.
5. Program D18F2x9C_x0000_00[52:50]_dct[0][PhRecFineDly] = SeedFine.
6. Program D18F2x9C_x0000_00[52:50]_dct[0][PhRecGrossDly] = SeedPreGross.
Table 51: DDR3 Write Leveling Seed Values
DIMM Type
Seed Value1
Solder-down
DRAM
0Eh
SODIMM
0Eh
UDIMM
15h
1. DDR3-667 (333 MHz).
2.9.7.9.2
DQS Receiver Enable Training
Receiver enable delay training is used to dynamically determine the optimal delay value for
D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0] [DRAM DQS Receiver Enable Timing]. The optimal DQS
receiver enable delay value is platform and load specific, and occurs in the middle of a received read preamble.
The timing of the preamble includes the inbound DQS propagation delay, which is unknown by BIOS. The
training for delay values involves:
1.
2.
3.
4.
Configuring the phy PRE for an initial expected phase value (seed).
Generating a stream of read DQS edges from the DRAM by issuing multiple read commands.
The phy PRE determining the phase between the received DQS edges and a reference clock.
Calculating a final delay value for enabling receivers during normal read operations using the phase determined by the phy PRE.
Prior to DQS Receiver Enable Training, BIOS must program D18F2x210_dct[0]_nbp[3:0][MaxRdLatency]
based on the seeded value of D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0]. See 2.9.7.9.5 [Calculating
MaxRdLatency].
Training is accomplished on a per channel, per rank basis. If the target frequency is greater than 333 MHz then
BIOS performs two passes; otherwise only one pass is required. See 2.9.7.4.2 [DRAM Channel Frequency
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Change].
• Pass 1: Configure the memory subsystem for 333 MHz MEMCLK frequency.
• Pass 2: Configure the memory subsystem for the target MEMCLK frequency. BIOS must reconfigure the
phy and the DRAM devices to the new target frequency.
The following describes the steps used for each pass of receiver enable training for each channel:
For each rank:
1. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][TrChipSel] to specify the target rank to be trained.
2. For each lane program an initial value to registers D18F2x9C_x0000_00[52:50]_dct[0] to set the gross and
fine delay as specified in 2.9.7.9.2.1 [DQS Receiver Enable Training Seed Value].
3. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][DqsRcvTrEn]=1.
4. Issue 192 read requests to the target rank. See 2.9.8 [Continuous Pattern Generation].
5. Program D18F2x9C_x0000_0008_dct[0]_mp[1:0][DqsRcvTrEn]=0.
6. Read D18F2x9C_x0000_00[52:50]_dct[0][PhRecGrossDly, PhRecFineDly] to get the gross and fine delay
values for each lane.
7. For each lane, calculate and program the corresponding receiver enable delay values for
D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay]. Save the
result for use later.
• DqsRcvEnFineDelay = PhRecFineDly.
• DqsRcvEnGrossDelay = SeedGross + PhRecGrossDly - SeedPreGross + 1. “+1” to add 1 UI to enable
the receiver in the mid point of preamble.
2.9.7.9.2.1
DQS Receiver Enable Training Seed Value
The seed value for pass 1 of receiver enable delay training is design and platform specific and should be determined by characterization for best performance. The seed value represents the total delay from a reference
point to the first expected rise edge of DQS on a read CAS measured at the processor pins, in 1 UI/32 increments. The reference point is defined as the clock in which CAS is asserted + CL - 1.
The following steps are taken to determine the seed values needed to program the DRAM Phase Recovery
Control Registers:
For each pass and each lane:
1. Calculate the total seed based on the following:
• Pass 1: SeedTotal = The seed value found in Table 52 + the total delay values obtained from the first pass
of write levelization training. See 2.9.7.9.1 [Write Levelization Training].
• Write Leveling Total Delay = D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][WrDqsGrossDly,
WrDqsFineDly] - (0x20 * D18F2x20C_dct[0]_mp[1:0][WrDqDqsEarly])
• Pass N:
• RegisterDelay = 0
• SeedTotalPreScaling = (the total delay values in D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0]
from the previous (N-1) pass of training) - RegisterDelay - 20h. Stored value was adjusted 1 UI to
enable the receiver in the mid point of preamble. Subtract 1 UI to get back to the preamble left edge.
• SeedTotal = RegisterDelay + FLOOR(SeedTotalPreScaling*(target frequency)/(frequency from previous pass)).
2. SeedGross = SeedTotal DIV 32.
3. SeedFine = SeedTotal MOD 32.
4. If (SeedGross is odd)
then SeedPreGross =1
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else SeedPreGross = 2. Only LSB is used to effect starting PRE gross delay. Setting MSB allows the phase
recovery engine a positive and negative adjustment range.
5. Program D18F2x9C_x0000_00[52:50]_dct[0][PhRecFineDly] = SeedFine.
6. Program D18F2x9C_x0000_00[52:50]_dct[0][PhRecGrossDly] = SeedPreGross.
7. Program D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay] = IF ((NBCOF / DdrRate
< 1) && (D18F2x200_dct[0]_mp[1:0][Tcl]=5) && (SeedGross<1) THEN 1 ELSE SeedGross ENDIF.
Table 52.
DDR3 DQS Receiver Enable Training Seed Values
Seed Value1
DIMM Type
Solder-down DRAM
SODIMM
UDIMM
1. DDR3-667 (333 MHz)
2.9.7.9.3
Char.Temp:20h
Char.Temp:32h
Char.Temp:32h
DQS Receiver Enable Cycle Training
Receiver enable delay cycle training is used to train the gross delay settings of
D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0] to the middle of the received read preamble using the phy PRE
phase results.
For each rank and lane:
1. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[0][BlockRxDqsLock] = 1.
2. RxEnOrig = D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay]
result from 2.9.7.9.2 [DQS Receiver Enable Training]. (expected mid-preamble position based on the
seed)
3. RxEnOffset = MOD(RxEnOrig + 10h, 40h) (offset by 1/4 MEMCLK, keep only the phase)
4. For each DqsRcvEn value beginning from RxEnOffset incrementing by 1 MEMCLK:
A. Program D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] with the current value.
B. Perform 2.9.7.9.4 [DQS Position Training].
• Record the result for the current DqsRcvEn setting as a pass or fail depending if a data eye is found.
5. Process the array of results and determine a pass-to-fail transition. (Consider a pass in the last array element as a pass-to-fail transition)
A. DqsRcvEnCycle = the total delay value of the pass result.
B. Program D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] = DqsRcvEnCycle - 10h. (subtract 1/4 MEMCLK to place the final DqsRcvEn mid-preamble)
6. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[0][BlockRxDqsLock] = 0.
2.9.7.9.4
DQS Position Training
DQS position training is used to place the DQS strobe in the center of the read DQ data eye and to center the
write DQ data eye across the write DQS strobe. Determining the correct DRAM DQS and DQ delay settings
for both reads and writes is conducted by performing a two dimensional search of the delay settings found in
D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0] [DRAM Read DQS Timing] and
D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0] [DRAM Write Data Timing].
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Training is accomplished on a per channel, per rank, and per lane basis.
For DQS position training, BIOS generates a training pattern using continuous read or write data streams. A
2k-bit-time training pattern is recommended for optimal results. To achieve this, BIOS programs
D18F2x260_dct[0][CmdCount] = 256, D18F2x250_dct[0][CmdTgt]=01b, and D18F2x25[8,4]_dct[0] to
access two different banks of the same CS. See 2.9.8 [Continuous Pattern Generation].
Prior to DQS position training, BIOS must program D18F2x210_dct[0]_nbp[3:0][MaxRdLatency] based on
the current greatest value of D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0]. See 2.9.7.9.5 [Calculating
MaxRdLatency].
The following describes the steps used for DQS position training for each channel:
• Program D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0] for all lanes.
• RxDqInsDly = 0. This could be reset from a prior frequency step. Start out with zero added delay for first
try.
For each rank and lane:
1. Select a 64 byte aligned test address.
2. For each write data delay value in D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0] from Wr-DQS to WrDQS plus 1 UI, using the Wr-DQS delay value found in 2.9.7.9.1 [Write Levelization Training]:
• Program the write data delay value for the current lane.
• Write the DRAM training pattern to the test address.
3. For each read DQS delay value in D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0] from 0 to 1 UI:
• Program the read DQS delay value for the current lane.
• Read the DRAM training pattern from the test address.
• Record the result for the current settings as a pass or fail depending if the pattern is read correctly.
• Process the array of results and determine the longest string of consecutive passing read DQS delay values.
• If the read DQS delay results for the current lane contain three or more consecutive passing delay
values, then program D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0] with the average value of the
smallest and largest delay values in the string of consecutive passing results.
• If the average value of passing read DQS delay for the lane is negative, then adjust the input receiver
DQ delay in D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0][RxDqInsDly] for the lane as follows:
• IF (RxDqInsDly < 3) THEN increment RxDqInsDly and repeat step 3 above for all ranks and
lanes; See note below.
• ELSE program the read DQS delay for the lane with a value of zero. BIOS should also flag an
error message for debug analysis.
• ENDIF.
4. Process the array of results and determine the longest string of consecutive passing write data delay values
for the read DQS delay value found in the step above.
• If the write data delay results for the current lane contain three or more consecutive passing delay values,
then program D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0] with the average value of the smallest
and largest delay values in the string of consecutive passing results.
See Figure 2.
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31
RdDqsTime
Figure 2: DQS Position Training Example Results
In some cases, a non-zero process, voltage, and temperature dependent insertion delay is added to the DLL programmed read DQS delay. This has the effect of sampling data later than intended and can result in missing the
left edge of the passing region when sweeping from 0 to 1 UI because a read DQS delay value of 0 is already in
the passing region. Since DQS is periodic, BIOS can recover the missing information by adjusting the algorithm described above to analyze both the in phase data and the data shifted by one bit time at each step of the
read DQS delay sweep. See D18F2x268_dct[0][NibbleErrSts] and D18F2x26C_dct[0][NibbleErr180Sts].
As shown in Figure 3, for each delay setting BIOS records a passing result of PΦ for the data comparison
shifted by one bit time if the data at bit times N=0, 1, …, 6, is read correctly when compared against the data
written at bit times N=1, 2, …, 7. In the array of results, these passing values make up the left piece of information that had been lost due to insertion delay. In order to process the array of results, BIOS calculates the read
DQS delay value for a PΦ result as RdDqsTimeByte minus 1 UI.
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7 F F F F F F F F F F F F F F F F F F F F F F F
6 F F F F F F F F F F F F F F F F F F F F F F F
5 F F F F F F F F F F F F F F F F F F F F F F F
4 F F F F F F F F F F F F F F F F F F F F F F F
3 F F F F F F F F F F F F F F F F F F F F F F F
2 F F F F F F F F F F F F F F F F F F F F F F F
1 F F F F F F F F F F F F F F F F F F F F F F F
0 F F F F F F F F F F F F F F F F F F F F F F F
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Φ -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10
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-3
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PΦ PΦ
PΦ PΦ
PΦ PΦ
PΦ PΦ
PΦ PΦ
PΦ PΦ
PΦ PΦ
PΦ PΦ
PΦ PΦ
F F
F F
F F
F F
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F F
F F
F F
F F
F F
F F
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F F
F F
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30 31
-2 -1
RdDqsTime
Figure 3: DQS Position Training Insertion Delay Recovery Example Results
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2.9.7.9.5
BKDG for AMD Family 16h Models 00h-0Fh Processors
Calculating MaxRdLatency
The MaxRdLatency value determines when the memory controller can receive incoming data from the DCTs.
Calculating MaxRdLatency consists of summing all the synchronous and asynchronous delays in the path from
the processor to the DRAM and back at a given MEMCLK frequency. BIOS incrementally calculates the
MaxRdLatency and then finally programs the value into D18F2x210_dct[0]_nbp[3:0][MaxRdLatency].
The following steps describe the algorithm used to compute D18F2x210_dct[0]_nbp[3:0][MaxRdLatency]
used for DRAM training. P, N, and T are used as a temporary placeholders for the incrementally summed
value.
1. P = N = T = 0
2. If (D18F2x9C_x0000_0004_dct[0]_mp[1:0][AddrCmdSetup] = 0 &
D18F2x9C_x0000_0004_dct[0]_mp[1:0][CsOdtSetup] = 0 &
D18F2x9C_x0000_0004_dct[0]_mp[1:0][CkeSetup] = 0)
then P = P + 1
else P = P + 2
3. P = P + (8 - D18F2x210_dct[0]_nbp[3:0][RdPtrInit])
• Worst case in real silicon. See step 4.
4. P = P + NumPclks
• NumPclks =6
5. P = P + (2 * (D18F2x200_dct[0]_mp[1:0][Tcl] - 1 clocks))
6. P = P + CEIL(MAX(D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] + D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0][RdDqsTime] PCLKs)) + 1
• Prior to DQS position training, use maximum value for RdDqsTime.
7. If (NclkFreq/MemClkFreq < 2) then P = P + 4.5
Else P = P + 2.5
8. T = T + 1050 ps
9. N = (P/(MemClkFreq * 2) + T) * NclkFreq; Convert from PCLKs plus time to NCLKs.
• See D18F5x16[C:0][NbDid, NbFid] and D18F2x94_dct[0][MemClkFreq].
10. D18F2x210_dct[0]_nbp[3:0][MaxRdLatency] = CEIL(N) + NumNclks
• NumNclks =1
2.9.7.9.5.1
MaxRdLatency Training
After DRAM DQS receiver enable training, BIOS optimizes D18F2x210_dct[0]_nbp[3:0][MaxRdLatency]
using the following algorithm. For MaxRdLatency training, BIOS generates a training pattern using continuous read or write data streams. See 2.9.8 [Continuous Pattern Generation].
For each channel:
1. Calculate a starting MaxRdLatency delay value by executing the steps in 2.9.7.9.5, excluding steps 4, 7, 8,
and 10. It is expected that the first value will result in a test fail.
2. Select 32 64-byte aligned test addresses associated with the rank that has the worst case
(D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay, DqsRcvEnFineDelay] +
D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0][RdDqsTime]) register setting.
3. Write the DIMM test addresses with the training pattern.
4. For each MaxRdLatency value incrementing from the value calculated in step 1:
A. Program D18F2x210_dct[0]_nbp[3:0][MaxRdLatency] with the current value.
B. Read the DIMM test addresses.
C. Compare the values read against the pattern written.
• If the pattern is read correctly, go to step 5.
D. Program D18F2x9C_x0000_0050_dct[0]=00000000h to reset the RcvFifo.
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5. Program D18F2x210_dct[0]_nbp[3:0][MaxRdLatency] = CEIL(current value + 1 NCLK + (IF (Verification) THEN 1.0 MEMCLK ELSE 1.5 MEMCLK ENDIF) + IF (NclkFreq/MemClkFreq < 2) THEN 1.0
MEMCLK ELSE 0 ENDIF) .
2.9.7.10
DRAM Phy Power Savings
For power savings, BIOS should perform the following actions for each channel:
1. Program D18F2x88_dct[0][MemClkDis] to disable unused MEMCLK pins.
2. Program D18F2x9C_x0D0F_2[F,2:0]30_dct[0][PwrDn] for unused MEMCLK pairs.
3. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[0][PwrDn] to disable the ECC lane if
D18F2x90_dct[0][DimmEccEn]==0.
4. Program D18F2x9C_x0000_000C_dct[0][CKETri, ODTTri, ChipSelTri] to disable unused pins.
5. Per byte, if none of D18F2x9C_x0D0F_0[F,8:0][17:14][EarlyLateU[3:0]] is set to 1, then Program
D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0][DllDisEarlyU] = 1.
6. Per byte, if none of D18F2x9C_x0D0F_0[F,8:0][17:14][EarlyLateL[3:0]] is set to 1, then Program
D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0][DllDisEarlyL] = 1.
7. D18F2x9C_x0D0F_812F_dct[0][PARTri] = 1.
8. D18F2x9C_x0D0F_812F_dct[0][Add17Tri, Add16Tri] = {1b, 1b}
9. Program D18F2x9C_x0D0F_0[F,8:0]10_dct[0]_mp[1:0][EnRxPadStandby] = IF (DdrRate <= 1600)
THEN 1 ELSE 0 ENDIF.
10. Program D18F2x9C_x0000_000D_dct[0]_mp[1:0] as follows:
• If (DdrRate <= 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h
else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
• TxCPUpdPeriod = RxCPUpdPeriod = 011b.
• TxDLLWakeupTime = RxDLLWakeupTime = 11b.
11. Program D18F2x9C_x0D0F_0[F,8:0]1C_dct[0]_mp[1:0] as follows:
• If D18F2x90_dct[0][DimmEccEn] Numlanes = 9 Else Numlanes = 8.
• If (DdrRate >= 1866) DllWakeTime = 1 Else DllWakeTime = 0.
• Let MaxRxStggrDly = ((Tcl-1)*2) + MIN(DqsRcvEnGrossDelay for all byte lanes) - 6.
• See D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0].
• Let (real) dRxStggrDly = (MaxRxStggrDly - DllWakeTime) / (Numlanes - 1).
• For each byte lane in the ordered sequence below, program RxDllStggrDly[5:0] = an increasing value,
starting with 0 for the first byte lane in the sequence and increasing at a rate of dRxStggrDly for each
subsequent byte lane.
• Sequence: If D18F2x90_dct[0][DimmEccEn] {8, 4, 3, 5, 2, 6, 1, 7, 0} else {4, 3, 5, 2, 6, 1, 7, 0}.
• Let MaxTxStggrDly = MIN(((Tcwl-1)*2) + MIN(WrDqsGrossDly for all byte lanes) - WrDqDqsEarly 4, MaxRxStggrDly)
• See D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0].
• See D18F2x20C_dct[0]_mp[1:0].
• Let (real) dTxStggrDly = (MaxTxStggrDly - DllWakeTime) / (Numlanes - 1).
• For each byte lane in the ordered sequence below, program TxDllStggrDly[5:0] = an increasing integer
value, starting with 0 for the first byte lane in the sequence and increasing at a rate of dTxStggrDly for
each subsequent byte lane.
• Sequence: If D18F2x90_dct[0][DimmEccEn] {0, 7, 1, 6, 2, 5, 3, 4, 8} else {0, 7, 1, 6, 2, 5, 3, 4}.
• RxDllStggrEn = TxDllStggrEn = 1.
12. Program D18F2x248_dct[0]_mp[1:0] and then D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0] as follows:
• For M0 & M1 context program RxChMntClkEn=RxSsbMntClkEn=0.
13. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[0][TxPclkGateEn, PchgPdPClkGateEn, DataCtlPipePclkGateEn] = {1, 1, 1}.
14. Program D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0][TriDM] = IF (DataMaskMbType == 0) THEN 1
ELSE 0 ENDIF.
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2.9.8
BKDG for AMD Family 16h Models 00h-0Fh Processors
Continuous Pattern Generation
DRAM training relies on the ability to generate a string of continuous reads or writes between the processor
and DRAM, such that worst case electrical interactions can be created. This section describes how these continuous strings of accesses may be generated.
2.9.8.1
DCT Training Pattern Generation (Reliable Read Write Mode)
DCT training pattern generation uses pattern generators in the DCT to generate controlled read and write traffic streams. During write pattern generation, data values based off of a deterministic pattern are burst to the
DRAM interface. Conversely for reads, data bursts from the DRAM interface are compared against expected
data values on a per nibble basis.
Two address modes are available for DRAM training pattern generation, as configured by
D18F2x250_dct[0][CmdTgt]. For generating a stream of reads or writes to the same rank, address target A
mode is used. To generate a stream of accesses to up to two different ranks, address target A and B mode is
used.
An overview of the BIOS sequence to generate training patterns is as follows:
• Configure the DCT for pattern generation. See 2.9.7.7 [DCT Training Specific Configuration].
• Ensure DIMMs are configured to support 8-beat bursts (BL8 or dynamic burst length on the fly).
• Wait for D18F2x250_dct[0][CmdSendInProg] = 0.
• Program D18F2x250_dct[0][CmdTestEnable] = 1.
• Send activate commands as appropriate. See 2.9.8.1.1 [Activate and Precharge Command Generation].
• Send read or write commands as desired. See 2.9.8.1.2 [Read and Write Command Generation].
• Send precharge commands as appropriate. See 2.9.8.1.1 [Activate and Precharge Command Generation].
• Program D18F2x250_dct[0][CmdTestEnable] = 0.
2.9.8.1.1
Activate and Precharge Command Generation
Prior to sending read or write commands, BIOS must send an activate command to a row in a particular bank
of the DRAM devices for access. To send an activate command, BIOS performs the following steps:
• Program D18F2x28C_dct[0] to the desired address as follows:
• CmdChipSelect = CS[7:0].
• CmdBank = BA[2:0].
• CmdAddress = A[17:0] (row address).
• Program D18F2x28C_dct[0][SendActCmd] = 1.
• Wait until D18F2x28C_dct[0][SendActCmd] = 0.
• Wait 75 MEMCLKs. (D18F2x200_dct[0]_mp[1:0][Tras, Trcd], D18F2x204_dct[0]_mp[1:0][FourActWindow, Trrd, Trc])
After completing its accesses, BIOS must deactivate open rows in the DRAM devices. To send a precharge or
precharge all command to deactivate open rows in a bank or in all banks, BIOS performs the following steps:
• Wait 25 MEMCLKs. (D18F2x204_dct[0]_mp[1:0][Trtp])
• Program D18F2x28C_dct[0] to the desired address as follows:
• CmdChipSelect = CS[7:0].
• Precharge all command:
• CmdAddress[10] = 1.
• Precharge command:
• CmdAddress[10] = 0.
• CmdBank = BA[2:0].
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• Program D18F2x28C_dct[0][SendPchgCmd] = 1.
• Wait until D18F2x28C_dct[0][SendPchgCmd] = 0.
• Wait 25 MEMCLKs. (Trp)
2.9.8.1.2
Read and Write Command Generation
BIOS performs the following steps for read pattern generation:
• Program D18F2x27C_dct[0], D18F2x278_dct[0], and D18F2x274_dct[0] with the data comparison
masks for bit lanes of interest.
• Program D18F2x270_dct[0][DataPrbsSeed] the seed for the desired PRBS.
• Program D18F2x260_dct[0][CmdCount] equal to the number of cache line commands.
• Program D18F2x25C_dct[0][BubbleCnt, CmdStreamLen]. See 2.9.8.1.5 [BubbleCnt and CmdStreamLen Programming].
• Program D18F2x25[8,4]_dct[0] to the initial address (column address).
• Program D18F2x250_dct[0] as follows:
• ResetAllErr and StopOnErr as desired. See 2.9.8.1.4 [Data Comparison].
• CmdTgt corresponding to D18F2x25[8,4]_dct[0].
• CmdType = 000b.
• SendCmd = 1.
• If D18F2x260_dct[0][CmdCount] != 0 (not in infinite mode) then
Wait for D18F2x250_dct[0][TestStatus] = 1 and D18F2x250_dct[0][CmdSendInProg] = 0.
Else
Wait the desired amount of time.
Program D18F2x260_dct[0][CmdCount] = 1.
Wait for D18F2x250_dct[0][TestStatus] = 1 and D18F2x250_dct[0][CmdSendInProg] = 0.
• Program D18F2x250_dct[0][SendCmd] = 0.
• Read D18F2x264_dct[0], D18F2x268_dct[0], and D18F2x26C_dct[0] if applicable.
BIOS performs the following steps for write pattern generation:
• Program D18F2x270_dct[0][DataPrbsSeed] the seed for the desired PRBS.
• Program D18F2x260_dct[0][CmdCount] equal to the number of cache line commands desired.
• Program D18F2x25C_dct[0][BubbleCnt, CmdStreamLen]. See 2.9.8.1.5 [BubbleCnt and CmdStreamLen Programming].
• Program D18F2x25[8,4]_dct[0] to the initial address.
• Program D18F2x250_dct[0] as follows:
• CmdTgt corresponding to D18F2x25[8,4]_dct[0].
• CmdType = 001b.
• SendCmd = 1.
• If D18F2x260_dct[0][CmdCount] != 0 (not in infinite mode) then
Wait for D18F2x250_dct[0][TestStatus] = 1 and D18F2x250_dct[0][CmdSendInProg] = 0.
Else
Wait the desired amount of time.
Program D18F2x260_dct[0][CmdCount] = 1.
Wait for D18F2x250_dct[0][TestStatus] = 1 and D18F2x250_dct[0][CmdSendInProg] = 0.
• Program D18F2x250_dct[0][SendCmd] = 0.
BIOS combines the two sets of steps listed above for alternating write and read pattern generation.
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2.9.8.1.3
BKDG for AMD Family 16h Models 00h-0Fh Processors
Configurable Data Patterns
In addition to PRBS mode, D18F2x250_dct[0][DataPatGenSel] and D18F2x2[B4,B0,AC,A8]_dct[0] allow
configurable data pattern generation. E.g. Simultaneous Switching Output (SSO) and Inversion Patterns.
Table 53.
DQ/
Beat
Configurable Data Pattern Example with 1 Address Target
Write TgtA Cmd 0
Write TgtA Cmd 1
Write TgtA Cmd 2
Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 1 0 0
0 0 1 0 0 0 1 0 0 0 1 0
0 1 1 0 0 1 1 0 0 1 1 0
0 0 0 1 0 0 0 1 0 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1 0 0 1 1
0 1 1 1 0 1 1 1 0 1 1 1
1 0 0 0 1 0 0 0 1 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0
1 1 1 0 1 1 1 0 1 1 1 0
1 0 0 1 1 0 0 1 1 0 0 1
1 1 0 1 1 1 0 1 1 1 0 1
1 0 1 1 1 0 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1
...
ECC0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECC1 1
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
ECC2 0
1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0
ECC3 1
1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
ECC4 0
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
ECC5 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ECC6 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ECC7 1
1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1
1. D18F2x250_dct[0][DataPatGenSel] = 10b //Configurable data pattern
D18F2x2[B4,B0,AC,A8]_dct[0] = {FFEE_DDCCh, BBAA_9988h, 7766_5544h, 3322_1100h}
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
...
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
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Table 54.
DQ/
Beat
BKDG for AMD Family 16h Models 00h-0Fh Processors
Configurable Data Pattern Circular Shift Example with 1 Address Target
Write TgtA Cmd 0
Write TgtA Cmd 1
Write TgtA Cmd 2
Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1 1 1 1 1 0 1 1 1 0 1 1
0 0 0 0 0 1 1 1 1 1 1 1
0 1 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 1 0 0 0 1 0 0
0 1 1 0 0 0 1 0 0 0 1 0
0 0 0 1 0 1 1 0 0 1 1 0
0 1 0 1 0 0 0 1 0 0 0 1
0 0 1 1 0 1 0 1 0 1 0 1
0 1 1 1 0 0 1 1 0 0 1 1
1 0 0 0 1 1 1 1 0 1 1 1
1 1 0 0 1 0 0 0 1 0 0 0
1 0 1 0 1 1 0 0 1 1 0 0
1 1 1 0 1 0 1 0 1 0 1 0
1 0 0 1 1 1 1 0 1 1 1 0
1 1 0 1 1 0 0 1 1 0 0 1
1 0 1 1 1 1 0 1 1 1 0 1
...
ECC0 0
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1
ECC1 1
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
ECC2 0
1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
ECC3 1
1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0
ECC4 0
0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0
ECC5 1
0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 1 1 0
ECC6 0
1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1
ECC7 1
1 1 0 1 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
1. D18F2x250_dct[0][DataPatGenSel] = 11b //User data pattern with circular lane shift
D18F2x2[B4,B0,AC,A8]_dct[0] = {FFEE_DDCCh, BBAA_9988h, 7766_5544h, 3322_1100h}
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.9.8.1.3.1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
...
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Static Data Pattern Override
Software is also able to use the bits of D18F2x280_dct[0], D18F2x284_dct[0], and D18F2x288_dct[0] to override the DCT pattern generator on a DQ basis. This can only be used in the D18F2x250_dct[0][DataPatGenSel]
= 10b mode. Software programs the following to enable the mode:
• Program D18F2x288_dct[0][PatOvrVal] to the data value desired.
• Program D18F2x280_dct[0][DQPatOvrEn[31:0]], D18F2x284_dct[0][DQPatOvrEn[63:32]], and
D18F2x288_dct[0][EccPatOvrEn] to enable the override on the desired bit lanes.
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Table 55.
DQ/
Beat
BKDG for AMD Family 16h Models 00h-0Fh Processors
Data Pattern Override Example with 1 Address Target
Write TgtA Cmd 0
Write TgtA Cmd 1
Write TgtA Cmd 2
Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat Beat
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 1 0 0
0 0 1 0 0 0 1 0 0 0 1 0
0 1 1 0 0 1 1 0 0 1 1 0
0 0 0 1 0 0 0 1 0 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0
1 1 1 0 1 1 1 0 1 1 1 0
1 0 0 1 1 0 0 1 1 0 0 1
1 1 0 1 1 1 0 1 1 1 0 1
1 0 1 1 1 0 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1
...
ECC0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECC1 1
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
ECC2 0
1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0
ECC3 1
1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
ECC4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECC5 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ECC6 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
ECC7 1
1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1
1. D18F2x250_dct[0][DataPatGenSel] = 10b //Configurable data pattern
D18F2x2[B4,B0,AC,A8]_dct[0] = {FFEE_DDCCh, BBAA_9988h, 7766_5544h, 3322_1100h}
D18F2x288_dct[0][PatOvrVal] = 0. //Static 0’s
D18F2x280_dct[0][DQPatOvrEn[31:0]] = 0x0000_0080. // DQ7 Override
D18F2x284_dct[0][DQPatOvrEn[63:32]] = 0x0000_0000. // No Override
D18F2x288_dct[0][EccPatOvrEn] = 0x10. // ECC4 Override
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
...
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
2.9.8.1.3.2
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
...
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
Xor Data Pattern Override
Software is also able to use the bits of D18F2x288_dct[0][XorPatOvr] to override the DCT pattern generator
with the same XOR function for all byte lanes. This feature can only be used with select
D18F2x250_dct[0][DataPatGenSel] PRBS modes. Software programs the following to enable the mode:
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• Program D18F2x288_dct[0][XorPatOvr] to the data value of the XOR function desired.
• Output data = IF (DQPatOvrEn) THEN PatOvrVal ELSE (DataPatGen ^ XorPatOvr) ENDIF.
2.9.8.1.4
Data Comparison
The DCT compares the incoming read data against the expected pattern sequence during pattern generation.
BIOS may choose to continue command generation and accumulate errors or stop command generation on the
first error occurrence by programming D18F2x250_dct[0][StopOnErr].
Error information is reported via D18F2x264_dct[0], D18F2x268_dct[0], D18F2x26C_dct[0],
D18F2x294_dct[0], D18F2x298_dct[0] and D18F2x29C_dct[0]. Error information can be masked on per-bit
basis by programming D18F2x274_dct[0], D18F2x278_dct[0], and D18F2x27C_dct[0].
BIOS resets the error information by programming D18F2x250_dct[0][ResetAllErr]=1.
Error information is only valid in certain modes of D18F2x250_dct[0][CmdType, CmdTgt] and
D18F2x260_dct[0][CmdCount] and when using 64 byte aligned addresses in D18F2x25[8,4]_dct[0][TgtAddress]. Some modes require a series of writes to setup a DRAM data pattern. See Table 56.
Table 56.
Command Generation and Data Comparison
Commands
Read
CmdType
Cmd
Tgt
Maximum CmdCount4
000b
00b1
128
010b
01b
00b
2562
Infinite
1
Write-Read
1.
2.
3.
4.
01b3
2562
Requires setup writes to store a data pattern in DRAM. The write commands are generated using the same CmdTgt, CmdCount, and DataPrbsSeed settings.
D18F2x254[TgtAddress] != D18F2x258[TgtAddress].
Requires setup writes to store a data pattern in DRAM. The write commands are generated programming D18F2x254[TgtAddress] to the intended
Target B, CmdTgt=00b, CmdCount to 1/2 of the intended command count,
and the same DataPrbsSeed setting.
D18F2x250_dct[0][LsfrRollOver]=0. The maximum CmdCount is infinite
for all modes listed if D18F2x250_dct[0][LsfrRollOver]=1.
2.9.8.1.4.1
Activate and Precharge Traffic Generation
The DCT generates ACT and PRE traffic in the available command bandwith during a WR or RD sequence
generated by D18F2x250_dct[0][SendCmd] when D18F2x250_dct[0][ActPchgGenEn]=1. This 16 command
sequence repeats until the WR or RD initiated by SendCmd hits a stopping condition.
Software is able to adjust the command spacing and address sequence by programming
D18F2x28C_dct[0][CmdChipSelect, CmdAddress[17:4]], D18F2x2B8_dct[0][ActPchgSeq, ActPchgCmdMin], and D18F2x2[C0,BC]_dct[0].
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The banks specified by D18F2x2[C0,BC]_dct[0] must be in the idle state and must not conflict with the banks
used by the SendCmd WR or RD traffic stream. Software is responsible for the ACT/PRE protocol of the WR
or RD targets initiated by SendCmd. On a stopping condition for the WR or RD traffic stream, software is
responsible for returning all of the possibly open banks to the idle state.
•
•
•
•
Example configuration for DRAM Training:
D18F2x250_dct[0][ActPchgGenEn, CmdTgt, CmdType] = {1b, 1b, 0b}. // Tgt A&B, Reads
D18F2x28C_dct[0][CmdChipSelect] = CS of TgtA
D18F2x28C_dct[0][CmdAddress[17:4]] = desired upper row address bits.
• Hardware places the sequence number in row address [3:0].
• D18F2x2B8_dct[0][ActPchgSeq, ActPchgCmdMin]= {0F0Fh, Fh}.
• D18F2x2BC_dct[0] = 5432_ 5432h; // Banks 2,3,4,5
• D18F2x2C0_dct[0] = 7632_ 7632h; // Banks 2,3,6,7
2.9.8.1.5
BubbleCnt and CmdStreamLen Programming
BIOS programs D18F2x25C_dct[0][BubbleCnt2, BubbleCnt, CmdStreamLen] to ensure proper channel command spacing in command generation mode.
For continuous pattern generation it is expected that BubbleCnt = 0. In other modes, BIOS programs BubbleCnt, BubbleCnt2, and CmdStreamLen greater than or equal to the relevant DRAM timing parameters
shown below to prevent contention on the DRAM bus. In all cases, if the minimum BubbleCnt > 0 or CmdType = 010b then BIOS programs CmdStreamLen = 1.
Table 57.
DDR3 Command Generation and BubbleCnt Programming
Commands
CmdType CmdTgt
Read-Read same CS
000b
0xb
Write-Write same CS
001b
0xb
Write-Read same CS
010b
00b
Read-Read different CS
000b
01b
Write-Write different CS
001b
01b
Write-Read different CS
010b
01b
BubbleCnt
D18F2x218_dct[0]_mp[1:0][
TrdrdSdSc] - 1; Exclude
banned spacing:
D18F2x218_dct[0]_mp[1:0][
TrdrdBan]
D18F2x214_dct[0]_mp[1:0][
TwrwrSdSc] - 1
D18F2x20C_dct[0]_mp[1:0]
[Twtr] +
D18F2x20C_dct[0]_mp[1:0]
[Tcwl] + 4 - 1
D18F2x218_dct[0]_mp[1:0][
TrdrdSdDc] - 1; Exclude
banned spacing:
D18F2x218_dct[0]_mp[1:0][
TrdrdBan]
D18F2x214_dct[0]_mp[1:0][
TwrwrSdDc] - 1
D18F2x218_dct[0]_mp[1:0][
Twrrd] - 1
BubbleCnt2
xh
xh
D18F2x21C_dct[0]_mp[
1:0][TrwtTO] - 1
xh
xh
D18F2x21C_dct[0]_mp[
1:0][TrwtTO] - 1
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Table 57.
BKDG for AMD Family 16h Models 00h-0Fh Processors
DDR3 Command Generation and BubbleCnt Programming
Commands
CmdType CmdTgt
Read-Read different DIMM
000b
01b
Write-Write different DIMM
001b
01b
Write-Read different DIMM
010b
01b
2.9.9
BubbleCnt
D18F2x218_dct[0]_mp[1:0][
TrdrdDd] - 1; Exclude
banned spacing:
D18F2x218_dct[0]_mp[1:0][
TrdrdBan]
D18F2x214_dct[0]_mp[1:0][
TwrwrDd] - 1
D18F2x218_dct[0]_mp[1:0][
Twrrd] - 1
BubbleCnt2
xh
xh
D18F2x21C_dct[0]_mp[
1:0][TrwtTO] - 1
Memory Interleaving Modes
The processor supports the following memory interleaving modes:
• Chip select: interleaves the physical address space over multiple DIMM ranks on a channel, as opposed
to each DIMM owning single consecutive address spaces. See 2.9.9.1 [Chip Select Interleaving].
Table 58.
Recommended Interleave Configurations
Interleaving
Mode
Chip Select
Interleaving
2.9.9.1
Enabled
Number of chip selects installed on
the channel is a power of two.
Disabled
Requirements not satisfied.
Chip Select Interleaving
The chip select memory interleaving mode has the following requirements:
• The number of chip selects interleaved is a power of two.
• The chip selects are the same size and type.
A BIOS algorithm for programming D18F2x[5C:40]_dct[0] [DRAM CS Base Address] and
D18F2x[6C:60]_dct[0] [DRAM CS Mask] in memory interleaving mode is as follows:
1.Program all DRAM CS Base Address and DRAM CS Mask registers using contiguous normalized
address mapping.
2.For each enabled chip select, swap the corresponding BaseAddr[38:27] bits with the BaseAddr[21:11]
bits as defined in Table 59.
3.For each enabled chip select, swap the corresponding AddrMask[38:27] bits with the AddrMask[21:11]
bits as defined in Table 59.
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Table 59.
BKDG for AMD Family 16h Models 00h-0Fh Processors
DDR3 Swapped Normalized Address Lines for CS Interleaving
Swapped Base Address and
Address Mask bits
Condition
DctSelBankSwap2
BankSwap2
DIMM
Address CS Size
Map1
4 way CS
interleaving
2 way CS
interleaving
0001b
256MB 0 [29:28] and [17:16] [28] and [16]
1 1
[29:28] and [12:11] [28] and [11]
1 0
[29:28] and [13:12] [28] and [12]
0010b
512MB 0 [30:29] and [17:16] [29] and [16]
1 1
[30:29] and [12:11] [29] and [11]
1 0
[30:29] and [13:12] [29] and [12]
0101b
1GB
0 [31:30] and [17:16] [30] and [16]
1 1
[31:30] and [12:11] [30] and [11]
1 0
[31:30] and [13:12] [30] and [12]
0111b
2GB
0 [32:31] and [17:16] [31] and [16]
1 1
[32:31] and [12:11] [31] and [11]
1 0
[32:31] and [13:12] [31] and [12]
1010b
4GB
0 [33:32] and [17:16] [32] and [16]
1 1
[33:32] and [12:11] [32] and [11]
1 0
[33:32] and [13:12] [32] and [12]
1011b
8GB
0 [34:33] and [18:17] [33] and [17]
1 1
[34:33] and [12:11] [33] and [11]
1 0
[34:33] and [13:12] [33] and [12]
1. See D18F2x80_dct[0] [DRAM Bank Address Mapping].
2. See D18F2xA8_dct[0][BankSwap] and D18F2x114[DctSelBankSwap].
2.9.10
Memory Hoisting
Memory hoisting reclaims the otherwise inaccessible DRAM that would naturally reside in memory regions
used by MMIO. When memory hoisting is configured by BIOS, DRAM physical addresses are repositioned
above the 4 GB address level in the address map. In operation, the physical addresses are remapped in hardware to the normalized addresses used by a DCT.
The region of DRAM that is hoisted is defined to be from D18F1xF0[DramHoleBase] to the 4 GB level. Hoisting is enabled by programming D18F1xF0 [DRAM Hole Address] and configuring the DCTs per the equations
in this section.
DramHoleSize is defined in order to simplify the following equations in this section and is calculated as follows:
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• Define the DRAM hole region as DramHoleSize[31:24] = 100h - D18F1xF0[DramHoleBase[31:24]].
2.9.10.1
DramHoleOffset Programming
D18F1xF0[DramHoleOffset] is programmed to account for the addresses from D18F1xF0[DramHoleBase] to
4 GB when it falls inside of a D18F1x2[1,0][8,0][DctBaseAddr] and D18F1x2[1,0][C,4][DctLimitAddr]
region. See Figure 4 as an example memory population.
• Program D18F1xF0[DramHoleOffset[31:23]] =
{DramHoleSize[31:24], 0b} + {DctBaseAddr[31:27], 0000b};
DRAM Populated
System
Address Map
DRAM
Normalized
Address Map
5GB
4GB
4GB
3GB
Hole
3GB
2GB
Region 0
2GB
1GB
1GB
0
DCT 0
2GB DRAM
DCT 1
2GB DRAM
0
Figure 4: Memory Configuration with Memory Hole inside of Region
D18F1xF0[DramHoleOffset] is unused when the memory hole falls outside of a region. Figure 5 shows an
example memory population which uses two memory regions. Region 1 is configured to begin above the memory hole.
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DRAM Populated
System
Address Map
DRAM
Normalized
Address Map
5GB
4GB
Region 1
4GB
3GB
Hole
3GB
2GB
2GB
1GB
1GB
Region 0
0
DCT 0
2GB DRAM
DCT 1
1.5GB DRAM
0
Figure 5: Memory Configuration with Memory Hole outside of Region
2.9.11
DRAM CC6/PC6 Storage
DRAM is used to hold the state information of cores entering the CC6 power management state. As part of the
system setup if CC6 or PC6 is enabled, BIOS configures a special region of DRAM to hold the state information. In operation, hardware protects this region from general system accesses while allowing the cores access
during C-state transitions.
2.9.11.1
Fixed Storage
The size of each special DRAM storage region is defined to be a fixed 16MB. BIOS configures the storage
region at the top of the DRAM range, adjusts D18F1x[7:4][C,4][DramLimit] and the processor top of DRAM
specified by MSRC001_001A[TOM] or MSRC001_001D[TOM2] downward accordingly. For UNB designs,
the 16MB range is implemented in HW by adjusting D18F1x124[DramLimitAddr]. See Table 60.
After finalizing the system DRAM configuration, BIOS must set D18F2x118[LockDramCfg] = 1 to enable the
hardware protection.
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Table 60.
Example storage region configuration
DRAM
Node
Populated
0
2.9.12
BKDG for AMD Family 16h Models 00h-0Fh Processors
256 MB
CC6
D18F1x[17C:140,7C:40]
DRAM
[DramBase, DramLimit]
Range
0 MB,
240 MB - 1
240 MB,
256 MB - 1
D18F4x128
D18F1x120[DramBaseAddr],
[CoreStateSa
D18F1x124[DramLimitAddr]
veDestNode]
0
0 MB,
256 MB - 1
DRAM On DIMM Thermal Management and Power Capping
Each DCT can throttle commands based on the state of the channel EVENT_L pin or when
D18F2xA4[BwCapEn]=1. The EVENT_L pin is used for thermal management while D18F2xA4[BwCapEn]
limits memory power independent of the thermal management solution.
The recommended BIOS configuration for the EVENT_L pin is as follows:
• BIOS may enable command throttling on a DRAM controller if the platform supports the EVENT_L pin by
programming D18F2xA4[ODTSEn] = 1.
• The recommended usage is for this pin to be connected to one or more JEDEC defined on DIMM temperature sensors. The DIMM SPD ROM indicates on DIMM temperature sensor support.
• BIOS configures the temperature sensor(s) to assert EVENT_L pin active low when the trip point is
exceeded and deassert EVENT_L when the temperature drops below the trip point minus the sensor
defined hysteresis.
• BIOS programs D18F2xA4[CmdThrottleMode] with the throttling mode to employ when the trip point
has been exceeded.
• The hardware enforces a refresh rate of 3.9 us while EVENT_L is asserted.
• BIOS configures D18F2x8C_dct[0][Tref] based on JEDEC defined temperature range options, as indicated
by the DIMM SPD ROM. The two defined temperature ranges are normal (with a case temperature of 85 °C)
and extended (with a case temperature of 95 °C). The following recommendation assumes JEDEC defined
SPD Byte 31[Extended Temperature Refresh Rate] = 1 devices will not be available in the near future.
• If all DIMMs support the normal temperature range, or if normal and extended temperature range
DIMMs are mixed, BIOS programs D18F2x8C_dct[0][Tref] to 7.8 us and D18F2xA4[ODTSEn] = 1, or
D18F2x8C_dct[0][Tref] to 3.9 us. BIOS configures the temperature sensor trip point for all DIMMs
according to the 85 °C case temperature specification.
• If all DIMMs support the extended temperature range, BIOS has two options:
a. Follow the recommendation for normal temperature range DIMMs.
b. Program D18F2x8C_dct[0][Tref] = 3.9 us and configure the temperature sensor trip point for all
DIMMs according to the 95 °C case temperature specification.
• At startup, the BIOS determines if the DRAMs are hot before enabling a DCT and delays for an amount of
time to allow the devices to cool under the influence of the thermal solution. This is accomplished by checking the temperature status in the temperature sensor of each DIMM.
• The DCT latched status of the EVENT_L pin for can be read by system software in D18F2xAC [DRAM
Controller Temperature Status].
The relationship between the DRAM case temperature, trip point, and EVENT_L pin sampling interval is outlined as follows:
• The trip point for each DIMM is ordinarily configured to the case temperature specification minus a guardband temperature for the DIMM.
• The temperature guardband is vendor defined and is used to account for sensor inaccuracy, EVENT_L pin
sample interval, and platform thermal design.
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• The sampling interval is vendor defined. It is expected to be approximately 1 second.
BIOS may enable bandwidth capping on a DRAM controller by setting D18F2xA4[BwCapEn] = 1 and programming D18F2xA4[BwCapCmdThrottleMode] with the throttling mode to employ. The DCT will employ
the larger of the two throttling percentages as specified by D18F2xA4[BwCapCmdThrottleMode] and
D18F2xA4[CmdThrottleMode] if the EVENT_L pin is asserted when both D18F2xA4[BwCapEn] = 1 and
D18F2xA4[ODTSEn] = 1.
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2.10 Thermal Functions
Thermal functions SB-TSI, HTC, PROCHOT_L and THERMTRIP are intended to maintain processor temperature in a valid range by:
• Providing a signal to external circuitry for system thermal management like fan control.
• Lowering power consumption by switching to lower-performance P-state.
• Sending processor to the THERMTRIP state to prevent it from damage.
The processor thermal-related circuitry includes (1) the temperature calculation circuit (TCC) for determining
the temperature of the processor and (2) logic that uses the temperature from the TCC. The processor includes
a thermal diode as an alternative method for temperature measurement when used with an external thermal
diode monitor. The thermal diode does not directly interact with the thermal functions.
2.10.1
The Tctl Temperature Scale
Tctl is a processor temperature control value used for processor thermal management. Tctl is accessible
through SB-TSI and D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the processors
cooling requirements. Therefore Tctl does not represent a temperature which could be measured on the die or
the case of the processor. Instead, it specifies the processor temperature relative to the maximum operating
temperature, Tctl,max. Tctl,max is specified in the power and thermal data sheet. Tctl,max is 70 C for lidded
processors and 100 C for lidless processors. Tctl is defined as follows for all parts:
A: For Tctl = Tctl_max to 255.875: the temperature of the part is [Tctl - Tctl_max] over the maximum operating temperature. The processor may take corrective actions that affect performance, such as HTC, to support
the return to Tctl range B.
B: For Tctl = 0 to Tctl_max - 0.125: the temperature of the part is [Tctl_max - Tctl] under the maximum operating temperature.
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Tctl
255.875
A
Maximum operating
temperature
Tctl_max
B
0.000
Figure 6: Tctl scale
2.10.2
Temperature Slew Rate Control
The temperature slew rate controls in D18F3xA4 are used to filter processor the processor temperature
provided in D18F3xA4[CurTmp] and through SB-TSI. Separate controls are provided for increasing and
decreasing temperatures. The latest measured temperature is referred to as Tctlm below.
If downward slew control is enabled (D18F3xA4[TmpSlewDnEn]), Tctl is not updated down unless Tctlm
remains below Tctl for a time specified by D18F3xA4[PerStepTimeDn]. If at any point before the timer expires
Tctlm equals or exceeds Tctl, then the timer resets and Tctl is not updated. If the timer expires, then Tctl is
reduced by 0.125. If downard slew control is disabled, then if Tctlm is less than Tctl, Tctl is immediately
updated to Tctlm.
The upward slew control works similar to downward slew control except that if Tctlm exceeds Tctl by a value
defined by D18F3xA4[TmpMaxDiffUp] then Tctl is immediately updated to Tctlm. Otherwise, Tctlm must
remain above Tctl for time specified by D18F3xA4[PerStepTimeUp] before Tctl is incremented by 0.125.
2.10.3
Temperature-Driven Logic
The temperature calculated by the TCC is used by SB-TSI, HTC, THERMTRIP, and PROCHOT_L.
2.10.3.1
PROCHOT_L and Hardware Thermal Control (HTC)
The processor HTC-active state is characterized by (1) the assertion of PROCHOT_L, (2) reduced power consumption, and (3) reduced performance. While in the HTC-active state, the processor reduces power consumption by limiting all cores to a P-state (specified by D18F3x64[HtcPstateLimit]). See 2.5.3 [CPU Power
Management]. While in the HTC-active state, software should not change the following: All D18F3x64 fields
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(except for HtcActSts and HtcEn), MSRC001_001F[DisProcHotPin]. Any change to the previous list of fields
when in the HTC-active state can result in undefined behavior. HTC status and control is provided through
D18F3x64.
The PROCHOT_L pin acts as both an input and as an open-drain output. As an output, PROCHOT_L is driven
low to indicate that the HTC-active state has been entered due to an internal condition, as described by the following text. The minimum assertion and deassertion time for PROCHOT_L is 15 ns.
The processor enters the HTC-active state if all of the following conditions are true:
• D18F3xE8[HtcCapable]=1
• D18F3x64[HtcEn]=1
• PWROK=1
• THERMTRIP_L=1
• The processor is not in the C3 ACPI state.
and any of the following conditions are true:
• Tctl is greater than or equal to the HTC temperature limit (D18F3x64[HtcTmpLmt]).
• PROCHOT_L=0
The processor exits the HTC-active state when all of the following are true:
• Tctl is less than the HTC temperature limit (D18F3x64[HtcTmpLmt]).
• Tctl has become less than the HTC temperature limit (D18F3x64[HtcTmpLmt]) minus the HTC hysteresis limit (D18F3x64[HtcHystLmt]) since being greater than or equal to the HTC temperature limit
(D18F3x64[HtcTmpLmt]).
• PROCHOT_L=1.
The default value of the HTC temperature threshold (Tctl_max) is specified in the Power and Thermal Datasheet.
2.10.3.2
Local Hardware Thermal Control (LHTC)
The LHTC-active state of a core is characterized by (1) reduced power consumption and (2) reduced performance of the core. While in the LHTC-active state, the core reduces power consumption by limiting the maximum P-state specified by D0F0xBC_x3FA1C[LhtcActivePstateLimit]. See 2.5.3.1 [Core P-states].
The LHTC trip point is the same for all cores and is specified by Fuse[LhtcTmpLmt]. The LHTC-active state is
independent from the HTC-active state. LHTC does not affect PROCHOT_L output and is not affected by
PROCHOT_L input.
A core enters the LHTC-active state if all of the following conditions are true:
• PWROK is asserted.
• The processor is not in the package C6 (PC6) state.
• Tctl maximum for all TCENs is greater than or equal to LHTC temperature limit (specified by
Fuse[LhtcTmpLmt]).
A core exits the LHTC-active state when all of the following are true:
• Tctl maximum for all TCENs is less than LHTC temperature low limit (specified by Fuse[LhtcHystLmt]) since being greater than or equal to the LHTC temperature high limit (specified by Fuse[LhtcTmpLmt]).
2.10.3.3
Software P-state Limit Control
D18F3x68 [Software P-state Limit] provides a software mechanism to limit the P-state MSRC001_0061[CurP-
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stateLimit]. See 2.5.3 [CPU Power Management].
2.10.3.4
THERMTRIP
If the processor supports the THERMTRIP state (as specified by D18F3xE4[ThermtpEn] or CPUID
Fn8000_0007_EDX[TTP], which are the same) and the temperature approaches the point at which the processor may be damaged, the processor enters the THERMTRIP state. The THERMTRIP function is enabled after
cold reset (after PWROK asserts and RESET_L deasserts). It remains enabled in all other processor states,
except during warm reset (while RESET_L is asserted). The THERMTRIP state is characterized as follows:
• The THERMTRIP_L signal is asserted.
• Nearly all clocks are gated off to reduce dynamic power.
• A low-value VID is generated. Specified by Fuse[ThermVid]; MSRC001_0071[MinVid] is ignored for this voltage transition.
• In addition, the external chipset is expected to place the system into the S5 ACPI state (power off) if
THERMTRIP_L is detected to be asserted.
A cold reset is required to exit the THERMTRIP state.
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2.11 Root Complex
2.11.1
Overview
NB
Bus 0
Device 0
Function 0
GNB Root Complex
Device 1
Function 0
Device 2
Function 0
Host Bridge Function
Internal Graphics
Device 1
Function 1
HD Audio
Device 2
Function 1
PCIe GPP Bridge 0
Device 2
Function 2
PCIe GPP Bridge 1
Device 2
Function 3
PCIe GPP Bridge 2
Device 2
Function 4
PCIe GPP Bridge 3
Device 2
Function 5
PCIe GPP Bridge 4
Figure 7: Root complex topology
2.11.2
Interrupt Routing
The GNB includes a fully programmable IOAPIC. The IOAPIC registers are accessed through the D0F0xF8
index and D0F0xFC data pair registers using two back-to-back config cycles. PCI defined INTx interrupts for
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each bridge are routed to IOAPIC pins via the bridge interrupt routing registers located at D0F0xFC_x1[4:0].
2.11.2.1
IOAPIC Configuration
The IOAPIC configuration is performed by the following sequence:
1. Set the base address for the memory mapped registers by programming D0F0xFC_x01[IoapicAddr] and
D0F0xFC_x02[IoapicAddrUpper].
2. Enable IOAPIC by programming D0F0xFC_x00[IoapicEnable] = 1.
3. Only if the system is in PIC mode, program D0F0xFC_x00[IoapicSbFeatureEn] = 1. This bit should be
programmed to 0 when the system is in APIC mode.
The IOAPIC has a total of 29 interrupt inputs. These inputs are as follows:
• 5 groups of PCIe interrupts each having a 4-bit external interrupt bus (INT A/B/C/D) and a 1-bit bridge interrupt, and
• a 4-bit external interrupt bus from GBIF.
The recommended interrupt routing and swizzling configuration is as shown in Table 61.
Table 61: Recommended Interrupt Routing and Swizzling Configuration
Device
Register
Setting
Description
Dev2Fn1
D0F0xFC_x10[BrExtIntrGrp]
0h
D0F0xFC_x10[BrExtIntrSwz]
0h
Map INT A/B/C/D to interrupt 0/1/2/3.
Map bridge interrupt to interrupt 24.
D0F0xFC_x10[BrIntIntrMap]
18h
D0F0xFC_x11[BrExtIntrGrp]
1h
D0F0xFC_x11[BrExtIntrSwz]
0h
D0F0xFC_x11[BrIntIntrMap]
19h
D0F0xFC_x12[BrExtIntrGrp]
2h
D0F0xFC_x12[BrExtIntrSwz]
0h
D0F0xFC_x12[BrIntIntrMap]
1Ah
D0F0xFC_x13[BrExtIntrGrp]
3h
D0F0xFC_x13[BrExtIntrSwz]
0h
D0F0xFC_x13[BrIntIntrMap]
1Bh
D0F0xFC_x14[BrExtIntrGrp]
4h
D0F0xFC_x14[BrExtIntrSwz]
0h
D0F0xFC_x14[BrIntIntrMap]
18h
D0F0xFC_x0F[GBIFExtIntrGrp]
5h
D0F0xFC_x0F[GBIFExtIntrSwz]
0h
Dev2Fn2
Dev2Fn3
Dev2Fn4
Dev2Fn5
GBIF
2.11.3
2.11.3.1
Map INT A/B/C/D to interrupt 4/5/6/7.
Map bridge interrupt to interrupt 25.
Map INT A/B/C/D to interrupt 8/9/10/11.
Map bridge interrupt to interrupt 26.
Map INT A/B/C/D to interrupt 12/13/14/15.
Map bridge interrupt to interrupt 27.
Map INT A/B/C/D to interrupt 16/17/18/19.
Map bridge interrupt to interrupt 24.
Map INT A/B/C/D to interrupt 20/21/22/23.
Links
Overview
There is one 5 x8 PCIe core with five configurable ports. These ports can be divided into 2 groups:
• Gfx: Contains 1 x4 port to create a 4-bit Gfx lane using the upper 4 lanes of the PCIe core.
• GPP: Contains upto 4 General Purpose Ports (GPP) using the lower 4 lanes of the PCIe core.
All PCIe links are capable of supporting Gen1/Gen2 data rates. Function 0 in Device 2 does not control any
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hardware. It is always enabled and allows software to scan through all the functions of the device.
Gfx and GPP ports each have a Type 1 Virtual PCI-to-PCI bridge header in the PCI configuration space
mapped to devices according to Figure 7.
Each PCIe lane is assigned a unique lane ID that software uses to communicate configuration information to
the SMU. Table 88 shows the mapping between lane ID's and lanes.
2.11.3.2
Link Configurations
Lanes of the Gfx ports can be assigned to IO links.
• For each 1x lane, program D0F0xE4_x0130_0[C:8]04[StrapBifMaxPayloadSupport]=1h. Max Payload Support = 256 for performance.
The following link configurations are supported for the GPP links:
Table 62: Supported General Purpose (GPP) Link Configurations
D0F0xE4
x0130_0080 x0110_0011
GPP Port Lane
Lanes[7:4]
3
0000_0001h 0000_0300h x4 Link (Gfx)
0000_0002h 0000_0203h x4 Link (Gfx)
2
1
0
x4 Link
x2 Link
0000_0003h 0000_0201h x4 Link (Gfx) x1 Link x1 Link
x2 Link
x2 Link
0000_0004h 0000_0200h x4 Link (Gfx) x1 Link x1 Link x1 Link x1 Link
2.11.4
2.11.4.1
Root Complex Configuration
LPC MMIO Requirements
To ensure proper operation of LPC generated DMA requests, the FCH must be configured to send processor
generated MMIO writes that target the LPC bus to the FCH as non-posted writes. The MMIO address space of
the LPC bus must not be included in the ranges specified by D18F1x[2CC:2A0,1CC:180,BC:80] [MMIO
Base/Limit] and non-posted protocol for memory writes must be enabled using the following programming
before LPC DMA transactions are initiated.
1. Program D0F0x98_x06[UmiNpMemWrEn] = 1.
2.11.4.2
Configuration for non-FCH Bridges
BIOS should program the following in non-FCH bridges:
1. Program D0F0xCC_x01[CrsEnable] = 1 for D0F0xC8[NbDevIndSel] = 11h-15h.
2. Program D0F0xCC_x01[SetPowEn] = 1 for D0F0xC8[NbDevIndSel] = 11h-15h.
2.11.4.3
Link Configuration and Initialization
Link configuration and initialization is performed by the fowllowing sequence:
1. 2.11.4.3.1 [Link Configuration and Core Initialization]
2. 2.11.4.3.2 [Link Training]
3. 2.11.4.5 [Link Power Management]
4. Lock link configuration registers.
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• Program D0F0xE4_x0140_0010[HwInitWrLock] = 1.
• Program D0F0x64_x00[HwInitWrLock] = 1.
2.11.4.3.1
Link Configuration and Core Initialization
Link configuration is done on a per link basis. Lane reversal, IO link selection, and lane enablement is configured through this sequence.
1. Place software-reset module into blocking mode:
A. Program D0F0xE4_x0130_8062[ConfigXferMode]=0.
B. Program D0F0xE4_x0130_8062[BlockOnIdle]=0.
2. If the link is an IO link, Program D0F0xE4_x0140_0011[DynClkLatency]=Fh.
3. Program D0F0xE4_x0130_0080 per Table 62.
4. Program D0F0xE4_x0130_802[4:1] per Table 62.
5. Program D0F0xE4_x0110_0010[RxDetectTxPwrMode]=1.
6. Program D0F0xE4_x0110_0010[Ls2ExitTime]=000b.
7. Program D0F0xE4_x0130_8013[MasterPciePllA, MasterPciePllB] per Table 62.
8. Initiate core reconfiguration sequence:
A. Program D0F0xE4_x0130_8062[ReconfigureEn]=1.
B. Program D0F0xE4_x0130_8060[Reconfigure]=1.
C. Wait for D0F0xE4_x0130_8060[Reconfigure]==0.
D. Program D0F0xE4_x0130_8062[ReconfigureEn]=0.
9. Return software-reset module to non-blocking mode:
A. Program D0F0xE4_x0130_8062[ConfigXferMode]=1.
10. Program D2F[5:1]xE4_xC1[StrapReverseLanes] if necessary.
11. Program D0F0xE4_x0110_0011 per Table 62.
12. For each nibble that has no PCIe lanes in use:
A. Program D0F0xE4_x0110_001[8:7,3:2][PllPowerStateInOff]=111b.
B. Program D0F0xE4_x0110_001[8:7,3:2][PllPowerStateInTxs2]=111b.
C. Program D0F0xE4_x0110_001[8:7,3:2][TxPowerStateInTxs2]=111b.
D. Program D0F0xE4_x0110_001[8:7,3:2][RxPowerStateInRxs2]=111b.
13. For each lane that is not in use, program the corresponding D0F0xE4_x0130_8029[LaneEnable]=0.
14. Configure PIF parings:
A. Program D0F0xE4_x0110_0011=0000_0300h.
2.11.4.3.2
Link Training
Link training is performed on a per link basis. BIOS may train the links in parallel.
2.11.4.4
2.11.4.4.1
Miscellaneous Features
Lane Reversal
Normally, the lanes of each port are physically numbered from n-1 to 0 where n is the number of lanes assigned
to the port. Physical lane numbering can be reversed according to the following methods:
• To reverse the physical lane numbering for a specific port, program D2F[5:1]xE4_xC1[StrapReverseLanes]=1.
• To reverse the physical lane numbering for all ports in the GPP or GFX interfaces, program
D0F0xE4_x0140_00C0[StrapReverseAll]=1.
Note that logical port numbering is established during link training regardless of the physical lane numbering.
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Link Speed Changes
Link speed changes can only occur on Gen2 capable links. To verify that Gen2 speeds are supported verify
D2F[5:1]x64[LinkSpeed]==02h.
2.11.4.4.2.1
Autonomous Link Speed Changes
To enable autonomous speed changes on a per port basis:
1. Program D2F[5:1]x88[TargetLinkSpeed]=2h.
2. Program D0F0xE4_x0130_0[C:8]03[StrapBifDeemphasisSel]=1.
3. Program D2F[5:1]xE4_xA4[LcGen2EnStrap]=1.
4. Program D2F[5:1]xE4_xC0[StrapAutoRcSpeedNegotiationDis]=0.
5. Program D2F[5:1]xE4_xA4[LcMultUpstreamAutoSpdChngEn]=1.
6. Program D2F[5:1]xE4_xA2[LcUpconfigureDis]=0.
2.11.4.4.3
Deemphasis
Deemphasis strength can be changed on a per-port basis by programming D2F[5:1]xE4_xB5[LcSelectDeemphasis].
2.11.4.5
2.11.4.5.1
Link Power Management
Link States
To enable support for L1 program D2F[5:1]xE4_xA0[LcL1Inactivity]=6h.
To enable support for L0s:
• Program D2F[5:1]xE4_xA1[LcDontGotoL0sifL1Armed]=1.
• Program D2F[5:1]xE4_xA0[LcL0sInactivity]=9h.
2.11.4.5.2
Dynamic Link-width Control
Dynamic link-width control is a power saving feature that reconfigures the link to run with fewer lanes. The
inactive lanes are turned off to conserve power.
The Gfx link can switch among widths of: x1, x2, and x4, upto the maximum programmed port width.
The GPP link can switch among widths of: x1, x2, and x4, upto the maximum programmed port width.
The link width is controlled by the following 3 mechanisms:
• Up/Down Reconfiguration: The link is retrained according to the PCI Express specification. This mechanism
is only available between Gen2 devices. .
The core has the capability to turn off the inactive lanes of trained links. To enable this feature program
D2F[5:1]xE4_xA2[LcDynLanesPwrState]=11b.
2.11.4.6
2.11.4.6.1
Link Test and Debug Features
Compliance Mode
To enable Gen1 software compliance mode program D2F[5:1]xE4_xC0[StrapForceCompliance]=1 for each
port to be placed in compliance mode.
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To enable Gen2 software compliance mode:
1. BIOS enables Gen2 capability by programming D0F0xE4_x0140_00C1[StrapGen2Compliance]=1.
2. Program D2F[5:1]xE4_xA4[LcGen2EnStrap]=1.
3. Program D2F[5:1]x88[TargetLinkSpeed]=2h for each port to be placed in compliance mode.
4. Program D2F[5:1]x88[EnterCompliance]=1 for each port to be placed in compliance mode.
2.11.5
BIOS Timer
The root complex implements a 32-bit microsecond timer (see D0F0xE4_x0130_80F0 and
D0F0xE4_x0130_80F1) that the BIOS can use to accurately time wait operations between initialization steps.
To ensure that BIOS waits a minimum number of microseconds between steps BIOS should always wait for
one microsecond more than the required minimum wait time.
2.11.6
PCIe Client Interface Control
This interface is accessed through the indexed space registers located at D0F2xF8 within the Device 0 Function 2 Configuration Registers.
BIOS should perform the following steps to initialize the interface:
1. Program D0F0x64_x0D[PciDev0Fn2RegEn] = 1h.
2. Program credits for the BIF client as follows:
A. Program D0F2xFC_x32_L1i[1][DmaNpHaltDis] = 1h.
B. Program D0F2xFC_x32_L1i[1][DmaBufCredits] = 8h.
C. Program D0F2xFC_x32_L1i[1][DmaBufMaxNpCred] = 8h.
3. Program credits for the PPD client as follows:
A. Program D0F2xFC_x32_L1i[0][DmaBufCredits] = 8h.
B. Program D0F2xFC_x32_L1i[0][DmaBufMaxNpCred] = 7h.
4. Program credits for the INTGEN client as follows:
A. Program D0F2xFC_x32_L1i[2][DmaBufCredits] = 4h.
B. Program D0F2xFC_x32_L1i[2][DmaBufMaxNpCred] = 4h.
5. Program clock gating as follows:
A. Program D0F2xFC_x33[L1DmaClkgateEn] = 1h.
B. Program D0F2xFC_x33[L1CacheClkgateEn] = 1h.
C. Program D0F2xFC_x33[L1CpslvClkgateEn] = 1h.
D. Program D0F2xFC_x33[L1DmaInputClkgateEn] = 1h.
E. Program D0F2xFC_x33[L1PerfClkgateEn] = 1h.
F. Program D0F2xFC_x33[L1MemoryClkgateEn] = 1h.
G. Program D0F2xFC_x33[L1RegClkgateEn] = 1h.
H. Program D0F2xFC_x33[L1HostreqClkgateEn] = 1h.
I. Program D0F2xFC_x33[L1L2ClkgateEn] = 1h.
6. Program D0F0x64_x0D[PciDev0Fn2RegEn] = 0h.
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2.12 System Management Unit (SMU)
The system management unit (SMU) is a subcomponent of the northbridge that is responsible for a variety of
system and power management tasks during boot and runtime. The SMU contains a Lattice LM32 microcontroller to assist with many of these tasks.
2.12.1
Software Interrupts
The microcontroller can be interrupted to cause it to perform several initialization and runtime tasks. BIOS and
ACPI methods can interrupt the SMU to request a specific action using the following sequence:
1. If a service request requires an argument, program D0F0xBC_xC210_003C[Argument] with the desired
argument.
1. Wait for D0F0xBC_xC210_0004[IntDone]==1.
2. Program D0F0xBC_xC210_0000[ServiceIndex] to the desired service index and toggle. This may be done
in a single write.
3. Wait for D0F0xBC_xC210_0004[IntAck]==1.
After performing the steps above, software may continue execution before the interrupt has been serviced.
However, software should not rely on the results of the interrupt until the service is complete (see
D0F0xBC_xC210_0004[IntDone]). Interrupting the SMU with a service index that does not exist results in
undefined behavior.
Table 63: SMU Software Interrupts
Service
Index
Notes
Description: BIOSSMC_MSG_LCLK_DPM_ENABLE. Enables LCLK DPM.
See 2.5.6.1.3 [LCLK DPM].
1Eh
Input: D0F0xBC_x3FDC8
Output: None.
Description: BIOSSMC_MSG_VDDNB_REQUEST. Request VDDNB voltage.
3Ah
Input:Program argument to desired voltage (encoded in mV with two fraction bits). Values outside
D18F5x17C[MaxVid, MinVid] range are invalid and result in undefined behavior.
• D0F0xBC_xC210_003C[Argument] = (Desired Voltage in mV) * 4.
Output: None.
Description: BIOSSMC_MSG_NBDPM_Enable. Enables NB P-state Adjustments.
43h
Input: D0F0xBC_x3F9E8
Output: D0F0xBC_x3F9EC
2.13 Graphics Processor (GPU)
The APU contains an integrated DX11 compliant graphics processor.
2.13.1
Graphics Memory Controller (GMC)
The graphics memory controller is responsible for servicing memory requests from the different blocks within
the GPU and forwarding routing them to the appropriate interface. The GMC is also responsible for translating
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GPU virtual address to GPU physical addresses and for translating GPU physical addresses to system
addresses.
2.13.2
Frame Buffer (FB)
The frame buffer is defined as the portion of system memory dedicated for GPU use.
Table 64: Recommended Frame Buffer Configurations
System Memory Size
< 1GB
>= 1GB & < 2GB
>= 2GB
Frame Buffer Size
64 MB
256 MB
512 MB
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2.14 RAS Features
2.14.1
Machine Check Architecture
The processor contains logic and registers to detect, log, and correct errors in the data or control paths in each
core and the Northbridge. The Machine Check Architecture (MCA) defines the facilities by which processor
and system hardware errors are logged and reported to system software. This allows system software to perform a strategic role in recovery from and diagnosis of hardware errors.
Refer to the AMD64 Architecture Programmer's Manual for an architectural overview and methods for determining the processor’s level of MCA support. See 1.2 [Reference Documents].
The ability of hardware to generate a machine check exception upon an error is indicated by CPUID
Fn0000_0001_EDX[MCE] or CPUID Fn8000_0001_EDX[MCE].
2.14.1.1
Machine Check Registers
CPUID Fn0000_0001_EDX[MCA] or CPUID Fn8000_0001_EDX[MCA] indicates the presence of the following machine check registers:
• MSR0000_0179 [Global Machine Check Capabilities (MCG_CAP)]
• Reports how many machine check register banks are supported.
• MSR0000_017A [Global Machine Check Status (MCG_STAT)]
• Provides basic information about processor state after the occurence of a machine check error.
• MSR0000_017B [Global Machine Check Exception Reporting Control (MCG_CTL)]
• Used by software to enable or disable the logging and reporting of machine check errors in the errorreporting banks.
The error-reporting machine check register banks supported in this processor are:
• MC0: Data cache (DC).
• MC1: Instruction cache (IC).
• MC2: Bus unit (BU), including L2 cache.
• MC3: Reserved.
• MC4: Northbridge (NB), including the IO link. These MSRs are also accessible from configuration
space. There is only one NB error-reporting bank, independent of the number of cores.
• MC5: Fixed-issue reorder buffer (FR) machine check registers.
• The register types within each bank are:
• MCi_CTL, Machine Check Control: Enables error reporting via machine check exception. The
MCi_CTL register in each bank must be enabled by the corresponding enable bit in MCG_CTL
(MSR0000_017B).
• MCi_STATUS, Machine Check Status: Logs information associated with errors.
• MCi_ADDR, Machine Check Address: Logs address information associated with errors.
• MCi_MISC, Machine Check Miscellaneous: Log miscellaneous information associated with errors, as
defined by each error type.
• MCi_CTL_MASK, Machine Check Control Mask: Inhibit detection of an error source unless otherwise
specified.
The following table identifies the registers associated with each error-reporting machine check register bank:
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Table 65: MCA register cross-reference table
Register
Bank
(MCi)
MCA Register
CTL
STATUS
ADDR
MISC
CTL_MASK
MC0
MSR0000_0400 MSR0000_0401 MSR0000_0402 MSR0000_0403
MSRC001_0044
MC1
MSR0000_0404 MSR0000_0405 MSR0000_0406 MSR0000_0407
MSRC001_0045
MC2
MSR0000_0408 MSR0000_0409 MSR0000_040A MSR0000_040B
MSRC001_0046
MC3
MSR0000_040C MSR0000_040D MSR0000_040E MSR0000_040F
MSRC001_0047
MC4
MSR0000_0410 MSR0000_0411 MSR0000_0412 MSR0000_0413
MSRC001_0048
MC5
MSR0000_0414 MSR0000_0415 MSR0000_0416 MSR0000_0417
MSRC001_0049
Corrected, deferred, and uncorrected errors are logged in MCi_STATUS and MCi_ADDR as they occur.
Uncorrected errors that are enabled in MCi_CTL result in a Machine Check exception.
Each MCi_CTL register must be enabled by the corresponding enable bit in MSR0000_017B [Global Machine
Check Exception Reporting Control (MCG_CTL)].
MCi_CTL_MASK allow BIOS to mask the presence of any error source from software for test and debug.
When error sources are masked, it is as if the error was not detected. Such masking consequently prevents error
responses and actions.
Each MCA bank implements a number of machine check miscellaneous registers, denoted as MCi_MISCj,
where j goes from 0 to a maximum of 8. If there is more than one MCi_MISC register in a given bank, a nonzero value in MCi_MISC0[BlkPtr] points to the contiguous block of additional registers.
The presence of valid information in the first MISC register in the bank (MCi_MISC0) is indicated by
MCi_STATUS[MiscV]. The presence of valid information in additional implemented MISC registers is indicated by MCi_MISCj[Val] in the target register.
2.14.1.2
Machine Check Errors
The classes of machine check errors are, in priority order from highest to lowest:
• Uncorrected
• Deferred
• Corrected
Uncorrected errors cannot be corrected by hardware and may cause loss of data, corruption of processor state,
or both. Uncorrected errors update the status and address registers if not masked from logging in
MCi_CTL_MASK. Information in the status and address registers from a previously logged lower priority
error is overwritten. Previously logged errors of the same priority are not overwritten. Uncorrected errors that
are enabled in MCi_CTL result in reporting to software via machine check exceptions. If an uncorrected error
is masked from logging, the error is ignored by hardware (exceptions are noted in the register definitions). If an
uncorrected error is disabled from reporting, containment of the error and logging/reporting of subsequent
errors may be affected. Therefore, enable reporting of unmasked uncorrected errors for normal operation. Disable reporting of uncorrected errors only for debug purposes.
Deferred errors are errors that cannot be corrected by hardware, but do not cause an immediate interruption in
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program flow, loss of data integrity, or corruption of processor state. These errors indicate that data has been
corrupted but not consumed; no exception is generated because the data has not been referenced by a core or an
IO link. Hardware writes information to the status and address registers in the corresponding bank that identifies the source of the error if deferred errors are enabled for logging. If there is information in the status and
address registers from a previously logged lower priority error, it is overwritten. Previously logged errors of the
same or higher priority are not overwritten. Deferred errors are not reported via machine check exceptions;
they can be seen by polling the MCi_STATUS registers.
Corrected errors are those which have been corrected by hardware and cause no loss of data or corruption of
processor state. Hardware writes the status and address registers in the corresponding register bank with information that identifies the source of the error if they are enabled for logging. Corrected errors are not reported
via machine check exceptions. Some corrected errors may be reported to software via error thresholding (see
2.14.1.7 [Error Thresholding]).
The implications of these categories of errors are:
1. Uncorrected error; hardware did not deal with the problem.
• Operationally (error handling), action required, because program flow is affected.
• Diagnostically (fault management), software may collect information to determine if any components
should be de-configured or serviced.
2. Deferred error; hardware partially dealt with the problem via containment.
• Operationally, action optional, because program flow has not been affected. However, steps may be
taken by software to prevent access to the data in error.
• Diagnostically, software may collect information to determine if any components should be de-configured or serviced.
3. Corrected error; hardware dealt with the problem.
• Operationally, no action required, because program flow is unaffected.
• Diagnostically, software may collect information to determine if any components should be de-configured or serviced.
Machine check conditions can be simulated to aid in debugging machine check handlers. See 2.14.3 [Error
Injection and Simulation] for more detail.
2.14.1.3
Error Detection, Action, Logging, and Reporting
Error detection is controlled by the MASK registers:
• Error detection for MCA controlled errors is enabled if not masked by MCi_CTL_MASK (see Table 65
[MCA register cross-reference table]).
• Error masking is performed regardless of MCA bank enablement in MCG_CTL (MSR0000_017B).
Error action refers to the hardware response to an error, aside from logging and reporting. Enablement of error
action for each error is enumerated in the EAC (Error Action Condition) column of the error descriptions tables
as follows:
• D: Detected. The error action is taken if the error is detected (i.e., not masked). These actions occur
regardless of whether the MCA bank is enabled in MCG_CTL.
• E: Enabled. The error action is taken if the error is detected and the bank is enabled in MCG_CTL.
Error logging refers to the storing of information in the status registers, and is enabled if all of the following are
true:
• Error detection is enabled.
• The MCA bank is enabled in MCG_CTL.
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Error reporting refers to active notification of errors to software via machine check exceptions, and is enabled
if all of the following are true:
• Error logging is enabled.
• The corresponding enable bit for the error in MCi_CTL is set to 1.
A machine check exception will be generated if all the following are true:
• The error is uncorrected.
• The error is enabled for reporting.
• CR4.MCE is enabled.
Notes:
1. If CR4.MCE is clear, an error configured to cause a machine check exception will cause a shutdown.
2. If error reporting is disabled, the setting of CR4.MCE has no effect.
3. If an uncorrected error is disabled from reporting, containment of the error and logging/reporting of subsequent errors may be affected. Therefore, unmasked uncorrected errors should be enabled for reporting for
normal operation. Uncorrected errors should only be disabled from reporting for debug purposes.
4. Errors not associated with a specific core are reflected to core 0 of the compute unit. The error description
tables identify which errors are associated or not associated with a specific core of the compute unit.
Throughout the MCA register descriptions, the terms “enabled” and “disabled” generally refer to reporting,
and the terms “masked” and “unmasked” generally refer to logging, unless otherwise noted.
Some logged errors increment a counter in MCi_MISC, which may trigger an interrupt (see 2.14.1.7 [Error
Thresholding]). Although no machine check exception will be generated, these notifications can be viewed as
“correctable machine check interrupts”.
For debug observability only, D18F3x180[ConvertUnCorToCorErrEn] can be used to log NB uncorrected
errors as corrected errors.
2.14.1.3.1
MCA conditions that cause Shutdown
The following architectural conditions cause the processor to enter the Shutdown state; see section “MachineCheck Errors” in APM volume 2 for more detail; see 1.2 [Reference Documents]:
• Attempting to generate an MCE when machine check reporting is disabled at the system level
(CR4.MCE=0).
• Attempting to generate an MCE when a machine check is in progess on the same core
(MSR0000_017A[MCIP]=1).
The following non-architectural conditions cause the processor to enter the Shutdown state:
• On MCA interrupts, if two or more uncorrected errors occur across MCA banks.
2.14.1.3.2
Error Logging During Overflow
An error to be logged when the status register contains valid data can result in an overflow condition. During
error overflow conditions, the new error may not be logged or an error which has already been logged in the
status register may be overwritten. For the rules on error overflow, priority, and overwriting, see
MSR0000_0401[Overflow].
Overflow alone does not indicate a shutdown condition. Uncorrected errors require software intervention.
Therefore, when an uncorrected error cannot be logged, critical error information may have been lost, and
MCi_STATUS[PCC] may be set. If PCC is indicated, software should terminate system processing to prevent
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data corruption (see 2.14.1.6 [Handling Machine Check Exceptions]). If PCC is not indicated, any MCA data
lost due to overflow was informational only and not critical to system hardware operation.
Table 66: Overwrite Priorities for All Banks
Older Error
Uncorrected
Enabled
Disabled
Newer
Error
2.14.1.4
Uncorrected
Corrected
Enabled
-1
-1
Disabled
-1
-
-1
-
Enabled
Disabled
Corrected
Enabled
Disabled
Overwrite Overwrite
Overwrite Overwrite
-
-
MCA Initialization
The following initialization sequence must be followed:
• MCi_CTL_MASK registers (see Table 65 [MCA register cross-reference table] for list):
• BIOS must initialize the mask registers to inhibit error detection prior to the initialization of
MCi_CTL and MSR0000_017B.
• BIOS must not clear MASK bits that are reset to 1.
• The MCi_CTL registers must be initialized by the operating system prior to enabling the error reporting
banks in MCG_CTL.
If initializing after a cold reset (see D18F0x6C[ColdRstDet]), then BIOS must clear the MCi_STATUS MSRs.
If initializing after a warm reset, then BIOS should check for valid MCA errors and if present save the status
for later diagnostic use (see 2.14.1.6 [Handling Machine Check Exceptions]).
BIOS may initialize the MCA without setting CR4.MCE; this will result in a system shutdown on any machine
check which would have caused a machine check exception (followed by a reboot if configured in the chipset).
Alternatively, BIOS that wishes to ensure continued operation in the event that a machine check occurs during
boot may write MCG_CTL with all ones and write zeros into each MCi_CTL. With these settings, a machine
check error will result in MCi_STATUS being written without generating a machine check exception or a system shutdown. BIOS may then poll MCi_STATUS during critical sections of boot to ensure system integrity.
Before passing control to the operating system, BIOS should restore the values of those registers to what the
operating system is expecting. (Note that using MCi_CTL to disable error reporting on uncorrected errors may
affect error containment; see 2.14.1.3 [Error Detection, Action, Logging, and Reporting].)
Before ECC memory has been initialized with valid ECC check bits, BIOS must ensure that no memory operations are initiated if MCA reporting is enabled. This includes memory operations that may be initiated by hardware prefetching or other speculative execution. It is recommended that, until all of memory has been
initialized with valid ECC check bits, the BIOS either does not have any valid MTRRs specifying a DRAM
memory type or does not enable DRAM ECC machine check exceptions.
2.14.1.5
Error Code
The MCi_STATUS[ErrorCode] field contains information used to identify the logged error. Table 67 [Error
Code Types] identifies how to decode ErrorCode. The MCi_STATUS[ErrorCodeExt] field contains detailed,
model-specific information that is used to further narrow identification for error diagnosis, but not error handling by software; see 2.14.1.6 [Handling Machine Check Exceptions].
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For a given error-reporting bank, Error Code Type is used in conjunction with the Extended Error Code
(MCi_STATUS[ErrorCodeExt]) to uniquely identify the Error Type; the value of ErrorCodeExt is unique
within Error Code Type. Details for each Error Type are described in the tables accompanying the
MCi_STATUS register for each bank.
• MC0 (DC); Table 196 [MC0 Error Signatures].
• MC1 (IC); Table 199 [MC1 Error Signatures].
• MC2 (BU); Table 202 [MC2 Error Signatures]
• MC4 (NB);Table 205 [MC4 Error Signatures, Part 1] and Table 206 [MC4 Error Signatures, Part 2].
• MC5 (FR); Table 214 [MC5 Error Signatures].
Table 67: Error Code Types
Error Code
Error Code Type Description
0000 0000 0001 TTLL TLB
TT = Transaction Type
LL = Cache Level
0000 0001 RRRR TTLL Memory
Errors in the cache hierarchy (not in NB)
RRRR = Memory Transaction Type
TT = Transaction Type
LL = Cache Level
0000 1PPT RRRR IILL Bus
General bus errors including link and DRAM
PP = Participation Processor
T = Timeout
RRRR = Memory Transaction Type
II = Memory or IO
LL = Cache Level
0000 01UU 0000 0000 Internal Unclassi- Internal unclassified errors
fied
UU = Internal Error Type
Table 68: Error codes: transaction type (TT)
TT
00
01
10
11
Transaction Type
Instr: Instruction
Data
Gen: Generic
Reserved
Table 69: Error codes: cache level (LL)
LL
00
01
10
11
Cache Level
L0: Emulation memory
L1: Level 1
L2: Level 2
LG: Generic
Table 70: Error codes: memory transaction type (RRRR)
RRRR Memory Transaction Type
0000 Gen: Generic. Includes scrub errors.
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Table 70: Error codes: memory transaction type (RRRR)
RRRR
0001
0010
0011
0100
0101
0110
0111
1000
Memory Transaction Type
RD: Generic Read
WR: Generic Write
DRD: Data Read
DWR: Data Write
IRD: Instruction Fetch
Prefetch
Evict
Snoop (Probe)
Table 71: Error codes: participation processor (PP)
PP
00
01
10
11
Participation Processor
SRC: Local node originated the request
RES: Local node responded to the request
OBS: Local node observed the error as a third party
Generic
Table 72: Error codes: memory or IO (II)
II
00
01
10
11
Memory or IO
Mem: Memory Access
Reserved
IO: IO Access
Gen: Generic
Table 73: Error codes: Internal Error Type (UU)
UU
00
01
10
11
2.14.1.6
Internal Error Type
Reserved
Reserved
HWA: Hardware Assertion
Reserved
Handling Machine Check Exceptions
A machine check handler is invoked to handle an exception for a particular core. Because MCA registers are
generally not shared among cores, the handler does not need to coordinate register usage with handler instances
on other cores. Those few MCA registers which are shared are noted in the register description. (See also
2.4.2.1 [Registers Shared by Cores in a L2 complex].)
For access to the core MC2 registers, MSRC001_10A0[McaToMstCoreEn] allows a single core to access the
registers through MSR space without contention from other cores. This organization of registers on a per core
basis allows independent execution, simplifies exception handling, and reduces the number of conditions
which are globally fatal.
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For access to the NB MCA registers, D18F3x44[NbMcaToMstCpuEn] allows a single core (the NBC) to
access the registers through MSR space without contention from other cores. This organization of registers on
a per core basis allows independent execution, simplifies exception handling, and reduces the number of conditions which are globally fatal.
At a minimum, the machine check handler must be capable of logging error information for later examination.
The handler should log as much information as is needed to diagnose the error.
More thorough exception handler implementations can analyze errors to determine if each error is recoverable
by software. If a recoverable error is identified, the exception handler can attempt to correct the error and
restart the interrupted program. An error may not be recoverable for the process or virtual machine it directly
affects, but may be containable, so that other processes or virtual machines in the system are unaffected and
system operation is recovered; see 2.14.1.6.1 [Differentiation Between System-Fatal and Process-Fatal Errors].
Machine check exception handlers that attempt to recover must be thorough in their analysis and the corrective
actions they take. The following guidelines should be used when writing such a handler:
• Data collection:
• All status registers in all error reporting banks must be examined to identify the cause of the machine
check exception.
• Read MSR0000_0179[Count] to determine the number of status registers visible to the core. The status registers are numbered from 0 to one less than the value found in MSR0000_0179[Count]. For
example, if the Count field indicates five status registers are supported, they are numbered
MC0_STATUS to MC4_STATUS. These are generically referred to as MCi_STATUS.
• Check the valid bit in each status register (MCi_STATUS[Val]). The remainder of the status register
should be examined only when its valid bit is set.
• When identifying the error condition and determining how to handle the error, portable exception
handlers should examine the following MCi_STATUS fields: ErrorCode, UC, PCC, CECC, UECC,
Deferred, Poison. The expected settings of these and other fields in MCi_STATUS are identified in
the error signatures tables which accompany the descriptions of each MCA status register. See
2.14.1.5 [Error Code] for a discussion of error codes and pointers to the error signatures tables.
• MCi_STATUS[ErrorCodeExt] should generally not be used by portable code to identify the
error condition because it is model specific. ErrorCodeExt is useful in determining the error subtype for root cause analysis.
• Error handlers should collect all available MCA information (status register, address register, miscellaneous register, etc.), but should only interrogate details to the level which affects their actions.
Lower level details may be useful for diagnosis and root cause analysis, but not for error handling.
• Recovery:
• Check the valid MCi_STATUS registers to see if error recovery is possible.
• Error recovery is not possible when the processor context corrupt indicator (MCi_STATUS[PCC]) is
set to 1.
• The error overflow status indicator (MCi_STATUS[Overflow]) does not indicate whether error
recovery is possible. See 2.14.1.3.2 [Error Logging During Overflow].
• If error recovery is not possible, the handler should log the error information and return to the operating system for system termination.
• Check MCi_STATUS[UC] to see if the processor corrected the error. If UC is set, the processor did not
correct the error, and the exception handler must correct the error prior to attempting to restart the interrupted program. If the handler cannot correct the error, it should log the error information and return to
the operating system. If the error affects only process data, it may be possible to terminate only the
affected process or virtual machine. If the error affects processor state, continued use of that processor
should not occur. See individual error descriptions for further guidance.
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• If MSR0000_017A[RIPV] is set, the interrupted program can be restarted reliably at the instruction
pointer address pushed onto the exception handler stack if any uncorrected error has been corrected by
software. If RIPV is clear, the interrupted program cannot be restarted reliably, although it may be possible to restart it for debugging purposes. As long as PCC is clear, it may be possible to terminate only the
affected process or virtual machine.
• When logging errors, particularly those that are not recoverable, check MSR0000_017A[EIPV] to see if
the instruction pointer address pushed onto the exception handler stack is related to the machine check. If
EIPV is clear, the address is not ensured to be related to the error.
• See 2.14.1.6.1 [Differentiation Between System-Fatal and Process-Fatal Errors] for more explanation on
the relationship between PCC, RIPV, and EIPV.
• Exit:
• When an exception handler is able to successfully log an error condition, clear the MCi_STATUS registers prior to exiting the machine check handler. Software is responsible for clearing at least
MCi_STATUS[Val].
• Prior to exiting the machine check handler, be sure to clear MSR0000_017A[MCIP]. MCIP indicates
that a machine check exception is in progress. If this bit is set when another machine check exception
occurs in the same core, the processor enters the shutdown state.
Additional machine check handler portability can be added by having the handler use the CPUID instruction to
identify the processor and its capabilities. Implementation specific software can be added to the machine check
exception handler based on the processor information reported by CPUID.
In cases where sync flood is the recommended response to a particular error, a machine check exception cannot
be used in lieu of the sync flood to stop the propagation of potentially bad data.
2.14.1.6.1
Differentiation Between System-Fatal and Process-Fatal Errors
The bits MCi_STATUS[PCC], MSR0000_017A[RIPV], and MSR0000_017A[EIPV] form a hierarchy, used
by software to determine the degree of corruption and recoverability in the system.
Table 74 shows how these bits are interpreted.
Table 74: Error Scope Hierarchy
PCC UC
1 1
0
1
RIPV EIPV
-
1
1
Deferred Poison Comments
System fatal error. Signaled via machine check exception, action required. Error has corrupted system state
(PCC=1). The error is fatal to the system and the system
processing must be terminated.
RIPV=1, EIPV=0: Should not occur. Restartable
errors will indicate the instruction in error in EIP.
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Table 74: Error Scope Hierarchy
PCC UC
0 1
RIPV EIPV
0
-
Deferred Poison Comments
0/1
Hardware uncorrected, software containable error.
Signaled via machine check exception, action required.
The error is confined to the process, however the process cannot be restarted even if the uncorrected error is
corrected by software.
0
0
-
-
1
0
0
0
-
-
0
0
2.14.1.7
Poison=1; the error is due to consumption of poison
data. If the affected process or virtual machine is terminated, the system may continue operation.
Deferred error. Action optional. A latent error has been
discovered, but not yet consumed; a machine check
exception will be generated if the affected data is consumed. Error handling software may attempt to correct
this data error, or prevent access by processes which
map the data, or make the physical resource containing
the data inaccessible.
Note: May be detected on a demand access or a scrub
access.
Corrected error.
Signaled via error thresholding mechanisms (2.14.1.7
[Error Thresholding]); no action required.
Error Thresholding
For some types of errors, the hardware maintains counts of the number of errors. When the counter reaches a
programmable threshold, an event may optionally be triggered to signal software. This is known as error
thresholding. The primary purpose of error thresholding is to help software recognize an excessive rate of
errors, which may indicate marginal or failing hardware. This information can be used to make decisions about
deconfiguring hardware or scheduling service actions. Counts are incremented for corrected, deferred, and
uncorrected errors.
The error thresholding hardware counts only the number of errors; it is up to software to track the errors
reported over time in order to determine the rate of errors. Thresholding gives error counts on groups of
resources. In order to make decisions on individual resources, a finer granularity of error information, such as
MCA information for specific errors, must be utilized in order to obtain more accurate counts and to limit the
scope of actions to affected hardware.
Thresholding is performed for “Error Threshold Groups” identified in the list below. For all error threshold
groups, some number of corrected errors is expected and normal. There are numerous factors influencing error
rates, including temperature, voltage, operating speed, and geographic location. The determination of expected
error rates is heuristic, with recommended error rates defined below. Although these recommendations are
deliberately conservative, they may need to be adjusted if operating in extreme conditions. In addition, the normal error rates are for long term averages and it may not be abnormal for bursts to occur. In order to accommodate the various factors, including software latency to respond and track the error thresholding, additional
guardband above the normal rates is recommended before error rates are considered abnormal for purposes of
hardware action. These recommendations are for error thresholding purposes, and are not design parameters.
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The {MC0, MC1, MC2, MC5} error thresholding banks maintains counters, but do not provide interrupts
when the threshold is reached; these counters must be polled.
Error thresholding groups:
• DRAM (MC4)
• Memory errors are counted and polled or reported via MSR0000_0413.
• DRAM errors are the errors listed in Table 204 [MC4 Error Descriptions] as “D” (DRAM) in the ETG
(Error Threshold Group) column.
• Operating systems can avoid or stop using memory pages with excessive errors.
• Links (MC4)
• Link errors are counted and reported via MSRC000_0408.
• Link errors are the errors listed in Table 204 [MC4 Error Descriptions] as “L” (Cache) in the ETG (Error
Threshold Group) column.
• For a link exhibiting excessive errors, it may be possible to reduce errors by lowering the link frequency
or reducing the link width (if a bad lane can be avoided). See 2.11 [Root Complex] for details and restrictions on configuring links.
In rare circumstances, such as two simultaneous errors in the same error thresholding group, it is possible for
one error not to increment the counter. In these conditions, MCi_STATUS[Overflow] may indicate that an
overflow occurred, but the error counter may only indicate one error.
2.14.1.8
Scrub Rate Considerations
This section gives guidelines for the scrub rate settings available in D18F3x58 [Scrub Rate Control] and
MSRC001_10A0 [L2I Configuration (L2I_CFG)]. Scrubbers are used to periodically read cacheline sized data
locations and associated tags. There are two primary benefits to scrubbing. First, scrubbing corrects any corrected errors which are discovered before they can migrate into uncorrected errors. This is particularly important for soft errors, which are caused by external sources such as radiation and which are temporary conditions
which do not indicate malfunctioning hardware. Second, scrubbers help identify marginal or failed hardware
by finding and logging repeated errors at the same locations (see also 2.14.1.7 [Error Thresholding]).
There are many factors which influence scrub rates. Among these are:
• The size of memory or cache to be scrubbed (higher rate for larger size)
• Resistance to upsets (higher rates for more sensitive technologies and lower voltages)
• Geographic location and altitude (higher rate for higher flux density of cosmic radiation)
• Alpha particle contribution of packaging (higher rate for less pure packaging)
• Performance sensitivity (lower rate for more performance sensitivity)
• Risk aversion (higher rate for higher risk aversion)
The baseline recommendations in Table 75 are intended to provide excellent protection at most geographic
locations, while having no measurable effect on performance or power consumption. DRAM:
F3x58[DramScrub] should be set to scrub all of memory every 24 hours, unless other guidelines are given by
the DRAM vendor. Adjustments may be necessary due to special circumstances. Refer to JEDEC standards for
guidelines on adjusting for geographic location.
Table 75: Recommended Scrub Rates per Node
Register
MSRC001_10A0[L2ScrubberInterval]
Memory Size per Node (GB)
-
Register Setting
100h
Scrub Rate
98.6 ms
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Table 75: Recommended Scrub Rates per Node
Register
D18F3x58[DramScrub]
Memory Size per Node (GB)
0 GB == Size
0 GB < Size <= 1 GB
1 GB < Size <= 2 GB
2 GB < Size <= 4 GB
4 GB < Size <= 8 GB
8 GB < Size <= 16 GB
16 GB < Size <= 32 GB
32 GB < Size <= 64 GB
64 GB < Size <= 128 GB
128 GB < Size <= 256 GB
256 GB < Size
Register Setting
00h
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
Scrub Rate
Disabled
5.24 ms
2.62 ms
1.31 ms
655.4 us
327.7 us
163.8 us
81.9 us
41.0 us
20.5 us
10.2 us
For steady state operation, finding a range of useful scrub rates may be performed by selecting a scrub rate
which is high enough to give good confidence about protection from accumulating errors and low enough that
it has no measurable effect on performance. The above baselines are made to maximize error coverage without
affecting performance and not based on specific processor soft error rates.
For low power states in which the processor core is halted, the power management configuration may affect
scrubbing; see 2.8.3 [Memory Scrubbers].
2.14.1.9
Error Diagnosis
This section describes generalized information and algorithms for diagnosing errors. The primary goal of diagnosis is to identify the failing component for repair purposes. The secondary goal is to identify the smallest
possible sub-component for deallocation, deconfiguration, or design/manufacturing root cause analysis.
Indictment means identifying the part in error. The simplest form of indictment is self-indictment, where the
bank reporting the error is the faulty unit. The next simplest form of indictment is eyewitness indictment, where
the faulty unit is not the bank reporting the error, but is identified unambiguously. Both of these forms can be
considered direct indictment; the information for indictment is contained in the MCA error information. If an
error is not directly indicted, then identifying the faulty unit is more difficult and may not be an explicit part of
the error log.
In general, an address logged in the MCA is useful for direct indictment only if the address identifies a physical
location in error, such as a cache index. Logical addresses, while identifying the data, do not identify the location of the data.
If possible, physical storage locations in caches should be checked to determine whether the error is a soft error
(a temporary upset of the stored value) or a hard fault (malfunctioning hardware). A location which has had a
soft error can be corrected by writing a new value to the location; a reread of the location should see the new
value. Hard faults cannot be corrected by writing a new value; the hardware persistently returns the previous
value. If such checking is not possible, a grossly simplifying assumption can be made that uncorrected errors
are hard and corrected errors are soft. Repeated corrected errors from the same location are an indication that
the fault is actually hard.
Determining whether corrected errors represent a hard fault or a soft error requires understanding the access
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patterns and any attempts to correct the faulty data in place. An attempt to correct the data in place creates two
epochs, one before the correction event, and one after. If an error is seen at the same location in two different
epochs (especially back-to-back epochs), it is more likely that the cause is a hard fault, since the error has persisted or repeated through an in place correction. The more epochs in which a error is seen, the higher the likelihood of it being caused by a hard fault.
As an example, consider a corrected error found during a read from DRAM. If the DRAM redirect scrubber is
enabled (D18F3x5C[ScrubReDirEn]), the data in error is corrected in place, and this event conceptually creates a new epoch. If the original fault was due to a soft error, a read of the same data in the new epoch should
not encounter a data error. If the original fault was due to a hard fault (e.g., a stuck bit), a read of the data in the
new epoch will likely result in another corrected or uncorrected error.
There are numerous correction events that can be used to separate time periods into epochs. These include
DRAM redirect scrubs, DRAM sequential scrubs, cache scrubs, cache writes, cache flushes, resets, and others.
2.14.1.9.1
Common Diagnosis Information
A common set of diagnosis information is useful for many problems. Table 76 indicates the minimum set of
generally useful diagnostic information that should be collected by software, unless the specifics of the problem are known to be narrower, based on the error code or other information.
It is useful to collect configuration information to ensure that the behavior is not caused by misconfiguration.
Table 76: Registers Commonly Used for Diagnosis
MCA
Status
Bank
MC0 MSR0000_0401
MSR0000_0402
MSR0000_0403
MC1 MSR0000_0405
MSR0000_0406
MSR0000_0407
MC2 MSR0000_0409
MSR0000_040A
MSR0000_040B
MC3 Reserved
MC4 MSR0000_0411
MSR0000_0412
MSR0000_0413
MSRC000_0408
D18F3x54
D18F2xAC
MC5
MSR0000_0415
MSR0000_0416
MSR0000_0417
Configuration
MSR0000_0400
MSRC001_1022
MSRC001_0044
MSR0000_0404
MSRC001_1021
MSR0000_0408
MSRC001_0046
MSRC001_1023
Reserved
MSR0000_0410
MSRC001_0048
D18F3x40
D18F3x44
D18F3xE4
D18F3xE8
MSRC001_001F
D18F3x188
MSR0000_0414
MSRC001_1020
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If examining MCA registers after startup, determine the cause of the startup:
• INIT; D18F0x6C[InitDet].
• Cold reset; D18F0x6C[ColdRstDet].
• Warm reset; if not INIT or cold reset.
To see if a link failure occurred, examine D18F0x[E4,C4,A4,84][LinkFail]. If set, look for additional information:
• Receipt of a sync, such as during a sync flood, saves a status of Sync Error in MC4_STATUS.
• CRC error saves a status of CRC Error in MC4_STATUS. See D18F0x[E4,C4,A4,84][CrcErr,CrcFloodEn].
• Link not present does not save status in MC4_STATUS. See D18F0x[E4,C4,A4,84][InitComplete].
Other registers may be needed depending on the specific error symptoms.
2.14.2
DRAM ECC Considerations
DRAM is protected by an error correcting code (ECC). The DRAM error correcting code features an ECC
word formed by a symbol based code. The x4 code uses thirty-six 4-bit symbols to make a 144-bit ECC word
made up of 128 data bits and 16 check bits.
The x4 code is a single symbol correcting (SSC) and a double symbol detecting (DSD) code. This means the
x4 code is able to correct 100% of single symbol errors (any bit error combination within one symbol), and
detect 100% of double symbol errors (any bit error combination within two symbols).
2.14.2.1
ECC Syndromes
For memory errors, the sections below describe how to find the DIMM in error. The process varies slightly
according to the ECC code in use. To determine which ECC code is being used, see D18F3x180[EccSymbolSize].
For correctable errors, the DIMM in error is uniquely identified by the error address
(MSR0000_0412[ErrAddr]) and the ECC syndrome (MSR0000_0411[Syndrome[15:8]] and
MSR0000_0411[Syndrome[7:0]]). The error address maps to the two DIMMs composing the 128-bit line, and
the ECC syndrome identifies one DIMM by identifying the symbol within the line.
2.14.2.1.1
x4 ECC
The use of x4 ECC is indicated in D18F3x180[EccSymbolSize].
The syndrome field uniquely identifies the failing bit positions of a correctable ECC error. Only syndromes
identified by Table 77 are correctable by the error correcting code.
Symbols 00h-0Fh map to data bits 0-63; symbols 10h-1Fh map to data bits 64-127; symbols 20-21h map to
ECC check bits for data bits 0-63; symbols 22-23h map to ECC check bits for data bits 64-127.
To use Table 77, first find the 16-bit syndrome value in the table. This is performed by using low order 4 bits of
the syndrome to select the appropriate error bitmask column. The entire four digit syndrome should then be in
one of the rows of that column. The Symbol In Error row indicates which symbol, and therefore which DIMM
has the error, and the column indicates which bits within the symbol. To map to the DIMM, use the algorithm
in 2.10.5 [Routing DRAM Requests].
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For example, if the ECC syndrome is 6913h, then symbol 05h has the error, and bits 0 and 1 within that symbol
are corrupted, since the syndrome is in column 3h (0011b). Symbol 05h maps to bits 23-20, so the corrupted
bits are 20 and 21.
Table 77: x4 ECC Correctable Syndromes
Symbol
Error Bitmask
In Error 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Data 0
e821 7c32 9413 bb44 5365 c776 2f57 dd88 35a9 a1ba 499b 66cc 8eed 1afe f2df
Data 1
5d31 a612 fb23 9584 c8b5 3396 6ea7 eac8 b7f9 4cda 11eb 7f4c 227d d95e 846f
Data 2
0001 0002 0003 0004 0005 0006 0007 0008 0009 000a 000b 000c 000d 000e 000f
Data 3
2021 3032 1013 4044 6065 7076 5057 8088 a0a9 b0ba 909b c0cc e0ed f0fe d0df
Data 4
5041 a082 f0c3 9054 c015 30d6 6097 e0a8 b0e9 402a 106b 70fc 20bd d07e 803f
Data 5
be21 d732 6913 2144 9f65 f676 4857 3288 8ca9 e5ba 5b9b 13cc aded c4fe 7adf
Data 6
4951 8ea2 c7f3 5394 1ac5 dd36 9467 a1e8 e8b9 2f4a 661b f27c bb2d 7cde 358f
Data 7
74e1 9872 ec93 d6b4 a255 4ec6 3a27 6bd8 1f39 f3aa 874b bd6c c98d 251e 51ff
Data 8
15c1 2a42 3f83 cef4 db35 e4b6 f177 4758 5299 6d1a 78db 89ac 9c6d a3ee b62f
Data 9
3d01 1602 2b03 8504 b805 9306 ae07 ca08 f709 dc0a e10b 4f0c 720d 590e 640f
Data 10
9801 ec02 7403 6b04 f305 8706 1f07 bd08 2509 510a c90b d60c 4e0d 3a0e a20f
Data 11
d131 6212 b323 3884 e9b5 5a96 8ba7 1cc8 cdf9 7eda afeb 244c f57d 465e 976f
Data 12
e1d1 7262 93b3 b834 59e5 ca56 2b87 dc18 3dc9 ae7a 4fab 642c 85fd 164e f79f
Data 13
6051 b0a2 d0f3 1094 70c5 a036 c067 20e8 40b9 904a f01b 307c 502d 80de e08f
Data 14
a4c1 f842 5c83 e6f4 4235 1eb6 ba77 7b58 df99 831a 27db 9dac 396d 65ee c12f
Data 15
11c1 2242 3383 c8f4 d935 eab6 fb77 4c58 5d99 6e1a 7fdb 84ac 956d a6ee b72f
Data 16
45d1 8a62 cfb3 5e34 1be5 d456 9187 a718 e2c9 2d7a 68ab f92c bcfd 734e 369f
Data 17
63e1 b172 d293 14b4 7755 a5c6 c627 28d8 4b39 99aa fa4b 3c6c 5f8d 8d1e eeff
Data 18
b741 d982 6ec3 2254 9515 fbd6 4c97 33a8 84e9 ea2a 5d6b 11fc a6bd c87e 7f3f
Data 19
dd41 6682 bbc3 3554 e815 53d6 8e97 1aa8 c7e9 7c2a a16b 2ffc f2bd 497e 943f
Data 20
2bd1 3d62 16b3 4f34 64e5 7256 5987 8518 aec9 b87a 93ab ca2c e1fd f74e dc9f
Data 21
83c1 c142 4283 a4f4 2735 65b6 e677 f858 7b99 391a badb 5cac df6d 9dee 1e2f
Data 22
8fd1 c562 4ab3 a934 26e5 6c56 e387 fe18 71c9 3b7a b4ab 572c d8fd 924e 1d9f
Data 23
4791 89e2 ce73 5264 15f5 db86 9c17 a3b8 e429 2a5a 6dcb f1dc b64d 783e 3faf
Data 24
5781 a9c2 fe43 92a4 c525 3b66 6ce7 e3f8 b479 4a3a 1dbb 715c 26dd d89e 8f1f
Data 25
bf41 d582 6ac3 2954 9615 fcd6 4397 3ea8 81e9 eb2a 546b 17fc a8bd c27e 7d3f
Data 26
9391 e1e2 7273 6464 f7f5 8586 1617 b8b8 2b29 595a cacb dcdc 4f4d 3d3e aeaf
Data 27
cce1 4472 8893 fdb4 3155 b9c6 7527 56d8 9a39 12aa de4b ab6c 678d ef1e 23ff
Data 28
a761 f9b2 5ed3 e214 4575 1ba6 bcc7 7328 d449 8a9a 2dfb 913c 365d 688e cfef
Data 29
ff61 55b2 aad3 7914 8675 2ca6 d3c7 9e28 6149 cb9a 34fb e73c 185d b28e 4def
Data 30
5451 a8a2 fcf3 9694 c2c5 3e36 6a67 ebe8 bfb9 434a 171b 7d7c 292d d5de 818f
Data 31
6fc1 b542 da83 19f4 7635 acb6 c377 2e58 4199 9b1a f4db 37ac 586d 82ee ed2f
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Table 77: x4 ECC Correctable Syndromes
Symbol
Error Bitmask
In Error 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Check0
be01 d702 6903 2104 9f05 f606 4807 3208 8c09 e50a 5b0b 130c ad0d c40e 7a0f
Check1
4101 8202 c303 5804 1905 da06 9b07 ac08 ed09 2e0a 6f0b f40c b50d 760e 370f
Check2
c441 4882 8cc3 f654 3215 bed6 7a97 5ba8 9fe9 132a d76b adfc 69bd e57e 213f
Check3
7621 9b32 ed13 da44 ac65 4176 3757 6f88 19a9 f4ba 829b b5cc c3ed 2efe 58df
2.14.3
Error Injection and Simulation
Error injection allows the introduction of errors into the system for test and debug purposes. See the following
sections for error injection details:
• DRAM: See 2.14.3.1 [DRAM Error Injection].
• Link:
• D18F3x44[GenLinkSel, GenSubLinkSel, GenCrcErrByte1, GenCrcErrByte0].
Error simulation involves creating the appearance to software that an error occurred, and can be used to debug
machine check interrupt handlers. This is performed by manually setting the MCA registers with desired values, and then driving the software via INT18. See MSRC001_0015[McStatusWrEn] for making MCA registers
writable for non-zero values. When McStatusWrEn is set, privileged software can write non-zero values to the
specified registers without generating exceptions, and then simulate a machine check using the INT18 instruction (INTn instruction with an operand of 18). Setting a reserved bit in these registers does not generate an
exception when this mode is enabled. However, setting a reserved bit may result in undefined behavior.
2.14.3.1
DRAM Error Injection
This section gives details and examples on injecting errors into DRAM using D18F3xBC_x8 [DRAM ECC].
The intent of DRAM error injection is to cause a discrepancy between the stored data and the stored ECC
value. Therefore, DRAM error injection is only possible on DRAM which supports ECC, and in which
D18F2x90_dct[0][DimmEccEn] and D18F3x44[DramEccEn] are set.
The memory subsystem operates on 64-byte cachelines. The following fields are used to set how the cacheline
is to be corrupted in DRAM:
• D18F3xB8[ArrayAddress] selects a cacheline quadrant (16-byte section) of the cacheline. Each cacheline quadrant is protected by an ECC word. Note that there are special requirements for which bits are
used to specify the target quadrant.
• D18F3xBC_x8[ErrInjEn] selects a 16-bit word of the cacheline quadrant selected in ArrayAddress. The
16-bit word identified as ECC[15:0] refers to the bits which store the ECC value; the other 16-bit words
address the data on which the ECC is calculated. One or more of these 16-bit words can be selected, and
the error bitmask indicated in EccVector is applied to each of the selected words.
• D18F3xBC_x8[EccVector] is a bitmask which selects the individual bits to be corrupted in the 16-bit
words selected by ErrInjEn. When selecting the bits to be corrupted for correctable or uncorrectable
errors, consider the ECC scheme being used, including symbol size; see 2.14.2 [DRAM ECC Considerations] for more details. Note that corrupting more than two symbols may exceed the limits of the ECC
to detect the errors; for testing purposes it is recommended that no more than two symbols be corrupted
in a single cacheline quadrant.
The distinction between D18F3xBC_x8[DramErrEn] and D18F3xBC_x8[EccWrReq] is that DramErrEn is
used to continuously inject errors on every write. This bit is set and cleared by software. EccWrReq is used to
inject an error on only one write. This bit is set by software and is cleared by hardware after the error is
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injected.
When performing DRAM error injection on multi-node systems, D18F3xB8 and D18F3xBC_x8 of the NB to
which the memory is attached must be programmed.
The following can be used to trigger the injection:
• For implicit addressing, the memory address is not an explicit parameter of the error injection interface.
Once the error injection registers D18F3xB8 and D18F3xBC are set, the next non-cached access of the
appropriate type will trigger the mechanism and apply it to the accessed address. The access should be
non-cached so that it is ensured to be seen by the memory controller. Possible methods to ensure a noncached access include using the appropriate MTRR to set the memory type to UC or turning off caches.
If it is important to know the address, then system activity must be quiesced so that the access can take
place under careful software control. Once the error injection pattern is set in D18F3xB8 and
D18F3xBC_x8:
• Set either D18F3xBC_x8[EccWrReq] or D18F3xBC_x8[DramErrEn] to enable the triggering mechanism.
• The next non-cached access of the appropriate type will trigger the mechanism and apply it to the
accessed address.
After the error is injected, the data must be accessed in order for the error detection to be triggered. The error
address logged in MSR0000_0412 will correspond to the cacheline quadrant that contains the error.
When using MSR0000_0411 to read MC4_STATUS after an error injection and subsequent error detection, be
aware that the setting of D18F3x44[NbMcaToMstCpuEn] can cause different cores to see different values.
Alternatively, MC4_STATUS can be read through the PCI-defined configuration space aliases D18F3x4C and
D18F3x48, which do not return different values to different cores, regardless of the setting of D18F3x44[NbMcaToMstCpuEn].
Example 1: Injecting a correctable error with implicit addressing:
• Program error pattern:
• D18F3xB8[ArraySelect]=1000b // select DRAM as target
• D18F3xB8[ArrayAddress]=000000000b // select 16-byte (128-bit) section
• D18F3xBC_x8[ErrInjEn]=000000001b // select 16-bit word in 16-byte section
• D18F3xBC_x8[EccRdReq]=0 // not a read request
• D18F3xBC_x8[EccVector]=0001h // set bitmask to inject error into only one symbol
• Program error trigger:
• D18F3xBC_x8[DramErrEn]=0 // inject only a single error
• D18F3xBC_x8[EccWrReq]=1 // a write request; enable injection on next write
• Clean up // if programmed for continuous errors
• D18F3xBC_x8[DramErrEn]=0 // inject only a single error
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2.15 Fusion Controller Hub
The processor contains an integrated Fusion Controller Hub (FCH). The FCH supports the following interfaces:
• Universal Serial Bus (USB) versions 1.1, 2.0, and 3.0
• Serial ATA revision 3.0
• Secure Digital (SD)
• System Management Bus (SMBus)
• Low Pin Count (LPC) bus and SPI interface
• High Definition (HD) audio
• Serial IRQ
• Serial Peripheral Interface (SPI) ROM
• Advanced Configuration and Power Interface (ACPI)
The FCH also comprises the following functions:
• Real-Time Clock (RTC)
• Programmable Interrupt Controller (PIC)
• System clock generation
• System Management Interrupt (SMI)
• General-Purpose I/O (GPIO)
• Power management
• Watchdog Timer (WDT)
2.15.1
MMIO Programming for Legacy Devices
The legacy devices LPC, IOAPIC, ACPI, TPM and Watchdog Timer require the base address of the Memory
Mapped IO registers to be assigned before these logic blocks are accessed. The Memory Mapped IO register
base address and its entire range should be mapped to non-posted memory region by programming the CPU
register. See BIOS Developer's Guide for details.
2.15.2
USB Controllers
The processor supports ten USB ports using the BP_USB_HSD[9:0]P/N pins. Ports 0 through 7 are compatible
with USB 2.0 (EHCI) and USB 1.1 (OHCI). Ports 8 and 9 are connected to an EHCI/OHCI controller pair or to
an xHCI controller, as specified by PMxEF[PortRoutingSelect]. The xHCI controller operates at USB1.1, USB
2.0, or USB 3.0 speeds. Support for USB 3.0 varies by product; see PMxD9_x03[XhcDis].
When ports 8 and 9 are connected to the xHCI controller, these ports are accessed using either the
BP_USB_HSD[9,8]P/N pins (USB 1.1 and USB2.0) or the BP_USB_SS[1,0][RX,TX]P/N pins (USB 3.0).
When ports 8 and 9 are connected to an EHCI/OHCI controller pair, only the BP_USB_HSD[9,8]P/N pins are
used.
Table 78: USB Port Mapping
Ports
3-0
PMxEF[PortRoutingSelect]
X
USB
Version
1.1
2.0
Controller
Registers
Pins
OHCI 1
EHCI 1
D12F0xXX, OHCI1xXX
D12F2xXX, EHCI1xXX
BP_USB_HSD[3:0]P/N
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Table 78: USB Port Mapping
7-4
PMxEF[PortRoutingSelect]
X
9-8
0
Ports
1
USB
Version
1.1
2.0
1.1
2.0
1.1
2.0
3.0
Controller
Registers
Pins
OHCI 2
EHCI 2
OHCI 3
EHCI 3
xHCI
D13F0xXX, OHCI2xXX
D13F2xXX, EHCI2xXX
D16F0xXX, OHCI3xXX
D16F2xXX, EHCI3xXX
D10F0xXX, XHCI*
(See 3.26.4.3.2)
BP_USB_HSD[7:4]P/N
BP_USB_HSD[9,8]P/N
BP_USB_HSD[9,8]P/N
BP_USB_SS[1,0][RX,TX]P/N
Refer to the following for the USB controller register definitions:
• Section 3.26.4.1 [USB 1.1 (OHCI)] for the OHCI controllers
2.15.2.1
USB Power Management
USB power management functions are controlled by registers outside the USB controller registers spaces.
See the following register definitions in 3.26.13 [Power Management (PM) Registers]:
• PMx80[UsbPeriodicalSetBmSts, Usb20SetBmSts, Usb11SetBmSts, Usb11BmStsEn]
• PMxED [USB Gating]
• PMxEF [USB Enable]
• PMxF0 [USB Control]
2.15.2.2
USB Interrupts
The interrupt mapping is specified by IOC00 [Pci_Intr_Index] and IOC01 [Pci_Intr_Data]. By default, USB
interrupts are routed to PCI INTA#, B#, and C#.
For normal operations, MSI must be disabled in all OHCI and EHCI controllers.
2.15.2.3
BIOS Programming Requirements For USB Reset During S3 Resume
Set PMxF0[UsbKbResetEnable]=1 to enable the USB controller to get reset by any software that generates a
PCIRST# condition (e.g. a keyboard reset or a write to IOCF9). To avoid losing the USB connection status during the S3 resume procedure, BIOS must ensure that PMxF0[UsbKbResetEnable]=0 before any software-generated PCIRST# reset condition during S3 resume.
2.15.2.4
Enabling the xHCI Controller
Software performs the following sequence to enable the xHCI controller:
1. Program PMxEF[Usb3OhciEnable]=0.
2. Program PMxEF[Usb3EhciEnable]=0.
3. Program PMxEF[PortRoutingSelect]=1.
4. Program XHCI_PMx00[Xhci0Enable]=1.
2.15.2.5
OHCI Arbiter Mode
Software should program the following sequence for all OHCI controllers to set OHCI arbiter mode:
1. Whenever the system resumes from S3/S4/S5, software should reset the USB controllers as follows:
A. Program PMxD3[AssertUsbRstB]=0.
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B. Wait for <1 ms.
C. Program PMxD3[AssertUsbRstB]=1.
2. Program D[16,13,12]F0x80[OHCIArbiterMode]=11b.
3. Program D[16,13,12]F0x80[OHCIArbVldCtl]=1b.
2.15.2.6
USB2.0 Controller PHY Configuration and Calibration
Software performs the following sequence to configure EHCI common PHY for each USB port to be used
shortly after chip boot up and after USB2.0 EHCI controller initiated the calibration. The register settings have
be to re-established to ensure USB2.0 PHY is properly calibrated. It is not needed after waking up from S3.
1. Program HSSLEW=10b.
A. Program EHCI[3:1]xB4[PortNumber] with the controller port number according to Table 79.
B. Program EHCI[3:1]xB4[VControlModeSel]=0110b.
C. Program HSSLEW value at EHCI[3:1]xB4[1:0]=10b.
D. Program EHCI[3:1]xB4[VLoadB]=1.
E. Wait for EHCI[3:1]xB4[VBusy]=0.
F. Program EHCI[3:1]xB4[VLoadB]=0.
G. Wait for EHCI[3:1]xB4[VBusy]=0.
H. Program EHCI[3:1]xB4[VLoadB]=1 to lock the PHY control interface.
2. Program EHCI[3:1]xD0[BgAdj]=6.
3. Program EHCI[3:1]xC4[IRefAdj]=2.
4. Program EHCI[3:1]xC4[XRefAdj]=2.
5. Program EHCI[3:1]xC4[PVI]=1.
6. Program EHCI[3:1]xC4[CPAdj]=1.
7. Program EHCI[3:1]xC4[DLLControl]=90h.
8. Program EHCI[3:1]xD4[PllFilter]=1.
9. Program EHCI[3:1]xD4[CalEnable]=0.
10. Wait for 200 ns.
11. Program EHCI[3:1]xD4[CalEnable]=1.
12. Wait for 400 ns.
13. Program EHCI[3:1]xD4[CalEnable]=0.
2.15.2.7
USB2.0 Controller ISO Device CRC False Error Detection
Software performs the following sequence to program CDR phase shift limit for each USB port to be used:
1. Program EHCI[3:1]xB4[PortNumber] with the controller port number according to Table 79.
2. Program EHCI[3:1]xB4[VControlModeSel]=0111b.
3. Program EHCI[3:1]xB4[2:0]=101b.
4. Program EHCI[3:1]xB4[VLoadB]=1.
5. Wait for EHCI[3:1]xB4[VBusy]=0.
6. Program EHCI[3:1]xB4[VLoadB]=0.
7. Wait for EHCI[3:1]xB4[VBusy]=0.
8. Program EHCI[3:1]xB4[VLoadB]=1 to lock the PHY control interface.
Table 79: USB Port to EHCI[3:1]xB4[PortNumber] Mapping
USB Port
0
1
2
Software selects by programming
EHCI1xB4[PortNumber]=0h
EHCI1xB4[PortNumber]=1h
EHCI1xB4[PortNumber]=2h
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Table 79: USB Port to EHCI[3:1]xB4[PortNumber] Mapping
3
4
5
6
7
8
9
2.15.2.8
EHCI1xB4[PortNumber]=3h
EHCI2xB4[PortNumber]=0h
EHCI2xB4[PortNumber]=1h
EHCI2xB4[PortNumber]=2h
EHCI2xB4[PortNumber]=3h
EHCI3xB4[PortNumber]=0h
EHCI3xB4[PortNumber]=1h
xHC USB2.0 Common PHY Calibration
The following programming sequence has to be carried out shortly after chip boot up and after USB2.0
EHCI/XHCI controller initiated the calibration. The register settings have be to re-established to ensure
USB2.0 PHY is properly calibrated. It is not needed after waking up from S3.
1. Program HSSLEW=10b.
A. Program D10F0x4C_x4000_0000[PortNumber] with the controller port number according to
Table 80.
B. Program D10F0x4C_x4000_0000[VControlModeSel]=0110b.
C. Program HSSLEW value at D10F0x4C_x4000_0000[1:0]=10b.
D. Program D10F0x4C_x4000_0000[VLoadB]=1.
E. Wait for D10F0x4C_x4000_0000[VBusy]=0.
F. Program D10F0x4C_x4000_0000[VLoadB]=0.
G. Wait for D10F0x4C_x4000_0000[VBusy]=0.
H. Program D10F0x4C_x4000_0000[VLoadB]=1 to lock the PHY control interface.
2. Program D10F0x4C_x4000_0050[BgAdj]=6.
3. Program D10F0x4C_x4000_000C[IRefAdj]=2.
4. Program D10F0x4C_x4000_000C[XRefAdj]=2.
5. Program D10F0x4C_x4000_000C[PVI]=1.
6. Program D10F0x4C_x4000_000C[CPAdj]=1.
7. Program D10F0x4C_x4000_000C[DllControl]=90h.
8. Program D10F0x4C_x4000_0054[PllFilter]=1.
9. Program D10F0x4C_x4000_0054[CalEnable]=0.
10. Wait for 200 ns.
11. Program D10F0x4C_x4000_0054[CalEnable]=1.
12. Wait for 400 ns.
13. Program D10F0x4C_x4000_0054[CalEnable]=0.
2.15.2.9
USB3.0 PHY Auto-Calibration Enablement
BIOS enables USB3.0 PHY auto-calibration as follows:
1. Program XHCI_PMx8C[PllVcoTune[3:0]]=0011b.
2. Program XHCI_PMx8C[CrPllCalibEn]=1.
2.15.2.10
xHCI ISO Device CRC False Error Detection
Software performs the following sequence to program CDR phase shift limit for each USB port to be used:
1. Program D10F0x4C_x4000_0000[PortNumber] with the controller port number according to Table 80.
2. Program D10F0x4C_x4000_0000[VControlModeSel]=0111b.
3. Program D10F0x4C_x4000_0000[2:0]=101b.
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5.
6.
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Program D10F0x4C_x4000_0000[VLoadB]=1.
Wait for D10F0x4C_x4000_0000[VBusy]=0.
Program D10F0x4C_x4000_0000[VLoadB]=0.
Wait for D10F0x4C_x4000_0000[VBusy]=0.
Program D10F0x4C_x4000_0000[VLoadB]=1 to lock the PHY control interface.
Table 80: USB Port to D10F0x4C_x4000_0000[PortNumber] Mapping
USB Port
8
9
Software selects by programming
D10F0x4C_x4000_0000[PortNumber]=0h
D10F0x4C_x4000_0000[PortNumber]=1h
2.15.2.11
xHCI PHY Clock Gating
The following programming sequence configures the clock gating in the xHCI PHY. They must be performed
for each port after enabling xHCI controller and need to be restored after all power state resumes.
1. Program D10F0x4C_x4000_0000[VLoadB]=1.
2. Program D10F0x4C_x4000_0000[PortNumber] with the controller port number according to Table 80.
3. Program D10F0x4C_x4000_0000[VControlModeSel]=0011b.
4. Program D10F0x4C_x4000_0000[2]=1.
5. Read D10F0x4C_x4000_0000[VBusy] to ensure it is 0.
6. Program D10F0x4C_x4000_0000[VLoadB]=0.
7. Wait for D10F0x4C_x4000_0000[VBusy]=0.
8. Program D10F0x4C_x4000_0000[VLoadB]=1 to lock the PHY control interface.
2.15.2.12
xHCI Firmware Preload
Software performs the following programming sequence for firmware preload. Firmware preload should be
executed before BIOS de-asserts XHCI_PMx00[U3CoreReset].
1. Enable firmware preload by programming XHCI_PMx00[FwLoadMode]=1.
2. Program XHCI_PMx04[XhciFwPreloadType] with 1 for boot RAM preload and 0 for instruction RAM
preload.
3. Program XHCI_PMx04[XhciFwRomAddr] with the offset of the application firmware in the external
ROM.
4. Program XHCI_PMx08[XhciFwRamAddr]= 0.
5. Program XHCI_PMx08[XhciFwSize]=8000h.
6. Program XHCI_PMx00[FwPreloadStart]=1 to start firmware preload.
7. Wait for XHCI_PMx00[FwPreloadComplete]=1.
8. Program XHCI_PMx00[FwPreloadStart]=0.
9. Program XHCI_PMx00[U3CoreReset]=0 to de-assert xHC reset.
2.15.2.13
xHCI Clear Pending PME on Sx State Entry
During S3/S4 entry with wake from Sx state enabled, if the xHCI controller received a wake event before the
system shutdown into Sx state is completed, D10F0x54[PmeStatus] may remain set when the system enters
into Sx state. This will prevent subsequent wake events from being propagated to the ACPI controller. BIOS
should write 1 to clear D10F0x54[PmeStatus] if D10F0x54[PmeStatus] is 1 and ACPI GEvent status bit is
clear on entry into S3/S4 state.
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xHCI Enable OHCI3/EHCI3 on S4/S5 State Entry
If xHCI controller is enabled, OHCI3/EHCI3 controllers are disabled for normal operations. See 2.15.2.4
[Enabling the xHCI Controller]. On S4/S5 entry, OHCI3/EHCI3 controllers should be enabled to avoid possibly stalled IRQ1/IRQ12 interrupts, which could cause keyboard/mouse hang during wake up.
• Program PMxEF[Usb3OhciEnable]=1.
• Program PMxEF[Usb3EhciEnable]=1.
2.15.3
2.15.3.1
SATA
SATA Operating Mode
The SATA host controller can operate in the following modes:
• IDE mode.
• AHCI mode.
Software programs the subclass code and programming interface register to enable the SATA controller as
RAID controller, IDE controller, or AHCI controller.
1. Program D11F0x40[SubclassCodeWriteEnable]=1.
2. Program D11F0x08[SubclassCode] and D11F0x08[ProgramIF[7:0]] according to Table 230 [SATA Controller Subclass Code and ProgramIF Settings].
3. Program D11F0x40[SubclassCodeWriteEnable]=0.
2.15.3.2
SATA Drive Detection in IDE mode
The following sequence should be included in the SBIOS drive identification loop for SATA drive detection in
IDE mode.
1. If any of the SATA port status register at SATAx1[A,2]8[DET]==03h, program IDE[1:0]x06[DriveHead]=A0h for the corresponding port and go to Step 2.
Else, no SATA drives are attached; exit the detection loop program.
2. If (IDE[1:0]x06[DriveHead]==A0h) && (IDE[1:0]x07[7]==0) && (IDE[1:0]x07[3]==0) for a port, the
SATA device on that port is ready.
Else, loop until 30 s time-out; There is no SATA device attached if a time-out occurs.
Note: Most drives don’t need 30 s time-out. The 30 s time-out is only needed for some particularly large
capacity SATA drives, which require a longer spin-up time during a cold boot.
2.15.3.3
SATA PHY Auto-Calibration Enablement
BIOS enables SATA PHY auto-calibration as follows:
1. Program D11F0x88[PllVcoTune]=0011b.
2. Program PMxDC[PllCalibEn]=1.
3. Reset PHY:
A. Program D11F0x84[RSTB]=0 to assert reset.
B. Wait for 100 us.
C. Program D11F0x84[RSTB]=1 to release PHY reset.
2.15.3.4
SATA PHY Fine Tuning
The SBIOS should program the SATA controller in the sequence indicated below to fine tune the PHY. Performing this procedure provides sufficient time for the SATA controllers to correctly complete SATA drive
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detection. The same procedure is required after the system resumes from the S3 state.
• Gen 3 settings:
• Program D11F0x80[15:0]=0130h to select Gen 3 for all ports.
• Program D11F0x98[31:0]=0040f407h.
• Gen 2 settings:
• Program D11F0x80[15:0]=0120h to select Gen 2 for all ports.
• Program D11F0x98[31:0]=00403204h to fine tune PHY for Gen 2.
• Gen 1 settings:
• Program D11F0x80[15:0]=0110h to select Gen 1 for all ports.
• Program D11F0x98[31:0]=00403103h to fine tune PHY for Gen 1.
• Squelch detector settings:
A. Program PMxC8[EPromEFuseSelect]=1b to select Efuse access.
B. Program PMxD8[EpromEfuseIndex]=01h.
C. Read from PMxD9[4] to get the setting of APU_FCH_FUSE[12].
D. IF (PMxD9[4]==0) THEN
SATA RX squelch detection threshold is not fused, program the squelch detector threshold for all ports
at all generation speed as follows:
• Program D11F0x80[15:0]=0130h.
• Program D11F0x9C[RX_SQDET_TH]=101b.
• Program D11F0x80[15:0]=0120h.
• Program D11F0x9C[RX_SQDET_TH]=101b.
• Program D11F0x80[15:0]=0110h.
• Program D11F0x9C[RX_SQDET_TH]=101b.
ELSE
a. Program PMxD8[EpromEfuseIndex]=02h.
b. Read from PMxD9[2:0] to get the fused setting for SATA port 1 squelch detector threshold.
c. Program the squelch detector threshold control register for port 1 at all generation speed:
• Program D11F0x80[15:0]=0031h.
• Program D11F0x9C[RX_SQDET_TH]=PMxD9[2:0].
• Program D11F0x80[15:0]=0021h.
• Program D11F0x9C[RX_SQDET_TH]=PMxD9[2:0].
• Program D11F0x80[15:0]=0011h.
• Program D11F0x9C[RX_SQDET_TH]=PMxD9[2:0].
d. Program PMxD8[EpromEfuseIndex]=01h.
e. Read from PMxD9[7:5] to get the fused setting for SATA port 0 squelch detector threshold.
f. Program the squelch detector threshold control register for port 0 at all generation speed:
• Program D11F0x80[15:0]=0030h.
• Program D11F0x9C[RX_SQDET_TH]=PMxD9[7:5].
• Program D11F0x80[15:0]=0020h.
• Program D11F0x9C[RX_SQDET_TH]=PMxD9[7:5].
• Program D11F0x80[15:0]=0010h.
• Program D11F0x9C[RX_SQDET_TH]=PMxD9[7:5].
ENDIF.
2.15.3.5
SATA PHY Reference Clock Selection
SATA PHY reference clock can originate from either internal or external clock. The following steps select
SATA PHY reference clock source:
1. Select one of the following options for reference clock.
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• Internal 48 MHz differential non-spread clock from pad (default):
a. Program PMxDA[RefClkSel]=1 to select reference clock from internal RDL.
b. Program PMxDA[RefDivSel]=0 to set PHY divider to div-by-1.
c. Program D11F0x8C[PLL_CLKF]=7Dh to set PLL feedback clock divider value to
6 GHz/48 MHz=7Dh.
• External 25 MHz crystal non-spread clock from external clock chip (the clock path has to be routed on
the board, in order for the setting to take effect):
a. Program PMxDA[RefClkSel]=0 to select reference clock from an external source, via the
PAD_XTALI and PAD_XTALO, to SATA PHY.
b. Program PMxDA[RefDivSel]=0 to set PHY divider to div-by-1.
c. Program D11F0x8C[PLL_CLKF]=F0h to set PLL feedback clock divider value to
6 GHz/25 MHz=F0h.
2. Reset PHY:
A. Program D11F0x84[RSTB]=0 to assert reset.
B. Wait for 100 us.
C. Program D11F0x84[RSTB]=1 to release PHY reset.
2.15.3.6
2.15.3.6.1
SATA Power Management
SATA PHY Power Saving
The SATA PHY has different power saving states with the Active state consuming the most power. The table
below summarizes the different controls during each power saving state.
2.15.3.7
Enable Shadow Register Reload
When default PHY settings are not optimal, they need to be adjusted by software. Once these settings are reprogrammed, software shall program D11F0x84[S5ShadowLdDis] to 0 to turn on shadow register reloading.
When default PHY settings are optimal and need no adjustment, D11F0x84[S5ShadowLdDis] needs not to be
altered and shadow register preloading is effectively disabled.
2.15.3.8
2.15.3.8.1
SATA Interrupt Handling
Line Interrupt
The SATA interrupt mapping is specified by IOC00 [Pci_Intr_Index] and IOC01 [Pci_Intr_Data].
2.15.3.8.2
MSI Message
SATA controller supports message-based interrupts. When MSI is enabled and the SATA controller owns N
ports, as specified by SATAx0C [Ports Implemented (PI)], D11F0x50[MMC] should be programmed according to platform configurations:
• If SATAx00[CCCS]==1, D11F0x50[MMC] should be the minimum of 2M which satisfies 2M >= (N+1).
For example: if BIOS knows that system has 2 SATA ports in AHCI mode (N=2). If SATAx00[CCCS]==1,
BIOS should program D11F0x50[MMC]=2 to request 4 MSI interrupts. If SATAx00[CCCS]==0, BIOS
should program D11F0x50[MMC]=1 to request 2 MSI interrupts.
MSI capability pointer should be hidden when SATA subclass is configured in IDE mode (see 2.15.3.1 [SATA
Operating Mode]). To hide SATA MSI capability, the capability pointer offset needs to be re-programmed from
its default setting to prevent the driver from enabling this feature.
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Clear status of SATA PERR
BIOS should clear SATA PERR status soon after a cold boot, warm boot, any S3/S1 resume events, or an
IOCF9 initiated reset outside a warm boot before any SATA activity is initiated.
• Write 1 to clear SMIx3C[SataPerr].
• Write 1 to clear SMIx84[RasEvent55].
2.15.4
LPC Bus Interface
BIOS should program D14F3xA0[SpiBaseAddr] with non-zero address to enable the MMIO access to SPI
ROM control registers.
2.15.4.1
Enabling LPC DMA function
If DMA is required for the LPC interface, program the registers as the following:
• Program D14F3x40[LegacyDmaEnable]=1.
• Program D14F3x78[NoHog]=1.
• Program PMx08[ArbDmaDis]=1.
• Program D14F3x78[LDRQ1]=1 and D14F3x78[LDRQ0]=1.
• Program PMx04[LegacyDmaPrefetchEnhance]=1 for non-DOS mode. Note: This bit should only be enabled
in the ACPI method (called by the OS). This ensures that it is enabled only when the system is in Windows®
mode. Under DOS mode, this feature may not work properly and may cause the floppy to malfunction.
2.15.4.2
Enabling SPI 100
To enable the support for SPI 100 MHz speed, software needs to program SPIx20[UseSpi100]=1. SPI 100
should be enabled on after the Auto ROM sizing has been completed (Auto ROM sizing is done by the software only during the initial boot when the system power state transitions from G3->S5->S0). The actual read
speed also depends on the settings at SPIx22 [SPI100 Speed Config].
2.15.5
SD Controller
The SD controller is SD 3.0 compliant host controller.
2.15.6
HD Audio
The FCH has one High Definition Audio controller (HD audio aka. Azalia), which can be enabled/disabled by
programming PMxEB[AzEnable].
The HD audio controller supports up to 4 codecs with one AZ_SDIN pin from each codec. The four AZ_SDIN
pins are multiplexed with GPIO167-170 (GPIOxA7-GPIOxAA). If a particular pin is to be used for HD audio
functionality and the integrated pull-down is to be used rather than external pull-down resistor, in addition to
being configured for HD audio, the following bits need to be set:
• GPIOxA7=3Eh
• GPIOxA8=3Eh
• GPIOxA9=3Eh
• GPIOxAA=3Eh
For example, if only GPIO167 and GPIO168 are to be used for HD audio, then only GPIOxA7 and GPIOxA8
need to be programmed to 3Eh. See 3.26.12 [GPIO Pin control registers].
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HD Audio AF and MSI Capability
The Advanced Feature (AF) capability and MSI capability in HD audio controller are controlled by
D14F2x44[EnAFCap] and D14F2x44[EnMsiCap] respectively. The settings of these two bits affect how the
AF capability and MSI capability are linked to the capability pointer linked list.
Table 81: HD Audio AF and MSI Capability Settings
D14F2x44
[EnAFCap]
0
0
1
1
2.15.7
D14F2x44
[EnMsiCap]
0
1
0
1
D14F2x50 D14F2x60 D14F2x60 D14F2x70 D14F2x70
[NextPtr] [CapID] [NextPtr] [AFC[NextPtr]
apID]
0h
0h
0h
0h
0h
60h
5h
0h
0h
0h
70h
0h
0h
13h
0h
60h
5h
70h
13h
0h
D14F2x70
[AFLengt
h]
0h
0h
6h
6h
D14F2x70
[25:24]
0h
0h
3h
3h
ASF Controller
The ASF controller can be used in a slave mode to support DASH clients. When the platform is configured for
DASH the BIOS should at the minimum set the following registers to ensure the ASF is configured in slave
mode and the control commands are defined properly in the ASF tables.
• When operating in Master mode, BIOS should program PMx28[AsfSmMasterEn]=1. BIOS should program
PMx28[AsfSmMasterEn] back to 0 after the master operations are done.
• When operating in Slave mode, BIOS should program PMx28[AsfSmMasterEn]=0.
In addition to support remote DASH operations, BIOS should ensure that the ASF tables define the correct
command codes and ASFx0E [RemoteCtrlAdr] has to be programmed with the same value reported in the ASF
control data table.
ASF controller can behave like remote control device to accept the command from client side to do the
reset/power down/power up/power cycle. BIOS reports those in ASF control data table. The command and
command data are defined in Table 82.
Table 82: ASF Remote Control Commands
Remote Control
Reset
Power Up
Power Down
Power Cycle
2.15.8
Control Command
50h
51h
52h
53h
Control data
00h
00h
00h
00h
Integrated Micro-Controller
The FCH supports an integrated micro-controller (IMC) to run the keyboard BIOS and/or other algorithms.
The IMC is an enhanced 8051 with a RISC-like architecture which allows it to perform most instructions in 14 clocks (instead of 12 clocks in the original 8051).
The IMC can also be enabled by programming PMxD6[ImcEnable].
2.15.9
On-Chip Clock Generator
There are two clocking modes in which this chip can be brought up based on the boot strap pin LPCCLK1.
SBIOS should read MISCx80[ClkGenStrap] to determine clock generator mode. SBIOS should program
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MISCx40[OscClkSwitchEn] to 1 to select average 14 MHz OSC clock provided by internal PLL in both internal and external clocking mode.
2.15.9.1
Power Saving In Internal Clock Mode
GPP_CLK_P/N pins are powered off when this chip is strapped to use an external clock, and powered on when
strapped to operate in internal clock mode. The GPP_CLK clocks are mapped to corresponding CLK_REQ#
pins. The GPP_CLK0/1/2/3 mapping is defined at MISCx00[15:0]. SLT_GFX_CLK mapping is defined at
MISCx04[7:4]. In internal clock mode, a selected GPP_CLK can be powered off when the corresponding
CLK_REQ# is asserted. See MISCx00 && MISCx04 for details.
Software can also program MISCx04[PCIE_RCLK_PowerDownEnable]=1 to turn off 100 MHz reference
clock input buffer in internal clock generator mode for power saving.
2.15.9.2
Global A-Link / B-Link Clock Gating
Software needs to program MISCx2C[AlinkClkGateOffEn]=1 and PMx04[ABLinkClkGateEn]=1 to enable
global A-link clock gate off function.
Software needs to program MISCx2C[BlinkClkGateOffEn]=1 and PMx04[ABLinkClkGateEn]=1 to enable
global B-link clock gate off function.
PMx04[ABLinkClkGateEn] is a non-sticky bit and needs to be programmed to 1 after PCI reset and S3/S4/S5
state, if global A-link / B-link gating function has been enabled. MISCx2C[AlinkClkGateOffEn] and
MISCx2C[BlinkClkGateOffEn] are sticky bits.
2.15.9.3
CG_PLL CMOS Clock Driver Setting for Power Saving
Software programs the following registers to select CMOS clock driver for CG1_PLL in internal & external
clock mode for power saving:
A. Program MISCx1C[CgpllClkDriverUpdate]=0.
B. Program MISCx1C[Cg1ClkDriverType]=1011b and Program
MISCx1C[Cg1RefClk48MHzDriverType]=0010b.
C. Perform a software reset through IOCF9.
These settings will only need to be applied once when the chip is booting up from G3-S5->S0. These is no
need to do this for every reset since the setting is sticky.
2.15.10
Scallion Gasket
The Scallion gasket (SBG) is responsible for converting between the protocols used by the Scallion interface
and the A-link bridge interface. BIOS should program PMxE0 to set up base address before accessing AB configuration registers.
2.15.11
A-Link Bridge
The A-link bridge (AB) sits behind the Scallion gasket and acts as the bridge between Scallion and A-link/Blink bus.
2.15.11.1
Detection of Upstream Interrupts
BIOS should enable AB to detect upstream interrupts for the purpose of system management.
• Program ABx04_x94[MsiAddr[39:20]] with CPU interrupt delivery address [39:20].
• Program ABx04_x94[MsiAddrEn]=1.
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AB Memory Power Saving
The following sequence enables AB memory power saving:
A. Program MISCx68[ABBypassMemDsd]=0 to enable AB memory DSD.
B. Program ABx04_x58[BlMemSDEn]=1 to enable B-link memory shutdown.
C. Program ABx04_x58[AlMemSDEn]=1 to enable A-link memory shutdown.
2.15.11.3
AB Internal Clock Gating
The following sequence enables AB internal clock gating:
A. Program ABx04_x54[BlClkGateDelay]=10h to set the number of cycles to delay before gating B-link
clocks.
B. Program ABx04_x10054[AlClkGateDelay]=10h to set the number of cycles to delay before gating Alink clocks.
C. Program ABx04_x54[BlClkGateEn]=1 to enable medium grain B-link clock gating.
D. Program ABx04_x54[DbgClkGateEn]=1 to disable debug only B-link clocks.
E. Program ABx04_x10054[AlClkGateEn]=1 to enable medium grain A-link clock gating.
F. Program ABx04_x10054[DbgClkGateEn]=1 to disable debug only A-link clocks.
2.15.11.4
AB 32/64 Byte DMA Write Enable
To enable AB 32 byte/64 byte DMA write, software needs to program ABx04_x54[UpWr16BMode]=0 and
ABx04_x54[UpSWrByteCntSbgMode]=1 to disable 16 byte write splitting and enable SBG mode byte-count
calculation logic. Software should also make sure ABx04_x204[Dma16ByteMode]=0.
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Registers
This section provides detailed field definitions for the core register sets in the processor.
3.1
Register Descriptions and Mnemonics
Each register in this document is referenced with a mnemonic. Each mnemonic is a concatenation of the register-space indicator and the offset of the register. Here are the mnemonics for the various register spaces:
• IOXXX: x86-defined input and output address space registers; XXX specifies the hexidecimal byte address
of the IO instruction. This space includes IO-space configuration access registers, IOCF8 [IO-Space Configuration Address] and IOCFC [IO-Space Configuration Data Port], the GPU VGA registers, and the legacy
block configuration registers. Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any core on that node. See 3.2 [IO Space Registers] and 3.26.1 [Legacy
Block Configuration Registers (IO)].
• APICXX0: APIC memory-mapped registers; XX0 is the hexidecimal byte address offset from the base
address. See 2.4.8.1.2 [APIC Register Space].
• CPUID FnXXXX_XXXX_EiX[_xYYY]: processor capabilities information returned by the CPUID
instruction. See 3.18 [CPUID Instruction Registers]. Each core may only access this information for itself.
• MSRXXXX_XXXX: MSRs; XXXX_XXXX is the hexidecimal MSR number. This space is accessed
through x86-defined RDMSR and WRMSR instructions. Unless otherwise specified there is one set of these
registers Per-core. See 2.4.1 [L2 complex].
• DXFYxZZZ: PCI-defined configuration space; X specifies the hexadecimal device number (this may be 1or
2 digits), Y specifies the function number, and ZZZ specifies the hexidecimal byte address (this may be 2 or
3 digits); e.g., D18F3x40 specifies the register at device 18h, function 3, and address 40h. See 2.7 [Configuration Space], for details about configuration space.
• Some register in D18F2xXXX have the _dct[0] mnemonic suffix. See 2.9.3 [DCT Configuration Registers].
• PMCxXXX: core performance monitor events; XXX is the hexidecimal event counter number programmed
into MSRC001_00[03:00][EventSelect]; See 2.6.1.1 [Core Performance Monitor Counters].
• When PMCxXXX is followed by [z:y] then UnitMask[z:y] is being specified.
• L2IPMCxXXX: L2 performance monitor events; XXX is the hexidecimal event counter number programmed into MSRC001_023[6,4,2,0][EventSelect]; See 2.6.1.2 [L2I Performance Monitor Counters].
• When PMCxXXX is followed by [z:y] then UnitMask[z:y] is being specified.
• NBPMCxXXX: NB performance monitor events; XXX is the hexadecimal event counter number programmed into MSRC001_024[6,4,2,0][EventSelect]; See 2.6.1.3 [NB Performance Monitor Counters].
• When NBPMCxXXX is followed by [z:y] then UnitMask[z:y] is being specified.
• ABxXX: ALink Bridge registers; XX specifies the hexadecimal byte address offset from the base address.
The base address for this space is specified by PMxE0 [ABRegBar]. Unless otherwise specified, there is one
set of these registers per node; the registers in a node are accessible to any core on that node. See 3.26.2 [AB
Configuration Registers (Scallion)].
• IDE[Y]xXX: SATA controller IDE mode IO mapped registers; XX specifies the hexadecimal byte address
offset from the base address; Y specifies primary drive (0) or secondary drive (1). The base address for this
space is specified in Table 231 [IDE Compatibility Mode and Native Mode Address Mapping]. Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any core on
that node. See 3.26.3.2.1 [IDE Compatibility Mode and Native Mode (BAR0, BAR1, BAR2, BAR3) Registers].
• IDE_BMxXX: SATA controller IDE mode IO mapped bus master registers; XX specifies the hexadecimal
byte address offset from the base address. The base address for this space is specified by D11F0x20 [Bus
Master Interface Register Base Address (BAR4)]. Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any core on that node. See 3.26.3.2.2 [IDE Bus Master
(BAR4) Registers].
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• SATAxXXX: SATA controller AHCI mode memory mapped registers; XXX specifies the hexadecimal byte
address offset from the base address. The base address for this space is specified by D11F0x24 [AHCI Base
Address (BAR5)]. Unless otherwise specified, there is one set of these registers per node; the registers in a
node are accessible to any core on that node. See 3.26.3.3 [SATA Memory Mapped AHCI Registers].
• SATA_EMxXX: SATA controller AHCI mode memory mapped enclosure buffer management registers; XX
specifies the hexadecimal byte address offset. Unless otherwise specified, there is one set of these registers
per node; the registers in a node are accessible to any core on that node. See 3.26.3.3.3 [Enclosure Buffer
Management Registers].
• OHCI[Y]xXXX: USB OHCI controller memory mapped registers; XXX specifies the hexadecimal byte
address offset from the base address; Y specifies the OHCI controller number; e.g., OHCI[1]x04 specifies
OHCI controller 1 memory mapped control register offset 04. The base address for this space is specified by
D[16,13,12]F0x10 [OHCI Base Address]. Unless otherwise specified, there is one set of these registers per
node; the registers in a node are accessible to any core on that node. See 3.26.4.1.2 [OHCI Memory Mapped
IO Registers].
• EHCI[Y]xXX: USB EHCI controller memory mapped registers; XX specifies the hexadecimal byte address
offset from the base address; Y specifies the EHCI controller number; e.g., EHCI[1]x04 specifies EHCI controller 1 memory mapped control register offset 04. The base address for this space is specified by
D[16,13,12]F2x10 [BAR_EHCI]. Unless otherwise specified, there is one set of these registers per node; the
registers in a node are accessible to any core on that node. See 3.26.4.2.2 [EHCI Memory Mapped IO Registers].
• xHCI_PMxXX: USB xHCI controller ACPI memory mapped registers; XX specifies the hexadecimal byte
address offset from the base address. Unless otherwise specified, there is one set of these registers per node;
the registers in a node are accessible to any core on that node. See 3.26.4.3.2 [xHCI Power Management
Registers].
• SDHCxXX: Secure Digital host controller memory mapped registers; XX specifies the hexadecimal byte
address offset from the base address. The base address for this space is specified by {D14F7x14 [Upper Base
Address Reg 0], D14F7x10 [Base Address Reg 0]}. Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any core on that node. See 3.26.6.2 [SD Host Controller Configuration Registers (SDHC)].
• ASFxXX: ASF registers; XX specifies the hexadecimal byte address offset. Unless otherwise specified,
there is one set of these registers per node; the registers in a node are accessible to any core on that node. See
3.26.7.2 [ASF (Alert Standard Format) Registers].
• SMBUSxXX: SMBus registers; XX specifies the hexadecimal byte address offset. Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any core on that
node. See 3.26.7.3 [SMBus Registers].
• IOAPICxXX: IOAPIC registers; XX specifies the hexadecimal byte address offset from the base address.
Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible
to any core on that node. See 3.26.8 [IOAPIC Registers].
• SPIxXX: SPI memory mapped registers; XX specifies the hexadecimal byte address offset from the base
address. The base address is specified by D14F3xA0 [SPI Base_Addr]. Unless otherwise specified, there is
one set of these registers per node; the registers in a node are accessible to any core on that node. See
3.26.9.2 [SPI Registers].
• HPETxXXX: HPET registers; XXX specifies the hexadecimal byte address offset. Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any core on that
node. See 3.26.10 [High Precision Event Timer (HPET) Registers].
• MISCxXX: ACPI miscellaneous control registers; XX specifies the hexadecimal byte address offset. Unless
otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any
core on that node. See 3.26.11 [Miscellaneous (MISC) Registers].
• GPIOxXX: GPIO registers; XX specifies the hexadecimal byte address offset. Unless otherwise specified,
there is one set of these registers per node; the registers in a node are accessible to any core on that node. See
3.26.12.1 [GPIO Registers].
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• IOMUXxXX: IOMux registers; XX specifies the hexadecimal byte address offset. Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any core on that
node. See 3.26.12.2 [IOMux Registers].
• PMxXX: power management registers; XX specifies the hexadecimal byte address offset. Unless otherwise
specified, there is one set of these registers per node; the registers in a node are accessible to any core on that
node. See 3.26.13 [Power Management (PM) Registers].
• PM2xXX: power management block 2 registers; XX specifies the hexadecimal byte address offset. Unless
otherwise specified, there is one set of these registers per node; the registers in a node are accessible to any
core on that node. See 3.26.14 [Power Management Block 2 (PM2) Registers].
• SMIxXX: SMI registers; XX specifies the hexadecimal byte address offset. Unless otherwise specified, there
is one set of these registers per node; the registers in a node are accessible to any core on that node. See
3.26.16 [SMI Registers].
• WDTxXX: Watchdog timer registers; XX specifies the hexadecimal byte address offset. Unless otherwise
specified, there is one set of these registers per node; the registers in a node are accessible to any core on that
node. See 3.26.17 [Watchdog Timer (WDT) Registers].
• AcDcTimerxXX: AC/DC wake alarm timer registers; XX specifies the hexadecimal byte address offset.
Unless otherwise specified, there is one set of these registers per node; the registers in a node are accessible
to any core on that node. See 3.26.18 [Wake Alarm Device (AcDcTimer) Registers].
Each mnemonic may specify the location of one or more registers that share the same base definition. A mnemonic that specifies more than one register will contain one or more ranges within braces. The ranges are specified as follows:
• Comma separated lists [A,B]: Define specific instances of a register, e.g., D0F3x[1,0]40 defines two registers D0F3x40 and D0F3x140.
• Colon separated ranges [A:B]: Defines all registers that contain the range between A and B. Examples:
• D0F3x[50:40] defines five registers D0F3x40, D0F3x44, D0F3x48, D0F3x4C, and D0F3x50.
• D[8:2]F0x40 defines seven registers D2F0x40, D3F0x40, D4F0x40, D5F0x40, D6F0x40, D7F0x40, and
D8F0x40.
• D0F0xE4_x013[2:0]_0000 defines three registers D0F0xE4_x0130_0000, D0F0xE4_x0131_0000, and
D0F0xE4_x0132_0000.
• Colon separated ranges with a explicit step [A:BstepC]: Defines the registers from A to B, C defines the offset between registers., e.g., D0F3x[50:40:step8] defines three registers D0F3x40, D0F3x48, and D0F3x50.
The processor includes a single set of IO-space and configuration-space registers. However, APIC, CPUID,
and MSR register spaces are implemented once per processor core. Access to IO-space and configuration space
registers may require software-level techniques to ensure that no more than one core attempts to access a register at a time.
The following is terminology found in the register descriptions.
Table 83: Terminology in Register Descriptions
Term
BIOS
SBIOS
See
Alias
Definition
Software recommendation syntax. See 3.1.2 [Software Recommendation (BIOS,
SBIOS, IBIOS)].
Reference to remote definition. See 3.1.3 [See Keyword (See:)].
The alias keyword allows the definition of a soft link between two registers.
• X is an alias of Y: X is a soft link to the register Y.
• X1, X2 are an alias of Y: Both X1 and X2 are soft links to Y.
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Table 83: Terminology in Register Descriptions
Term
IF
THEN
ELSEIF
ELSE
ENDIF
Access Types
Read
Read-only
Write
Write-only
Read-write
Set-by-hardware
Cleared-by-hardware
Updated-by-hardware
Updated-by-SMU
Write-1-to-clear
Write-1-only
Reset-applied
GP-read
GP-write
GP-read-write
Per-core
Per-compute-unit
Per-L2
Per-node
Not-same-for-all
Same-for-all
Definition
Allows conditional definition as a function of register fields. The syntax is:
• IF (conditional-expression) THEN definition ENDIF.
• IF (conditional-expression) THEN definition ELSE definition ENDIF.
• IF (conditional-expression) THEN definition ELSEIF (conditional-expression)
THEN definition ELSE definition ENDIF.
Capable of being read by software.
Capable of being read but not written by software.
Capable of being written by software.
Write-only. Capable of being written by software. Reads are undefined.
Capable of being written by software and read by software.
Register field is set high by hardware, set low by hardware, or updated by hardware.
Software must write a 1 to the bit in order to clear it. Writing a 0 to these bits has no
affect.
Software can set the bit high by writing a 1 to it. Writes of 0 have no effect.
Takes effect on warm reset.
GP exception occurs on read.
GP exception occurs on write.
GP exception occurs on a read or a write.
One instance per core. Only valid for MMIO config space. Writes of these bits from
one core only affect that core’s register. Reads return the values appropriate to that
core.
One instance per compute unit. Writes of these bits from one core only affect that
compute unit’s register. Reads return the values appropriate to that compute unit.
See 2.4.2.1 [Registers Shared by Cores in a L2 complex].
One instance per L2 cache. See CPUID
Fn8000_001D_EAX_x2[NumSharingCache].
One instance per node. Only valid for MSR space. See 3.1.1 [Northbridge MSRs In
Multi-Core Products].
Provide indication as to whether all instances of a given register should be the same
across all cores/nodes according to the following equation:
SameOnAllCheckEnabled = (Writable && (same-for-all | MSR) && ~(not-samefor-all || UpdatedByHw)). UpdatedByHw = (Updated-by-hardware || set-byhardware || cleared-by-hardware || set-when-done || cleared-when-done). MSR’s
should not be marked with Same-for-all because it is the default setting.
Field Definitions
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Table 83: Terminology in Register Descriptions
Term
Reserved
Unused
MBZ
RAZ
Reset Definitions
Reset
Cold reset
Value
3.1.1
Definition
Field is reserved for future use. Software is required to preserve the state read from
these bits when writing to the register. Software may not depend on the state of
reserved fields nor on the ability of such fields to return the state previously written.
Reset must be specified if the reset value is not 0. Reset may be omitted if the reset
value is 0. Read-write, if it exists, must be in internal-only text. Read-only is
implied if Read-write is not specified.
Field is reserved for future use. Software is not required to preserve the state read
from these bits when writing to the register. Software may not depend on the state
of unused fields nor on the ability of such fields to return the state previously written.
Must be zero. If software attempts to set an MBZ bit to 1, a general-protection
exception (#GP) occurs.
Read as zero. Writes are ignored, unless RAZ is combined with write-only or write1-only. Reset may be omitted.
The reset value of each register is provided below the mnemonic or in the field
description. Unless otherwise noted, the register state matches the reset value when
RESET_L is asserted (either a cold or a warm reset). Reset values may include:
• X: an X in the reset value indicates that the field resets (warm or cold) to an
unspecified state.
The field state is not affected by a warm reset (even if the field is labeled “cold
reset: X”); it is placed into the reset state when PWROK is deasserted. See "Reset"
above for the definition of characters that may be found in the cold reset value.
The current value of a read-only field or register. A value statement explicitly
defines the field or register as read-only and the value returned under all conditions
including after reset events. A field labeled “Value:” will not have a separate reset
definition.
Northbridge MSRs In Multi-Core Products
MSRs that control Northbridge functions are shared between all cores on the node in a multi-core processor
(e.g. MSRC001_001F). If control of Northbridge functions is shared between software on all cores, software
must ensure that only one core at a time is allowed to access the shared MSR. Some MSR’s are conditionally
shared; see D18F3x44[NbMcaToMstCpuEn].
3.1.2
Software Recommendation (BIOS, SBIOS, IBIOS)
The following keywords specify the recommended value to be set by software.
• BIOS: AMD BIOS.
• SBIOS: Platform BIOS.
Syntax: BIOS: integer-expression. Any of the supported tags can be substituted for BIOS.
If “BIOS:” occurs in a register field then the recommended value is applied to the field. If “BIOS:” occurs after
a register name but outside of a register field table row then the recommended value is applied to the width of
the register.
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See Keyword (See:)
There is a special meaning applied to the use of “See:” that differs from the use of See not followed by a “:”.
• See, not followed by a “:”, simply refers the reader to a document location that contains related information.
• See followed by a “:” is a shorthand notation that indicates that the definition for this register or register
field inherits all properties and definitions from the register or register field that follows "See:". Any definition local to the register or register field supercedes this inheritance.
“See:” can be used in the following ways:
• Full register width. CPUID Fn0000_0001_EAX inherits it’s full register width definition from
D18F3xFC.
• Register field. MSR0000_0277[PA1MemType] inherits it’s definition from PA0MemType, however, the
local reset of 4h overrides the inherited PA0MemType reset of 6h.
• Valid values definition. MSR0000_020[E,C,A,8,6,4,2,0][MemType], for example, inherits the valid values definition from Table 191 [Valid Values for Memory Type Definition].
3.1.4
Mapping Tables
The following mapping table types are defined.
3.1.4.1
Register Mapping
The register mapping table specifies the specific function for each register in a range of registers.
Table 176, for example, specifies that the D18F5x160 function is for NB P-state 0.
3.1.4.2
Index Mapping
The index mapping table is similar to the register mapping table, but specifies the register by index instead of
by full register mnemonic.
Table 135 [Index Mapping for D18F2x9C_x0D0F_0[F,8:0]02_dct[0]], for example, specifies that the
D18F2x98_dct[0][31:0]==0D0F_0002h, or D18F2x9C_x0D0F_0002_dct[0], function is for Byte 0.
3.1.4.3
Field Mapping
The field mapping table maps the fields of a range of registers. The rows are the registers that are mapped.
Each column specifies a field bit range that is mapped by that column for all registers. The cell at the intersection of the register and the field bit range specifies the suffix that is appended to the register field. “Reserved”
specifies that the field is reserved for the register of that row. “-” indicates no specification and the table cell
should be skipped.
3.1.4.4
Broadcast Mapping
The broadcast mapping table maps a register address to a range of register addresses that are read or written as
a group when the broadcast register address is read or written. The register address is formed by the concatenation of the row address with the column address. The cell at the intersection of the row and column address is a
range of register addresses that will be read or written as a group when the row and column address is read or
written.
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Reset Mapping
The reset mapping table specifies the reset, cold reset, or value for each register in a range of registers.
Table 186 [Reset Mapping for CPUID Fn8000_0000_E[D,C,B]X], for example, specifies that the CPUID
Fn0000_0000_EBX register has a value of 6874_7541h, with a comment of “The ASCII characters “h t u A””.
3.1.4.6
Valid Values
The valid values table defines the valid values for one or more register fields. The valid values table is equivalent in function to the Bits/Description tables in register fields (E.g. MSR0000_0277[PA0MemType]) and is
most often used when the table becomes too large and unwieldy to be included into the register field. (E.g.
Table 191 [Valid Values for Memory Type Definition])
3.1.4.7
BIOS Recommendations
The BIOS recommendations table defines “BIOS:” recommendations that are conditional and complex enough
to warrent a table.
Table 164 [BIOS Recommendations for D18F2x1B[4:0]], for example, specifies the BIOS recommendations
for D18F2x1B0[DcqBwThrotWm] and D18F2x1B4[DcqBwThrotWm1, DcqBwThrotWm2]. All cells under
the “Condition” header for a given row are ANDed to form the condition for the values to the right of the condition. For example, rows 1-3 and column 1 provide the following equivalent BIOS recommendation:
• D18F2x1B0[DcqBwThrotWm]: BIOS: IF (DdrRate==667) THEN 4h ELSEIF (DdrRate==800) THEN
5h ELSEIF (DdrRate==1066) THEN 6h ESEIF etc.
3.2
IO Space Registers
See 3.1 [Register Descriptions and Mnemonics] for a description of the register naming convention.
IOCF8 IO-Space Configuration Address
Reset: 0. IOCF8 [IO-Space Configuration Address], and IOCFC [IO-Space Configuration Data Port], are used
to access system configuration space, as defined by the PCI specification. IOCF8 provides the address register
and IOCFC provides the data port. Software sets up the configuration address by writing to IOCF8. Then,
when an access is made to IOCFC, the processor generates the corresponding configuration access to the
address specified in IOCF8. See 2.7 [Configuration Space].
IOCF8 may only be accessed through aligned, DW IO reads and writes; otherwise, the accesses are passed to
the appropriate IO link. Accesses to IOCF8 and IOCFC received from an IO link are treated as all other IO
transactions received from an IO link and are forwarded based on the settings in D18F1x[DC:C0] [IO-Space
Base/Limit]. IOCF8 and IOCFC in the processor are not accessible from an IO link.
Bits
31
Description
ConfigEn: configuration space enable. Read-write. 1=IO read and write accesses to IOCFC are
translated into configuration cycles at the configuration address specified by this register. 0=IO read
and write accesses are passed to the appropriate IO link and no configuration access is generated.
30:28 Reserved.
27:24 ExtRegNo: extended register number. Read-write. ExtRegNo provides bits[11:8] and RegNo provides bits[7:2] of the byte address of the configuration register. ExtRegNo is reserved unless it is
enabled by MSRC001_001F[EnableCf8ExtCfg].
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23:16 BusNo: bus number. Read-write. Specifies the bus number of the configuration cycle.
15:11 Device: bus number. Read-write. Specifies the device number of the configuration cycle.
10:8
Function. Read-write. Specifies the function number of the configuration cycle.
7:2
RegNo: register address. Read-write. See IOCF8[ExtRegNo].
1:0
Reserved.
IOCFC IO-Space Configuration Data Port
Bits
Description
31:0 Data. Read-write. Reset: 0. See IOCF8.
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Device 0 Function 0 (Root Complex) Configuration Registers
See 3.1 [Register Descriptions and Mnemonics] for a description of the register naming convention. See 2.7
[Configuration Space] for details about how to access this space.
D0F0x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID. Read-only.
Value: 1536h.
15:0 VendorID: vendor ID. Read-only. Value: 1022h.
D0F0x04 Status/Command
Reset: 0000_0004h.
Bits
Description
31:21 Reserved.
20
CapList: capability list. Read-only. 1=Capability list supported.
19:3 Reserved.
2
BusMasterEn: bus master enable. Read-only.
1
MemAccessEn: memory access enable. Read-only.
0
IoAccessEn: IO access enable. Read-only.
D0F0x08 Class Code/Revision ID
Reset: 0600_0000h.
Bits
Description
31:8 ClassCode: class code. Read-only. Provides the host bridge class code as defined in the PCI specification.
7:0
RevID: revision ID. Read-only.
D0F0x0C Header Type
Reset: 0080_0000h.
Bits
Description
31:24 Reserved.
23
DeviceType. Read-only. 0b=Single function device. 1b=Multi-function device.
22:16 HeaderType. Read-only.
15:8 LatencyTimer. Read-only.
7:0
CacheLineSize. Read-only.
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D0F0x2C Subsystem and Subvendor ID
Bits
Description
31:16 SubsystemID. Read-only; updated-by-hardware. Value: D0F0x50[SubsystemID].
15:0 SubsystemVendorID. Read-only; updated-by-hardware. Value: D0F0x50[SubsystemVendorID].
D0F0x34 Capabilities Pointer
Reset: 0000_0000h.
Bits
Description
31:8 Reserved.
7:0
CapPtr: capabilities pointer. Read-only. There is no capability list.
D0F0x48 NB Header Write Register
Reset: 0000_0080h.
Bits
Description
31:8 Reserved.
7
6:0
DeviceType: device type. Read-write. This field sets the value in the corresponding field in
D0F0x0C[DeviceType]. 0b=Single function device. 1b=Multi-function device.
Reserved.
D0F0x4C PCI Control
Reset: 0000_0000h.
Bits
Description
31:27 Reserved.
26
HPDis: hot plug message disable. Read-write. 1=Hot plug message generation is disabled.
25:24 Reserved.
23
MMIOEnable: memory mapped IO enable. Read-write. 1=Decoding of MMIO cycles is enabled.
The MMIO Base/Limit pair (D0F0x64_x17 and D0F0x64_x18) are decoded. This range is used to
create an MMIO hole in the DRAM address range used for DMA decoding. DMA writes that fall into
the MMIO range are treated as potential p2p requests. DMA reads that fall into the MMIO range are
aborted as unsupported requests.
14:6 Reserved.
5
SerrDis: system error message disable. Read-write. 1=The generation of SERR messages is disabled.
4
PMEDis: PME disable. Read-write. 1=The generation of PME messages is disabled.
3:0
Reserved.
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D0F0x60 Miscellaneous Index
Reset: 0000_0000h. The index/data pair registers, D0F0x60 and D0F0x64, are used to access the registers at
D0F0x64_x[FF:00]. To access any of these registers, the address is first written into the index register,
D0F0x60, and then the data is read from or written to the data register, D0F0x64.
Bits
Description
31:7 Reserved.
6:0
MiscIndAddr: miscellaneous index register address. Read-write.
D0F0x64 Miscellaneous Index Data
See D0F0x60. Address: D0F0x60[MiscIndAddr].
Bits
Description
31:0 MiscIndData: miscellaneous index data register.
D0F0x64_x00 Northbridge Control
Reset: 0000_0000h.
Bits
Description
31:8 Reserved.
7
6:0
HwInitWrLock. Read-write. 1=Lock HWInit registers. 0=Unlock HWInit registers. This bit prevents
updates to the IOC shadow copies of the BIF core configuration registers locked by
D0F0xE4_x0140_0010[HwInitWrLock].
Reserved.
D0F0x64_x0C IOC Bridge Control
Reset: 0000_0000h.
Bits
Description
D0F0x64_x0D IOC PCI Configuration
Bits
0
Description
PciDev0Fn2RegEn. Read-write. Reset: 0. 1=Enable configuration accesses to device 0 function 2.
D0F0x64_x16 IOC Advanced Error Reporting Control
Reset: 0000_0001h.
Bits
0
Description
AerUrMsgEn: AER unsupported request message enable. Read-write. BIOS: 0. 1=AER unsupported request messages are enabled.
193
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D0F0x64_x17 Memory Mapped IO Base Address
Reset: 0000_0000h.
Bits
Description
31:0 MmioBase[47:16]: memory mapped IO base address. Read-write.
D0F0x64_x18 Memory Mapped IO Limit
Reset: 0000_0000h.
Bits
Description
31:0 MmioLimit[47:16]: memory mapped IO limit. Read-write.
D0F0x64_x19 Top of Memory 2 Low
Reset: 0000_0000h.
Bits
Description
31:23 Tom2[31:23]: top of memory 2. Read-write. BIOS: MSRC001_001D[TOM2[31:23]]. This field
specifies the maximum system address for upstream read and write transactions that are forwarded to
the host bridge (from the GNB to the UNB). All addresses less than this system address are forwarded
to DRAM and are not checked to determine if the transaction is a peer-to-peer transaction. All
upstream reads with addresses greater than or equal to this system address are master aborted.
D0F0x64_x46[P2PMode] controls the GNB response to writes with addresses greater than this system address.
22:1 Reserved.
0
TomEn: top of memory enable. Read-write. BIOS: MSRC001_0010[MtrrTom2En]. 1=Top of memory check enabled.
D0F0x64_x1A Top of Memory 2 High
Reset: 0000_0000h.
Bits
Description
31:8 Reserved.
7:0
Tom2[39:32]: top of memory 2. Read-write. BIOS: MSRC001_001D[TOM2[39:32]]. See
D0F0x64_x19[Tom2].
D0F0x64_x1D Internal Graphics PCI Control
Reset: 0000_0000h.
Bits
Description
3
Vga16En: VGA IO 16 bit decoding enable. Read-write. 1=Address bits 15:10 for VGA IO cycles
are decoded. 0=Address bits 15:10 for VGA IO cycles are ignored.
2
Reserved.
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1
VgaEn: VGA enable. Read-write. 1=Enable VGA range in Intgfx.
0
Reserved.
D0F0x64_x1F FCH Location
Reset: 0002_0001h. NOTE: Register value of 32’b0 indicates the GNB is secondary and there is no FCH connected.
Bits
Description
31:16 SBLocatedCore: Indicates which GPP Core has the FCH attached to it. Read-write. This is a
one-hot encoded field.
Definition
Bits
0000h
No FCH attached.
0001h
FCH located under PPD.
0002h
FCH located under SBG.
FFFFh-0003h
Reserved.
15:0 SBLocatedPort: Indicates which Port on the SBLocatedCore has the FCH. Read-write. This is a
one-hot encoded field.
Definition
Bits
0000h
No FCH attached.
0001h
FCH located on Port A of SBLocatedCore.
0002h
FCH located on Port B of SBLocatedCore.
0003h
Reserved.
0004h
FCH located on Port C of SBLocatedCore.
0007h-0005h
Reserved.
0008h
FCH located on Port D of SBLocatedCore.
FFFFh-0009h
Reserved.
D0F0x64_x22 LCLK Control 0
Reset: 7F3F_8100h.
Bits
Description
31
Reserved.
30
SoftOverrideClk0. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for the host request path
to the PCIe cores.
29
SoftOverrideClk1. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for the host request path
to the internal graphics and the host response path.
28
SoftOverrideClk2. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for the host configuration
requests.
27
SoftOverrideClk3. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for the debug bus path.
26
SoftOverrideClk4. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for the host request path
to the configuration block.
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D0F0x64_x23 LCLK Control 1
Reset: 7F3F_8100h.
Bits
Description
31
Reserved.
30
SoftOverrideClk0. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for upstream DMA
requests from all sources.
29
SoftOverrideClk1. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for upstream DMA
requests from the GPPFCH link core.
28
SoftOverrideClk2. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for upstream DMA
requests from internal graphics and its DMA response reordering path.
27
SoftOverrideClk3. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for upstream DMA
requests from internal graphics.
26
SoftOverrideClk4. Read-write. BIOS: 0. 1=Dynamic clock gating disabled for upstream DMA
requests from the Gfx link core.
D0F0x64_x3[4:0] Programmable Device Remap Register
Table 84: Reset values for D0F0x64_x3[4:0]
Register
D0F0x64_x30
D0F0x64_x31
D0F0x64_x32
D0F0x64_x33
D0F0x64_x34
Reset
0000_0011h
0000_0012h
0000_0013h
0000_0014h
0000_0015h
Function
Program [7:3]DevNum, [2:0]FnNum to map to PortA of PPD.
Program [7:3]DevNum, [2:0]FnNum to map to PortB of PPD.
Program [7:3]DevNum, [2:0]FnNum to map to PortC of PPD.
Program [7:3]DevNum, [2:0]FnNum to map to PortD of PPD.
Program [7:3]DevNum, [2:0]FnNum to map to PortE of PPD.
Software can only utilize device and function number combinations that are used by other (local) PCIe bridges.
This effectively allows swapping of device and function numbers between bridges.
Bits
Description
31:8 Reserved.
7:0
DevFnMap. Read-write. Program [7:3]DevNum, [2:0]FnNum to map to PortA/B/C/D of each PCIe
core.
D0F0x64_x46 IOC Features Control
Reset: 0001_1063h.
Bits
Description
27:24 Reserved.
21:17 Reserved.
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16
CgttLclkOverride. Read-write. BIOS: 0. Global bit to disable all LCLK gating branches.
2:1
P2PMode: peer-to-peer mode. Read-write. Specifies how upstream write transactions above
D0F0x64_x19[Tom2] are completed.
Bits
Definition
00b
Mode 0. Master abort writes that do not hit one of the internal PCI bridges. Forward writes that hit one of the internal PCI bridges to the bridge.
01b
Mode 1. Forward writes to the host bridge that do not hit one of the internal PCI
bridges. Forward writes that hit one of the internal PCI bridges to the bridge.
10b
Mode 2. Forward all writes to the host bridge0.
11b
Reserved.
D0F0x7C IOC Configuration Control
Cold reset: 0000_0000h.
Bits
Description
31:1 Reserved.
0
ForceIntGfxDisable: internal graphics disable. Read-write. Setting this bit disables the internal
graphics and the HD Audio controller.
D0F0x84 Link Arbitration
Bits
Description
9
PmeTurnOff: PME_Turn_Off message trigger. Read-write. Reset: 0. 1=Trigger a PME_Turn_Off
message to all downstream devices if PmeMode=1.
8
PmeMode: PME message mode. Read-write. Reset: 0. 1=PME_Turn_Off message is triggered by
writing PmeTurnOff. 0=PME_Turn_Off message is triggered by a PME_Turn_Off message from the
FCH.
7:4
3
2:0
Reserved.
VgaHole: vga memory hole. Read-write. Reset: 1. This bit creates a hole in memory for the VGA
memory range. 1=Requests hitting the VGA range are checked against PCI bridge memory ranges
instead of being forwarded to system memory.
Reserved.
D0F0x90 Northbridge Top of Memory
Reset: 0000_0000h.
Bits
Description
31:23 TopOfDram. Read-write. BIOS: MSRC001_001A[TOM[31:23]]. Specifies the address that divides
between MMIO and DRAM. From TopOfDram to 4G is MMIO; below TopOfDram is DRAM.
See 2.4.3 [Access Type Determination].
22:0 Reserved.
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D0F0x94 Northbridge ORB Configuration Offset
Reset: 0000_0000h.
The index/data pair registers, D0F0x94 and D0F0x98, are used to access the registers at D0F0x98_x[FF:00].
To access any of these registers, the address is first written into the index register, D0F0x94, and then the data
is read from or written to the data register, D0F0x98.
Bits
Description
31:7 Reserved.
6:0
OrbIndAddr: ORB index register address. Read-write.
D0F0x98 Northbridge ORB Configuration Data Port
See D0F0x94. Address: D0F0x94[OrbIndAddr].
Bits
Description
31:0 OrbIndData: ORB index data register.
D0F0x98_x06 ORB Downstream Control 0
Reset: 0000_0000h.
Bits
Description
31:27 Reserved.
26
UmiNpMemWrEn. Read-write. BIOS: See 2.11.4. 1=NP protocol over UMI for memory-mapped
writes targeting LPC enabled. This bit may be set to avoid a deadlock condition.
D0F0x98_x07 ORB Upstream Arbitration Control 0
Reset: 0000_0080h.
Bits
31
Description
SMUCsrIsocEn. Read-write. BIOS: 1. 1=CSR accesses go through ISOC channel. If this bit is set,
D0F0x98_x1E[HiPriEn] must also be set.
30:17 Reserved.
16
SyncFloodOnParityErr. Read-write. Enable short circuit syncflood when arb_np detects a parity
error for error containment.
15
DropZeroMaskWrEn. Read-write. BIOS: 1. 1=Drop byte write request that have all bytes masked.
0=Forward byte write request that have all bytes masked.
14:8 Reserved.
7
IommuIsocPassPWMode. Read-write. BIOS: 1. 1=Always set PassPW for IOMMU upstream isochronous requests.
6
DmaReqRespPassPWMode. Read-write. BIOS: 0. Specifies the RespPassPW bit for non-posted
upstream DMA requests.
Bit
Description
0
Always 1.
1
Value passed from IOC.
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5
Reserved.
4
IommuBwOptEn. Read-write. BIOS: 1. 1=Optimize IOMMU L2 byte write by detecting consecutive DW mask and translate the request to DW write.
3
Reserved.
2
IocRdROMapDis. Read-write. 1=Disable mapping relax ordering bit to RdRespPpw bit for IOC
reads.
1
IocWrROMapDis. Read-write. 1=Disables mapping relax ordering bit to PassPw bit for IOC writes.
0
IocBwOptEn. Read-write. BIOS: 1. 1=Enable optimization of byte writes by detecting consecutive
DW masks and translating the request to DW writes.
D0F0x98_x08 ORB Upstream Arbitration Control 1
This register specifies the weights of the weighted round-robin arbiter in stage 1 of the upstream arbitration for
non-posted reads.
Bits
Description
31:24 NpWrrLenD. Read-write. Reset: 8h. BIOS: 8h. This field defines the maximum number of non-
posted read requests from the SPG (PSP) that are serviced before the arbiter switches to the
next client.
23:16 NpWrrLenC. Read-write. Reset: 8h. BIOS: 1h. This field defines the maximum number of non-
posted read requests from the SMU that are serviced before the arbiter switches to the next
client.
15:8 NpWrrLenB. Read-write. Reset: 8h. BIOS: 8h. This field defines the maximum number of nonposted read requests from IOMMU that are serviced before the arbiter switches to the next
client.
7:0
NpWrrLenA. Read-write. Reset: 8h. BIOS: 8h. This field defines the maximum number of non-
posted read requests from IOC that are serviced before the arbiter switches to the next client.
D0F0x98_x09 ORB Upstream Arbitration Control 2
Reset: 0000_0808h.
This register specifies the weights of the weighted round-robin arbiter in stage 1 of the upstream arbitration for
posted writes.
Bits
Description
31:16 Reserved.
15:8 PWrrLenB. Read-write. This field defines the maximum number of posted write requests from
the IOMMU that are serviced before the arbiter switches to the next client.
7:0
PWrrLenA. Read-write. This field defines the maximum number of posted write requests from
the IOC that are serviced before the arbiter switches to the next client.
D0F0x98_x0C ORB Upstream Arbitration Control 5
Reset: 0000_0808h. This register specifies the weights of the weighted round-robin arbiter in stage 2 of the
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upstream arbitration.
Bits
Description
31:24 Reserved.
23:16 Reserved.
15:8 GcmWrrLenB. Read-write. BIOS: 08h.
This field defines the maximum number of non-posted read requests from stage 1 that are get-
ting serviced in the round-robin before the stage 2 arbiter switches to the next client.
7:0
GcmWrrLenA. Read-write. BIOS: 08h.
This field defines the maximum number of posted write requests from stage 1 that are getting
serviced in the round-robin before the stage 2 arbiter switches to the next client.
D0F0x98_x1E ORB Receive Control 0
Reset: 4800_0000h.
Bits
Description
31:24 RxErrStatusDelay. Read-write. BIOS: 48h. Delay error status by number of LCLK cycles to filter
false errors caused by reset skew.
23:2 Reserved.
1
HiPriEn. Read-write. BIOS: 1. 1=High priority channel enabled. See D0F0x98_x27[UrRedirectAddr[31:6]] . IF (D0F0x98_x1E[HiPriEn]==0) THEN (D0F0x98_x07[SMUCsrIsocEn]==0).
IF (D0F0x98_x1E[HiPriEn]==1) THEN (D18F0x[E4,C4,A4,84][IsocEn]==1) in order to fully
enable the Isoc channel on the ONION Link.
D0F0x98_x26 ORB IOMMU Control 0
Reset: 0000_0000h.
Bits
Description
31:8 Reserved.
7:0
UrRedirectAddr[39:32]. Read-write. See: D0F0x98_x27[UrRedirectAddr[31:6]].
D0F0x98_x27 ORB IOMMU Control 1
Reset: 0000_0000h.
Bits
Description
31:6 UrRedirectAddr[31:6]. Read-write. BIOS: UrRedirectAddr[39:6] must be programmed to a safe
system memory address. UrRedirectAddr[39:6] = {D0F0x98_x26[UrRedirectAddr[39:32]], UrRedirectAddr[31:6]}. IOMMU requests that are not directed to system memory are redirected to UrRedirectAddr.
5:0
Reserved.
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D0F0x98_x28 ORB Transmit Control 0
Reset: 0000_0002h.
Bits
Description
1
ForceCoherentIntr. Read-write. BIOS: 1. 1=Interrupt request are forced to have coherent bit set.
0
Reserved.
D0F0x98_x2C ORB Clock Control
Reset: 000F_0204h.
Bits
Description
31:16 WakeHysteresis. Read-write. Char.Temp.BIOS: 19h. Specifies the amount of time hardware waits
after ORB becomes idle before deasserting the wake signal to the NB. Wait time = WakeHysteresis *
200ns. (Wait time = WakeHysteresis * SMU timer pulse distance.)Changes to this field
should be done prior to setting DynWakeEn.
15:10 Reserved.
9
8:3
SBDmaActiveMask. Read-write. BIOS: 1. 0=SB_DMA_ACTIVE_L state affects OnInbWake state.
1= SB_DMA_ACTIVE_L state is masked out.
Reserved.
2
CgttLclkOverride. Read-write. BIOS: 0h. Global bit to disable all LCLK gating branches in the
ORB.
1
DynWakeEn. Read-write. BIOS: 1. 1=Enable dynamic toggling of the wake signal between ORB
and NB. 0=Disable dynamic toggling of the wake signal. See WakeHysteresis.
0
Reserved.
D0F0x98_x37 ORB Allow LDTSTOP Control 0
Reset: 0020_0000h.
Bits
Description
31:28 Reserved.
27:16 LDTStopHystersis. Read-write. Specifies the number of timer periods (200 ns) (SMU timer
pulse distance.) the AllowLDTStop signal is held low before ORB asserts the signal again.
15:2 Reserved.
1
DmaActiveOutEn. Read-write. 1=Enable ORB to drive the DMAACTIVE_L pin. Meaningful only
when D0F0x98_x37[AllowLDTStopPinMode]==0.
0
AllowLDTStopPinMode. Read-write. Indicates the definition of the ALLOW_LDTSTOP pin. 0=Pin
is used as DMAACTIVE_L. 1=Pin is used as ALLOW_LDTSTOP.
D0F0x98_x3A ORB Source Tag Translation Control 2
Reset: 0000_0000h.
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Bits
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Description
31:0 ClumpingEn. Read-write. BIOS should follow the below requirements.
Valid only for PPD and GBIF client clumping; internal unit ID ranges 4h-8h and 14h-17h respectively.
Legal PPD clumping settings are: [8:4]=00010b, applicable only in x0/0/0/0/8 system configuration,
recommended.
Legal GBIF clumping settings are: [23:20]=0010b, 0110b and 1110b which are applicable in any system configuration. 1110b is the recommended value.
All other bits of this register must always remain 0. See D18F0x[11C,118,114,110].
D0F0x98_x3B ORB Source Tag Translation Control 3
Reset: 0000_0000h.
Bits
Description
31:0 IocOutstandingMask. Read-write. Limit number of outstanding requests for very dma client via the
IOC.
D0F0x98_x4[A,9] ORB LCLK Clock Control 1-0
Reset: 7F3F_8100h.
Bits
Description
31
Reserved.
30
SoftOverrideClk0. Read-write.
BIOS: 0.
See SoftOverrideClk6.
29
SoftOverrideClk1. Read-write.
BIOS: 0.
See SoftOverrideClk6.
28
SoftOverrideClk2. Read-write.
BIOS: 0.
See SoftOverrideClk6.
27
SoftOverrideClk3. Read-write.
BIOS: 0.
See SoftOverrideClk6.
26
SoftOverrideClk4. Read-write.
BIOS: 0.
See SoftOverrideClk6.
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25
SoftOverrideClk5. Read-write.
BIOS: 0.
See SoftOverrideClk6.
24
SoftOverrideClk6. Read-write.
BIOS: 0.
1=Clock gating disabled. 0=Clock gating enabled. RULE: IF (SoftOverrideClk6==0) THEN
(SoftOverrideClk3==0) ENDIF.
D0F0xB8 SMU Index Address
The index/data pair registers, D0F0xB8 and D0F0xBC, are used to access the registers at
D0F0xBC_x[FFFFFFFF:00000000]. To access any of these registers, the address is first written into the index
register, D0F0xB8, and then the data is read from or written to the data register, D0F0xBC. Only a subset of
SMU registers are listed in the BKDG.
Bits
Description
31:0
NbSmuIndAddr: smu index address. Read-write. Reset: 0.
D0F0xBC SMU Index Data
See D0F0xB8. Address: D0F0xB8[NbSmuIndAddr].
Bits
Description
31:0 NbSmuIndData: smu index data.
D0F0xBC_x3F800 FIRMWARE_FLAGS
Reset: xxxx_xxxxh.
Bits
Description
31:24 TestCount. Read-write; updated-by-SMU. Test count. Increments when ever Test service (Service
Index 0) is called.
23:1
0
Reserved. Read-write.
InterruptsEnabled. Read-write.
Bits
Definition
0
Firmware has not yet enabled interrupts. BIOS/Driver cannot yet send message
interrupts to SMC.
1
Firmware has enabled interrupts. BIOS/Driver can send message interrupts to
SMC.
D0F0xBC_x3F804 FIRMWARE_VID
Reset: xxxx_xxxxh.
Bits
Description
7:0
FirmwareVid. Read-write. Current voltage set by firmware voltage controller. The default value is
specified by Fuse[SclkVid3].
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D0F0xBC_x3F820 PM_INTERVAL_CNTL_0
Reset: xxxx_xxxxh.
Bits
Description
31:24 Loadline. Read-write.
23:16 VoltageCntl. Read-write.
15:8
ThermalCntl. Read-write. Specifies the period at which the GNB thermal algorithm is run.
Period=D0F0xBC_x3F828[TimerPeriod] period*ThermalCntl. See 2.11.6.3 [GNB Thermal Control].
7:0
LclkDpm. Read-write.
D0F0xBC_x3F828 PM_TIMER_PERIOD
Bits
Description
31:0
TimerPeriod. Read-write. Reset: X. Specifies the period at which various power management related
algorithms are run. Period = TimerPeriod / REFCLK.
D0F0xBC_x3F9D8 PM_CONFIG
Reset: xxxx_xxxxh.
Bits
Description
31:30 Reserved. Read-write.
29
SviMode. Read-write.
Bits
Description
0
SVI1.
1
SVI2.
28
BapmCoeffOverride. Read-write.
Bits
Description
0
Calculate filter coefficients.
1
Use SW programmed filter coefficients; ignored if D18F4x15C[BoostLock]==1.
27
NbPstateAllCpusIdle. Read-write. BIOS: For CPU P-state associated with D18F3xA8[PopDownPstate], IF (MSRC001_00[6B:64][NbPstate]==0) THEN 1. ELSE 0. ENDIF.
Bits
Description
0
Use low NB P-state voltage when AllCpusIdle.
1
Use high NB P-state voltage when AllCpusIdle.
26:24 PstateAllCpusIdle. Read-write. BIOS: D18F3xA8[PopDownPstate]. This field specifies the core Pstate to use for IDD calculation when AllCpusIdle.
5
EnableNbDpm. Read-write.
Bits
Description
0
Disable Dynamic NB Pstate Management. Should be cleared before sending
BIOSSMC_MSG_NBDPM_Disable message to SMU.
1
Enable Dynamic NB Pstate Management. Should be set before sending
BIOSSMC_MSG_NBDPM_Enable message to SMU.
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3
EnableLpmx. Read-write.
Bits
Description
0
Disable LPMx. Should be cleared before sending
BIOSSMC_MSG_LPMX_DISABLE message to SMU.
1
Enable LPMx. Should be set before sending
BIOSSMC_MSG_LPMX_ENABLE message to SMU.
2
EnableTdcLimit. Read-write.
Description
Bits
0
Disable TDC Limit Check. Should be cleared before sending
BIOSSMC_MSG_TDC_LIMIT_DISABLE message to SMU.
1
Enable TDC Limit Check. Should be set before sending
BIOSSMC_MSG_TDC_LIMIT_ENABLE message to SMU.
1
EnableBapm. Read-write.
Description
Bits
0
Disable BAPM. Should be cleared before sending
BIOSSMC_MSG_BAPM_DISABLE message to SMU.
1
Enable BAPM. Should be set before sending
BIOSSMC_MSG_BAPM_ENABLE message to SMU.
0
EnableVpcAccumulators. Read-write.
Description
Bits
0
Disable Voltage, Power, Current Accumulator. Should be cleared before sending SMC_MSG_CONFIG_VPC_ACCUMULATOR message to SMU.
1
Enable Voltage, Power, Current Accumulator. Should be set before sending
SMC_MSG_CONFIG_VPC_ACCUMULATOR message to SMU.
D0F0xBC_x3F9E8 NB_DPM_CONFIG_1
Reset: xxxx_xxxxh.
Bits
Description
31:24 DpmXNbPsHi. Read-write. See: Dpm0PgNbPsLo.
23:16 DpmXNbPsLo. Read-write. See: Dpm0PgNbPsLo.
15:8
Dpm0PgNbPsHi. Read-write. See: Dpm0PgNbPsLo.
7:0
Dpm0PgNbPsLo. Read-write. Indexes the NB P-state used during specific levels of GPU activity.
See 2.5.4.1 [NB P-states].
Bits
NB P-state Indexed
00b
D18F3x160 (see D18F5x16[C:0]).
01b
D18F3x164 (see D18F5x16[C:0]).
10b
D18F3x168 (see D18F5x16[C:0]).
11b
D18F3x16C (see D18F5x16[C:0]).
D0F0xBC_x3F9EC NB_DPM_CONFIG_2
Reset: xxxx_xxxxh.
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Bits
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Description
31:25 Reserved.
24
EnableNbPsi1. Read-write. Specifies how PSI1_L functions for VDDNB. 0=SMU firmware clears
D18F5x188[NbPsi1] to 0. 1=SMU firmware sets D18F5x188[NbPsi1] to 1 whenever the GPU is
power gated and in DPM0. See 2.5.6.1.2 [SCLK DPM] and 2.5.6.2 [GPU and Root Complex Power
Gating].
23:17 Reserved.
16
15:9
8
7:0
SkipDPM0. Read-write. Specifies whether SMU waits for SCLK DPM to transition to state 0 before
transitioning UNB to the NB P-states indexed Dpm0PgNbPsHi and Dpm0PgNbPsLo. 0=Wait for
SCLK DPM state 0. 1=Do not wait for SCLK DPM state 0. See 2.5.4.1 [NB P-states].
Reserved.
SkipPG. Read-write. Specifies whether SMU waits for the GPU to be power gated before transitioning UNB to the NB P-states indexed Dpm0PgNbPsHi and Dpm0PgNbPsLo. 0=Wait for GPU power
gating. 1=Do not wait for GPU power gating. See 2.5.4.1 [NB P-states].
Hysteresis. Read-write. Specifies the time the GPU must be idle before transitioning to the NB Pstates indexed by Dpm0PgNbPsHi and Dpm0PgNbPsLo.
D0F0xBC_x3F9F4 CSR_GNB_1
Bits
Description
31:24 SviTrimValueVddNB. Read-write. Reset: x. BIOS: D18F5x188[NbLoadLineTrim].
23:16 SviTrimValueVdd. Read-write. Reset: x. BIOS: D18F5x12C[CoreLoadLineTrim].
15:0
Reserved.
D0F0xBC_x3F9F8 CSR_GNB_3
Reset: xxxx_xxxxh.
Bits
Description
31:16 Reserved. Read-write.
15:8
SviLoadLineOffsetVddNB. Read-write. Reset: x. BIOS: D18F5x188[NbOffsetTrim].
7:0
SviLoadLineOffsetVdd. Read-write. Reset: x. BIOS: D18F5x12C[CoreOffsetTrim].
D0F0xBC_x3FD[8C:00:step14] LCLK DPM Control 0
Reset: xxxx_xxxxh. See 2.5.6.1.3 [LCLK DPM]. Each register in D0F0xBC_x3FD[8C:00:step14] corresponds
to one LCLK DPM state as follows.
Table 85: Register Mapping for D0F0xBC_x3FD[8C:00:step14]
Register
D0F0xBC_x3FD00
D0F0xBC_x3FD14
D0F0xBC_x3FD28
D0F0xBC_x3FD3C
Function
State 0
State 1
State 2
State 3
Register
D0F0xBC_x3FD50
D0F0xBC_x3FD64
D0F0xBC_x3FD78
D0F0xBC_x3FD8C
Function
State 4
State 5
State 6
State 7
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48751 Rev 3.00 - May 30, 2013
Bits
BKDG for AMD Family 16h Models 00h-0Fh Processors
Description
31:24 StateValid. Read-write. 1=DPM state is valid. 0=DPM state is invalid.
23:16 LclkDivider. Read-write. Specifies the LCLK divisor for this DPM state.
15:8
VID. Read-write. Specifies the VDDNB VID for this DPM state.
7:0
LowVoltageReqThreshold. Read-write.
D0F0xBC_x3FD[94:08:step14] LCLK DPM Control 2
Reset: xxxx_xxxxh. See 2.5.6.1.3 [LCLK DPM]. Each register in D0F0xBC_x3FD[94:08:step14] corresponds
to one LCLK DPM state as follows.
Table 86: Register Mapping for D0F0xBC_x3FD[94:08:step14]
Register
D0F0xBC_x3FD08
D0F0xBC_x3FD1C
D0F0xBC_x3FD30
D0F0xBC_x3FD44
Bits
Function
State 0
State 1
State 2
State 3
Register
D0F0xBC_x3FD58
D0F0xBC_x3FD6C
D0F0xBC_x3FD80
D0F0xBC_x3FD94
Function
State 4
State 5
State 6
State 7
Description
31:16 ResidencyCounter. Read-write; S3-check-exclude.
15:8
HysteresisUp. Read-write; S3-check-exclude.
7:0
HysteresisDown. Read-write; S3-check-exclude.
D0F0xBC_x3FD[9C:10:step14] LCLK DPM Activity Thresholds
Reset: xxxx_xxxxh. See 2.5.6.1.3 [LCLK DPM]. Each register in D0F0xBC_x3FD[9C:10:step14] corresponds
to one LCLK DPM state as follows.
Table 87: Register Mapping for D0F0xBC_x3FD[9C:10:step14]
Register
D0F0xBC_x3FD10
D0F0xBC_x3FD24
D0F0xBC_x3FD38
D0F0xBC_x3FD4C
Bits
Function
State 0
State 1
State 2
State 3
Register
D0F0xBC_x3FD60
D0F0xBC_x3FD74
D0F0xBC_x3FD88
D0F0xBC_x3FD9C
Function
State 4
State 5
State 6
State 7
Description
31:24 ActivityThreshold. Read-write. This field specifies the activity threshold as a percentage from 0 to
100%. When the current activity is above the threshold, DPM state is shifted up and when current
activity is below the threshold, DPM state is shifted down.
23:16 EnabledForThrottle. Read-write.
15:0
Reserved.
207
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BKDG for AMD Family 16h Models 00h-0Fh Processors
D0F0xBC_x3FDC8 SMU_LCLK_DPM_CNTL
Reset: xxxx_xxxxh.
Bits
Description
31:24 LclkDpmEn. Read-write. 1b=Enable LCLK DPM
23:16 VoltageChgEn. Read-write. 1=Enable voltage change during LCLK DPM state transition.
15:8
LclkDpmBootState. Read-write.
7:0
Reserved.
D0F0xBC_x3FDD0 SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL
Reset: xxxx_xxxxh. See 2.11.6.3 [GNB Thermal Control].
Bits
Description
31:24 TtHtcActive. Read-write.
23:16 LclkTtMode. Read-write; updated-by-SMU.
Bits
Definition
000b
LCLK thermal throttling is not active. The temperature is below the threshold.
100b
High temperature threshold has been reached and LCLK state is shifted down
15:8
TemperatureSel. Read-write.
Bits
Definition
0
Use local (GNB) maximum temperature for LCLK thermal throttling.
1
Use global maximum temperature for LCLK thermal throttling.
7:0
LclkThermalThrottlingEn. Read-write. 1=Enable LCLK thermal throttling.
D0F0xBC_x3FDD4 SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS
Reset: xxxx_xxxxh. See 2.11.6.3 [GNB Thermal Control].
Bits
Description
31:16 HighThreshold. Read-write. Specifies the high thermal threshold for LCLK thermal throttling. See
D18F5xA8_x383[GblMaxTemp].
15:0
LowThreshold. Read-write. Specifies the low thermal threshold for LCLK thermal throttling. See
D18F5xA8_x383[GblMaxTemp].
208
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BKDG for AMD Family 16h Models 00h-0Fh Processors
D0F0xBC_xC020_008C LCLK_DEEP_SLEEP_CNTL
Bits
Description
2:0
DivId. Read-write. Reset: 5. BIOS: 100b.
Description
Bits
000b
Clock OFF
001b
Divide by 2
010b
Divide by 4
011b
Divide by 8
100b
Divide by 16
101b
Divide by 32
110b
Reserved
111b
Reserved
D0F0xBC_xC020_0110 Activity Monitor Control
Bits
Description
31:11 Reserved.
10
EnOrbDsCnt. Read-write. Reset: X. 1=Enable ORB downstream counter.
9
EnOrbUsCnt. Read-write. Reset: X. 1=Enable ORB upstream counter.
8
EnBifCnt. Read-write. Reset: X. 1=Enable BIF counter.
4:3
BusyCntSel. Read-write. Reset: 0. Specifies subcomponents or activity monitored by the LCLK
activity monitor.
Bits
Definition
Bits
Definition
00b
GFX DMA (BIF)
10b
ORB Downstream activity
01b
ORB Upstream activity
11b
ORB Up/downstream activity max
2
Reserved.
1
PeriodCntRst. Read-write. Reset: X.
0
ActivityCntRst. Read-write. Reset: X.
D0F0xBC_xC210_0000 CPU Interrupt Request
See 2.12.1 [Software Interrupts].
Bits
Description
31:17 Reserved.
16:1
0
ServiceIndex. Read-write; S3-check-exclude. Reset: 0.
IntToggle. Read-write; S3-check-exclude. Reset: 0.
D0F0xBC_xC210_0004 CPU Interrupt Status
See 2.12.1 [Software Interrupts].
Bits
Description
31:2
Reserved.
209
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BKDG for AMD Family 16h Models 00h-0Fh Processors
1
IntDone. Read-only; updated-by-hardware. Reset: 0.
0
IntAck. Read-only; updated-by-hardware. Reset: 0.
D0F0xBC_xC210_003C CPU Interrupt Argument
See 2.12.1 [Software Interrupts].
Bits
Description
31:0
Argument. Read-write. Reset: 0. Optional argument for a software interrupt.
D0F0xBC_xC210_0040 CPU Interrupt Response
See 2.12.1 [Software Interrupts].
Bits
Description
31:0
Argument. Read-write. Reset: 0. Optional response data upon completing a software interrupt.
D0F0xC8 DEV Index Address
The index/data pair registers, D0F0xC8 and D0F0xCC are used to access the registers at D0F0xCC_x[FF:00].
To access any of these registers, the address is first written into the index register, D0F0xC8, and then the data
is read from or written to the data register, D0F0xCC. Specific bridges (Device/Function) are selected using the
D0F0xC8[NbDevIndSel] field.
Bits
Description
31:24 Reserved.
23:16 NbDevIndSel: Device selector. Read-write. Reset: 0.
Bits
Definition
Bits
Definition
10h-00h Reserved
15h
D2F5
11h
D2F1
FFh-16h Reserved
12h
D2F2
13h
D2F3
14h
D2F4
15:7
Reserved.
6:0
NbDevIndAddr: Bridge (Device) index address. Read-write. Reset: 0.
D0F0xCC DEV Index Data
See D0F0xC8. Address: D0F0xC8[NbDevIndAddr].
Bits
Description
31:0
NbDevIndData: dev index data.
D0F0xCC_x01 IOC Bridge Control
Reset: 0000_0000h.
210
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Bits
BKDG for AMD Family 16h Models 00h-0Fh Processors
Description
31:24 ApicRange. Read-write. Sets the bridge APIC range.
23
ApicEnable. Read-write. 1=Enables the bridge APIC range decoding. Requests fall in bridge APIC
range if addr[39:12]={20’h00_FEC, APIC_Range[7:0]}.
22:21 Reserved.
20
SetPowEn. Read-write. 1=Enable generation of set_slot_power message to the bridge.
19
Reserved.
18
CrsEnable. Read-write. 1=Enables the hardware retry on receiving configuration request retry status.
17
ExtDevCrsEn. Read-write. 1=Reset the bridge CRS counter when an external device is plugged in or
the link is down.
16
ExtDevPlug. Read-write. 1=Indicates to IOC that an external device is being plugged on the bridge.
15:4
Reserved.
3
P2pDis. Read-write. 1=Disables local peer-to-peer transactions forwarded to this bridge.
2
CfgDis. Read-write. 1=Configuration accesses to this bridge are disabled. Non-FCH bridges are not
expected to set this bit.
1
BusMasterDis. Read-write. 1=The bridge’s ability to operate as a bus master is disabled. This overrides the Bus Master Enable bit in the bridge.
0
BridgeDis. Read-write. 1=The bridge is hidden and no accesses are allowed to this bridge.
D0F0xD4_x0109_14C3 Bif Doorbell Control Ind
Reset: 0000_0000h.
Bits
Description
D0F0xD4_x0109_14E1 CC Bif Bx Strap0 Ind
Reset: 0000_C004h.
Bits
Description
12
StrapBifDoorbellBarDis. Read-write.
5:3
StrapBifMemApSize. Read-write.
2:1
StrapBifRegApSize. Read-write.
0
Reserved.
D0F0xD4_x0109_14E2 CC Bif Bx Strap1 Ind
Reset: 0000_0000h.
Bits
Description
3
StrapBifF064BarDisA. Read-write.
1
StrapBifIoBarDis. Read-write.
0
Reserved.
211
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BKDG for AMD Family 16h Models 00h-0Fh Processors
D0F0xD4_x0109_1507 CC Bif Bx Pinstrap0 Ind
Reset: 0000_0802h.
Bits
Description
7:5
StrapBifMemApSizePin. Read-write.
D0F0xE0 Link Index Address 1
Reset: 0130_8001h.
D0F0xE0 and D0F0xE4 are used to access D0F0xE4_x[FFFF_FFFF:0000_0000]. To read or write to one of
these register, the address is written first into the address register D0F0xE0 and then the data is read from or
written to the data register D0F0xE4.
The phy index registers (D0F0xE4_x0[2:1]xxx_xxxx]) mapping to a specific phy, pin or pin group is shown in
a table in the register definition. For example, to perform a read or write operation to configure Gfx phy 0
(P_GFX_[T,R]X[P,N][7:0] pin group) compensation, software should program D0F0xE0[31:0]=0120_0000h.
Accessing any register number that is not listed in the mapping table may result in undefined behavior.
Some phy registers support broadcast write operations to groups of 4 or 8 lanes. For example, to perform
broadcast write operation to configure Gfx Link[3:0] (P_GFX_RX[P,N][3:0] lanes) receiver phase loop filter,
software should program D0F0xE0[31:0]=0120_5602h.
Bits
Description
31:24 BlockSelect: block select. Read-write; S3-check-exclude. This field is used to select the specific register block to access. The encodings supported depends on the FrameType selected.
Encoding
FrameType
01h
1=GPP link core
10h
1=Phy interface 0
20h
1=Phy 0
30h
1=Wrapper
40h
1=IO link core
23:16 FrameType: frame type. Read-write; S3-check-exclude. This field is used to select the type of register block to access.
Bits
Destination
10h
GPP Phy interface block registers.
20h
GPP Phy registers.
30h
GPP Wrapper registers.
40h
GPP IO Link registers.
15:0 PcieIndxAddr: index address. Read-write; S3-check-exclude.
D0F0xE4 Link Index Data 1
S3-check-exclude. See D0F0xE0. Address: {D0F0xE0[BlockSelect],D0F0xE0[FrameType],D0F0xE0[PcieIndxAddr]}.
212
48751 Rev 3.00 - May 30, 2013
Bits
BKDG for AMD Family 16h Models 00h-0Fh Processors
Description
31:0 PcieIndxData: index data.
3.3.1
PIF Registers
D0F0xE4_x0110_0010 PIF Control (GPPSB_PIF0_CNTL)
Reset: 3190_44D8h.
Bits
Description
19:17 Ls2ExitTime: LS2 exit time. Read-write.
Bits
Definition
000b
14us
001b
10us
010b
15us
011b
20us
Bits
100b
101b
110b
111b
Definition
30us
100ns
100us
50us
7
RxDetectTxPwrMode: receiver detection transmitter power mode. Read-write. 1=Transmitter is
powered on.
6
RxDetectFifoResetMode: receiver detect FIFO reset mode. Read-write. BIOS: 1. 1=The transmit
FIFO is reset after receiver detection. 0=The transmit FIFO is not reset after receiver detection.
4
EiDetCycleMode: electrical idle detect mode. Read-write. 1=Electrical idle cycle detection mode is
enabled in L1. 0=Electrical idle detection is always enabled in L1.
D0F0xE4_x0110_0011 PIF Pairing (PIF0_PAIRING)
Reset: 0200_0000h.
Bits
Description
31:26 Reserved.
25
MultiPif: x16 link. Read-write. 1=Lanes 7:0 are paired with a second PIF to create a x16 link.
24:21 Reserved.
20
X16Lane150: x16 link lanes 15:0. Read-write. 1=Lanes 15:0 are paired to create a x16 link.
19:18 Reserved.
17
X8Lane158: x8 link lanes 15:8. Read-write. 1=Lanes 15:8 are paired to create a x8 link.
16
X8Lane70: x8 link lanes 7:0. Read-write. 1=Lanes 7:0 are paired to create a x8 link.
15:12 Reserved.
11
X4Lane1512: x4 link lanes 15:12. Read-write. 1=Lanes 15:12 are paired to create a x4 link.
10
X4Lane118: x4 link lanes 11:8. Read-write. 1=Lanes 11:8 are paired to create a x4 link.
9
X4Lane74: x4 link lanes 7:4. Read-write. 1=Lanes 7:4 are paired to create a x4 link.
8
X4Lane30: x4 link lanes 3:0. Read-write. 1=Lanes 3:0 are paired to create a x4 link.
7
X2Lane1514: x2 link lanes 15:14. Read-write. 1=Lanes 15:14 are paired to create a x2 link
6
X2Lane1312: x2 link lanes 13:12. Read-write. 1=Lanes 13:12 are paired to create a x2 link
5
X2Lane1110: x2 link lanes 11:10. Read-write. 1=Lanes 11:10 are paired to create a x2 link
4
X2Lane98: x2 link lanes 9:8. Read-write. 1=Lanes 9:8 are paired to create a x2 link
213
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BKDG for AMD Family 16h Models 00h-0Fh Processors
3
X2Lane76: x2 link lanes 7:6. Read-write. 1=Lanes 7:6 are paired to create a x2 link.
2
X2Lane54: x2 link lanes 5:4. Read-write. 1=Lanes 5:4 are paired to create a x2 link.
1
X2Lane32: x2 link lanes 3:2. Read-write. 1=Lanes 3:2 are paired to create a x2 link.
0
X2Lane10: x2 link lanes 1:0. Read-write. 1=Lanes 1:0 are paired to create a x2 link.
D0F0xE4_x0110_001[8:7,3:2] PIF Power Down Control [3:0] (PIF0_PWRDOWN)
Reset: 0001_1FA2h.
Table 88: Index addresses for D0F0xE4_x0110_001[8:7,3:2]
D0F0xE0[31:16]
0110h
Bits
D0F0xE0[15:0]
0018h
0017h
0013h
0012h
PIF Lanes 15-12
PIF Lanes 11-8
PIF Lanes 7-4
PIF Lanes 3-0
Description
31:29 PllPwrOverrideVal: PLL power state override value. Read-write. See TxPowerStateInTxs2.
28
PllPwrOverrideEn: PLL power state override enable. Read-write. 1=PLL forced to the power
state specified by PllPwrOverrideVal.
27
Reserved.
26:24 PllRampUpTime: PLL ramp time. Read-write.
Bits
Definition
000b
10 us
001b
5 us
010b
15 us
011b
22 us
Bits
100b
101b
110b
111b
Definition
50 us
300 us
500 us
800 us
23:17 Reserved.
16
Tx2p5clkClockGatingEn. Read-write. 1=The 2.5x TxClk is gated if the lane is idle 0=The 2.5x
TxClk is never gated.
15:13 Reserved.
12:10 PllPowerStateInOff: PLL off power state. Read-write. See: TxPowerStateInTxs2. All links associated with the PLL must be in the off state to transition the PLL to this state.
9:7
PllPowerStateInTxs2: PLL L1 power state. Read-write. See: TxPowerStateInTxs2. All links associated with the PLL must be in L1 to transition the PLL to this state.
6:4
RxPowerStateInRxs2: receiver L1 power state. Read-write. See: TxPowerStateInTxs2.
3
2:0
ForceRxEnInL0s: force receiver enable in L0s. Read-write. 1=The phy CDR is always enabled in
L0s.
TxPowerStateInTxs2: transmitter L1 power state. Read-write.
Bits
Definition
Bits
000b
L0
100b
001b
LS1
101b
010b
LS2
110b
011b
Reserved
111b
Definition
Reserved
Reserved
Reserved
Off
214
48751 Rev 3.00 - May 30, 2013
3.3.2
3.3.2.1
BKDG for AMD Family 16h Models 00h-0Fh Processors
Phy Registers
Global Phy Control Registers
D0F0xE4_x0120_0004 Phy Global Control 0
Bits
Description
17:16 CfgIdleDetTh. Read-write. Reset: 1. BIOS: 0. Idle detector threshold control
D0F0xE4_x0120_4440 Phy RO PLL Control
Bits
Description
14:13 PllDbgRoIPFDResetCntrl. Read-write. Reset: 0. BIOS: 2. PFD reset pulse width control.
Bits
Definition
00b
PFD reset pulse width = 603 ps (@85C_tt)
01b
PFD reset pulse width =190 ps (@85C_tt)
10b
PFD reset pulse width = 397 ps (@85C_tt)
11b
PFD reset pulse width = 82 ps (@85C_tt)
D0F0xE4_x0120_4450 PhyRO PLL Override Control 0
Bits
Description
30
PllCfgROVTOIBiasCntrlOvrdVal0. Read-write. Reset: 1. BIOS: 0. Override value bit for
CP_PLL_CFG_RO_VTOI_BIAS_CNTRL.
7:0
PllCfgROBWCntrlOvrdVal0. Read-write. Reset: 8Dh. BIOS: 90h. Override value bit for
CP_PLL_CFG_RO_BW_CNTRL.
Bit
Definition
[7:3]
Proportional CP current setting
[2:0]
Integral CP current setting
215
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3.3.3
BKDG for AMD Family 16h Models 00h-0Fh Processors
Wrapper Registers
D0F0xE4_x0130_0046 Subsystem and Vendor ID
Bits
Description
31:16 SubsystemID: subystem id. Read-write. Reset: 1234h. Specifies the value returned by
D2F[5:1]xB4[SubsystemID].
15:0 SubsystemVendorID: subsystem vendor id . Read-write. Reset: 1022h. Specifies the value returned
by D2F[5:1]xB4[SubsystemVendorID].
D0F0xE4_x0130_0080 Link Configuration (PCIE_LINK_CONFIG)
Reset: 0000_0000h.
Bits
Description
31:4 Reserved.
3:0
StrapBifLinkConfig. Read-write; strap.
BIOS: See Table 62.
Bits
Definition
0000b Reserved
0001b x4 IO Link (GPPFCH Only)
0010b 2 x2 IO Links (GPPFCH Only)
0011b
1 x2 IO Link, 2 x1 IO Links (GPPFCH Only)
Bits
0100b
0101b
011xb
1xxxb
Definition
4 x1 IO Links (GPPFCH Only)
Reserved
Reserved
Reserved
D0F0xE4_x0130_0[C:8]00 Link Hold Training Control (PCIE_HOLD_TRAINING)
Table 89: Index address mapping for D0F0xE4_x0130_0[C:8]00
Index
0130_0800h
0130_0900h
0130_0A00h
0130_0B00h
0130_0C00h
Bits
Function
GPPSB PortA
GPPSB PortB
GPPSB PortC
GPPSB PortD
GPPSB PortE
Description
31:1 Reserved.
0
HoldTraining: hold link training. Read-write. Reset: 1. 1=Hold training on link.
216
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
D0F0xE4_x0130_0[C:8]03 Link Deemphasis Control (LC_MISC_PORT)
Table 90: Index address mapping for D0F0xE4_x0130_0[C:8]03
Index
0130_0803h
0130_0903h
0130_0A03h
0130_0B03h
0130_0C03h
Bits
Function
GPPSB PortA
GPPSB PortB
GPPSB PortC
GPPSB PortD
GPPSB PortE
Description
31:6 Reserved.
5
StrapBifDeemphasisSel. Read-write; strap. Reset: 1. Controls the default value of
D2F[5:1]x88[SelectableDeemphasis]. 1=RC advertises -3.5dB. 0=RC advertises -6dB.
D0F0xE4_x0130_0[C:8]04 Link AER Control
Bits
Description
3:1
StrapBifMaxPayloadSupport. Read-write; strap. Reset: 2h. BIOS: See 2.11.3.2 [Link Configurations].
D0F0xE4_x0130_0[C:8]05 Link Training Control
Reset: 1800_0000h.
Table 91: Index address mapping for D0F0xE4_x0130_0[C:8]05
Index
0130_0805h
0130_0905h
0130_0A05h
0130_0B05h
0130_0C05h
Bits
Function
GPPSB PortA
GPPSB PortB
GPPSB PortC
GPPSB PortD
GPPSB PortE
Description
31:24 StrapBifInitialNFts. Read-write; strap. BIOS: 40h. Specifies the number of Fast Training Sets(FTS)
transmitted. FTS are special packets transmitted to exit out of the PCIe L0s sleep state.
D0F0xE4_x0130_8002 IO Link Wrapper Scratch
Cold reset: 0000_0000h.
Bits
Description
31:0 PcieWrapScratch: Scratch. Read-write.
217
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BKDG for AMD Family 16h Models 00h-0Fh Processors
D0F0xE4_x0130_8011 Link Transmit Clock Gating Control
Bits
Description
25
Reserved.
24
TxclkLcntGateEnable. Read-write. Reset: 0. BIOS: 1. 1=Enable clock gating the lane counter.
23
DebugBusClkEnable. Read-write. Reset: 1. BIOS: 0. 1=Enable the debug bus clock.
22:17 TxclkPermGateLatency. Read-write. Reset: 3Fh. Specifies the number of clocks to wait after detecting an entry into L1 before gating off the permanent clock branches.
16
RcvrDetClkEnable. Read-write. Reset: 0. 1=Enable the receiver detect clock.
15:10 TxclkRegsGateLatency. Read-write. Reset: 3Fh. Specifies the number of clocks to wait after idle is
signalled before gating off the register clock branch.
9
TxclkRegsGateEnable. Read-write. Reset: 0. BIOS: 1. 1=Enable clock gating the register clock.
8
TxclkPermStop. Read-write. Reset: 0. 1=All transmitter clocks disabled. This bit should only be set
if all links associated with the PCIe core are unconnected.
7
TxclkDynGateEnable. Read-write. Reset: 0. BIOS: 1. 1=Dynamic clock gating enabled. 0=Dynamic
clock gating disabled.
6
TxclkPermGateEven. Read-write. Reset: 1. 1=Gate the permanent clock branches for an even number of clocks.
5:0
TxclkDynGateLatency. Read-write. Reset: 3Fh. Specifies the number of clocks to wait after idle is
signalled before gating off the dynamic clock branch.
D0F0xE4_x0130_8012 Link Idle-Resume Clock Gating Control
Bits
Description
31:14 Reserved.
13:8 Pif1xIdleResumeLatency. Read-write. Reset: 00_0111b. Specifies the number of clocks to wait after
enabling TXCLK1X_PIF before sending the acknowledge.
7
Pif1xIdleGateEnable. Read-write. Reset: 0. BIOS: 1. 1=Enable idle resume gating of
TXCLK1X_PIF.
6
Reserved.
5:0
Pif1xIdleGateLatency. Read-write. Reset: 0_0001b. Specifies the number of clocks to wait before
turning off TXCLK1X_PIF.
D0F0xE4_x0130_8013 Transmit Clock Pll Control
Reset: 0000_0001h.
Bits
Description
31:15 Reserved.
14:13 PhyRxIsoDis. Read-write. 1=Isolate PHY signals to PIF.
12
Reserved.
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11
Reserved.
10
TxclkSelPifBOverride. Read-write. 1=Override TxclkPifB selection.
9
TxclkSelPifAOverride. Read-write. 1=Override TxclkPifA selection.
8
TxclkSelCoreOverride. Read-write. 1=Override TxclkCore selection.
7
Reserved.
6
Reserved.
5
ClkDividerResetOverrideB. Read-write. 1=Force clock divider B enabled.
4
ClkDividerResetOverrideA. Read-write. 1=Force clock divider A enabled.
3
Reserved.
2
Reserved.
1
MasterPciePllB. Read-write. 1=Pll B is the master source for all PCIe transmitter clock branches.
0
MasterPciePllA. Read-write. 1=Pll A is the master source for all PCIe transmitter clock branches.
D0F0xE4_x0130_8014 Link Transmit Clock Gating Control 2
Reset: 0000_0000h.
Bits
Description
31:28 SpareRegRw. Read-write. Spare register.
27
Reserved.
26
Reserved.
25
Reserved.
24
Reserved.
23:21 Reserved.
20
TxclkPermGateOnlyWhenPllPwrDn. Read-write. BIOS: 1. 1=Gating of the permanent clock
branch only occurs when the PLL is powered down.
19:16 Reserved.
15
Reserved.
14
Reserved.
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13
PcieGatePifB1xEnable. Read-write. BIOS: 1. 1=Enable gating of the PIF B 1x clock branches in
PCIe mode.
12
PcieGatePifA1xEnable. Read-write. BIOS: 1. 1=Enable gating of the PIF A 1x clock branches in
PCIe mode.
11:6 Reserved.
5
Reserved.
4
Reserved.
3
Reserved.
2
Reserved.
1
TxclkPrbsGateEnable. Read-write. BIOS: 1. 1=Enable gating of the PRBS clock branch.
0
TxclkPermGateEnable. Read-write. BIOS: 1. 1=Enable gating of the permanent clock branch.
D0F0xE4_x0130_8015 IO Link IOC Control
Bits
Description
31:24 Reserved.
23
RefclkRegsGateEnable. Read-write. Reset:0. BIOS: 1. 1=Enable gating of REFCLK_REGS.
22
Reserved.
21:16 RefclkRegsGateLatency. Read-write. Reset:3Fh. Specifies the number of clocks to wait before turning of f REFCLK_REGS.
D0F0xE4_x0130_8016 Link Clock Switching Control
Reset: 003F_001Fh.
Bits
Description
31:24 Reserved.
23
LclkDynGateEnable. Read-write. 1=Enable LCLK_DYN clock gating.
22
LclkGateFree. Read-write. IF (REG== D0F0xE4_x013[1:0]_8016) THEN BIOS: 1. ENDIF.
1=LCLK gating is controlled independent of TXCLK gating.
21:16 LclkDynGateLatency. Read-write. Specifies the number of clocks to wait before turning off
LCLK_DYN.
5:0
CalibAckLatency. Read-write.
Specifies the number of clocks after calibration is complete before the acknowledge signal is asserted.
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D0F0xE4_x0130_802[4:1] Transmitter Lane Mux
Table 92: Lane index addresses for D0F0xE4_x0130_802[4:1]
D0F0xE0[31:4]
0130_802h
D0F0xE0[3:0]
4h
3h
Lanes[15:12] Lanes[11:8]
2h
Lanes[7:4]
1h
Lanes[3:0]
Table 93: Reset Mapping for D0F0xE4_x0130_802[4:1]
Register
D0F0xE4_x0130_8024
D0F0xE4_x0130_8023
D0F0xE4_x0130_8022
D0F0xE4_x0130_8021
Reset
0F0E_0D0Ch
0B0A_0908h
0706_0504h
0302_0100h
Table 94: Field mapping for D0F0xE4_x0130_802[4:1]
Register
Bits
Bits
31:24
23:16
15:8
7:0
D0F0xE4_x0130_8024
TXLane15
TXLane14
TXLane13
TXLane12
D0F0xE4_x0130_8023
TXLane11
TXLane10
TXLane9
TXLane8
D0F0xE4_x0130_8022
TXLane7
TXLane6
TXLane5
TXLane4
D0F0xE4_x0130_8021
TXLane3
TXLane2
TXLane1
TXLane0
Description
31:24 TXLane. Read-write. Specifies the controller lanes that are mapped to TX lane n of the PIF. See:
D0F0xE4_x0130_802[4:1][7:0].
23:16 TXLane. Read-write. Specifies the controller lanes that are mapped to TX lane n of the PIF. See:
D0F0xE4_x0130_802[4:1][7:0].
15:8 TXLane. Read-write. Specifies the controller lanes that are mapped to TX lane n of the PIF. See:
D0F0xE4_x0130_802[4:1][7:0].
7:0
TXLane. Read-write. Specifies the controller lanes that are mapped to TX lane n of the PIF.
Bits Definition
Bits Definition
0h
Controller lane 0.
8h
Controller lane 8.
1h
Controller lane 1.
9h
Controller lane 9.
2h
Controller lane 2.
10h Controller lane 10.
3h
Controller lane 3.
11h
Controller lane 11.
4h
Controller lane 4.
12h Controller lane 12.
5h
Controller lane 5.
13h Controller lane 13.
6h
Controller lane 6.
14h Controller lane 14.
7h
Controller lane 7.
15h Controller lane 15.
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D0F0xE4_x0130_802[8:5] Receiver Lane Mux (LM_PCIERXMUX)
Reset: 0302_0100h.
Table 95: Lane index addresses for D0F0xE4_x0130_802[8:5]
D0F0xE0[3:0]
D0F0xE0[31:4]
0130_802h
8h
7h
Lanes[15:12] Lanes[11:8]
6h
5h
Lanes[7:4]
Lanes[3:0]
Table 96: Reset Mapping for D0F0xE4_x0130_802[8:5]
Register
D0F0xE4_x0130_8028
D0F0xE4_x0130_8027
D0F0xE4_x0130_8026
D0F0xE4_x0130_8025
Reset
0F0E_0D0Ch
0B0A_0908h
0706_0504h
0302_0100h
Table 97: Field mapping for D0F0xE4_x0130_802[8:5]
Register
Bits
Bits
31:24
23:16
15:8
7:0
D0F0xE4_x0130_8028
RXLane15
RXLane14
RXLane13 RXLane12
D0F0xE4_x0130_8027
RXLane11
RXLane10
RXLane9
RXLane8
D0F0xE4_x0130_8026
RXLane7
RXLane6
RXLane5
RXLane4
D0F0xE4_x0130_8025
RXLane3
RXLane2
RXLane1
RXLane0
Description
31:24 RXLane. Read-write. Specifies the PIF RX lanes that are mapped to controller lane n. See:
D0F0xE4_x0130_802[8:5][7:0].
23:16 RXLane. Read-write. Specifies the PIF RX lanes that are mapped to controller lane n. See:
D0F0xE4_x0130_802[8:5][7:0].
15:8 RXLane. Read-write. Specifies the PIF RX lanes that are mapped to controller lane n. See:
D0F0xE4_x0130_802[8:5][7:0].
7:0
RXLane. Read-write. Specifies the PIF RX lanes that are mapped to controller lane n.
Bits Definition
Bits Definition
0h
PIF RX lane 0.
8h
PIF RX lane 8.
1h
PIF RX lane 1.
9h
PIF RX lane 9.
2h
PIF RX lane 2.
10h PIF RX lane 10.
3h
PIF RX lane 3.
11h
PIF RX lane 11.
4h
PIF RX lane 4.
12h PIF RX lane 12.
5h
PIF RX lane 5.
13h PIF RX lane 13.
6h
PIF RX lane 6.
14h PIF RX lane 14.
7h
PIF RX lane 7.
15h PIF RX lane 15.
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D0F0xE4_x0130_8029 Lane Enable (LM_LANEENABLE)
Reset: 0000_FFFFh.
Bits
Description
31:16 Reserved.
15:0 LaneEnable. Read-write. 1=Lane enabled for transmit.
Definition
Bit
[15:0]
Lane <BIT> enable
D0F0xE4_x0130_8060 Soft Reset Command 0
Cold reset: 0000_0000h.
Bits
Description
17
Bif0CalibrationReset. Read-write. 1=The BIF 0 calibration block reset is asserted.
16
Bif0GlobalReset. Read-write. 1=The BIF 0 global reset is asserted.
3
WaitState. Read-only. 1=Reset cycle is in the wait state.
2
ResetComplete. Read-only; real-time-update. 1=Reset cycle is complete.
0
Reconfigure. Read-write; Cleared-when-done. 1=Trigger atomic reconfiguration if
D0F0xE4_x0130_8062[ReconfigureEn]=1.
D0F0xE4_x0130_8062 Soft Reset Control 0
Cold reset: 0001_0880h.
Bits
Description
11
ConfigXferMode. Read-write. 1=PCIe core strap settings take effect immediately. 0=PCIe core strap
settings take effect when the PCIe core is reset.
10
BlockOnIdle. Read-write. 1=The PCIe core must be idle before hardware initiates a reconfiguration.
0=The PCIe core does not have to be idle before hardware initiates a reconfiguration.
4:2
ResetPeriod. Read-write. BIOS:2h. Specifies the amount of time that resets are asserted during an
atomic reset or reconfiguration. 5h-7h: Reserved.
0
ReconfigureEn. Read-write. 1=Atomic reconfiguration enabled.
D0F0xE4_x0130_80F0 BIOS Timer
Reset: 0000_0000h.
Bits
Description
31:0 MicroSeconds. Read-write; Updated-by-hardware; real-time-update. This field increments once
every microsecond when the timer is enabled. The counter rolls over and continues counting when it
reaches its FFFF_FFFFh. A write to this register causes the counter to reset and begin counting from
the value written.
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D0F0xE4_x0130_80F1 BIOS Timer Control
Reset: 0000_0064h.
Bits
Description
31:8 Reserved.
7:0
3.3.4
ClockRate. Read-write. Specifies the frequency of the reference clock in 1 MHz increments.
Definition
Bits
00h
Timer disabled
FFh-01h
<ClockRate> MHz
IO Link Registers
D0F0xE4_x0140_0002 IO Link Hardware Debug
Reset: 0000_0000h.
Bits
0
Description
HwDebug[0]: ignore DLLPs in L1. Read-write. BIOS: 1. 1=DLLPs are ignored in L1 so the
TXCLK can be turned off.
D0F0xE4_x0140_0010 IO Link Control 1
Reset: 80E3_110Bh.
Bits
Description
12:10 RxUmiAdjPayloadSize. Read-write. BIOS: 100b. Payload size for the UMI link.
Bits
Definition
Bits
Definition
00xb
Reserved.
100b
64 bytes
010b
16 bytes
101b
Reserved.
011b
32 bytes.
11xb
Reserved.
9
3:1
0
UmiNpMemWrite: memory write mapping enable. Read-write. 1=Internal non-posted memory
writes are transferred to UMI.
LcHotPlugDelSel: enhanced hot plug counter select. Read-write.
Bits
Definition
Bits
Definition
0h
15 ms
4h
150 ms
1h
20 ms
5h
200 ms
2h
50 ms
6h
275 ms
3h
100 ms
7h
335 ms
HwInitWrLock: hardware init write lock. Read-write. 1=Lock HWInit registers. 0=Unlock
HWInit registers.
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D0F0xE4_x0140_0011 IO Link Config Control
Reset: 0000_000Fh.
Bits
Description
3:0
DynClkLatency: dynamic clock latency. Read-write. BIOS: See 2.11.4.3.1 [Link Configuration and
Core Initialization]. Specifies the number of clock cycles after logic goes idle before clocks are gated
off.
D0F0xE4_x0140_001C IO Link Control 2 (PCIE_CNTL2)
Reset: 0E00_0109h.
Bits
Description
10:6 TxArbMstLimit: transmitter arbitration master limit. Read-write. BIOS: 4h. Defines together
with TxArbSlvLimit a round robin arbitration pattern for downstream accesses. TxArbMstLimit
defines the weight for downstream CPU requests and TxArbSlvLimit for the downstream read
responses.
5:1
0
TxArbSlvLimit: transmitter arbitration slave limit. Read-write. BIOS: 4h. See TxArbMstLimit
for details
TxArbRoundRobinEn: transmitter round robin arbitration enabled. Read-write. BIOS: 1.
1=Enable transmitter round robin arbitration. 0=Disable transmitter round robin arbitration.
D0F0xE4_x0140_0020 IO Link Chip Interface Control (PCIE_CI_CNTL)
Reset: 0000_0050h.
Bits
9
Description
CiRcOrderingDis: chip interface RC ordering disable. Read-write.
0=RC ordering logic is enabled. 1=RC ordering logic is disabled.
D0F0xE4_x0140_0040 IO Link Phy Control (PCIE_P_CNTL)
Reset: 0001_0000h.
Bits
Description
15:14 PElecIdleMode: electrical idle mode for physical layer. Read-write. BIOS: 01b. Defines which
electrical idle signal is used, either inferred by link controller of from phy.
Bits
Definition
00b
Gen1 - entry:PHY, exit:PHY; Gen2 - entry:INF, exit:PHY.
01b
Gen1 - entry:INF, exit:PHY; Gen2 - entry:INF, exit:PHY.
10b
Gen1 - entry:PHY, exit:PHY; Gen2 - entry:PHY, exit:PHY.
11b
Gen1 - entry: PHY, exit: PHY; Gen2 - entry: PHY, exit: PHY.
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D0F0xE4_x0140_00B0 IO Link Strap Control (PCIE_STRAP_F0)
Reset: 0000_8001h.
Bits
Description
5
StrapF0AerEn. Read-write. 1=AER support enabled. 0=AER support disabled.
2
StrapF0MsiEn. Read-write. BIOS: 1. Overrides MSI enable.
D0F0xE4_x0140_00C0 IO Link Strap Miscellaneous (PCIE_STRAP_MISC)
Bits
Description
30
StrapFlrEn. Read-write. Reset:0.
29
StrapMstAdr64En. Read-write. Reset: 0.
28
StrapReverseAll. Read-write. Reset: 0.
D0F0xE4_x0140_00C1 IO Link Strap Miscellaneous2 (PCIE_STRAP_MISC2)
Bits
Description
1
StrapGen2Compliance. Read-write. Reset: 0.
0
StrapLinkBwNotificationCapEn. Read-write. Reset: 0.
D0F0xF8 Northbridge IOAPIC Index
Reset: 0000_0000h. The index/data pair registers, D0F0xF8 and D0F0xFC, are used to access the registers at
D0F0xFC_x[FF:00]. To access any of these registers, the address is first written into the index register,
D0F0xF8, and then the data is read from or written to the data register, D0F0xFC.
Bits
Description
31:8 Reserved.
7:0
IOAPICIndAddr: IOAPIC index register address. Read-write.
D0F0xFC Northbridge IOAPIC Data
Reset: 0000_0000h. See D0F0xF8. Address: D0F0xF8[IOAPICIndAddr].
Bits
Description
31:0 IOAPICIndData: IOAPIC index data register. Read-write.
D0F0xFC_x00 IOAPIC Feature Control Register
Reset: 0000_0004h.
Bits
Description
31:5 Reserved.
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4
IoapicSbFeatureEn. Read-write. 1=Enable masked interrupts to be routed back to the FCH
PIC/IOAPIC.
3
Reserved.
2
IoapicIdExtEn. Read-write. Extend the IOAPIC ID from 4-bit to 8-bit. 0=4-bit ID. 1=8-bit ID.
1
Reserved.
0
IoapicEnable. Read-write. 1=Enables the INTGEN block to decode IOAPIC addresses. BIOS: 1.
BIOS should always set this bit after programming the IOAPIC BAR in the init sequence.
D0F0xFC_x01 IOAPIC Base Address Lower
Reset: FEC0_0000h. See 3.16 [Northbridge IOAPIC Registers].
Bits
Description
31:8 IoapicAddr. Read-write. IOAPIC Base Address bits [31:8].
7:0
Reserved.
D0F0xFC_x02 IOAPIC Base Address Upper
Reset: 0000_0000h. See 3.16 [Northbridge IOAPIC Registers].
Bits
Description
31:0 IoapicAddrUpper. Read-write. IOAPIC Base Address bits [63:32].
D0F0xFC_x0F IOAPIC GBIF Interrupt Routing Register
Reset: 0000_0000h.
Bits
Description
31:6 Reserved.
5:4
3
2:0
GBIFExtIntrSwz. Read-write. Swizzle GBIF INTA/B/C/D based on the value in this field before
mapping them onto the IOAPIC pins.
Bits
Interrupt Swizzling
00b
ABCD
01b
BCDA
10b
CDAB
11b
DABC
Reserved.
GBIFExtIntrGrp. Read-write. Map GBIF INTA/B/C/D to IOAPIC pins [((grp+1)*4)-1:(grp*4)].
For GBIF, only INTA/B are used. INTC/D should be tied off.
D0F0xFC_x1[4:0] IOAPIC BR Interrupt Routing Register
Reset: 0000_0000h.
Bits
Description
31:21 Reserved.
20:16 BrIntIntrMap. Read-write. Map bridge n interrupts to IOAPIC redirection table entry.
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15:6 Reserved.
5:4
3
2:0
BrExtIntrSwz. Read-write. Swizzle bridge n external INTA/B/C/D based on the value in this field
before mapping them onto the IOAPIC pins.
Bits
Interrupt Swizzling
00b
ABCD
01b
BCDA
10b
CDAB
11b
DABC
Reserved.
BrExtIntrGrp. Read-write. Map bridge n external INTA/B/C/D to IOAPIC pins [((grp+1)*4)1:(grp*4)].
D0F0xFC_x30 IOAPIC Serial IRQ Status
Reset: 0000_0000h.
Bits
Description
31:0 InternalIrqSts. Read-only. Shows the status of the 32 IOAPIC interrupt pins.
D0F0xFC_x3[F:E] IOAPIC Scratch [1:0] Register
Reset: 0000_0000h.
Bits
Description
31:0 Scratch. Read-write.
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Device 0 Function 2 Configuration Registers
See 3.1 [Register Descriptions and Mnemonics]. See 2.7 [Configuration Space]. See 2.11.6 [PCIe Client Interface Control].
D0F2xF8 PCIe Client Interface Index
The index/data pair registers, D0F2xF8 and D0F2xFC are used to access the registers at
D0F2xFC_x[FFFF:0000]_L1i[3:0]. To access any of these registers, the address is first written into the index
register, D0F2xF8, and then the data is read from or written to the data register, D0F2xFC.
Registers in the L1 indexed space have one instance per L1 denoted by _L1i[x] where x=D0F2xF8[L1cfgSel].
The syntax for this register type is described by example as follows:
• D0F2xFC_x32 refers to all instances of the D0F2xFC_x32_L1i registers.
• D0F2xFC_x32_L1i_L1i[1] refers to the D0F2xFC_x32 register instance for the BIF L1.
Bits
31
Description
L1cfgEn. Read-write. Reset: 0. 1=Enable writes to D0F2xFC.
30:20 Reserved.
19:16 L1cfgSel. Read-write. Reset: 0. This field selects one of the four L1s to access.
Description
Bits
0h
PPD L1
1h
BIF L1
2h
INTGEN L1
Fh-3h
Reserved
15:0
L1cfgIndex. Read-write. Reset: 0.
D0F2xFC PCIe Client Interface Data
IF (D0F2xF8[L1cfgEn]) THEN Read-write. ELSE Read-only. ENDIF. Reset: 0000_0000h. See D0F2xF8.
Address: D0F2xF8[L1cfgIndex].
Bits
Description
31:0
L1cfgData.
D0F2xFC_x32_L1i L1_CNTRL_4
Bits
Description
31:20 Reserved.
19:17 Reserved.
16
DmaNpHaltDis. Read-write. Reset: 0.
15:10 DmaBufMaxNpCred. Read-write. Reset: Fh.
9:4
3
DmaBufCredits. Read-write. Reset: 10h.
Reserved.
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2
Reserved.
1
Reserved.
0
Reserved.
BKDG for AMD Family 16h Models 00h-0Fh Processors
D0F2xFC_x33_L1i L1_CLKCNTRL_0
Bits
31
Description
L1L2ClkgateEn. Read-write. Reset: 0. BIOS: 1.
30:12 Reserved.
11
L1HostreqClkgateEn. Read-write. Reset: 0. BIOS: 1.
10
L1RegClkgateEn. Read-write. Reset: 0. BIOS: 1.
9
L1MemoryClkgateEn. Read-write. Reset: 0. BIOS: 1.
8
L1PerfClkgateEn. Read-write. Reset: 0. BIOS: 1.
7
L1DmaInputClkgateEn. Read-write. Reset: 0. BIOS: 1.
6
L1CpslvClkgateEn. Read-write. Reset: 0. BIOS: 1.
5
L1CacheClkgateEn. Read-write. Reset: 0. BIOS: 1.
4
L1DmaClkgateEn. Read-write. Reset: 0. BIOS: 1.
3:2
Reserved.
1:0
L1ClkgateLen. Read-write. Reset: 0.
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Device 1 Function 0 (Internal Graphics) Configuration Registers
See 3.1 [Register Descriptions and Mnemonics]. See 2.7 [Configuration Space].
D1F0x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID.
Read-only. Value: Fuse[DEVICE_ID]. See: D0F0xD4_x0130_14AA[StrapBifF0DeviceId].
15:0 VendorID: vendor ID. Read-only. Value: IF (Fuse[StrapBifVendorId] == 0) THEN 1002h ELSE
1022h ENDIF.
D1F0x04 Status/Command Register
Reset: 0010_0000h.
Bits
Description
31
ParityErrorDetected: detected parity error. Read; Write-1-to-clear. 1=Poisoned TLP received.
30
SignaledSystemError: signaled system error. Read; Write-1-to-clear. 1=A non-fatal or fatal error
message was sent and SerrEn=1.
29
ReceivedMasterAbort: received master abort. Read; Write-1-to-clear. 1=A completion with an
unsupported request completion status was received.
28
ReceivedTargetAbort: received target abort. Read; Write-1-to-clear. 1=A completion with completer abort completion status was received.
27
SignalTargetAbort: Signaled target abort. Read-only.
26:25 DevselTiming: DEVSEL# Timing. Read-only.
24
MasterDataPerr: master data parity error. Read; Write-1-to-clear. 1=ParityErrorEn=1 and either a
poisoned completion was received or the device poisoned a write request.
23
FastBackCapable: fast back-to-back capable. Read-only.
22
UDFEn: UDF enable. Read-only.
21
PCI66En: 66 MHz capable. Read-only.
20
CapList: capability list. Read-only. 1=Capability list supported.
19
IntStatus: interrupt status. Read-only. 1=INTx interrupt message pending.
18:11 Reserved.
10
IntDis: interrupt disable. Read-write. 1=INTx interrupt messages generation disabled.
9
FastB2BEn: fast back-to-back enable. Read-only.
8
SerrEn: System error enable. Read-write. 1=Enables reporting of non-fatal and fatal errors
detected.
7
Stepping: Stepping control. Read-only.
6
ParityErrorEn: parity error response enable. Read-write.
5
PalSnoopEn: VGA palette snoop enable. Read-only.
4
MemWriteInvalidateEn: memory write and invalidate enable. Read-only.
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3
SpecialCycleEn: special cycle enable. Read-only.
2
BusMasterEn: bus master enable. Read-write. 1=Memory and IO read and write request generation
enabled.
1
MemAccessEn: IO access enable. Read-write. This bit controls if memory accesses targeting this
device are accepted. 1=Enabled. 0=Disabled.
0
IoAccessEn: IO access enable. Read-write. This bit controls if IO accesses targeting this device are
accepted. 1=Enabled. 0=Disabled.
D1F0x08 Class Code/Revision ID Register
Bits
Description
31:8 ClassCode. Value: IF (D0F0xD4_x0130_14B6[StrapBifVgaDis]==0) THEN 03_0000h. ELSE
03_8000h. ENDIF.
7:0
RevID: revision ID. Value: {Fuse[MajorRevId], Fuse[MinorRevId]}.
D1F0x0C Header Type Register
Reset: 0080_0000h.
Bits
Description
31:24 BIST. Read-only.
23:16 HeaderTypeReg. Read-only. The header type field indicates a header type 0 and that this is a multifunction device.
15:8 LatencyTimer. Read-only. These bits are fixed at their default value.
7:0
CacheLineSize. Read-write. This field specifies the system cache line size in units of double words.
D1F0x10 Graphic Memory Base Address
IF (D0F0xD4_x0109_14E2[StrapBifF064BarDisA]==1) THEN Reset: 0000_0008h. ELSE Reset:
0000_000Ch. ENDIF.
Bits
Description
31:26 BaseAddr[31:26]: base address. Read-write. The amount of memory requested by the graphics
memory BAR is controlled by D0F0xD4_x0109_1507[StrapBifMemApSizePin] and
D0F0xD4_x0109_14E1[StrapBifMemApSize].
25:4 BaseAddr[25:4]: base address. Read-only.
3
2:1
0
Pref: prefetchable. Read-only. 1=Prefetchable memory region.
Type: base address register type. Read-only.
Bits
Description
00b
32-bit BAR
01b
Reserved
10b
64-bit BAR
11b
Reserved
MemSpace: memory space type. Read-only. 0=Memory mapped base address.
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D1F0x14 Graphics Memory Base Address 64
Reset: 0000_0000h.
Bits
Description
31:0 BaseAddr[63:32]: base address. Read-write. This field is reseved if
(D0F0xD4_x0109_14E2[StrapBifF064BarDisA]==1).
D1F0x18 Graphics Doorbell Base Address
IF (D0F0xD4_x0109_14E2[StrapBifF064BarDisA]==1) THEN Reset: 0000_0008h. ELSE Reset:
0000_000Ch. ENDIF. This register is reserved and reset is 0000_0000h if (D0F0xD4_x0109_14E1[StrapBifDoorbellBarDis]==1).
Bits
Description
31:23 BaseAddr[31:23]: base address. Read-write.
22:4 BaseAddr[22:4]: base address. Read-only.
3
2:1
0
Pref: prefetchable. Read-only. 1=Prefetchable memory region.
Type: base address register type. Read-only.
Bits
Description
00b
32-bit BAR
01b
Reserved
10b
64-bit BAR
11b
Reserved
MemSpace: memory space type. Read-only. 0=Memory mapped base address.
D1F0x1C Graphics Doorbell Base Address 64
Reset: 0000_0000h.
Bits
Description
31:0 BaseAddr[63:32]: base address. Read-write. This field is reserved if
(D0F0xD4_x0109_14E1[StrapBifDoorbellBarDis]==1 ||
D0F0xD4_x0109_14E2[StrapBifF064BarDisA]==1).
D1F0x20 Graphics IO Base Address
Reset: 0000_0000h. This register is called Base Address 4 if
(D0F0xD4_x0109_14E2[StrapBifF064BarDisA]==1).
Bits
Description
31:0 Reserved.
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D1F0x24 Graphics Memory Mapped Registers Base Address
Reset: 0000_0000h.
Bits
Description
31:16 BaseAddr[31:16]: base address. Read-write. The amount of memory requested by the graphics
memory mapped registers BAR is controlled by D0F0xD4_x0109_14E1[StrapBifRegApSize].
15:4 BaseAddr[15:4]: base address. Read-only.
3
2:1
0
Pref: prefetchable. Read-only. 0=Non-prefetchable memory region.
Type: base address register type. Read-only. 00b=32-bit BAR.
MemSpace: memory space type. Read-only. 0=Memory mapped base address.
D1F0x2C Subsystem and Subvendor ID Register
Reset: 0000_0000h. This register can be modified through D1F0x4C.
Bits
Description
31:16 SubsystemID. Read-only.
15:0 SubsystemVendorID. Read-only.
D1F0x30 Expansion ROM Base Address
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
D1F0x34 Capabilities Pointer
Reset: 0000_0050h.
Bits
Description
31:8 Reserved.
7:0
CapPtr: capabilities pointer. Read-only. Pointer to PM capability.
D1F0x3C Interrupt Line
Reset: 0000_01FFh.
Bits
Description
31:16 Reserved.
15:8 InterruptPin: interrupt pin. Read-only. This field identifies the legacy interrupt message the function uses.
7:0
InterruptLine: interrupt line. Read-write. This field contains the interrupt line routing information.
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D1F0x4C Subsystem and Subvendor ID Mirror
Reset: 0000_0000h.
Bits
Description
31:16 SubsystemID. Read-write. This field sets the value in the corresponding field in D1F0x2C.
15:0 SubsystemVendorID. Read-write. This field sets the value in the corresponding field in D1F0x2C.
D1F0x50 Power Management Capability
Bits
Description
31:27 PmeSupport. Value: 0_0000b. Indicates that there is no PME support.
26
D2Support: D2 support. Value: 1. D2 is supported
25
D1Support: D1 support. Value: 1. D1 is supported
24:22 AuxCurrent: auxiliary current. Value: 0.
21
DevSpecificInit: device specific initialization. Value: 0. Indicates that there is no device specific initialization necessary.
20
Reserved.
19
PmeClock. Value: 0.
18:16 Version: version. Value: 011b.
15:8 NextPtr: next pointer. Value: 58h
7:0
CapID: capability ID.Value: 01h. Indicates that the capability structure is a PCI power management
data structure.
D1F0x54 Power Management Control and Status
Reset: 0000_0000h.
Bits
Description
31:24 PmeData. Read-only.
23
BusPwrEn. Read-only.
22
B2B3Support. Read-only. B states are not supported.
21:16 Reserved.
15
PmeStatus: PME status. Read-only.
14:13 DataScale: data scale. Read-only.
12:9 DataSelect: data select. Read-only.
8
7:4
3
PmeEn: PME# enable. Read-only.
Reserved.
NoSoftReset: no soft reset. Read-only. Software is required to re-initialize the function when returning from D3hot.
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Reserved.
PowerState: power state. Read-write. This 2-bit field is used both to determine the current power
state of the root port and to set the root port into a new power state.
Bits
Definition
00b
D0
11b
D3hot
D1F0x58 PCI Express Capability
Bits
Description
31:30 Reserved.
29:25 IntMessageNum: interrupt message number. Value: 0. This field indicates which MSI vector is
used for the interrupt message.
24
SlotImplemented: Slot implemented. Value: 0.
23:20 DeviceType: device type. Value: 9h.
19:16 Version. Value: 2h.
15:8 NextPtr: next pointer. Value: IF (D0F0xD4_x0130_14BE[StrapBifMsiDis]==0) THEN A0h. ELSE
00h. ENDIF.
7:0
CapID: capability ID. Value: 10h.
D1F0x5C Device Capability
Bits
Description
31:29 Reserved.
28
FlrCapable: function level reset capability. Value: 0.
27:26 CapturedSlotPowerScale: captured slot power limit scale. Value: 0.
25:18 CapturedSlotPowerLimit: captured slot power limit value. Value: 0.
17:16 Reserved.
15
RoleBasedErrReporting: role-based error reporting. Value: 1.
14:12 Reserved.
11:9 L1AcceptableLatency: endpoint L1 Acceptable Latency. Value: 111b.
8:6
5
L0SAcceptableLatency: endpoint L0s Acceptable Latency. Value: 110b.
ExtendedTag: extended tag support. Value: 1. 8 bit tag support.
4:3
PhantomFunc: phantom function support. Value: 0. No phantom functions supported.
2:0
MaxPayloadSupport: maximum supported payload size. Value: 000b. 128 bytes max payload
size.
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D1F0x60 Device Control and Status
Reset: 0000_0810h.
Bits
Description
31:22 Reserved.
21
TransactionsPending: transactions pending. Read-only.
20
AuxPwr: auxiliary power. Read-only.
19
UsrDetected: unsupported request detected. Read; Write-1-to-clear. 1=Unsupported request
received.
18
FatalErr: fatal error detected. Read; Write-1-to-clear. 1=Fatal error detected.
17
NonFatalErr: non-fatal error detected. Read; Write-1-to-clear. 1=Non-fatal error detected.
16
CorrErr: correctable error detected. Read; Write-1-to-clear. 1=Correctable error detected.
15
BridgeCfgRetryEn: bridge configuration retry enable. Read-only.
14:12 MaxRequestSize: maximum request size. Read-only.
11
NoSnoopEnable: enable no snoop. Read-write. 1=The device is permitted to set the No Snoop bit in
requests.
10
AuxPowerPmEn: auxiliary power PM enable. Read-only. This capability is not implemented.
9
PhantomFuncEn: phantom functions enable. Read-only. Phantom functions are not supported.
8
ExtendedTagEn: extended tag enable. Read-write. 1=8-bit tag request tags. 0=5-bit request tag.
7:5
MaxPayloadSize: maximum supported payload size. Read-only. 000b=Indicates a 128 byte maximum payload size.
4
RelaxedOrdEn: relaxed ordering enable. Read-write. 1=The device is permitted to set the Relaxed
Ordering bit.
3
UsrReportEn: unsupported request reporting enable. Read-write. 1=Enables signaling unsupported requests by sending error messages.
2
FatalErrEn: fatal error reporting enable. Read-write. 1=Enables sending ERR_FATAL message
when a fatal error is detected.
1
NonFatalErrEn: non-fatal error reporting enable. Read-write. 1=Enables sending
ERR_NONFATAL message when a non-fatal error is detected.
0
CorrErrEn: correctable error reporting enable. Read-write. 1=Enables sending ERR_CORR message when a correctable error is detected.
D1F0x64 Link Capability
Bits
Description
31:24 PortNumber: port number. Read-only. Value: 0.This field indicates the PCI Express port number
for the given PCI Express link.
23
Reserved.
22
AspmOptionalityCompliance: ASP Optionality ECN capability. Read-only. Value: 0b.
21
LinkBWNotificationCap: link bandwidth notification capability. Read-only. Value: 0b.
20
DlActiveReportingCapable: data link layer active reporting capability. Read-only. Value: 0b.
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19
SurpriseDownErrReporting: surprise down error reporting capability. Read-only. Value: 0b.
18
ClockPowerManagement: clock power management. Read-only. Value: 0b.
17:15 L1ExitLatency: L1 exit latency. Read-only. Value: 0b.
14:12 L0sExitLatency: L0s exit latency. Read-only. Value: 0b.
11:10 PMSupport: active state power management support. Read-only. Value: 0b.
9:4
LinkWidth: maximum link width. Read-only. Value: 0.
3:0
LinkSpeed: link speed. Read-only. Value: 0b.
D1F0x68 Link Control and Status
Reset: 0000_0000h.
Bits
Description
31
LinkAutonomousBWStatus: link autonomous bandwidth status. Read-only.
30
LinkBWManagementStatus: link bandwidth management status. Read-only.
29
DlActive: data link layer link active. Read-only. This bit indicates the status of the data link control
and management state machine. Reads return a 1 to indicate the DL_Active state, otherwise 0 is
returned.
28
SlotClockCfg: slot clock configuration. Read-only. 1=the root port uses the same clock that the platform provides.
27
LinkTraining: link training. Read-only. 1=Indicates that the physical layer link training state
machine is in the configuration or recovery state, or that 1b was written to the RetrainLink bit but link
training has not yet begun. Hardware clears this bit when the link training state machine exits the configuration/recovery state.
26
Reserved.
25:20 NegotiatedLinkWidth: negotiated link width. Read-only. This field indicates the negotiated width
of the given PCI Express link.
19:16 LinkSpeed: link speed. Read-only.
15:12 Reserved.
11
LinkAutonomousBWIntEn: link autonomous bandwidth interrupt enable. Read-only.
10
LinkBWManagementEn: link bandwidth management interrupt enable. Read-only.
9
HWAutonomousWidthDisable: hardware autonomous width disable. Read-only. 1=Hardware not
allowed to change the link width except to correct unreliable link operation by reducing link width.
8
ClockPowerManagementEn: clock power management enable. Read-only.
7
ExtendedSync: extended sync. Read-only. 1=Forces the transmission of additional ordered sets
when exiting the L0s state and when in the recovery state.
6
CommonClockCfg: common clock configuration. Read-only. 1=Indicates that the root port and the
component at the opposite end of this Link are operating with a distributed common reference clock.
0=Indicates that the upstream port and the component at the opposite end of this Link are operating
with asynchronous reference clock.
5
RetrainLink: retrain link. Read-only. This bit does not apply to endpoints.
4
LinkDis: link disable. Read-only. This bit does not apply to endpoints.
3
ReadCplBoundary: read completion boundary. Read-only. 0=64 byte read completion boundary.
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Reserved.
PmControl: active state power management enable. Read-only. This field controls the level of
ASPM supported on the given PCI Express link.
Bits
Definition
Bits
Definition
00b
Disabled.
10b
L1 Entry Enabled.
01b
L0s Entry Enabled.
11b
L0s and L1 Entry Enabled.
D1F0x7C Device Capability 2
Reset: 0000_0000h.
Bits
Description
31:24 Reserved.
23:22 MaxEndEndTlpPrefixes: Max number of End-End TLP prefixes supported. Read-only. IF
(D1F0x7C[EndEndTlpPrefixSupported]==0) THEN Reserved. ENDIF.
Bits
Definition
Bits
Definition
00b
4 End-End TLP Prefixes.
10b
2 End-End TLP Prefixes.
01b
1 End-End TLP Prefix.
11b
3 End-End TLP Prefixes.
21
EndEndTlpPrefixSupported: End-End TLP Prefix supported. Read-only.
20
ExtendedFmtFieldSupported. Read-only. 1=Function supports 3-bit definition of Fmt field.
0=Function supports 2-bit definition of Fmt field.
19:18 ObffSupported: Optimized buffer flush/fill supported. Read-only.
17:14 Reserved.
13:12 TphCplrSupported. Read-only.
11
LtrSupported: Latency Tolerance Reporting supported. Read-only.
10
NoRoEnabledP2pPassing. Read-only.
9:6
Reserved.
5
AriForwardingSupported: ARI forwarding supported. Read-only.
4
CplTimeoutDisSupported: completion timeout disable supported. Read-only.
3:0
CplTimeoutRangeSupported: completion timeout range supported. Read-only.
D1F0x80 Device Control and Status 2
Reset: 0000_0000h.
Bits
Description
31:16 Reserved.
15
EndEndTlpPrefixBlocking. Read-only.
14:13 ObffEn. Read-only.
12:11 Reserved.
10
LtrEn. Read-only.
9
IdoCompletionEn. Read-only.
8
IdoRequestEn. Read-only.
7:6
Reserved.
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5
AriForwardingEn. Read-only.
4
CplTimeoutDis: completion timeout disable. Read-only.
3:0
CplTimeoutValue: completion timeout range supported. Read-only.
D1F0x84 Link Capability 2
Bits
Description
31:9 Reserved.
8
7:1
0
CrosslinkSupported: Crosslink Spported. Read-only. Reset: 0. 1=Crosslink supported.
SupportedLinkSpeed: Supported Link Speed. Read-only. Reset: 07h. Specifies what link speeds
are supported. Bit 1 = 2.5 GT/s, Bit2 = 5.0 Gt/s, Bit 3 = 8.0 GT/s.
Reserved.
D1F0x88 Link Control and Status 2
Reset: 0000_0000h.
Bits
Description
31:22 Reserved.
21
LinkEqualizationRequest. Read-only. Set when hardware requests link equalization to be performed.
20
EqualizationPhase3Success: Phase3 of Tx equalization procedure completed. Read-only.
19
EqualizationPhase2Success: Phase2 of Tx equalization procedure completed. Read-only.
18
EqualizationPhase1Success: Phase1 of Tx equalization procedure completed. Read-only.
17
EqualizationComplete: Tx equalization procedure completed. Read-only.
16
CurDeemphasisLevel: current deemphasis level. Read-only. 1=-3.5 dB. 0=-6 dB.
15:13 Reserved.
12
ComplianceDeemphasis: compliance deemphasis. Read-only. This bit defines the deemphasis level
used in compliance mode. 1=-3.5 dB. 0=-6 dB.
11
ComplianceSOS: compliance SOS. Read-only. 1=The device transmits skip ordered sets in between
the modified compliance pattern.
10
EnterModCompliance: enter modified compliance. Read-only. 1=The device transmits modified
compliance pattern.
9:7
XmitMargin: transmit margin. Read-only. This field controls the non-deemphasized voltage level
at the transmitter pins.
6
SelectableDeemphasis: selectable deemphasis. Read-only.
5
HwAutonomousSpeedDisable: hardware autonomous speed disable. Read-only. 1=Disables hardware generated link speed changes.
4
EnterCompliance: enter compliance. Read-only. 1=Force link to enter compliance mode.
3:0
TargetLinkSpeed: target link speed. Read-only. This field defines the upper limit of the link operational speed.
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D1F0xA0 MSI Capability
Bits
Description
31:24 Reserved.
23
Msi64bit: MSI 64 bit capability. Read-only. Reset: 1. 1=The device is capable of sending 64-bit
MSI messages. 0=The device is not capable of sending a 64-bit message address.
22:20 MsiMultiEn: MSI multiple message enable. Read-write. Reset: 000b. Software writes to this field
to indicate the number of allocated vectors (equal to or less than the number of requested vectors).
When MSI is enabled, a function is allocated at least 1 vector.
19:17 MsiMultiCap: MSI multiple message capability. Read-only. Reset: 000b. 000b=The device is
requesting one vector.
16
MsiEn: MSI enable. Read-write. Reset: 0. 1=MSI generation is enabled and INTx generation is disabled. 0=MSI generation disabled and INTx generation is enabled.
15:8 NextPtr: next pointer. Read-only. Reset:00h
7:0
CapID: capability ID. Read-only. Reset: 05h. 05h=MSI capability structure.
D1F0xA4 MSI Message Address Low
Reset: 0000_0000h.
Bits
Description
31:2 MsiMsgAddrLo: MSI message address. Read-write. This register specifies the dword aligned
address for the MSI memory write transaction.
1:0
Reserved.
D1F0xA8 MSI Message Address High
Reset: 0000_0000h.
Bits
Description
31:8 Reserved.
7:0
MsiMsgAddrHi: MSI message address. Read-write. This register specifies the upper 8-bits of the
MSI address in 64 bit MSI mode.
D1F0xAC MSI Message Data
Reset: 0000_0000h.
Bits
Description
31:16 Reserved.
15:0 MsiData: MSI message data. Read-write. This register specifies lower 16 bits of data for the MSI
memory write transaction. The upper 16 bits are always 0.
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D1F0x100 Vendor Specific Enhanced Capability
Reset: 0061_000Bh.
Bits
Description
31:20 NextPtr: next pointer. Read-only.
19:16 CapVer: capability version. Read-only.
15:0 CapID: capability ID. Read-only.
D1F0x104 Vendor Specific Header
Reset: 0101_0001h.
Bits
Description
31:20 VsecLen: vendor specific enhanced next pointer. Read-only.
19:16 VsecRev: vendor specific enhanced capability version. Read-only.
15:0 VsecID: vendor specific enhanced capability ID. Read-only.
D1F0x108 Vendor Specific 1
Reset: 0000_0000h.
Bits
Description
31:0 Scratch: scratch. Read-write.
D1F0x10C Vendor Specific 2
Reset: 0000_0000h.
Bits
Description
31:0 Scratch: scratch. Read-write.
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Device 1 Function 1 (Audio Controller) Configuration Registers
See 3.1 [Register Descriptions and Mnemonics] for a description of the register naming convention. See 2.7
[Configuration Space] for details about how to access this space.
D1F1x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID. Read-only.
Value: Fuse[STRAP_AZALIA_DID].
15:0 VendorID: vendor ID. Read-only. Value: IF (Fuse[StrapBifVendorId] == 0) THEN 1002h ELSE
1022h ENDIF.
D1F1x04 Status/Command
Reset: 0010_0000h.
Bits
Description
31
ParityErrorDetected: detected parity error. Read; Write-1-to-clear. 1=Poisoned TLP received.
30
SignaledSystemError: signaled system error. Read; Write-1-to-clear. 1=A non-fatal or fatal error
message was sent and SerrEn=1.
29
ReceivedMasterAbort: received master abort. Read; Write-1-to-clear. 1=A completion with an
unsupported request completion status was received.
28
ReceivedTargetAbort: received target abort. Read; Write-1-to-clear. 1=A completion with completer abort completion status was received.
27
SignalTargetAbort: Signaled target abort. Read-only.
26:25 DevselTiming: DEVSEL# Timing. Read-only.
24
MasterDataPerr: master data parity error. Read; Write-1-to-clear. 1=ParityErrorEn=1 and either a
poisoned completion was received or the device poisoned a write request.
23
FastBackCapable: fast back-to-back capable. Read-only.
22
UDFEn: UDF enable. Read-only.
21
PCI66En: 66 MHz capable. Read-only.
20
CapList: capability list. Read-only. 1=capability list supported.
19
IntStatus: interrupt status. Read-only. 1=INTx interrupt message pending.
18:11 Reserved.
10
IntDis: interrupt disable. Read-write. 1=INTx interrupt messages generation disabled.
9
FastB2BEn: fast back-to-back enable. Read-only.
8
SerrEn: System error enable. Read-write. 1=Enables reporting of non-fatal and fatal errors
detected.
7
Stepping: Stepping control. Read-only.
6
ParityErrorEn: parity error response enable. Read-write.
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5
PalSnoopEn: VGA palette snoop enable. Read-only.
4
MemWriteInvalidateEn: memory write and invalidate enable. Read-only.
3
SpecialCycleEn: special cycle enable. Read-only.
2
BusMasterEn: bus master enable. Read-write. 1=Memory and IO read and write request generation
enabled.
1
MemAccessEn: IO access enable. Read-write. This bit controls if memory accesses targeting this
device are accepted. 1=Enabled. 0=Disabled.
0
IoAccessEn: IO access enable. Read-write. This bit controls if IO accesses targeting this device are
accepted. 1=Enabled. 0=Disabled.
D1F1x08 Class Code/Revision ID
Reset: 0403_0000h.
Bits
Description
31:8 ClassCode. Read-only.
7:0
RevID: revision ID. Read-only.
D1F1x0C Header Type
Reset: 0080_0000h.
Bits
Description
31:24 BIST. Read-only. These bits are fixed at their default values.
23:16 HeaderTypeReg. Read-only. 80h=Type 0 multi-function device.
15:8 LatencyTimer. Read-only. These bits are fixed at their default value.
7:0
CacheLineSize. Read-write.This field specifies the system cache line size in units of double words.
D1F1x10 Audio Registers Base Address
Reset: 0000_0000h.
Bits
Description
31:14 BaseAddr: base address. Read-write.
13:4 Reserved.
3
Pref: prefetchable. Read-only. 0=Non-prefetchable memory region.
2:1
Type: base address register type. Read-only. 00b=32-bit base address register.
0
MemSpace: memory space type. Read-only. 0=Memory mapped base address.
D1F1x14 Base Address 1
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
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D1F1x18 Base Address 2
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
D1F1x1C Base Address 3
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
D1F1x20 Base Address 4
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
D1F1x24 Base Address 5
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
D1F1x2C Subsystem and Subvendor ID
Reset: 0000_0000h. This register can be modified through D1F1x4C.
Bits
Description
31:16 SubsystemID. Read-only.
15:0 SubsystemVendorID. Read-only.
D1F1x30 Expansion ROM Base Address
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
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D1F1x34 Capabilities Pointer
Reset: 0000_0050h.
Bits
Description
31:8 Reserved.
7:0
CapPtr: capabilities pointer. Read-only. Pointer to PM capability.
D1F1x3C Interrupt Line
Reset: 0000_02FFh.
Bits
Description
31:16 Reserved.
15:8 InterruptPin: interrupt pin. Read-only. This field identifies the legacy interrupt message the function uses.
7:0
InterruptLine: interrupt line. Read-write. This field contains the interrupt line routing information.
D1F1x4C Subsystem and Subvendor ID Mirror
Reset: 0000_0000h.
Bits
Description
31:16 SubsystemID. Read-write. This field sets the value in the corresponding field in D1F1x2C.
15:0 SubsystemVendorID. Read-write. This field sets the value in the corresponding field in D1F1x2C.
D1F1x50 Power Management Capability
Bits
Description
31:27 PmeSupport. Value: 0_0000b. Indicates that there is no PME support.
26
D2Support: D2 support. Value: 1. D2 is supported
25
D1Support: D1 support. Value: 1. D1 is supported
24:22 AuxCurrent: auxiliary current. Value: 0.
21
DevSpecificInit: device specific initialization. Value: 0. Indicates that there is no device specific initialization necessary.
20
Reserved.
19
PmeClock. Value: 0.
18:16 Version: version. Value: 011b.
15:8 NextPtr: next pointer. Value: IF (D0F0xD4_x0130_14BE[StrapBifMsiDis]==0) THEN A0h. ELSE
00h. ENDIF.
7:0
CapID: capability ID.Value: 01h. Indicates that the capability structure is a PCI power management
data structure.
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D1F1x54 Power Management Control and Status
Reset: 0000_0000h.
Bits
Description
31:24 PmeData. Read-only.
23
BusPwrEn. Read-only.
22
B2B3Support. Read-only. B states are not supported.
21:16 Reserved.
15
PmeStatus: PME status. Read-only.
14:13 DataScale: data scale. Read-only.
12:9 DataSelect: data select. Read-only.
8
7:4
PmeEn: PME# enable. Read-only.
Reserved.
3
NoSoftReset: no soft reset. Read-only. Software is required to re-initialize the function when returning from D3hot.
2
Reserved.
1:0
PowerState: power state. Read-write. This 2-bit field is used both to determine the current power
state of the root port and to set the root port into a new power state.
Bits
Definition
00b
D0
01b, 10b
Reserved
11b
D3hot
D1F1x58 PCI Express Capability
Bits
Description
31:30 Reserved.
29:25 IntMessageNum: interrupt message number. Value: 0. This field indicates which MSI vector is
used for the interrupt message.
24
SlotImplemented: Slot implemented. Value: 0.
23:20 DeviceType: device type. Value: 9h.
19:16 Version. Value: 2h.
15:8 NextPtr: next pointer. Value: IF (D0F0xD4_x0130_14BE[StrapBifMsiDis]==0) THEN A0h. ELSE
00h. ENDIF.
7:0
CapID: capability ID. Value: 10h.
D1F1x5C Device Capability
Bits
Description
31:29 Reserved.
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FlrCapable: function level reset capability. Value: IF (D0F0xD4_x0130_14BC[StrapBifFlrEn]==1) THEN 1h. ELSE 0h. ENDIF.
27:26 CapturedSlotPowerScale: captured slot power limit scale. Value: 0.
25:18 CapturedSlotPowerLimit: captured slot power limit value. Value: 0.
17:16 Reserved.
15
RoleBasedErrReporting: role-based error reporting. Value: 1.
14:12 Reserved.
11:9 L1AcceptableLatency: endpoint L1 Acceptable Latency. Value: 111b.
8:6
5
L0SAcceptableLatency: endpoint L0s Acceptable Latency. Value: 110b.
ExtendedTag: extended tag support. Value: 1. 8 bit tag support.
4:3
PhantomFunc: phantom function support. Value: 0. No phantom functions supported.
2:0
MaxPayloadSupport: maximum supported payload size. Value: 000b. 128 bytes max payload
size.
D1F1x60 Device Control and Status
Reset: 0000_0810h.
Bits
Description
31:22 Reserved.
21
TransactionsPending: transactions pending. Read-only.
20
AuxPwr: auxiliary power. Read-only.
19
UsrDetected: unsupported request detected. Read; Write-1-to-clear. 1=Unsupported request
received.
18
FatalErr: fatal error detected. Read; Write-1-to-clear. 1=Fatal error detected.
17
NonFatalErr: non-fatal error detected. Read; Write-1-to-clear. 1=Non-fatal error detected.
16
CorrErr: correctable error detected. Read; Write-1-to-clear. 1=Correctable error detected.
15
BridgeCfgRetryEn: bridge configuration retry enable. Read-only.
14:12 MaxRequestSize: maximum request size. Read-only. 0=The root port never generates read requests
with size exceeding 128 bytes.
11
NoSnoopEnable: enable no snoop. Read-write. 1=The device is permitted to set the No Snoop bit in
requests.
10
AuxPowerPmEn: auxiliary power PM enable. Read-only. This capability is not implemented.
9
PhantomFuncEn: phantom functions enable. Read-only. Phantom functions are not supported.
8
ExtendedTagEn: extended tag enable. Read-write. 1=8-bit tag request tags. 0=5-bit request tag.
7:5
MaxPayloadSize: maximum supported payload size. Read-only. 000b=Indicates a 128 byte maximum payload size.
4
RelaxedOrdEn: relaxed ordering enable. Read-write. 1=The device is permitted to set the Relaxed
Ordering bit.
3
UsrReportEn: unsupported request reporting enable. Read-write. 1=Enables signaling unsupported requests by sending error messages.
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2
FatalErrEn: fatal error reporting enable. Read-write. 1=Enables sending ERR_FATAL message
when a fatal error is detected.
1
NonFatalErrEn: non-fatal error reporting enable. Read-write. 1=Enables sending
ERR_NONFATAL message when a non-fatal error is detected.
0
CorrErrEn: correctable error reporting enable. Read-write. 1=Enables sending ERR_CORR message when a correctable error is detected.
D1F1x64 Link Capability
Bits
Description
31:24 PortNumber: port number. Value: 0.This field indicates the PCI Express port number for the given
PCI Express link.
23:22 Reserved.
21
LinkBWNotificationCap: link bandwidth notification capability. Read-only. Value: 0b.
20
DlActiveReportingCapable: data link layer active reporting capability. Read-only. Value: 0b.
19
SurpriseDownErrReporting: surprise down error reporting capability. Read-only. Value: 0b.
18
ClockPowerManagement: clock power management. Read-only. Value: 0b.
17:15 L1ExitLatency: L1 exit latency. Read-only. Value: 0b.
14:12 L0sExitLatency: L0s exit latency. Read-only. Value: 0b.
11:10 PMSupport: active state power management support. Read-only. Value: 0b.
9:4
LinkWidth: maximum link width. Read-only. Value: 0.
3:0
LinkSpeed: link speed. Read-only. Value: 0b.
D1F1x68 Link Control and Status
Reset: 0000_0000h.
Bits
Description
31
LinkAutonomousBWStatus: link autonomous bandwidth status. Read-only.
30
LinkBWManagementStatus: link bandwidth management status. Read-only.
29
DlActive: data link layer link active. Read-only. This bit indicates the status of the data link control
and management state machine. Reads return a 1 to indicate the DL_Active state, otherwise 0 is
returned.
28
SlotClockCfg: slot clock configuration. Read-only. 1=The root port uses the same clock that the
platform provides.
27
LinkTraining: link training. Read-only. 1=Indicates that the physical layer link training state
machine is in the configuration or recovery state, or that 1b was written to the RetrainLink bit but link
training has not yet begun. Hardware clears this bit when the link training state machine exits the configuration/recovery state.
26
Reserved.
25:20 NegotiatedLinkWidth: negotiated link width. Read-only. This field indicates the negotiated width
of the given PCI Express link.
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19:16 LinkSpeed: link speed. Read-only.
Description
Bits
0h
Reserved
1h
2.5 Gb/s.
2h
5 Gb/s.
Fh-3h
Reserved
15:12 Reserved.
11
LinkAutonomousBWIntEn: link autonomous bandwidth interrupt enable. Read-only.
10
LinkBWManagementEn: link bandwidth management interrupt enable. Read-only.
9
HWAutonomousWidthDisable: hardware autonomous width disable. Read-only. 1=Hardware not
allowed to change the link width except to correct unreliable link operation by reducing link width.
8
ClockPowerManagementEn: clock power management enable. Read-only.
7
ExtendedSync: extended sync. Read-only. 1=Forces the transmission of additional ordered sets
when exiting the L0s state and when in the recovery state.
6
CommonClockCfg: common clock configuration. Read-only. 1=Indicates that the root port and the
component at the opposite end of this Link are operating with a distributed common reference clock.
0=Indicates that the upstream port and the component at the opposite end of this Link are operating
with asynchronous reference clock.
5
RetrainLink: retrain link. Read-only. This bit does not apply to endpoints.
4
LinkDis: link disable. Read-only. This bit does not apply to endpoints.
3
ReadCplBoundary: read completion boundary. Read-only. 0=64 byte read completion boundary.
2
Reserved.
1:0
PmControl: active state power management enable. Read-only. This field controls the level of
ASPM supported on the given PCI Express link.
Bits
Definition
Bits
Definition
00b
Disabled.
10b
L1 Entry Enabled.
01b
L0s Entry Enabled.
11b
L0s and L1 Entry Enabled.
D1F1x7C Device Capability 2
Reset: 0000_0000h.
Bits
Description
31:5 Reserved.
4
3:0
CplTimeoutDisSup: completion timeout disable supported. Read-only.
CplTimeoutRangeSup: completion timeout range supported. Read-only.
D1F1x80 Device Control and Status 2
Reset: 0000_0000h.
Bits
Description
31:5 Reserved.
4
3:0
CplTimeoutDis: completion timeout disable. Read-only.
CplTimeoutValue: completion timeout range supported. Read-only.
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D1F1x84 Link Capability 2
Bits
Description
31:0 Reserved.
D1F1x88 Link Control and Status 2
Reset: 0000_0000h.
Bits
Description
31:17 Reserved.
16
CurDeemphasisLevel: current deemphasis level. Read-only. 1=-3.5 dB. 0=-6 dB.
15:13 Reserved.
12
ComplianceDeemphasis: compliance deemphasis. Read-only. This bit defines the deemphasis level
used in compliance mode. 1=-3.5 dB. 0=-6 dB.
11
ComplianceSOS: compliance SOS. Read-only. 1=The device transmits skip ordered sets in between
the modified compliance pattern.
10
EnterModCompliance: enter modified compliance. Read-only. 1=The device transmits modified
compliance pattern.
9:7
XmitMargin: transmit margin. Read-only. This field controls the non-deemphasized voltage level
at the transmitter pins.
6
SelectableDeemphasis: selectable deemphasis. Read-only.
5
HwAutonomousSpeedDisable: hardware autonomous speed disable. Read-only. 1=Disables hardware generated link speed changes.
4
EnterCompliance: enter compliance. Read-only. 1=Force link to enter compliance mode.
3:0
TargetLinkSpeed: target link speed. Read-only. This fields defines the upper limit of the link operational speed.
D1F1xA0 MSI Capability
Bits
Description
31:24 Reserved.
23
Msi64bit: MSI 64 bit capability. Read-only. Reset: 1. 1=The device is capable of sending 64-bit
MSI messages. 0=The device is not capable of sending a 64-bit message address.
22:20 MsiMultiEn: MSI multiple message enable. Read-write. Reset: 000b. Software writes to this field
to indicate the number of allocated vectors (equal to or less than the number of requested vectors).
When MSI is enabled, a function is allocated at least 1 vector.
19:17 MsiMultiCap: MSI multiple message capability. Read-only. Reset:000b. 000b=The device is
requesting one vector.
16
MsiEn: MSI enable. Read-write. Reset: 0. 1=MSI generation is enabled and INTx generation is disabled. 0=MSI generation disabled and INTx generation is enabled.
15:8 NextPtr: next pointer. Read-only. Reset: 00h.
7:0
CapID: capability ID. Read-only. Reset: 05h. 05h=MSI capability structure.
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D1F1xA4 MSI Message Address Low
Reset: 0000_0000h.
Bits
Description
31:2 MsiMsgAddrLo: MSI message address. Read-write. This register specifies the dword aligned
address for the MSI memory write transaction.
1:0
Reserved.
D1F1xA8 MSI Message Address High
Reset: 0000_0000h.
Bits
Description
31:8 Reserved.
7:0
MsiMsgAddrHi: MSI message address. Read-write. This register specifies the upper 8-bits of the
MSI address in 64 bit MSI mode.
D1F1xAC MSI Message Data
Reset: 0000_0000h.
Bits
Description
31:16 Reserved.
15:0 MsiData: MSI message data. Read-write. This register specifies lower 16 bits of data for the MSI
memory write transaction. The upper 16 bits are always 0.
D1F1x100 Vendor Specific Enhanced Capability
Reset: 0111_000Bh.
Bits
Description
31:20 NextPtr: next pointer. Read-only.
19:16 CapVer: capability version. Read-only.
15:0 CapID: capability ID. Read-only.
D1F1x104 Vendor Specific Header
Reset: 0101_0001h.
Bits
Description
31:20 VsecLen: vendor specific enhanced next pointer. Read-only.
19:16 VsecRev: vendor specific enhanced capability version. Read-only.
15:0 VsecID: vendor specific enhanced capability ID. Read-only.
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D1F1x108 Vendor Specific 1
Reset: 0000_0000h.
Bits
Description
31:0 Scratch: scratch. Read-write.
D1F1x10C Vendor Specific 2
Reset: 0000_0000h.
Bits
Description
31:0 Scratch: scratch. Read-write.
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Device 2 Function 0 (Host Bridge) Configuration Registers
See 3.1 [Register Descriptions and Mnemonics] for a description of the register naming convention. See 2.7
[Configuration Space] for details about how to access this space. D2F0 registers do not control any hardware.
They ensure that software can configure functions 1 through 4.
D2F0x00 Device/Vendor ID (Host Bridge)
Bits
Description
31:16 DeviceID: device ID. Read-only.
Value: 1538h.
15:0 VendorID: vendor ID. Read-only. Value: 1022h.
D2F0x04 Status/Command
Reset: 0000_0000h.
Bits
Description
31:16 Status. Read-only. Tied to 0x0h.
15:0 Command. Read-only. Tied to 0x0h.
D2F0x08 Class Code/Revision ID
Reset: 0600_0000h.
Bits
Description
31:8 ClassCode: class code. Read-only. Tied to 0x06_0000h.
7:0
RevId: revision identifier. Read-only. Tied to 0x0h.
D2F0x0C Header Type
Reset: 0080_0000h.
Bits
Description
31:24 Reserved.
23
DeviceType. Read-only. 1=Indicates that the northbridge block is a multi-function device. 0=Indicates that the northbridge block is a single function device.
22:16 HeaderType. Read-only. Indicates multiple functions present in this device.
15:0 Reserved.
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D2F0x40 Header Type Write
Reset: 0000_0080h.
Bits
Description
31:8 Reserved.
7
6:0
3.8
DeviceType. Read-write. This field sets the value in D2F0x0C[DeviceType]. 0=Single function
device. 1=Multi-function device.
Reserved.
Device 2 Function [5:1] (Root Port) Configuration Registers
See 3.1 [Register Descriptions and Mnemonics] for a description of the register naming convention. See 2.7
[Configuration Space] for details about how to access this space. See 2.11.1 [Overview].
D2F[5:1]x00 Device/Vendor ID
Table 98: Register Mapping for D2F[5:1]x00
D2F[5:1]x00
D2F1x00
D2F2x00
D2F3x00
D2F4x00
D2F5x00
Bits
Function
GPP Bridge 0
GPP Bridge 1
GPP Bridge 2
GPP Bridge 3
GPP Bridge 4
Description
31:16 DeviceID: device ID. Read-only.
Value: 1439h.
15:0 VendorID: vendor ID. Read-only.
Value: 1022h.
D2F[5:1]x04 Status/Command Register
Reset: 0010_0000h.
Bits
Description
31
ParityErrorDetected: detected parity error. Read; Write-1-to-clear.
30
SignaledSystemError: signaled system error. Read; Write-1-to-clear. 1=System error signalled.
29
ReceivedMasterAbort: received master abort. Read; Write-1-to-clear.
28
ReceivedTargetAbort: received target abort. Read; Write-1-to-clear.
27
SignalTargetAbort: signaled target abort. Read; Write-1-to-clear.
26:25 DevselTiming: DEVSEL# Timing. Read-only.
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24
DataPerr: data parity error. Read; Write-1-to-clear.
23
FastBackCapable: fast back-to-back capable. Read-only.
22
Reserved.
21
PCI66En: 66 MHz capable. Read-only.
20
CapList: capability list. Read-only. 1= Capability list present.
19
IntStatus: interrupt status. Read-only. 1=An INTx interrupt Message is pending in the device.
18:11 Reserved.
10
IntDis: interrupt disable. Read-write.
9
FastB2BEn: fast back-to-back enable. Read-only.
8
SerrEn: system error enable. Read-write. 1=System error reporting enabled.
7
Stepping: Stepping control. Read-only.
6
ParityErrorEn: parity error response enable. Read-write.
5
PalSnoopEn: VGA palette snoop enable. Read-only.
4
MemWriteInvalidateEn: memory write and invalidate enable. Read-only.
3
SpecialCycleEn: special cycle enable. Read-only.
2
BusMasterEn: bus master enable. Read-write.
1
MemAccessEn: IO access enable. Read-write. This bit controls if memory accesses targeting this
device are accepted or not. 1=Enabled. 0=Disabled.
0
IoAccessEn: IO access enable. Read-write. This bit controls if IO accesses targeting this device are
accepted or not. 1=Enabled. 0=Disabled.
D2F[5:1]x08 Class Code/Revision ID Register
Reset: 0604_00xxh.
Bits
Description
31:8 ClassCode. Read-only. Provides the host bridge class code as defined in the PCI specification.
7:0
RevID: revision ID. Read-only.
D2F[5:1]x0C Header Type Register
Reset: 0001_0000h.
Bits
Description
31:24 BIST. Read-only. These bits are fixed at their default values.
23
DeviceType. Read-only. 0=Single function device. 1=Multi-function device.
22:16 HeaderType. Read-only. These bits are fixed at their default values. Indicates a Type 0 or Type 1 configuration space.
15:8 LatencyTimer. Read-only. This field does not control any hardware.
7:0
CacheLineSize. Read-write.
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D2F[5:1]x18 Bus Number and Secondary Latency Register
Reset: 0000_0000h.
Bits
Description
31:24 SecondaryLatencyTimer: secondary latency timer. Read-only. This field is always 0.
23:16 SubBusNumber: subordinate number. Read-write. This field contains the highest-numbered bus
that exists on the secondary side of the bridge.
15:8 SecondaryBus: secondary bus number. Read-write. This field defines the bus number of the secondary bus interface.
7:0
PrimaryBus: primary bus number. Read-write. This field defines the bus number of the primary
bus interface.
D2F[5:1]x1C IO Base and Secondary Status Register
Reset: 0000_0101h.
Bits
Description
31
ParityErrorDetected: detected parity error. Read; Write-1-to-clear. A Poisoned TLP was received
regardless of the state of the D2F[5:1]x04[ParityErrorEn].
30
ReceivedSystemError: signaled system error. Read; Write-1-to-clear. 1=A System Error was
detected.
29
ReceivedMasterAbort: received master abort. Read; Write-1-to-clear. 1=A CPU transaction is terminated due to a master-abort.
28
ReceivedTargetAbort: received target abort. Read; Write-1-to-clear. 1=A CPU transaction (except
for a special cycle) is terminated due to a target-abort.
27
SignalTargetAbort: signaled target abort. Read; Write-1-to-clear.
26:25 DevselTiming: DEVSEL# Timing. Read-only.
24
MasterDataPerr: master data parity error. Read; Write-1-to-clear. 1=The link received a poisoned
or poisoned a downstream write and D2F[5:1]x3C[ParityResponseEn]=1.
23
FastBackCapable: fast back-to-back capable. Read-only.
22
Reserved.
21
PCI66En: 66 MHz capable. Read-only.
20
CapList: capability list. Read-only.
19:16 Reserved.
15:12 IOLimit[15:12]. Read-write. Lower part of the limit address. Upper part is defined in D2F[5:1]x30.
11:8 IOLimitType. Read-only. 0=16-bit. 1=32-bit.
7:4
IOBase[15:12]. Read-write. Lower part of the base address. Upper part is defined in D2F[5:1]x30.
3:0
IOBaseType. Read-only. 0=16-bit. 1=32-bit.
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D2F[5:1]x20 Memory Limit and Base Register
Reset: 0000_0000h.
Bits
Description
31:20 MemLimit[31:20]. Read-write.
19:16 MemLimitType. Read-only. 0=32-bit. 1=64-bit.
15:4 MemBase[31:20]. Read-write.
3:0
MemBaseType. Read-only. 0=32-bit. 1=64-bit.
D2F[5:1]x24 Prefetchable Memory Limit and Base Register
Reset: 0001_0001h.
Bits
Description
31:20 PrefMemLimit. Read-write. Lower part of the limit address. Upper part is defined in D2F[5:1]x2C.
19:16 PrefMemLimitType. Read-only. 0=32-bit. 1=64-bit.
15:4 PrefMemBase[31:20]. Read-write. Lower part of the base address. Upper part is defined in
D2F[5:1]x28.
3:0
PrefMemBaseType. Read-only. 0=32-bit. 1=64-bit.
D2F[5:1]x28 Prefetchable Memory Base High Register
Reset: 0000_0000h.
Bits
Description
31:0 PrefMemBase[63:32]. Read-write. Upper part of the base address. Lower part is defined in
D2F[5:1]x24.
D2F[5:1]x2C Prefetchable Memory Limit High Register
Reset: 0000_0000h.
Bits
Description
31:0 PrefMemLimit[63:32]. Read-write. Upper part of the limit address. Lower part is defined in
D2F[5:1]x24.
D2F[5:1]x30 IO Base and Limit High Register
Reset: 0000_0000h.
Bits
Description
31:16 IOLimit[31:16]. Read-write. Upper part of the limit address. Lower part is defined in D2F[5:1]x1C.
15:0 IOBase[31:16]. Read-write. Upper part of the base address. Lower part is defined in D2F[5:1]x1C.
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D2F[5:1]x34 Capabilities Pointer Register
Reset: 0000_0050h.
Bits
Description
31:8 Reserved.
7:0
CapPtr: capabilities pointer. Read-only. Pointer to PM capability.
D2F[5:1]x3C Bridge Control Register
Reset: 0000_00FFh.
Bits
Description
31:24 Reserved.
23
FastB2BCap: Fast back-to-back capability. Read-only.
22
SecondaryBusReset: Secondary bus reset. Read-write. Setting this bit triggers a hot reset on the
corresponding PCI Express Port.
21
MasterAbortMode: Master abort mode. Read-only.
20
Vga16En: VGA IO 16 bit decoding enable. Read-write. 1= Address bits 15:10 for VGA IO cycles
are decoded. 0=Address bits 15:10 for VGA IO cycles are ignored.
19
VgaEn: VGA enable. Read-write. Affects the response by the bridge to compatible VGA addresses.
When it is set, the bridge decodes and forwards the following accesses on the primary interface to the
secondary interface:
Memory accesses in the range of A_0000h to B_FFFFh and
IO address where address bits 9:0 are in the ranges of 3B0h to 3BBh or 3C0h to 3DFh. For IO cycles
the decoding of address bits 15:10 depends on Vga16En.
18
IsaEn: ISA enable. Read-write.
17
SerrEn: SERR enable. Read-write.
16
ParityResponseEn: Parity response enable. Read-write. Controls the bridge's response to poisoned
TLPs on its secondary interface. 1=The bridge takes its normal action when a poisoned TLP is
received. 0=The bridge ignores any poisoned TLPs that it receives and continues normal operation.
15:11 IntPinR: interrupt pin. Read-only.
10:8 IntPin: interrupt pin. IF (D0F0xE4_x0140_0010[HwInitWrLock]==1) THEN Read-only. ELSE
Read-write. ENDIF.
7:0
IntLine: Interrupt line. Read-write.
D2F[5:1]x50 Power Management Capability Register
Reset: 0003_5801h.
Bits
Description
31:27 PmeSupport. Read-only.
26
D2Support: D2 support. Read-only. D2 is not supported
25
D1Support: D1 support. Read-only. D1 is not supported
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24:22 AuxCurrent: auxiliary current. IF (D0F0xE4_x0140_0010[HwInitWrLock]==1) THEN Readonly. ELSE Read-write. ENDIF. Auxiliary current is not supported.
21
DevSpecificInit: device specific initialization. Read-only. This field is hardwired to 0 to indicate
that there is no device specific initialization necessary.
20
Reserved.
19
PmeClock. Read-only. 0=Indicate that PCI clock is not needed to generate PME messages.
18:16 Version: version. Read-only. 3=PMI Spec 1.2
15:8 NextPtr: next pointer. Read-only. 58h=Address of the next capability structure.
7:0
CapID: capability ID. Read-only. 01h=PCI power management data structure.
D2F[5:1]x54 Power Management Control and Status Register
Bits
Description
31:24 PmiData. Read-only. Reset: 0.
23
BusPwrEn. Read-only. Reset: 0.
22
B2B3Support. Read-only. Reset: 0. B states are not supported.
21:16 Reserved.
15
PmeStatus: PME status. Read; Write-1-to-clear. Reset: 0. This bit is set when the root port would
issue a PME message (independent of the state of the PmeEn bit). Once set, this bit remains set until it
is reset by writing a 1 to this bit location. Writing a 0 has no effect.
14:13 DataScale: data scale. Read-only. Reset: 0.
12:9 DataSelect: data select. Read-only. Reset: 0.
8
7:4
PmeEn: PME# enable. Read-write. Reset: 0.
Reserved.
3
NoSoftReset: no soft reset. Read-only. Reset: 0. Software is required to re-initialize the function
when returning from D3hot.
2
Reserved.
1:0
PowerState: power state. Read-write. Reset: 0. This 2-bit field is used both to determine the current
power state of the root port and to set the root port into a new power state.
Bits
Definition
Bits
Definition
00b
D0
10b
Reserved
01b
Reserved
11b
D3
D2F[5:1]x58 PCI Express Capability Register
Reset: 0042_A010h.
Bits
Description
31:30 Reserved.
29:25 IntMessageNum: interrupt message number. Read-only. This register indicates which MSI vector
is used for the interrupt message.
24
SlotImplemented: Slot implemented. IF (D0F0xE4_x0140_0010[HwInitWrLock]==1) THEN
Read-only. ELSE Read-write. ENDIF. 1=The IO Link associated with this port is connected to a slot.
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23:20 DeviceType: device type. Read-only. 4h=Root complex.
19:16 Version. Read-only. 2h=GEN 2 compliant.
15:8 NextPtr: next pointer. Read-only. A0h=Pointer to the next capability structure.
7:0
CapID: capability ID. Read-only. 10h=PCIe® Capability structure.
D2F[5:1]x5C Device Capability Register
Reset: 0000_0020h.
Bits
Description
31:29 Reserved.
28
FlrCapable: function level reset capability. Read-only.
27:26 CapturedSlotPowerScale: captured slot power limit scale. Read-only.
25:18 CapturedSlotPowerLimit: captured slot power limit value. Read-only.
17:16 Reserved.
15
RoleBasedErrReporting: role-based error reporting. Read-only.
14:12 Reserved.
11:9 L1AcceptableLatency: endpoint L1 Acceptable Latency. Read-only.
8:6
5
L0SAcceptableLatency: endpoint L0s Acceptable Latency. Read-only.
ExtendedTag: extended tag support. Read-only.
1: 8 bit tag supported
0: 5 bit tag supported.
4:3
PhantomFunc: phantom function support. Read-only. 0=No phantom functions supported.
2:0
MaxPayloadSupport: maximum supported payload size. Read-only. 000b=128 bytes max payload
size.
D2F[5:1]x60 Device Control and Status Register
Reset: 0000_2810h.
Bits
Description
31:22 Reserved.
21
TransactionsPending: transactions pending. Read-only. 0=No internally generated non-posted
transactions pending.
20
AuxPwr: auxiliary power. IF (D0F0xE4_x0140_0010[HwInitWrLock]==1) THEN Read-only.
ELSE Read-write. ENDIF.
19
UsrDetected: unsupported request detected. Read; Write-1-to-clear. 1=The port received an unsupported request. Errors are logged in this register even if error reporting is disabled.
18
FatalErr: fatal error detected. Read; Write-1-to-clear. 1=The port detected a fatal error. Errors are
logged in this register even if error reporting is disabled.
17
NonFatalErr: non-fatal error detected. Read; Write-1-to-clear. T1=The port detected a non-fatal
error. Errors are logged in this register even if error reporting is disabled.
16
CorrErr: correctable error detected. Read; Write-1-to-clear. 1=The port detected a correctable
error. Errors are logged in this register even if error reporting is disabled.
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BridgeCfgRetryEn: bridge configuration retry enable. Read-only.
14:12 MaxRequestSize: maximum request size. Read-write.
11
NoSnoopEnable: enable no snoop. Read-write. 1=The port is permitted to set the No Snoop bit in
the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency.
10
AuxPowerPmEn: auxiliary power PM enable. Read-only.
9
PhantomFuncEn: phantom functions enable. Read-only.
8
ExtendedTagEn: extended tag enable. Read-write. 1=8-bit tags generation enabled. 0=5-bit tags are
used.
7:5
MaxPayloadSize: maximum supported payload size. Read-write.
Bits
Definition
Bits
Definition
0h
128B
3h
1024B
1h
256B
4h
2048B
2h
512B
5h
4096B
4
RelaxedOrdEn: relaxed ordering enable. Read-write. 1=The root port is permitted to set the
relaxed ordering bit in the attributes field of transactions it initiates that do not require strong write
ordering.
3
UsrReportEn: unsupported request reporting enable. Read-write. 1=Reporting of unsupported
requests enabled.
2
FatalErrEn: fatal error reporting enable. Read-write. 1=Enable sending ERR_FATAL messages.
1
NonFatalErrEn: non-fatal error reporting enable. Read-write. 1=Enable sending
ERR_NONFATAL messages.
0
CorrErrEn: correctable error reporting enable. Read-write. 1=Enable sending ERR_CORR messages.
D2F[5:1]x64 IO Link Capability Register
Read-only.
Bits
Description
31:24 PortNumber: port number. Reset: 0. This field indicates the port number for the given IO link.
23
Reserved.
22
AspmOptionalityCompliance. Reset: 1. This field indicates if the compenent supports the ASPM
Optionality ECN.
21
LinkBWNotificationCap: link bandwidth notification capability. Reset: 0. This bit is controlled
by ~D2F[5:1]xE4_xB1[LcLinkBwNotificationDis].
20
DlActiveReportingCapable: data link layer active reporting capability. Reset: 0.
19
SurpriseDownErrReporting. Reset: 0. 1=This field indicates if the component supports the detecting and reporting of a Surprise Down error condition.
18
ClockPowerManagement: clock power management. Reset: 0. 0=Indicates that the reference clock
must not be removed while in L1 or L2/L3 ready link states.
17:15 L1ExitLatency: L1 exit latency. Reset: 010b. 010b=Indicate an exit latency between 2 us and 4 us.
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14:12 L0sExitLatency: L0s exit latency. Reset: 001b. 001b=Indicates an exit latency between 64 ns and
128 ns.
11:10 PMSupport: active state power management support. Reset: 11b. 11b=Indicates support of L0s
and L1.
9:4
LinkWidth: maximum link width. Value: 10h.
Bits
Definition
00h
Reserved.
01h
1 lanes
02h
2 lanes
03h
Reserved.
04h
4 lanes
07h-05h
Reserved.
08h
8 lanes
0Bh-09h
Reserved.
0Ch
12 lanes
0Fh-0Dh
Reserved.
10h
16 lanes
1Fh-11h
Reserved.
20h
32 lanes
3Fh-21h
Reserved.
3:0
LinkSpeed: link speed. Value:
IF (D2F[5:1]xE4_xA4[LcGen2EnStrap]==0 THEN 1h
ELSEIF (D2F[5:1]xE4_xA4[LcGen2EnStrap]==1 THEN 2h
ENDIF.
Definition
Bits
0h
Reserved.
1h
2.5 Gb/s
2h
5.0 Gb/s
Fh-3h
Reserved.
D2F[5:1]x68 IO Link Control and Status Register
Reset: 1001_0000h.
Bits
Description
31
LinkAutonomousBWStatus: link autonomous bandwidth status. IF (D2F[5:1]x64[LinkBWNotificationCap]==0) THEN Read-only. ELSE Read-write; updated-by-hardware. ENDIF.
30
LinkBWManagementStatus: link bandwidth management status. IF (D2F[5:1]x64[LinkBWNotificationCap]==0) THEN Read-only. ELSE Read-write; updated-by-hardware. ENDIF.
29
DlActive: data link layer link active. Read-only; updated-by-hardware. This bit indicates the status
of the data link control and management state machine. 1=DL_Active state. 0=All other states.
28
SlotClockCfg: slot clock configuration. Read-only; updated-by-hardware. 1=The root port uses the
same clock that the platform provides.
27
LinkTraining: link training. Read-only; updated-by-hardware. This read-only bit indicates that the
physical layer link training state machine is in the configuration or recovery state, or that 1b was written to the RetrainLink bit but link training has not yet begun. Hardware clears this bit when the link
training state machine exits the configuration/recovery state.
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Reserved.
25:20 NegotiatedLinkWidth: negotiated link width. Read-only; updated-by-hardware. This field indicates the negotiated width of the given PCI Express link.
Bits
Definition
00h
Reserved.
01h
1 lanes
02h
2 lanes
03h
Reserved.
04h
4 lanes
07h-05h
Reserved.
08h
8 lanes
0Bh-09h
Reserved.
0Ch
12 lanes
0Fh-0Dh
Reserved.
10h
16 lanes
1Fh-11h
Reserved.
20h
32 lanes
3Fh-21h
Reserved.
19:16 LinkSpeed: link speed. Read-only; updated-by-hardware.
Definition
Bits
00h
Reserved.
01h
2.5 Gb/s
02h
5.0 Gb/s
Fh-3h
Reserved.
15:12 Reserved.
11
LinkAutonomousBWIntEn: link autonomous bandwidth interrupt enable. Read-write.
1=Enables the generation of an interrupt to indicate that the Link AutonomousBWStatus bit has been
set.
10
LinkBWManagementIntEn: link bandwidth management interrupt enable. Read-write.
1=Enables the generation of an interrupt to indicate that the LinkBWManagementStatus has been set.
9
HWAutonomousWidthDisable: hardware autonomous width disable. Read-write. 1=Disables
hardware from changing the link width for reasons other than attempting to correct unreliable link
operation by reducing link width.
8
ClockPowerManagementEn: clock power management enable. Read-write.
7
ExtendedSync: extended sync. Read-write. 1=Forces the transmission of additional ordered sets
when exiting the L0s state and when in the recovery state.
6
CommonClockCfg: common clock configuration. Read-write. 1=Indicates that the root port and
the component at the opposite end of this IO link are operating with a distributed common reference
clock. 0=Indicates that the root port and the component at the opposite end of this IO Link are operating with asynchronous reference clock.
5
RetrainLink: retrain link. Read-write; cleared-when-done. 1=Initiate link retraining.
4
LinkDis: link disable. Read-write. 1=Disable link. Writes to this bit are immediately reflected in the
value read from the bit, regardless of actual link state.
3
ReadCplBoundary: read completion boundary. Read-only. 0=64 byte read completion boundary.
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Reserved.
PmControl: active state power management enable. Read-write. This field controls the level of
ASPM supported on the given IO link.
Bits
Definition
Bits
Definition
00b
Disabled.
10b
L1 Entry Enabled.
01b
L0s Entry Enabled.
11b
L0s and L1 Entry Enabled.
D2F[5:1]x6C Slot Capability Register
Reset: 0004_0000h.
Bits
Description
31:19 PhysicalSlotNumber: physical slot number. IF (D0F0xE4_x0140_0010[HwInitWrLock]==0)
THEN Read-write. ELSE Read-only. ENDIF.
This field indicates the physical slot number attached to this port. This field is set to a value that
assigns a slot number that is unique within the chassis, regardless of the form factor associated with
the slot. This field must be initialized to 0 for ports connected to devices that are on the system board.
18
NoCmdCplSupport: no command completed support. Read-write. 1 =Indicates that this slot does
not generate software notification when an issued command is completed by the hot-plug controller.
17
ElecMechIlPresent: electromechanical interlock present. Read-write. 0=Indicates that a electromechanical interlock is not implemented for this slot.
16:15 SlotPwrLimitScale: slot power limit scale. IF (D0F0xE4_x0140_0010[HwInitWrLock]==0) THEN
Read-write. ELSE Read-only. ENDIF. Specifies the scale used for the SlotPwrLimitValue. Range of
Values:
Bits
Definition
Bits
Definition
00b
1.0
10b
0.01
01b
0.1
11b
0.001
14:7 SlotPwrLimitValue: slot power limit value. IF (D0F0xE4_x0140_0010[HwInitWrLock]==0)
THEN Read-write. ELSE Read-only. ENDIF. In combination with the SlotPwrLimitScale value,
specifies the upper limit on power supplied by slot. Power limit (in Watts) calculated by multiplying
the value in this field by the value in the SlotPwrLimitScale field.
6
HotplugCapable: hot-plug capability. IF (D0F0xE4_x0140_0010[HwInitWrLock]==0) THEN
Read-write. ELSE Read-only. ENDIF. 1=Indicates that this slot is capable of supporting hot-plug
operations.
5
HotplugSurprise: hot-plug surprise. IF (D0F0xE4_x0140_0010[HwInitWrLock]==0) THEN
Read-write. ELSE Read-only. ENDIF. 1=Indicates that an adapter present in this slot might be
removed from the system without any prior notification.
4
PwrIndicatorPresent: power indicator present. Read-write. 0=Indicates that a power indicator is
not implemented for this slot.
3
AttnIndicatorPresent: attention indicator present. Read-write. 0=Indicates that a attention indicator is not implemented for this slot.
2
MrlSensorPresent: manual retention latch sensor present. Read-write. 0=Indicates that a manual
retention latch sensor is not implemented for this slot.
1
PwrControllerPresent: power controller present. Read-write. 0=A power controller is not implemented for this slot.
0
AttnButtonPresent: attention button present. Read-write. 0=An attention button is not implemented for this slot.
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D2F[5:1]x70 Slot Control and Status Register
IF (D2F[5:1]x58[SlotImplemented]==0) THEN Reset: 0040_0000h. ELSE Reset: 0000_0000h. ENDIF.
Bits
Description
31:25 Reserved.
24
DlStateChanged: data link layer state change. Read; Write-1-to-clear. This bit is set when the value
reported in the D2F[5:1]x68[DlActive] is changed. In response to a data link layer state changed
event, software must read D2F[5:1]x68[DlActive] to determine if the link is active before initiating
configuration cycles to the hot plugged device.
23
ElecMechIlSts: electromechanical interlock status. Read-only.
22
PresenceDetectState: presence detect state. Read-only. This bit indicates the presence of an adapter
in the slot based on the physical layer in-band presence detect mechanism. The in-band presence
detect mechanism requires that power be applied to an adapter for its presence to be detected.
0=Slot empty.
1=Card present in slot.
For root ports not connected to slots (D2F[5:1]x58[SlotImplemented]=0b), this bit returns always 1.
21
MrlSensorState. Read-only.
20
CmdCpl: command completed. Read-only.
19
PresenceDetectChanged: presence detect changes. Read; Write-1-to-clear. This bit is set when the
value reported in PresenceDetectState is changed.
18
MrlSensorChanged. Read; Write-1-to-clear.
17
PwrFaultDetected. Read; Write-1-to-clear.
16
AttnButtonPressed: attention button pressed. Read-only.
15:13 Reserved.
12
DlStateChangedEn: data link layer state changed enable. Read-write. 1=Enables software notification when D2F[5:1]x68[DlActive] is changed.
11
ElecMechIlCntl: electromechanical interlock control. Read-only.
10
PwrControllerCntl: power controller control. Read-only.
9:8
PwrIndicatorCntl: power indicator control. Read-only.
7:6
AttnIndicatorControl: attention indicator control. Read-only.
5
HotplugIntrEn: hot-plug interrupt enable. Read-only.
4
CmdCplIntrEn: command complete interrupt enable. Read-only.
3
PresenceDetectChangedEn: presence detect changed enable. Read-only.
2
MrlSensorChangedEn: manual retention latch sensor changed enable. Read-only.
1
PwrFaultDetectedEn: power fault detected enable. Read-only.
0
AttnButtonPressedEn: attention button pressed enable. Read-only.
D2F[5:1]x74 Root Complex Capability and Control Register
Reset: 0001_0000h.
Bits
Description
31:17 Reserved.
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CrsSoftVisibility: CRS software visibility. Read-only. 1=Indicates that the root port supports returning configuration request retry status (CRS) completion status to software.
15:5 Reserved.
4
CrsSoftVisibilityEn: CRS software visibility enable. Read-write. 1=Enables the root port returning
configuration request retry status (CRS) completion status to software.
3
PmIntEn: PME interrupt enable. Read-write. 1=Enables interrupt generation upon receipt of a
PME message as reflected D2F[5:1]x78[PmeStatus]. A PME interrupt is also generated if
D2F[5:1]x78[PmeStatus]=1 and this bit is set by software.
2
SerrOnFatalErrEn: system error on fatal error enable. Read-write. 1=Indicates that a system
error should be generated if a fatal error (ERR_FATAL) is reported by any of the devices in the hierarchy associated with this root port, or by the root port itself.
1
SerrOnNonFatalErrEn: system error on non-fatal error enable. Read-write. 1=Indicates that a
system error should be generated if a non-fatal error (ERR_NONFATAL) is reported by any of the
devices in the hierarchy associated with this root port, or by the root port itself. See 2.13.7.8 [SERR
Message].
0
SerrOnCorrErrEn: system error on correctable error enable. Read-write. 1=Indicates that a system error should be generated if a correctable error (ERR_COR) is reported by any of the devices in
the hierarchy associated with this root port, or by the root port itself. See 2.13.7.8 [SERR Message].
D2F[5:1]x78 Root Complex Status Register
Reset: 0000_0000h.
Bits
Description
31:18 Reserved.
17
PmePending: PME pending. Read-only. This bit indicates that another PME is pending when PmeStatus is set. When PmeStatus is cleared by software; the PME is delivered by hardware by setting the
PmeStatus bit again and updating the requestor ID appropriately. PmePending is cleared by hardware
if no more PMEs are pending.
16
PmeStatus: pme status. Read; Write-1-to-clear. This bit indicates that PME was asserted by the
requestor ID indicated in the PmeRequestorID field. Subsequent PMEs are kept pending until PmeStatus is cleared by writing a 1.
15:0 PmeRequestorId: pme requestor ID. Read-only. This field indicates the PCI requestor ID of the last
PME requestor.
D2F[5:1]x7C Device Capability 2
Reset: 0000_0000h.
Bits
Description
31:24 Reserved.
23:22 MaxEndEndTlpPrefixes: Max number of End-End TLP prefixes supported. Read-only. IF
(D2F[5:1]x7C[EndEndTlpPrefixSupported]==0) THEN Reserved. ENDIF.
Bits
Definition
Bits
Definition
00b
4 End-End TLP Prefixes.
10b
2 End-End TLP Prefixes.
01b
1 End-End TLP Prefix.
11b
3 End-End TLP Prefixes.
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21
EndEndTlpPrefixSupported: End-End TLP Prefix supported. Read-only.
20
ExtendedFmtFieldSupported. Read-only. 1=Supports the 3-bit definition of the Fmt field. 0=Supports the 2-bit definition of the Fmt field. Must be set for functions that support End-End TLP prefixes.
19:18 ObffSupported: optimized buffer flush/fill supported. Read-only.
17:14 Reserved.
13:12 Reserved.
11
LtrSupported: latency tolerance supported. Read-only.
10
Reserved.
9:6
Reserved.
5
AriForwardingSupported. Read-only.
4
CplTimeoutDisSup: completion timeout disable supported. Read-only.
3:0
CplTimeoutRangeSup: completion timeout range supported. Read-only. Fh=Completion timeout
range is 64s to 50us.
D2F[5:1]x80 Device Control and Status 2
Reset: 0000_8000h.
Bits
Description
31:16 Reserved.
15
EndEndeTlpPrefixBlocking. Read-only. 1=Forwarding of End-End TLP Prefixes is not supported.
This bit is hardwired to 1b.
14:13 ObffEn: optimized buffer flush/fill enable. Read-write.
12:11 Reserved.
10
LtrEn: latency tolerance reporting enable. Read-write.
9
Reserved.
8
Reserved.
7:6
Reserved.
5
AriForwardingEn. Read-write.
4
CplTimeoutDis: completion timeout disable. Read-write. 1=Completion timeout disabled.
3:0
CplTimeoutValue: completion timeout value. Read-write. BIOS: 6h.
Bits
Timeout Range
Bits
Timeout Range
0h
50ms-50us
9h
900ms-260ms
1h
100us-50us
Ah
3.5s-1s
2h
10ms-1ms
Ch-Bh Reserved
4h-3h
Reserved
Dh
13s-4s
5h
55ms-16ms
Eh
64s-4s
6h
210ms-65ms
Fh
Reserved
8h-7h
Reserved
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D2F[5:1]x84 IO Link Capability 2
Bits
Description
31:9 Reserved.
8
CrossLinkSupported. Read-only. Reset: 0.
7:3
Reserved.
2:1
SupportedLinkSpeed. Read-only. Reset: 3h. Specifies the supported link speeds. Bit 1=2.5GT/s, Bit
2=5.0GT/s.
0
Reserved.
D2F[5:1]x88 IO Link Control and Status 2
Bits
Description
31:22 Reserved.
21
LinkEqualizationRequest. Read; write-1-to-clear. Reset: 0. 1=Hardware requests link equalization
to be performed.
20
EqualizationPhase3Success. Read-only. Reset: 0. 1=Phase 3 of the Transmitter Equalization procedure has completed successfully. Write 1 to clear.
19
EqualizationPhase2Success. Read-only. Reset: 0. 1=Phase 2 of the Transmitter Equalization procedure has completed successfully. Write 1 to clear.
18
EqualizationPhase1Success. Read-only. Reset: 0. 1=Phase 1 of the Transmitter Equalization procedure has completed successfully. Write 1 to clear.
17
EqualizationComplete. Read-only. Reset: 0. 1=Transmitter Equalization procedure has completed.
Write 1 to clear.
16
CurDeemphasisLevel: current deemphasis level. Read-only. Reset:
D2F[5:1]xE4_xA4[LcGen2EnStrap]. 1=-3.5 dB. 0=-6 dB
15:12 ComplianceDeemphasis: compliance deemphasis. Read-write. Reset: 0. In Gen2 this field defines
the compliance deemphasis level when EnterCompliance is set. Software should leave this field in its
default state.
Bits
Definition
0h
DeEmph=-6 dB, Preshoot=0 dB
1h
DeEmph=-3.5 dB, Preshoot=0 dB
2h
DeEmph=-4.5 dB, Preshoot=0 dB
3h
DeEmph=-2.5 dB, Preshoot=0 dB
4h
DeEmph=-0 dB, Preshoot=0 dB
5h
DeEmph=-0 dB, Preshoot=2 dB
6h
DeEmph=-0 dB, Preshoot=2.5 dB
7h
DeEmph=-6 dB, Preshoot=3.5 dB
8h
DeEmph=-3.5 dB, Preshoot=3.5 dB
9h
DeEmph=-0 dB, Preshoot=3.5 dB
Fh-Ah
Reserved.
11
ComplianceSOS: compliance SOS. Read-write. Reset: 0. 1=The device transmits skip ordered sets
in between the modified compliance pattern.
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10
EnterModCompliance: enter modified compliance. Read-write. Reset: 0. 1=The device transmits
modified compliance pattern. Software should leave this field in its default state.
9:7
XmitMargin: transmit margin. Read-write. Reset: 0. This field controls the non-deemphasized
voltage level at the transmitter pins. Software should leave this field in its default state.
6
SelectableDeemphasis: selectable deemphasis. Read-only. Reset:
D2F[5:1]xE4_xA4[LcGen2EnStrap]. 0=Selectable deemphasis is not supported. 1=Selectable deemphasis supported.
5
HwAutonomousSpeedDisable: hardware autonomous speed disable. Read-write. Cold reset: 0.
1=Support for hardware changing the link speed for device specific reasons disabled.
4
EnterCompliance: enter compliance. Read-write. Cold reset: 0. 1=Force the link to enter the compliance mode.
3:0
TargetLinkSpeed: target link speed. Read-write. Reset: 2h.
This field defines the upper limit of the link operational speed. Writes of reserved encodings are not
valid. Hardware prevents writes of reserved encodings from changing the state of this field.
Bits
Definition
0h
Reserved
1h
2.5GT/s
2h
5.0GT/s
D2F[5:1]x8C Slot Capability 2
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
D2F[5:1]x90 Slot Control and Status 2
Reset: 0000_0000h.
Bits
Description
31:0 Reserved.
D2F[5:1]xA0 MSI Capability Register
Reset: 0000_B005h.
Bits
Description
31:24 Reserved.
23
Msi64bit: MSI 64 bit capability. Read-only. 1=The device is capable of sending 64-bit MSI messages. 0=The device is not capable of sending a 64-bit message address.
22:20 MsiMultiEn: MSI multiple message enable. Read-write. Software writes to this field to indicate the
number of allocated vectors (equal to or less than the number of requested vectors). When MSI is
enabled, a function is allocated at least 1 vector.
19:17 MsiMultiCap: MSI multiple message capability. Read-only. 000b=The device is requesting one
vector.
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MsiEn: MSI enable. Read-write. 1=MSI generation is enabled and INTx generation is disabled.
0=MSI generation disabled and INTx generation is enabled.
15:8 NextPtr: next pointer. Read-only.
7:0
CapID: capability ID. Read-only. 05h=MSI capability structure.
D2F[5:1]xA4 MSI Message Address Low
Reset: 0000_0000h.
Bits
Description
31:2 MsiMsgAddrLo: MSI message address. Read-write. This register specifies the dword aligned
address for the MSI memory write transaction.
1:0
Reserved.
D2F[5:1]xA8 MSI Message Address High
Reset: 0000_0000h.
Bits
Description
31:0 MsiMsgAddrHi: MSI message address. Read-write. This register specifies the upper 32-bits of the
MSI address.
D2F[5:1]xAC MSI Message Data
Reset: 0000_0000h.
Bits
Description
31:16 Reserved.
15:0 MsiData: MSI message data. Read-write. This register specifies lower 16 bits of data for the MSI
memory write transaction. The upper 16 bits are always 0.
D2F[5:1]xB0 Subsystem and Subvendor Capability ID Register
Reset: 0000_B80Dh.
Bits
Description
31:16 Reserved.
15:8 NextPtr: next pointer. Read-only.
7:0
CapID: capability ID. Read-only.
D2F[5:1]xB4 Subsystem and Subvendor ID Register
Reset: 0000_0000h.
Bits
Description
31:16 SubsystemID. Read-only.
15:0 SubsystemVendorID. Read-only.
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D2F[5:1]xB8 MSI Capability Mapping
Reset: A803_0008h.
Bits
Description
31:27 CapType: capability type. Read-only.
26:18 Reserved.
17
FixD. Read-only.
16
En. Read-only.
15:8 NextPtr: next pointer. Read-only.
7:0
CapID: capability ID. Read-only.
D2F[5:1]xBC MSI Mapping Address Low
Bits
Description
31:20 MsiMapAddrLo. Read-only. Reset: 0. Lower 32-bits of the MSI address.
19:0 Reserved.
D2F[5:1]xC0 MSI Mapping Address High
Bits
Description
31:0 MsiMapAddrHi. Read-only. Reset: 0. Upper 32-bits of the MSI address.
D2F[5:1]xE0 Root Port Index
Reset: 0000_0000h.
The index/data pair registers, D2F[5:1]xE0 and D2F[5:1]xE4, are used to access the registers at
D2F[5:1]xE4_x[FF:00]. To access any of these registers, the address is first written into the index register,
D2F[5:1]xE0, and then the data is read from or written to the data register, D2F[5:1]xE4.
Bits
Description
31:8 Reserved.
7:0
PcieIndex. Read-write.
D2F[5:1]xE4 Root Port Data
See D2F[5:1]xE0. Address: D2F[5:1]xE0[PcieIndex].
Bits
Description
31:0 PcieData. Read-write.
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D2F[5:1]xE4_x20 Root Port TX Control
Reset: 0050_8000h.
Bits
15
Description
TxFlushTlpDis: TLP flush disable. Read-write. 1=Disable flushing TLPs when the link is down.
D2F[5:1]xE4_x50 Root Port Lane Status
Reset: 0000_0000h.
Bits
Description
31:7 Reserved.
6:1
0
PhyLinkWidth: port link width. Read-only; updated-by-hardware.
Bits
Definition
Bits
Definition
00_0000b disabled
00_1000b x8
00_0001b x1
01_0000b x12
00_0010b x2
10_0000b x16
00_0100b x4
PortLaneReversal: port lane reversal. Read-only. 1=Port lanes order is reversed.
D2F[5:1]xE4_x6A Root Port Error Control
Reset: 0000_0500h.
Bits
0
Description
ErrReportingDis: advanced error reporting disable. Read-write. BIOS: 1. 1=Error reporting disabled. 0=Error reporting enabled.
D2F[5:1]xE4_x70 Root Port Receiver Control
Reset: 0188_4000h.
Bits
19
Description
RxRcbCplTimeoutMode: RCB completion timeout mode. Read-write. BIOS: 1. 1=Timeout on
link down.
18:16 RxRcbCplTimeout: RCB completion timeout. Read-write.
Bits
Definition
Bits
Definition
000b
Disabled
100b
50ms
001b
50us
101b
100ms
010b
10ms
110b
500ms
011b
25ms
111b
1ms
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D2F[5:1]xE4_xA0 Per Port Link Controller (LC) Control
Reset: 4000_0030h.
Bits
23
Description
LcL1ImmediateAck: immediate ACK ASPM L1 entry. Read-write. BIOS: 1. 1=Alwyas ACK
ASPM L1 entry DLLPs.
15:12 LcL1Inactivity: L1 inactivity timer. Read-write.
Bits
Definition
Bits
Definition
0h
L1 disabled
8h
400us
1h
1us
9h
1ms
2h
2us
Ah
40us
3h
4us
Bh
10ms
4h
10us
Ch
40ms
5h
20us
Dh
100ms
6h
40us
Eh
400ms
7h
100us
Fh
reserved
11:8 LcL0sInactivity: L0s inactivity timer. Read-write.
Definition
Bits
Definition
Bits
0h
L0s disabled 8h
4us
1h
40ns
9h
10us
2h
80ns
Ah
40us
3h
120ns
Bh
100us
4h
200ns
Ch
400us
5h
400ns
Dh
1ms
6h
1us
Eh
4ms
7h
2us
Fh
reserved
7:4
Lc16xClearTxPipe. Read-write. BIOS: 3h. Specifies the number of clock to drain the TX pipe.
D2F[5:1]xE4_xA1 LC Training Control
Reset: 5400_1880h.
Bits
11
Description
LcDontGotoL0sifL1Armed: prevent Ls0 entry is L1 request in progress. Read-write. BIOS: 1.
1=Prevent the LTSSM from transitioning to Rcv_L0s if an acknowledged request to enter L1 is in
progress.
D2F[5:1]xE4_xA2 LC Link Width Control
Reset: 00A0_0006h.
Bits
Description
31:24 Reserved.
22:21 LcDynLanesPwrState: unused link power state. Read-write. Controls the state of unused links
after a reconfiguration.
Bits
Definition
Bits
Definition
00b
on
10b
SB2
01b
SB1
11b
Off
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20
LcUpconfigCapable: upconfigure capable. Read-only; updated-by-hardware. 1=Both ends of the
link are upconfigure capable. 0=Both ends of the link are not upconfigure capable.
13
LcUpconfigureDis: upconfigure disable. Read-write. 1=Disable link upconfigure.
12
LcUpconfigureSupport: upconfigure support. Read-write.
11
LcShortReconfigEn: short re-configuration enable. Read-write. 1=Enable short link re-configuration
10
LcRenegotiateEn: link reconfiguration enable. Read-write. 1=Enable link re-negotiation.
9
LcRenegotiationSupport: re-negotiation support. Read-only; updated-by-hardware. 1=Link renegotiation not supported by the downstream device.
8
LcReconfigNow: re-configure link. Read-write; cleared-when-done. 1=Initiate link width change.
7
LcReconfigArcMissingEscape. Read-write. 1=Expedite transition from Recovery.Idle to Detect during a long reconfiguration.
6:4
3
2:0
LcLinkWidthRd: current link width. Read-only; updated-by-hardware.
Bits
Definition
Bits
000b
0
100b
001b
1
101b
010b
2
110b
011b
4
111b
Definition
8
12
16
Reserved
Reserved.
LcLinkWidth: link width required. Read-write. See: LcLinkWidthRd.
D2F[5:1]xE4_xA3 LC Number of FTS Control
Reset: 00FF_020Ch.
Bits
9
Description
LcXmitFtsBeforeRecovery: transmit FTS before recovery. Read-write. 1=Transmit FTS before
recovery.
D2F[5:1]xE4_xA4 LC Link Speed Control
Reset: 0440_0100h.
Bits
Description
27
LcMultUpstreamAutoSpdChngEn: enable multiple automatic speed changes. Read-write.
1=Enable multiple automatic speed changes when D2F[5:1]xE4_xC0[StrapAutoRcSpeedNegotiationDis]=0 and no failures occured in previous speed change attempts.
19
LcOtherSideSupportsGen2: downstream link supports gen2. Read-only; updated-by-hardware.
1=The downstream link currently supports gen2.
12
LcSpeedChangeAttemptFailed: speed change attempt failed. Read-only; updated-by-hardware.
1=LcSpeedChangeAttemptsAllowed has been reached. This bit and the related counter can be cleared
using the LcClrFailedSpdChangeCnt bit.
9
LcInitiateLinkSpeedChange: initiate link speed change. Read-write; cleared-when-done. 1=Initiate link speed negotiation.
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6
LcForceDisSwSpeedChange: force disable software speed changes. Read-write. 1=Force the PCIe
core to disable speed changes initiated by private registers.
0
LcGen2EnStrap: Gen2 PCIe support enable. Read-write. 1=Gen2 PCIe support enabled. 0=Gen2
PCIe support disabled.
D2F[5:1]xE4_xA5 LC State 0
Cold reset: 0000_0000h.
Bits
Description
31:30 Reserved.
29:24 LcPrevState3: previous link state 3. Read-only; updated-by-hardware. See: Table 99 [Link controller state encodings].
23:22 Reserved.
21:16 LcPrevState2: previous link state 2. Read-only; updated-by-hardware. See: Table 99 [Link controller state encodings]
15:14 Reserved.
13:8 LcPrevState1: previous link state 1. Read-only; updated-by-hardware. See: Table 99 [Link controller state encodings].
7:6
Reserved.
5:0
LcCurrentState: current link state. Read-only; updated-by-hardware. See: Table 99 [Link controller state encodings].
Table 99: Link controller state encodings
Bits Description
Bits Description
Bits
Description
00h s_Detect_Quiet.
12h Rcv_L0_and_Tx_L0s.
24h
s_Rcvd_Loopback.
01h s_Start_common_Mode.
13h Rcv_L0_and_Tx_L0s_FTS.
25h
s_Rcvd_Loopback_Idle.
02h s_Check_Common_Mode.
14h Rcv_L0s_and_Tx_L0.
26h
s_Rcvd_Reset_Idle.
03h s_Rcvr_Detect.
15h Rcv_L0s_and_Tx_L0_Idle.
27h
s_Rcvd_Disable_Entry.
04h s_No_Rcvr_Loop
16h Rcv_L0s_and_Tx_L0s.
28h
s_Rcvd_Disable_Idle.
05h s_Poll_Quiet.
17h Rcv_L0s_and_Tx_L0s_FTS.
29h
s_Rcvd_Disable.
06h s_Poll_Active.
18h s_L1_Entry.
2Ah
s_Detect_Idle.
07h s_Poll_Compliance.
19h s_L1_Idle.
2Bh
s_L23_Wait.
08h s_Poll_Config.
1Ah s_L1_Wait
2Ch
Rcv_L0s_Skp_and_Tx_L0.
09h s_Config_Step1.
1Bh s_L1.
2Dh
Rcv_L0s_Skp_and_Tx_L0_Idle.
0Ah s_Config_Step3.
1Ch s_L23_Stall.
2Eh
Rcv_L0s_Skp_and_Tx_L0s.
0Bh s_Config_Step5.
1Dh s_L23_Entry.
2Fh
Rcv_L0s_Skp_and_Tx_L0_FTS.
0Ch s_Config_Step2.
1Eh s_L23_Entry.
30h
s_Config_Step2b.
0Dh s_Config_Step4.
1Fh s_L23_Ready.
31h
s_Recovery_Speed.
0Eh s_Config_Step6.
20h s_Recovery_lock.
32h
s_Poll_Compliance_Idle.
0Fh s_Config_Idle.
21h s_Recovery_Config.
33h
s_Rcvd_Loopback_Speed.
10h Rcv_L0_and_Tx_L0.
22h s_Recovery_Idle.
11h Rcv_L0_and_Tx_L0_Idle.
23h s_Training_Bit.
3Fh-34h Reserved.
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D2F[5:1]xE4_xB1 LC Control 2
Reset: 8608_0280h.
Bits Description
20
LcBlockElIdleinL0: block electrical idle in l0. Read-write. BIOS: 1. 1=Prevent electrical idle from
causing the receiver to transition from L0 to L0s.
19
LcDeassertRxEnInL0s: deassert RX_EN in L0s. Read-write. 1=Turn off transmitters in L0s.
D2F[5:1]xE4_xB5 LC Control 3
Reset: 2850_5020h.
Bits Description
30
LcGoToRecovery: go to recovery. Read-write. 1=Force link in the L0 state to transition to the
Recovery state.
3
LcRcvdDeemphasis: received deemphasis. Read-only; updated-by-hardware. Deemphasis advertised by the downstream device. 1=3.5dB. 0=6dB.
2:1
LcSelectDeemphasisCntl: deemphasis control. Read-write. Specifies the deemphasis used by the
transmitter.
Definition
Bits
00b
Use deemphasis from LcSelectDeemphasis.
01b
Use deemphasis advertised by the downstream device.
10b
6dB
11b
3.5dB
0
LcSelectDeemphasis: downstream deemphasis. Read-write. Specifies the downstream deemphasis.
1=3.5dB. 0=6dB.
D2F[5:1]xE4_xC0 LC Strap Override
Reset: 0000_0000h.
Bits
Description
15
StrapAutoRcSpeedNegotiationDis: autonomous speed negotiation disable strap override. Readwrite. 1=Disable autonomous root complex speed negotiation to Gen2.
13
StrapForceCompliance: force compliance strap override. Read-write.
D2F[5:1]xE4_xC1 Root Port Miscellaneous Strap Override
Reset: 0000_0000h.
Bits
Description
31:6 Reserved.
5
StrapLtrSupported. Read-write.
4:3
StrapObffSupported. Read-write.
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2
StrapExtendedFmtSupported: Extended Fmt Supported strap override. Read-write.
1
StrapE2EPrefixEn: E2E Prefix En strap override. Read-write.
0
StrapReverseLanes: reverse lanes strap override. Read-write.
D2F[5:1]xE4_xD0 Root Port ECC Skip OS Feature
Reset: 0000_0100h.
Bits
Description
31:16 BchEccErrorStatus. Read-write. Indicates that lane errors are above the specified threshold. (One bit
per lane.)
15:8 BchEccErrorThreshold. Read-write. Error threshold.
7:1
0
Reserved.
StrapBchEccEn. Read-write.
D2F[5:1]x100 Vendor Specific Enhanced Capability Register
Bits
Description
31:20 NextPtr: next pointer. Read-only.
IF (D0F0xE4_x0140_00B0[StrapF0VcEn] == 1) THEN Reset: 110h.
ELSEIF (D0F0xE4_x0140_00B0[StrapF0DsnEn] == 1) THEN Reset: 140h.
ELSEIF (D0F0xE4_x0140_00B0[StrapF0AerEn] == 1) THEN Reset: 150h.
ELSEIF (D0F0xE4_x0140_00C1[StrapGen3Compliance] == 1) THEN 270h.
ELSEIF (D0F0xE4_x0140_00B0[StrapF0AcsEn] == 1) THEN 2A0h.
ELSE Reset: 000h. ENDIF.
19:16 CapVer: capability version. Read-only. Reset: 1h.
15:0 CapID: capability ID. Read-only. Reset: Bh.
D2F[5:1]x104 Vendor Specific Header Register
Reset: 0101_0001h.
Bits
Description
31:20 VsecLen: vendor specific enhanced capability structure length. Read-only. Defined the number of
bytes of the entire vendor specific enhanced capability structure including the header.
19:16 VsecRev: vendor specific enhanced capability version. Read-only.
15:0 VsecID: vendor specific enhanced capability ID. Read-only.
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D2F[5:1]x108 Vendor Specific 1 Register
Reset: 0000_0000h.
Bits
Description
31:0 Scratch: scratch. Read-write. This field does not control any hardware.
D2F[5:1]x10C Vendor Specific 2 Register
Reset: 0000_0000h.
Bits
Description
31:0 Scratch: scratch. Read-write. This field does not control any hardware.
D2F[5:1]x128 Virtual Channel 0 Resource Status Register
Reset: 0002_0000h.
Bits
Description
31:18 Reserved.
17
VcNegotiationPending: virtual channel negotiation pending. Read-only; updated-by-hardware.
1=Virtual channel negotiation in progress. This bit must be 0 before the virtual channel can be used.
16
PortArbTableStatus: port arbitration table status. Read-only.
15:0 Reserved.
D2F[5:1]x150 Advanced Error Reporting Capability
Bits
Description
31:20 NextPtr: next pointer. Read-only.
IF (D0F0xE4_x0140_00C1[StrapGen3Compliance] == 1) THEN 270h.
ELSEIF (D0F0xE4_x0140_00B0[StrapF0AcsEn] == 1) THEN 2A0h.
ELSE Reset: 000h. ENDIF.
19:16 CapVer: capability version. Read-only. Reset: 2h.
15:0 CapID: capability ID. Read-only. Reset: 1h.
D2F[5:1]x154 Uncorrectable Error Status
Cold reset: 0000_0000h.
Bits
Description
31:26 Reserved.
25
TlpPrefixStatus: TLP prefix blocked status. Read; Write-1-to-clear.
24
AtomicOpEgressBlockedTLPStatus: atomic op egress blocked TLP status. Read; Write-1-toclear.
23
McBlockedTLPStatus: MC blocked TLP status. Read; Write-1-to-clear.
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22
UncorrInteralErrStatus: uncorrectable internal error status. Read; Write-1-to-clear.
21
AcsViolationStatus: access control service status. Read; Write-1-to-clear.
20
UnsuppReqErrStatus: unsupported request error status. Read; Write-1-to-clear. The header of
the unsupported request is logged.
19
EcrcErrStatus: end-to-end CRC error status. Read; Write-1-to-clear.
18
MalTlpStatus: malformed TLP status. Read; Write-1-to-clear. The header of the malformed TLP is
logged.
17
RcvOvflStatus: receiver overflow status. Read-only.
16
UnexpCplStatus: unexpected completion timeout status. Read; Write-1-to-clear. The header of the
unexpected completion is logged.
15
CplAbortErrStatus: completer abort error status. Read; Write-1-to-clear.
14
CplTimeoutStatus: completion timeout status. Read; Write-1-to-clear.
13
FcErrStatus: flow control error status. Read-only.
12
PsnErrStatus: poisoned TLP status. Read; Write-1-to-clear. The header of the poisoned transaction
layer packet is logged.
11:6 Reserved.
5
SurprdnErrStatus: surprise down error status. Read-only. 0=Detection and reporting of surprise
down errors is not supported.
4
DlpErrStatus: data link protocol error status. Read; Write-1-to-clear.
3:0
Reserved.
D2F[5:1]x158 Uncorrectable Error Mask
Cold reset: 0000_0000h.
Bits
Description
31:26 Reserved.
25
TlpPrefixMask: TLP prefix blocked mask. Read-only.
24
AtomicOpEgressBlockedTLPMask: atomic op egress blocked TLP mask. Read-only.
23
McBlockedTLPMask: MC blocked TLP mask. Read-only.
22
UncorrInteralErrMask: uncorrectable internal error mask. Read-write.
21
AcsViolationMask: access control service mask. IF (D0F0xE4_x0140_00B0[StrapF0AcsEn] ==1)
THEN Read-write. ELSE Read-only. ENDIF. 1=ACS violation errors are not reported.
20
UnsuppReqErrMask: unsupported request error mask. Read-write. 1=Unsupported request
errors are not reported.
19
EcrcErrMask: end-to-end CRC error mask. Read-write.
18
MalTlpMask: malformed TLP mask. Read-write. 1=Malformed TLP errors are not reported.
17
RcvOvflMask: receiver overflow mask. Read-only.
16
UnexpCplMask: unexpected completion timeout mask. Read-write. 1=Unexpected completion
errors are not reported.
15
CplAbortErrMask: completer abort error mask. Read-write.
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14
CplTimeoutMask: completion timeout mask. Read-write. 1=Completion timeout errors are not
reported.
13
FcErrMask: flow control error mask. Read-only.
12
PsnErrMask: poisoned TLP mask. Read-write.1=Poisoned TLP errors are not reported.
11:6 Reserved.
5
SurprdnErrMask: surprise down error mask. Read-only.
4
DlpErrMask: data link protocol error mask. Read-write. 1=Data link protocol errors are not
reported.
3:0
Reserved.
D2F[5:1]x15C Uncorrectable Error Severity
Cold reset: 0006_2030h.
Bits
Description
31:26 Reserved.
25
TlpPrefixSeverity: TLP prefix blocked severity. Read-only.
24
AtomicOpEgressBlockedTLPSeverity: atomic op egress blocked TLP severity. Read-only.
23
McBlockedTLPSeverity: MC blocked TLP severity. Read-only.
22
UncorrInteralErrSeverity: uncorrectable internal error severity. Read-only.
21
AcsViolationSeverity: access control service severity. IF (D0F0xE4_x0140_00B0[StrapF0AcsEn]
==1) THEN Read-write. ELSE Read-only. ENDIF.1=Fatal error. 0=Non-fatal error.
20
UnsuppReqErrSeverity: unsupported request error severity. Read-write. 1=Fatal error. 0=Nonfatal error.
19
EcrcErrSeverity: end-to-end CRC error severity. Read-only.
18
MalTlpSeverity: malformed TLP severity. Read-write. 1=Fatal error. 0=Non-fatal error.
17
RcvOvflSeverity: receiver overflow severity. Read-only.
16
UnexpCplSeverity: unexpected completion timeout severity. Read-write. 1=Fatal error. 0=Nonfatal error.
15
CplAbortErrSeverity: completer abort error severity. Read-only.
14
CplTimeoutSeverity: completion timeout severity. Read-write. 1=Fatal error. 0=Non-fatal error.
13
FcErrSeverity: flow control error severity. Read-only.
12
PsnErrSeverity: poisoned TLP severity. Read-write. 1=Fatal error. 0=Non-fatal error.
11:6 Reserved.
5
SurprdnErrSeverity: surprise down error severity. Read-only.
4
DlpErrSeverity: data link protocol error severity. Read-write. 1=Fatal error. 0=Non-fatal error.
3:0
Reserved.
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D2F[5:1]x160 Correctable Error Status
Cold reset: 0000_0000h.
Bits
Description
31:16 Reserved.
15
HdrLogOvflStatus: header log overflow status. Read-only.
14
CorrIntErrStatus: corrected internal error status. Read; Write-1-to-clear.
13
AdvisoryNonfatalErrStatus: advisory non-fatal error status. Read; Write-1-to-clear. 1=A nonfatal unsupported request errors or a non-fatal unexpected completion errors occurred.
12
ReplayTimerTimeoutStatus: replay timer timeout status. Read; Write-1-to-clear.
11:9 Reserved.
8
ReplayNumRolloverStatus: replay. Read; Write-1-to-clear. 1=The same transaction layer packet
has been replayed three times and has caused the link to re-train.
7
BadDllpStatus: bad data link layer packet status. Read; Write-1-to-clear. 1=A link CRC error was
detected.
6
BadTlpStatus: bad transaction layer packet status. Read; Write-1-to-clear. 1=A bad non-duplicated sequence ID or a link CRC error was detected.
5:1
0
Reserved.
RcvErrStatus: receiver error status. Read-only. 1=An 8B10B or disparity error was detected.
D2F[5:1]x164 Correctable Error Mask
Cold reset: 0000_6000h.
Bits
Description
31:16 Reserved.
15
HdrLogOvflMask: header log overflow mask. Read-only.
14
CorrIntErrMask: corrected internal error mask. Read-write.
13
AdvisoryNonfatalErrMask: advisory non-fatal error mask. Read-write. 1=Error is not reported.
12
ReplayTimerTimeoutMask: replay timer timeout mask. Read-write. 1=Error is not reported.
11:9 Reserved.
8
ReplayNumRolloverMask: replay. Read-write.1=Error is not reported.
7
BadDllpMask: bad data link layer packet mask. Read-write. 1=Error is not reported.
6
BadTlpMask: bad transaction layer packet mask. Read-write. 1=Error is not reported.
5:1
0
Reserved.
RcvErrMask: receiver error mask. Read-only. 1=Error is not reported.
D2F[5:1]x168 Advanced Error Control
Cold reset: 0000_0000h.
Bits
Description
31:12 Reserved.
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11
TlpPrefixLogPresent. Read-only. IF (D2F[5:1]x7C[EndEndTlpPrefixSupported]==0) THEN
Reserved. ENDIF. 1=If FirstErrPtr is valid then the TLP Prefix Log register contains valid information.
10
MultiHdrRecdEn. Read-only. 1=Enables recording more than one error header.
9
MultiHdrRecdCap. Read-only. 1=Specifies that the function is capable of recording more than one
error header.
8
EcrcCheckEn: data link protocol error severity. Read-write. 0=Specifies that End-to-end CRC
generation is not supported.
7
EcrcCheckCap: data link protocol error severity. Read-only. 0=Specifies that end-to-end CRC
check is not supported.
6
EcrcGenEn: end-to-end CRC enable. Read-only. 0=Specifies that End-to-end CRC generation is
not supported.
5
EcrcGenCap: end-to-end CRC capability. Read-only. 0=Specifies that end-to-end CRC generation
is not supported.
4:0
FirstErrPtr: first error pointer. Read-only. The First Error Pointer identifies the bit position of the
first error reported in the Uncorrectable Error Status register.
D2F[5:1]x16C Header Log DW0
Cold reset: 0000_0000h.
Bits
Description
31:0 TlpHdr: transaction layer packet header log. Read-only. Contains the header for a transaction
layer packet corresponding to a detected error. The upper byte represents byte 0 of the header.
D2F[5:1]x170 Header Log DW1
Cold reset: 0000_0000h.
Bits
Description
31:0 TlpHdr: transaction layer packet header log. Read-only. Contains the header for a transaction
layer packet corresponding to a detected error. The upper byte represents byte 4 of the header.
D2F[5:1]x174 Header Log DW2
Cold reset: 0000_0000h.
Bits
Description
31:0 TlpHdr: transaction layer packet header log. Read-only. Contains the header for a transaction
layer packet corresponding to a detected error. The upper byte represents byte 8 of the header.
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D2F[5:1]x178 Header Log DW3
Cold reset: 0000_0000h.
Bits
Description
31:0 TlpHdr: transaction layer packet header log. Read-only. Contains the header for a transaction
layer packet corresponding to a detected error. The upper byte represents byte 12 of the header.
D2F[5:1]x17C Root Error Command
Reset: 0000_0000h.
Bits
Description
31:3 Reserved.
2
FatalErrRepEn: fatal error reporting enable. Read-write. 1=Enables the generation of an interrupt
when a fatal error is reported by any of the devices in the hierarchy associated with this Root Port.
1
NonfatalErrRepEn: non-fatal error reporting enable. Read-write. 1=Enables generation of an
interrupt when a non-fatal error is reported by any of the devices in the hierarchy associated with this
Root Port.
0
CorrErrRepEn: correctable error reporting enable. Read-write. 1=Enables generation of an interrupt when a correctable error is reported by any of the devices in the hierarchy associated with this
Root Port.
D2F[5:1]x180 Root Error Status
Cold reset: 0000_0000h.
Bits
Description
31:27 AdvErrIntMsgNum: advanced error interrupt message number. Read-only.
26:7 Reserved.
6
NFatalErrMsgRcvd: fatal error message received. Read; Write-1-to-clear. Set to 1 when one or
more fatal uncorrectable error messages have been received.
5
NonFatalErrMsgRcvd: non-fatal error message received. Read; Write-1-to-clear. Set to 1 when
one or more non-fatal uncorrectable error messages have been received.
4
FirstUncorrFatalRcvd: first uncorrectable fatal error message received. Read; Write-1-to-clear.
Set to 1 when the first uncorrectable error message received is for a fatal error.
3
MultErrFatalNonfatalRcvd: ERR_FATAL/NONFATAL message received. Read; Write-1-toclear. Set when either a fatal or a non-fatal error is received and ErrFatalNonfatalRcvd is already set.
2
ErrFatalNonfatalRcvd: ERR_FATAL/NONFATAL message received. Read; Write-1-to-clear. Set
when either a fatal or a non-fatal error is received and this bit is not already set.
1
MultErrCorrRcvd: multiple ERR_COR messages received. Read; Write-1-to-clear. Set when a
correctable error message is received and ErrCorrRcvd is already set.
0
ErrCorrRcvd: ERR_COR message received. Read; Write-1-to-clear. Set when a correctable error
message is received and this bit is not already set.
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D2F[5:1]x184 Error Source ID
Cold reset: 0000_0000h.
Bits
Description
31:16 ErrFatalNonfatalSrcID: ERR_FATAL/ERR_NONFATAL source identification. Read-only.
Loaded with the requestor ID indicated in the received ERR_FATAL or ERR_NONFATAL message
when D2F[5:1]x180[ErrFatalNonfatalRcvd] is not already set.
15:0 ErrCorlSrcID: ERR_COR source identification. Read-only. Loaded with the requestor ID indicated in the received ERR_COR message when D2F[5:1]x180[ErrCorrRcvd] is not already set.
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Device 18h Function 0 Configuration Registers
See 3.1 [Register Descriptions and Mnemonics]. See 2.7 [Configuration Space].
D18F0x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID. Read-only.
Value: 1530h.
15:0 VendorID: vendor ID. Read-only. Value: 1022h.
D18F0x04 Status/Command
Bits
Description
31:16 Status. Read-only. Value: 0010h. Bit[20] is set to indicate the existence of a PCI-defined capability
block.
15:0 Command. Read-only. Value: 0000h.
D18F0x08 Class Code/Revision ID
Bits
Description
31:8 ClassCode. Read-only. Value: 060000h. Provides the host bridge class code as defined in the PCI
specification.
7:0
RevID: revision ID. Read-only. Value: 00h.
D18F0x0C Header Type
Read-only. Value: 0080_0000h.
Bits
Description
31:0 HeaderTypeReg. These bits are fixed at their default values. The header type field indicates that
there are multiple functions present in this device.
D18F0x34 Capabilities Pointer
Bits
Description
31:8 Reserved.
7:0
CapPtr: capabilities pointer. Read-only. Value: 00h.
D18F0x[5C:40] Routing Table
Reset: 0004_0201h. As each packet is processed by the node, it is routed to the appropriate links, or remains in
the node that is processing the packet, based on the source/destination node and the type of packet being pro-
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cessed. The destination of requests and responses determines which of these eight registers is used to route the
packet; the source of probes and broadcasts determines which of these eight registers is used to route the
packet. Once the routing table register is identified, the packet is routed to the destinations based on the state of
the field (in that routing table register) that corresponds to the packet type.
Table 100: Register Mapping for D18F0x[5C:40]
Register
D18F0x40
D18F0x[5C:44]
Bits
Function
Node 0
Reserved
Description
D18F0x60 Node ID
Bits
Description
20:16 CpuCnt[4:0]: CPU count bits[4:0]. Read-write. Reset: 0.
Specifies the number of cores to be enabled (the boot core plus those cores enabled through
D18F0x1DC[CpuEn]).
Description
Bits
00h
1 core
02h-01h
<CpuCnt[4:0] + 1> cores
03h
4 cores
1Fh-04h
Reserved
D18F0x64 Unit ID
Reset: 0000_00E0h.
Bits
Description
31:16 Reserved.
15:11 Reserved. Read-write.
10:8 Reserved. Read-write.
7:6
HbUnit: host bridge Unit ID. Read-only. Specifies the coherent link Unit ID of the host bridge used
by the coherent fabric.
5:4
MctUnit: memory controller Unit ID. Read-only. Specifies the coherent link Unit ID of the memory
controller.
3:0
Reserved.
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D18F0x68 Link Transaction Control
Bits
31
Description
Reserved. Read-write.
30:28 Reserved. Read-write.
27:26 Reserved.
25
Reserved. Read-write.
24
Reserved. Read-write.
23
InstallStateS. Read-write. Reset: 0. 1=Forces the default read block (RdBlk) install state to be shared
instead of exclusive.
22:21 DsNpReqLmt: downstream non-posted request limit. Read-write. Reset: 00b. BIOS: 10b. Note:
RS880 chipsets set this to 01b due to a chipset issue; this issue has been fixed in all chipsets after the
RS880. This specifies the maximum number of downstream non-posted requests issued by core(s)
which may be outstanding on the IO links attached to this node at one time.
Bits
Description
00b
No limit
01b
limited to 1
10b
limited to 4
11b
limited to 8
20
SeqIdSrcNodeEn: sequence ID source node enable. Read-write. Reset: 0. 1=The source node ID of
requests is provided in the SeqID field of the corresponding downstream IO link request packets. This
may be useful for debug applications, in order to match downstream packets with their originating
node. For normal operation, this bit should be cleared. Correct ordering of requests between different
nodes is not ensured when this bit is set. Semaphore sharing between differing nodes may not work
properly in systems which are capable of processing IO requests with differing non-zero SeqIds out of
request order.
19
ApicExtSpur: APIC extended spurious vector enable. Read-write. Reset: 0. This enables the
extended APIC spurious vector functionality; it affects APICF0[Vector]. 0=The lower 4 bits of the
spurious vector are read-only 1111b. 1=The lower 4 bits of the spurious vector are writable.
18
ApicExtId: APIC extended ID enable. Read-write. Reset: 0. Enables the extended APIC ID functionality. 0=APIC ID is 4 bits. 1=APIC ID is 8 bits.
17
ApicExtBrdCst: APIC extended broadcast enable. Read-write. Reset: 0. Enables the extended
APIC broadcast functionality. 0=APIC broadcast is 0Fh. 1=APIC broadcast is FFh. If ApicExtBrdCst=1 then software must assert ApicExtId.
16
LintEn: local interrupt conversion enable. Read-write. Reset: 0. 1=Enables the conversion of
broadcast ExtInt and NMI interrupt requests to LINT0 and LINT1 local interrupts, respectively,
before delivering to the local APIC. This conversion only takes place if the local APIC is hardware
enabled. LINT0 and LINT1 are controlled by APIC3[60:50]. 0=ExtInt/NMI interrupts delivered
unchanged.
15
LimitCldtCfg: limit coherent link configuration space range. Read-write. Reset: 0. BIOS: 1.
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14:13 Reserved. Read-write.
12
Reserved. Read-write.
11
RespPassPW: response PassPW. Read-write. Reset: 0. BIOS: 1. 1=The PassPW bit in all downstream link responses is set, regardless of the originating request packet. This technically breaks the
PCI ordering rules but it is not expected to be an issue in the downstream direction. Setting this bit
improves the latency of upstream requests by allowing the downstream responses to pass posted
writes. 0=The PassPW bit in downstream responses is based on the RespPassPW bit of the original
request.
10
DisFillP: disable fill probe. Read-write. Reset: 0. Controls probes for core-generated fills. 0=Probes
issued for cache fills. 1=Probes not issued for cache fills. BIOS: 0. BIOS may set if single core.
9
DisRmtPMemC: disable remote probe memory cancel. Read-write. Reset: 0. 1=Only probed
caches on the same node as the target memory controller may generate MemCancel coherent link
packets. MemCancels are used to attempt to save DRAM and/or link bandwidth associated with the
transfer of stale DRAM data. 0=Probes hitting dirty blocks may generate MemCancel packets, regardless of the location of the probed cache.
8
DisPMemC: disable probe memory cancel. Read-write. Reset: 0. Controls generation of MemCancel coherent link packets. MemCancels are used to attempt to save DRAM and/or coherent link bandwidth associated with the transfer of stale DRAM data. 0=Probes hitting dirty blocks of the core cache
may generate MemCancel packets. 1=Probes may not generate MemCancel packets.
7
CPURdRspPassPW: CPU read response PassPW. Read-write. Reset: 0. 1=Read responses to coregenerated reads are allowed to pass posted writes. 0=core responses do not pass posted writes. This
bit is not expected to be set. This bit may only be set during the boot process.
6
CPUReqPassPW: CPU request PassPW. Read-write. Reset: 0. 1=Core-generated requests are
allowed to pass posted writes. 0=Core requests do not pass posted writes. This bit is not expected to
be set. This bit may only be set during the boot process.
5
Reserved.
4
DisMTS: disable memory controller target start. Read-write. Reset: 0. BIOS: 1. 1=Disables use of
TgtStart. TgtStart is used to improve scheduling of back-to-back ordered transactions by indicating
when the first transaction is received and ordered at the memory controller.
3
DisWrDwP: disable write doubleword probes. Read-write. Reset: 0. BIOS: 1. 1=Disables generation of probes for core-generated, WrSized doubleword commands.
2
DisWrBP: disable write byte probes. Read-write. Reset: 0. BIOS: 1. 1=Disables generation of
probes for core-generated, WrSized byte commands.
1
DisRdDwP: disable read doubleword probe. Read-write. Reset: 0. BIOS: 1. 1=Disables generation
of probes for coregenerated, RdSized doubleword commands.
0
DisRdBP: disable read byte probe. Read-write. Reset: 0. BIOS: 1. 1=Disables generation of probes
for core-generated, RdSized byte commands.
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D18F0x6C Link Initialization Control
Bits
Description
30
RlsLnkFullTokCntImm: release upstream full token count immediately. Read-write. Reset: 0b.
BIOS: 1 after buffer counts have been programmed. 1=Apply buffer counts programmed in
D18F0x[F0,D0,B0,90] and D18F0x[F4,D4,B4,94] immediately without requiring warm reset. Once
this bit is set, additional changes to the buffer counts only take effect upon warm reset.
28
RlsIntFullTokCntImm: release internal full token count immediately. Read-write. Reset: 0b.
BIOS: 1 after buffer counts have been programmed. 1=Apply buffer counts programmed in
D18F3x6C, D18F3x70, D18F3x74, D18F3x78, D18F3x7C, D18F3x140, D18F3x144,
D18F3x1[54:48], D18F3x17C, and D18F3x1A0 immediately without requiring warm reset. Once this
bit is set, additional changes to the buffer counts only take effect upon warm reset.
27
ApplyIsocModeEnNow. Read-write. Reset: 0b. BIOS: 1 after RlsLnkFullTokCntImm and
RlsIntFullTokCntImm have been set. 1=Apply the programmed value in D18F0x[E4,C4,A4,84][IsocEn] immediately without requiring warm reset. This bit may only be set if RlsLnkFullTokCntImm
and RlsIntFullTokCntImm are set and isochronous buffers have been allocated. RULE: IF (ApplyIsocModeEnNow) THEN (D18F3x1[54:48][IsocPreqTok0] > 0).
23
Reserved. Read-write.
22:21 Reserved. Read-write.
20
Reserved. Read-write.
19:16 Reserved. Read-write.
15:12 Reserved. Read-write.
11
Reserved. Read-write.
10:9 BiosRstDet[2:1]: BIOS reset detect bits[2:1]. See: BiosRstDet[0].
8
Reserved.
6
InitDet: CPU initialization command detect. Read-write. Reset: 0. This bit may be used by software to distinguish between an INIT and a warm/cold reset by setting it to a 1 before an initialization
event is generated. This bit is cleared by RESET_L but not by an INIT command.
5
BiosRstDet[0]: BIOS reset detect bit[0]. Read-write; S3-check-exclude. Cold reset: 0. BiosRstDet[2:0] = {BiosRstDet[2:1], BiosRstDet[0]}. May be used to distinguish between a reset event generated by the BIOS versus a reset event generated for any other reason by setting one or more of the
bits to a 1 before initiating a BIOS-generated reset event.
4
ColdRstDet: cold reset detect. Read-write. Cold reset: 0. This bit may be used to distinguish
between a cold versus a warm reset event by setting the bit to a 1 before an initialization event is generated.
3:2
Reserved.
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1
Reserved. Read-write.
0
RouteTblDis: routing table disable. Read-write.
IF (BootFromDRAM) THEN Cold reset: 0. ELSE Reset: 1. ENDIF. BIOS: 0.
D18F0x[E4,C4,A4,84] Link Control
Table 101: Register Mapping for D18F0x[E4,C4,A4,84]
Register
D18F0x84
D18F0x[E4,C4,A4]
Function
ONION Link
Reserved
This register is derived from the link control register defined in the link specification.
Bits
15
Description
Addr64BitEn: 64-bit address packet enable. Read-write. Reset: 0000b. 1=Requests to addresses
greater than FF_FFFF_FFFFh are supported by this IO link. 0=Requests to addresses greater than
FF_FFFF_FFFFh are master aborted as if the end of chain was reached. BIOS is required to ensure
that the link-specification-defined “64 Bit Address Feature” bit in the device on the other side of the
link is set prior to setting this bit. For coherent links, this bit is unused. D18F0x68[CHtExtAddrEn] is
required to be set if this bit is set for any IO link. The link specification indicates that this bit is cleared
by a warm reset; therefore this bit may be in a different state than an IO device on the other side of the
link after a warm reset; care should be taken by BIOS to place devices on both sides of the link in the
same state after a warm reset, before any packets to the high-order addresses enabled by this bit are
generated.
14:13 Reserved. Read-write.
12
IsocEn: isochronous flow-control mode enable. Read-write. Reset: 0b. BIOS: 1 if the link is an
ONION Link. This bit is set to place the link into isochronous flow-control mode (IFCM), as defined
by the link specification. 1=IFCM. 0=Normal flow-control mode. See D18F0x6C[ApplyIsocModeEnNow].
5
Reserved.
4
LinkFail: link failure. Read; set-by-hardware; write-1-to-clear. Cold reset: 0. This bit is set high by
the hardware if a sync flood is received by the link. See 2.14.1.9.1 [Common Diagnosis Information].
D18F0x[EC,CC,AC,8C] Link Feature Capability
This register is derived from the link feature capability register defined in the link specification. Unless otherwise specified: 0=The feature is not supported; 1=The feature is supported.
Table 102: Register Mapping for D18F0x[EC,CC,AC,8C]
Register
D18F0x8C
D18F0x[EC,CC,AC]
Function
ONION Link
Reserved
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Bits
BKDG for AMD Family 16h Models 00h-0Fh Processors
Description
31:6 Reserved.
5
UnitIdReOrderDis: UnitID reorder disable. Read-write. Reset: 0. 1=Upstream reordering for different UnitIDs is not supported; i.e., all upstream packets are ordered as if they have the same UnitID.
0=Reordering based on UnitID is supported.
4
Reserved. Reset: 1.
3:2
Reserved.
1
Reserved. Reset: 1.
0
Reserved. Reset: 1.
D18F0x[F0,D0,B0,90] Link Base Channel Buffer Count
Read-write; Reset-applied.
Table 103: Register Mapping for D18F0x[F0,D0,B0,90]
Register
D18F0x90
D18F0x[F0,D0,B0]
Function
ONION Link
Reserved
D18F0x[F0,D0,B0,90] and D18F0x[F4,D4,B4,94] specify the hard-allocated link flow-control buffer counts
in each virtual channel available to the transmitter at the other end of the link; it also provides the free buffers
that may be used by any of the virtual channels, as needed. Base channel buffers are specified in
D18F0x[F0,D0,B0,90]; isochronous buffer counts (if in IFCM) are specified in D18F0x[F4,D4,B4,94]. For all
fields that specify buffer counts in D18F0x[F0,D0,B0,90] and D18F0x[F4,D4,B4,94], if the link is ganged,
then the number of buffers allocated is 2 times the value of the field; If the link is unganged, then the number of
buffers allocated is the value of the field.
The cold or warm reset value is determined by whether the link initializes, whether the link is IO/coherent,
whether the link is ganged/unganged, and whether the settings are locked by LockBc. Out of cold reset, the
processor allocates a minimal number of buffers that is smaller than the default values in the register. BIOS
must use D18F0x6C[RlsLnkFullTokCntImm] or D18F0x6C[RlsLnkFullTokCntOnRst] for the values in the
register to take effect. This is necessary even if the values are unchanged from the default values.
The hard-allocated buffer counts are transmitted to the device at the other end of the link in buffer release messages after link initialization. The remaining buffers are held in the free list (specified by FreeData and
FreeCmd) used to optimize buffer usage. When a transaction is received, if a free-list buffer is available, it is
used for storage instead of one of the hard allocated buffers; as a result, a buffer release (for one of the hard
allocated buffers used by the incoming request) can be immediately sent back to the device at the other end of
the link without waiting for the transaction to be routed beyond the flow-control buffers.
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Table 104: Link Buffer Definitions
Term
LpbSize
Definition
Link Packet Command Buffer size.
LpbSize = 24.
LpbdSize
Link Packet Data Buffer size.
LpbdSize = 16.
LcsSize
Link Command Scheduler size.
LcsSize = 32.
Buffer allocation rules:
• The total number of command buffers allocated in the base and isochronous registers of a link cannot
exceed LpbSize:
• Rule: (D18F0x[F0,D0,B0,90][NpReqCmd] + D18F0x[F0,D0,B0,90][PReq] +
D18F0x[F0,D0,B0,90][RspCmd] + D18F0x[F0,D0,B0,90][ProbeCmd] +
D18F0x[F0,D0,B0,90][FreeCmd] + D18F0x[F4,D4,B4,94][IsocNpReqCmd] +
D18F0x[F4,D4,B4,94][IsocPReq] + D18F0x[F4,D4,B4,94][IsocRspCmd]) <= LpbSize.
• The total number of data buffers allocated in the base and isochronous registers of a link cannot exceed
LpbdSize:
• Rule: (D18F0x[F0,D0,B0,90][NpReqData] + D18F0x[F0,D0,B0,90][RspData] +
D18F0x[F0,D0,B0,90][PReq] + D18F0x[F0,D0,B0,90][FreeData] +
D18F0x[F4,D4,B4,94][IsocPReq] + D18F0x[F4,D4,B4,94][IsocNpReqData] +
D18F0x[F4,D4,B4,94][IsocRspData]) <= LpbdSize.
• The total number of hard allocated command buffers cannot exceed LcsSize.
• Rule: (D18F0x[F0,D0,B0,90][ProbeCmd] + D18F0x[F0,D0,B0,90][RspCmd] +
D18F0x[F0,D0,B0,90][PReq] + D18F0x[F0,D0,B0,90][NpReqCmd] + +
D18F0x[F4,D4,B4,94][IsocRspCmd] + D18F0x[F4,D4,B4,94][IsocPReq] +
D18F0x[F4,D4,B4,94][IsocNpReqCmd]) <= LcsSize.
Bits Description
31
LockBc: lock buffer count register.
Cold reset: 0.
BIOS: 1.
1=The buffer count registers, D18F0x[F0,D0,B0,90] and D18F0x[F4,D4,B4,94] are locked such that
warm resets do not place the registers back to their default value. Setting this bit does not prevent the
buffer counts from being updated after a warm reset based on the value of the buffer counts before the
warm reset. 0=Upon warm reset, the buffer count registers return to their default value after the link
initializes regardless of the value before the warm reset.
30
PReq[3]: posted request command and data buffer count [3].
IF (LockBc) THEN Cold reset: 0. ELSE Reset: 0. ENDIF.
BIOS: 0.
See: PReq[2:0].
29:28 NpReqData[3:2]: non-posted request data buffer count [3:2].
IF (LockBc) THEN Cold reset: 00b. ELSE THEN Reset: 00b. ENDIF.
BIOS: IF (REG==D18F0x90) THEN 00b ELSE 11b ENDIF.
See: NpReqData[1:0].
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27:25 FreeData: free data buffer count.
IF (D18F0x[F0,D0,B0,90][LockBc]) THEN Cold reset: 0. ELSE THEN Reset: 0. ENDIF.
BIOS: 0.
24:20 FreeCmd: free command buffer count.
IF (D18F0x[F0,D0,B0,90][LockBc]) THEN Cold reset: 0. ELSE THEN Reset: 0. ENDIF.
BIOS: IF (REG==D18F0x90) THEN 00h ELSE 00h ENDIF.
19:18 RspData: response data buffer count.
IF (LockBc) THEN Cold reset: 1. ELSE THEN Reset: 1. ENDIF.
BIOS: IF (REG==D18F0x90) THEN 1 ELSE 0 ENDIF.
17:16 NpReqData[1:0]: non-posted request data buffer count [1:0].
NpReqData[3:0] = {NpReqData[3:2], NpReqData[1:0]}.
IF (LockBc) THEN Cold reset: 01b. ELSE THEN Reset: 01b. ENDIF.
BIOS: IF (REG==D18F0x90) THEN 01b ELSE 11b ENDIF.
15:12 ProbeCmd: probe command buffer count.
IF (LockBc) THEN Cold reset: 0h. ELSE THEN Reset: 0h. ENDIF.
BIOS: 0h.
11:8 RspCmd: response command buffer count.
IF (LockBc) THEN Cold reset: 1h. ELSE THEN Reset: 1h. ENDIF.
BIOS: IF (REG==D18F0x90) THEN 1h ELSE 0h ENDIF.
7:5
PReq[2:0]: posted request command and data buffer count [2:0].
PReq[3:0] = {PReq[3], PReq[2:0]}. Specifies the number of posted command and posted data buffers
allocated.
IF (LockBc) THEN Cold reset: 110b. ELSE Reset: 110b. ENDIF.
BIOS: 101b.
4:0
NpReqCmd: non-posted request command buffer count.
IF (LockBc) THEN Cold reset: 09h. ELSE THEN Reset: 09h. ENDIF.
BIOS: IF (REG==D18F0x90) THEN 05h ELSE 18h ENDIF.
D18F0x[F4,D4,B4,94] Link Isochronous Channel Buffer Count
Read-write; Reset-applied. See D18F0x[F0,D0,B0,90].
Table 105: Register Mapping for D18F0x[F4,D4,B4,94]
Register
D18F0x94
D18F0x[F4,D4,B4]
Bits
Function
ONION Link
Reserved
Description
31:29 Reserved.
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28:27 IsocRspData: isochronous response data buffer count. IF (D18F0x[F0,D0,B0,90][LockBc])
THEN Cold reset: 0. ELSE THEN Reset: 0. ENDIF. BIOS: 0.
26:25 IsocNpReqData: isochronous non-posted request data buffer count. IF
(D18F0x[F0,D0,B0,90][LockBc]) THEN Cold reset: 0. ELSE THEN Reset: 0. ENDIF. BIOS: IF
(REG==D18F0x94) THEN 1 ELSE 0 ENDIF.
24:22 IsocRspCmd: isochronous response command buffer count. IF (D18F0x[F0,D0,B0,90][LockBc])
THEN Cold reset: 0. ELSE THEN Reset: 0. ENDIF. BIOS: 0.
21:19 IsocPReq: isochronous posted request command and data buffer count. IF
(D18F0x[F0,D0,B0,90][LockBc]) THEN Cold reset: 0. ELSE THEN Reset: 0. ENDIF. This specifies
the number of isochronous posted command and posted data buffers allocated.
BIOS: 0.
18:16 IsocNpReqCmd: isochronous non-posted request command buffer count. IF
(D18F0x[F0,D0,B0,90][LockBc]) THEN Cold reset: 0. ELSE THEN Reset: 0. ENDIF.
BIOS: IF (REG==D18F0x94) THEN 1 ELSE 0 ENDIF.
15:8 SecBusNum: secondary bus number. Reset: 0. Specifies the configuration-space bus number of the
IO link. When configured as a coherent link, this register has no meaning.
This field should match the corresponding D18F1x[1DC:1D0,EC:E0][BusNumBase], unless
D18F1x[1DC:1D0,EC:E0][DevCmpEn]=1, in which case this field should be 00h).
• Rule: IF (~D18F1x[1DC:1D0,EC:E0][DevCmpEn]) THEN (D18F0x[F4,D4,B4,94][SecBusNum]==D18F1x[1DC:1D0,EC:E0][BusNumBase]).
• Rule: IF (D18F1x[1DC:1D0,EC:E0][DevCmpEn]) THEN (D18F0x[F4,D4,B4,94][SecBusNum]==00h).
7:0
Reserved.
D18F0x[F8,D8,B8,98] Link Type
Table 106: Register Mapping for D18F0x[F8,D8,B8,98]
Register
D18F0x98
D18F0x[F8,D8,B8]
Bits
Function
ONION Link
Reserved
Description
31:6 Reserved.
5
4:3
PciEligible. Read-only. Reset: 1. 1=Hardware has determined this is not a HyperTransport link.
Reserved.
2
Reserved. Reset: 1.
1
Reserved. Reset: 1.
0
Reserved. Reset: 1.
D18F0x[11C,118,114,110] Link Clumping Enable
Reset: 0000_0000h. D18F0x[11C,118,114,110] are associated with the whole link if it is ganged or sublink 0 if
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it is unganged; If the node does not support a link, then the corresponding register addresses become reserved.
Table 107: Register Mapping for D18F0x[11C,118,114,110]
Register
D18F0x110
D18F0x11[C:4]
Function
ONION Link
Reserved
These registers specify how UnitIDs of upstream non-posted requests may be clumped per the link specification. The processor does not clump requests that it generates in the downstream direction.
Bits
Description
31:1 ClumpEn. Read-write. Each bit of this register corresponds to a link UnitID number. E.g., bit 2
corresponds to UnitID 02h, etc. 1=The specified UnitID is ordered in the same group as the specified
UnitID - 1. For example if this register is programmed to 0000_00C0h, then UnitIDs 7h, 6h, and 5h
are all ordered as if they are part of the same UnitID. This is used to allow more than 32 tags to be
assigned to a single stream for the purposes of ordering. Bit 1 must be set by BIOS for the ONION
link. Other bits must be set per GNB requirements. (See D0F0x98_x3A.) For ONIONPlus links,
BIOS must program this field to 7FFF_FFF9h.
0
Reserved.
D18F0x150 Link Global Retry Control
Cold reset: 0000_0000h.
Bits
Description
31:0 Reserved.
D18F0x168 Extended Link Transaction Control
Read-write.
Bits
Description
20
XcsSecPickerDstNcHt. Reset: 0. BIOS: 1. 1=Enable scheduling un-ordered responses via the secondary XCS picker to the Onion bus(es). This feature is intended for single-node systems only.
18
Reserved.
14:12 Reserved. Read-write.
D18F0x16C Link Global Extended Control
Reset: 0000_0000h.
Bits
Description
D18F0x[18C:170] Link Extended Control
These registers provide control for each link. They are mapped to the links as follows:
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Table 108: Register Mapping for D18F0x[18C:170]
Register
D18F0x170
D18F0x1[8C:74]
Function
ONION Link
Reserved
Reset: 0000_0001h.
Bits
Description
D18F0x1A0 Link Initialization Status
Table 109: Onion Definitions
Term
OnionPlus
Bits
31
Definition
OnionPlus link detected. OnionPlus = (D18F0x1A0[OnionPlusCap]).
Description
InitStatusValid: initialization status valid. Read-only; Updated-by-hardware. Reset: 0. 1=Indicates
that the rest of the information in this register is valid for all links; each link is either not connected or
the initialization is complete.
30:28 Reserved.
27:24 OnionPlusCap. Read-only; Updated-by-hardware. Reset: 0h. 1=OnionPlus capable link detected.
Bit
Description
[0]
Link 0
[1]
Link 1
[2]
Link 2
[3]
Link 3
23:4 Reserved.
3:2
InitComplete1: initialization complete for link 1. See: InitComplete0.
1:0
InitComplete0: initialization complete for link 0. Read-only; Updated-by-hardware. Reset: 00b.
Bits
Description
00b
Internal northbridge link (ONION) has not completed initialization.
10b-01b
Reserved
11b
Internal northbridge link (ONION) has completed initialization.
D18F0x1DC Core Enable
Reset: 0000_0000h.
Bits
Description
31:16 Reserved. Reserved for CpuEn expansion.
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15:1 CpuEn: core enable. Read-write. This field is used to enable each of the cores after a reset. 1=Enable
the core to start fetching and executing code from the boot vector. The most significant bit N is indicated by CpuCoreNum, as defined in section 2.4.4 [Processor Cores and Downcoring]. All bits
greater than N are reserved.
Bit
Description
[0]
Core 1 enable
[1]
Core <BIT+1> enable
[2]
Core 3 enable
[15:3]
Reserved
0
Reserved.
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3.10 Device 18h Function 1 Configuration Registers
See 3.1 [Register Descriptions and Mnemonics]. See 2.7 [Configuration Space].
D18F1x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID. Read-only.
Value: 1531h.
15:0 VendorID: vendor ID. Read-only. Value: 1022h.
D18F1x08 Class Code/Revision ID
Bits
Description
31:8 ClassCode. Read-only. Value: 060000h. Provides the host bridge class code as defined in the PCI
specification.
7:0
RevID: revision ID. Read-only. Value: 00h. Processor revision. 00h=A0.
D18F1x0C Header Type
Reset: 0080_0000h.
Bits
Description
31:0 HeaderTypeReg. Read-only. These bits are fixed at their default values. The header type field
indicates that there are multiple functions present in this device.
D18F1x[17C:140,7C:40] DRAM Base/Limit
The following sets of registers specify the DRAM address ranges:
Table 110: Register Mapping for D18F1x[17C:140,7C:40]
Function
Range 0
Reserved
Base Low
D18F1x40
D18F1x48,
D18F1x[7:5][8,0]
Limit Low
D18F1x44
D18F1x4C,
D18F1x[7:5][C,4]
Base High
Limit High
D18F1x140
D18F1x144
D18F1x148,
D18F1x14C,
D18F1x1[7:5][8,0] D18F1x1[7:5][C,4]
Transaction addresses that are within the specified base/limit range are routed to the DstNode. See 2.8.2 [NB
Routing].
DRAM mapping rules:
F1x0XX registers provide the low address bits. F1x1XX registers are reserved.
• Transaction addresses are within the defined range if:
{DramBase[39:24], 00_0000h} <= address[39:0] <= {DramLimit[39:24], FF_FFFFh}.
• DRAM regions must not overlap each other.
• Accesses to addresses that map to both DRAM, as specified by the DRAM base and limit registers (F1x[1,
0][7C:40]), and MMIO, as specified by D18F1x[2CC:2A0,1CC:180,BC:80], are routed to MMIO only.
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• Programming of the DRAM address maps must be consistent with the Memory-Type Range Registers
(MTRRs) and the top of memory registers, MSRC001_001A and MSRC001_001D. CPU accesses only hit
within the DRAM address maps if the corresponding MTRR is of type DRAM. Accesses from IO links are
routed based on the DRAM base and limit registers (F1x[1, 0][7C:40]) only.
• The appropriate RE or WE bit(s) must be set. When initializing a base/limit pair, the BIOS must write the
[limit] register before either the RE or WE bit is set. When changing a base/limit pair that is already enabled,
the BIOS should clear RE and WE before changing the address range.
• See 2.8.2.1.1 [DRAM and MMIO Memory Space].
When memory hoisting is enabled in a node via D18F1x2[1,0][8,0][LgcyMmioHoleEn], the corresponding
BaseAddr/LimitAddr should be configured to account for the memory hoisted above the hole. See 2.9.10
[Memory Hoisting].
D18F1x[7:4][8,0] DRAM Base Low
IF (D18F2x118[LockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. IF (BootFromDRAM &&
REG==D18F1x40) THEN Cold reset: 0000_0003h. ELSE Reset: 0000_0000h. ENDIF.
Table 111: Register Mapping for D18F1x[7:4][8,0]
Register
D18F1x40
D18F1x48
D18F1x[7:5][8,0]
Bits
Function
Range 0
Reserved
Reserved
Description
31:16 DramBase[39:24]: DRAM base address register bits[39:24].
15:2 Reserved.
1
WE: write enable. 1=Writes to this address range are enabled.
0
RE: read enable. 1=Reads to this address range are enabled.
D18F1x[7:4][C,4] DRAM Limit Low
IF (D18F2x118[LockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF.
Table 112: Register Mapping for D18F1x[7:4][C,4]
Register
D18F1x44
D18F1x4C
D18F1x[7:5][C,4]
Bits
Function
Range 0
Reserved
Reserved
Description
31:16 DramLimit[39:24]: DRAM limit address register bits[39:24]. IF (BootFromDRAM &&
REG==D18F1x44) THEN Cold reset: 01FFh. ELSE Reset: FCFFh. ENDIF.
15:11 Reserved.
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10:8 Reserved.
7:3
Reserved.
2:0
DstNode: destination Node ID. Reset: 000b. Specifies the node that a packet is routed to if it is
within the address range.
D18F1x[2CC:2A0,1CC:180,BC:80] MMIO Base/Limit
These registers, The memory mapped IO base and limit registers D18F1x[2CC:2A0,1CC:180,BC:80] specify
the mapping from memory addresses to the corresponding node and IO link for MMIO transactions. Address
ranges are specified by upto 16 sets of base/limit registers.
Table 113: Register Mapping for D18F1x[2CC:2A0,1CC:180,BC:80]
Function
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
Reserved
MMIO Base Low
D18F1x80
D18F1x88
D18F1x90
D18F1x98
D18F1xA0
D18F1xA8
D18F1xB0
D18F1xB8
D18F1x1A0
D18F1x1A8
D18F1x1B0
D18F1x1B8
D18F1x2[B8,B0,A8,
A0]
MMIO Limit Low
D18F1x84
D18F1x8C
D18F1x94
D18F1x9C
D18F1xA4
D18F1xAC
D18F1xB4
D18F1xBC
D18F1x1A4
D18F1x1AC
D18F1x1B4
D18F1x1BC
D18F1x2[BC,B4,AC,
A4]
MMIO Base/Limit High
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Transaction addresses that are within the specified base/limit range are routed to the node specified by
DstNode and the link specified by DstLink. See 2.8.2 [NB Routing].
MMIO mapping rules:
• Transaction addresses are within the defined range if:
{MMIOBase[39:16], 0000h} <= address[39:0] <= {MMIOLimit[39:16], FFFFh}.
• MMIO regions must not overlap each other.
• Accesses to addresses that map to both DRAM, as specified by the DRAM base and limit registers (see
D18F1x[17C:140,7C:40]), and MMIO, as specified by the memory mapped IO base and limit registers
(F1x[BC:80]), are routed to MMIO only.
• Programming of the MMIO address maps must be consistent with the Memory-Type Range Registers
(MTRRs) and the top of memory registers, MSRC001_001A and MSRC001_001D. CPU accesses only hit
within the MMIO address maps if the corresponding MTRR is of type IO. Accesses from IO links are routed
based on D18F1x[2CC:2A0,1CC:180,BC:80].
• The appropriate RE or WE bit(s) must be set. When initializing a base/limit pair, the BIOS must write the
limit register before either the RE or WE bit is set. When changing a base/limit pair that is already enabled,
the BIOS should clear RE and WE before changing the address range.
• Scenarios in which the address space of multiple MMIO ranges target the same IO device is supported.
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• See 2.8.2.1.1 [DRAM and MMIO Memory Space].
D18F1x[2B:1A,B:8][8,0] MMIO Base Low
Table 114: Register Mapping for D18F1x[2B:1A,B:8][8,0]
Register
D18F1x80
D18F1x88
D18F1x90
D18F1x98
D18F1xA0
D18F1xA8
D18F1xB0
D18F1xB8
D18F1x1A0
D18F1x1A8
D18F1x1B0
D18F1x1B8
D18F1x2[B:A][8,0]
Bits
Function
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
Reserved
Description
31:8 MMIOBase[39:16]: MMIO base address register bits[39:16]. Read-write. Reset: 0.
7:4
Reserved.
3
Lock. Read-write. Reset: 0. 1=the memory mapped IO base and limit registers
(D18F1x[2CC:2A0,1CC:180,BC:80]) are read-only (including this bit). WE or RE in this register
must be set in order for this to take effect.
1
WE: write enable. Read-write. Reset: 0. 1=Writes to this address range are enabled.
0
RE: read enable. Read-write. Reset: 0. 1=Reads to this address range are enabled.
D18F1x[2B:1A,B:8][C,4] MMIO Limit Low
Table 115: Register Mapping for D18F1x[2B:1A,B:8][C,4]
Register
D18F1x84
D18F1x8C
D18F1x94
D18F1x9C
D18F1xA4
D18F1xAC
D18F1xB4
Function
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
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Table 115: Register Mapping for D18F1x[2B:1A,B:8][C,4]
D18F1xBC
D18F1x1A4
D18F1x1AC
D18F1x1B4
D18F1x1BC
D18F1x2[BC,B4,AC,
A4]
Bits
Range 7
Range 8
Range 9
Range 10
Range 11
Reserved.
Description
31:8 MMIOLimit[39:16]: MMIO limit address register bits[39:16]. Read-write. Reset: 0.
7
NP: non-posted. Read-write. Reset: 0. 1=CPU write requests to this MMIO range are passed through
the non-posted channel. This may be used to force writes to be non-posted for MMIO regions which
map to the legacy ISA/LPC bus, or in conjunction with D18F0x68[DsNpReqLmt] in order to allow
downstream CPU requests to be counted and thereby limited to a specified number. This latter use of
the NP bit may be used to avoid loop deadlock scenarios in systems that implement a region in an IO
device that reflects downstream accesses back upstream. See the link summary of deadlock scenarios
for more information. 0=CPU writes to this MMIO range use the posted channel. This bit does not
affect requests that come from IO links (the virtual channel of the request is specified by the IO
request).
If two MMIO ranges target the same IO device and the NP bit is set differently in both ranges, unexpected transaction ordering effects are possible. In particular, using PCI- and IO-link-defined producer-consumer semantics, if a producer (e.g., the processor) writes data using a non-posted MMIO
range followed by a flag to a posted MMIO range, then it is possible for the device to see the flag
updated before the data is updated.
6
DstSubLink: destination sublink. Read-write. Reset: 0. When a link is unganged, this bit specifies
the destination sublink of the link specified by the memory mapped IO base and limit registers
F1x[BC:80][DstLink]. 0=The destination link is sublink 0. 1=The destination link is sublink 1. If the
link is ganged, then this bit must be low.
5:4
DstLink: destination link ID. Read-write. Reset: 0. For transactions within this MMIO range, this
field specifies the destination IO link number of the destination node.
Description
Bits
00b
Link 0
01b
Link 1
10b
Link 2
11b
Link 3
3
2:0
Reserved.
DstNode: destination node ID bits. Read-write. Reset: 0. For transactions within this MMIO range,
this field specifies the destination node ID.
D18F1x[DC:C0] IO-Space Base/Limit
The IO-space base and limit registers, D18F1x[DC:C0], specify the mapping from IO addresses to the
corresponding node and IO link for transactions resulting from x86-defined IN and OUT instructions. IO
address ranges are specified by upto 8 sets of base/limit registers. The first set is F1xC0 and F1xC4, the second
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set is F1xC8 and F1xCC, and so forth. Transaction addresses that are within the specified base/limit range are
routed to the node specified by DstNode and the link specified by DstLink. See 2.8.2 [NB Routing].
IO mapping rules:
• IO-space transaction addresses are within the defined range if:
{IOBase[24:12], 000h} <= address <= {IOLimit[24:12], FFFh} and as specified by the IE bit; or
if the address is in the range specified by the VE bits.
• IO regions must not overlap each other.
• The appropriate RE or WE bit(s) must be set.
• See 2.8.2.1.2 [IO Space].
D18F1x[1F:1E,D:C][8,0] IO-Space Base
Table 116: Register Mapping for D18F1x[1F:1E,D:C][8,0]
Register
D18F1xC0
D18F1xC8
D18F1xD0
D18F1xD8
D18F1x1[F:E][8,0]
Bits
Function
Range 0
Range 1
Range 2
Range 3
Reserved
Description
31:25 Reserved.
24:12 IOBase[24:12]: IO base address register bits[24:12]. Read-write. Reset: 0.
11:6 Reserved.
5
IE: ISA enable. Read-write. Reset: 0. 1=The IO-space address window is limited to the first 256 B of
each 1 KB block specified; this only applies to the first 64 KB of IO space. 0=The PCI IO window is
not limited in this way.
4
VE: VGA enable. Read-write. Reset: 0. 1=Include IO-space transactions targeting the VGAcompatible address space within the IO-space window of this base/limit pair. These include IO
accesses in which address bits[9:0] range from 3B0h to 3BBh or 3C0h to 3DFh (address bits[15:10]
are not decoded); this only applies to the first 64 KB of IO space; i.e., address bits[24:16] must be
low). 0=IO-space transactions targeting VGA-compatible address ranges are not added to the IOspace window. This bit should only ever be set in one register. The MMIO range associated with the
VGA enable bit in the PCI specification is NOT included in the VE bit definition; to map this range to
an IO link, see D18F1xF4 [VGA Enable]. When D18F1xF4[VE] is set, the state of this bit is ignored.
3:2
Reserved.
1
WE: write enable. Read-write. Reset: 0. 1=Writes to this IO-space address range are enabled.
0
RE: read enable. Read-write. Reset: 0. 1=Reads to this IO-space address range are enabled.
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D18F1x[1F:1E,D:C][C,4] IO-Space Limit
Table 117: Register Mapping for D18F1x[1F:1E,D:C][C,4]
Register
D18F1xC4
D18F1xCC
D18F1xD4
D18F1xDC
D18F1x1[F:E][C,4]
Bits
Function
Range 0
Range 1
Range 2
Range 3
Reserved
Description
31:25 Reserved.
24:12 IOLimit[24:12]: IO limit address register bits[24:12]. Read-write. Reset: 0.
11:7 Reserved.
6
DstSubLink: destination sublink. Read-write. Reset: 0. When a link is unganged, this bit specifies
the destination sublink of the link specified by F1x[DC:C0][DstLink]. 0=The destination link is
sublink 0. 1=The destination link is sublink 1. If the link is ganged, then this bit must be low.
5:4
DstLink: destination link ID. Read-write. Reset: 0. For transactions within this IO-space range, this
field specifies the destination IO link number of the destination node.
Description
Bits
00b
Link 0
01b
Link 1
10b
Link 2
11b
Link 3
3
2:0
Reserved.
DstNode: destination node ID bits. Read-write. Reset: 0. For transactions within this IO-space
range, this field specifies the destination node ID.
D18F1x[1DC:1D0,EC:E0] Configuration Map
D18F1x[1DC:1D0,EC:E0] specify the mapping from configuration address to the corresponding node and IO
link. Configuration address ranges are specified by upto 8 pairs of base/limit registers. Transaction addresses
that are within the specified base/limit range are routed to the node specified by DstNode and the link specified
by DstLink. See 2.8.2 [NB Routing].
Table 118: Register Mapping for D18F1x[1DC:1D0,EC:E0]
Register
D18F1xE0
D18F1xE4
D18F1xE8
D18F1xEC
D18F1x1[DC:D0]
Function
Range 0
Range 1
Range 2
Range 3
Reserved
Configuration space mapping rules:
• Configuration addresses (to “BusNo” and “Device” as specified by IOCF8 [IO-Space Configuration
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Address] in the case of IO accesses or 2.7 [Configuration Space] in the case of MMIO accesses) are
within the defined range if:
( {BusNumBase[7:0]} <= BusNo<= {BusNumLimit[7:0]} ) & (DevCmpEn==0); or
( {BusNumBase[4:0]} <= Device <= {BusNumLimit[4:0]} ) & (DevCmpEn==1) & (BusNo== 00h).
• Configuration regions must not overlap each other.
• The appropriate RE or WE bit(s) must be set.
• See 2.8.2.1.3 [Configuration Space].
Bits
Description
31:24 BusNumLimit[7:0]: bus number limit bits[7:0]. Read-write. Reset: 0.
23:16 BusNumBase[7:0]: bus number base bits[7:0]. Read-write. Reset: 0.
2
DevCmpEn: device number compare mode enable. Read-write. Reset: 0. 1=A device number
range rather than a bus number range is used to specify the configuration-space window (see above).
This is used to enable multiple IO links to be configured as Bus 0.
1
WE: write enable. Read-write. Reset: 0. 1=Writes to this configuration-space address range are
enabled.
0
RE: read enable. Read-write. Reset: 0. 1=Reads to this configuration-space address range are
enabled.
D18F1xF0 DRAM Hole Address
IF (D18F2x118[LockDramCfg] && ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Readwrite. ENDIF. Same-for-all. Reset: 0000_0000h. See 2.9.10 [Memory Hoisting].
Bits
Description
31:24 DramHoleBase[31:24]: DRAM hole base address. Specifies the base address of the IO hole, below
the 4GB address level, that is used in memory hoisting. Normally, DramHoleBase >=
MSRC001_001A[TOM[31:24]].
23:16 Reserved.
15:7 DramHoleOffset[31:23]: DRAM hole offset address. When D18F1x2[1,0][8,0][LgcyMmioHoleEn]==1, this offset is subtracted from the physical address of certain accesses in forming the normalized address.
6:3
Reserved.
2
Reserved. Read-write.
1
DramMemHoistValid: dram memory hoist valid. 1=Memory hoisting for the address range is
enabled. 0=Memory hoisting is not enabled. This bit should be set if any D18F1x2[1,0][8,0][LgcyMmioHoleEn]==1 or DramHoleBase != 0.
0
DramHoleValid: dram hole valid. 1=Memory hoisting is enabled in the node. 0=Memory hoisting is
not enabled. This bit should be set in the node that owns the DRAM address space that is hoisted
above the 4 GB address level. See DramHoleBase.
D18F1xF4 VGA Enable
Reset: 0000_0000h. All these bits are read-write unless Lock is set.
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Description
31:15 Reserved.
14
DstSubLink: destination sublink. Read-write. When a link is unganged, this bit specifies the
destination sublink of the link specified by D18F1xF4[DstLink]. 0=The destination link is sublink 0.
1=The destination link is sublink 1. If the link is ganged, then this bit must be low.
13:12 DstLink: destination link ID. Read-write. For transactions within the D18F1xF4[VE]-defined
ranges, this field specifies the destination IO link number of the destination node.
Bits
Description
00b
Link 0
01b
Link 1
10b
Link 2
11b
Link 3
11:7 Reserved.
6:4
DstNode: destination node ID. Read-write. For transactions within the D18F1xF4[VE]-defined
range, this field specifies the destination node ID.
3
Lock. Read-write. 1=All the bits in this register (D18F1xF4) are read-only (including this bit).
1
NP: non-posted. Read-write. 1=CPU write requests to the D18F1xF4[VE]-defined MMIO range are
passed through the non-posted channel. 0=CPU writes may be posted.
0
VE: VGA enable. Read-write. 1=Transactions targeting the VGA-compatible address space are
routed and controlled as specified by this register. The VGA-compatible address space is: (1) the
MMIO range A_0000h through B_FFFFh; (2) IO-space accesses in which address bits[9:0] range
from 3B0h to 3BBh or 3C0h to 3DFh (address bits[15:10] are not decoded; this only applies to the
first 64 KB of IO space; i.e., address bits[24:16] must be low). 0=Transactions targeting the VGAcompatible address space are not affected by the state of this register. When this bit is set, the state of
D18F1xF4[VE] is ignored.
D18F1x10C DCT Configuration Select
Reset: 0000_0000h.
Bits
Description
5:4
NbPsSel: NB P-state configuration select. Read-write. Specifies the set of DCT Pstate registers to
which software configuration accesses are routed.
Bits
Description
00b
NB P-state 0
01b
NB P-state 1
10b
NB P-state 2
11b
NB P-state 3
The following registers must be programmed for each NB P-state enabled by
D18F5x16[C:0][NbPstateEn]:
• D18F2x210_dct[0]_nbp[3:0][MaxRdLatency, DataTxFifoWrDly].
• D18F2x210_dct[0]_nbp[3:0][RdPtrInit].
This field is ignored on accesses to registers other than listed above.
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MemPsSel: Memory P-state configuration select. Read-write. Specifies the set of DCT controller
registers to which software configuration accesses are routed. This register works independently of
NbPsSel. 0=Memory P-state 0. 1=Memory P-state 1. See 2.5.7.1 [Memory P-states] and 2.9.3 [DCT
Configuration Registers]. The following registers must be programmed for each memory P-state
enabled by D18F5x16[C:0][MemPstate]:
• D18F2x2E8_dct[0]_mp[1:0]
• D18F2x2EC_dct[0]_mp[1:0]
The _mp[D18F2x2E0_dct[0][CurMemPstate]] SPR state is used for MRS during h/w dram
init.
2:0
DctCfgSel: DRAM controller configuration select. Read-write. Specifies DCT controller to which
software configuration accesses are routed. See 2.9.3 [DCT Configuration Registers].
Bits
Description
000b
DCT 0
111b-001b
Reserved
D18F1x120 DRAM Base System Address
IF (D18F2x118[LockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. Cold reset: 0000_0000h.
D18F1x120 and D18F1x124 are required to specify the base and limit system address range of the DRAM
connected to the local node.
DRAM accesses to the local node with physical address Addr[47:0] that are within the following range are
directed to the DCTs:
{DramBaseAddr[47:27], 000_0000h} <= Addr[47:0] <= {DramLimitAddr[47:27], 7FF_FFFFh};
DRAM accesses to the local node that are outside of this range are master aborted.
The address of the DRAM transaction is normalized before passing it to the DCTs by subtracting
DramBaseAddr.
This range is also used to specify the range of DRAM covered by the scrubber (see D18F3x58 and
D18F3x5C).
Bits
Description
31:21 Reserved. Read-write.
20:0 DramBaseAddr[47:27].
D18F1x124 DRAM Limit System Address
IF (D18F2x118[LockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. See D18F1x120 [DRAM Base
System Address].
Bits
Description
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23:21 Reserved. Read-write.
20:0 DramLimitAddr[47:27]. IF (BootFromDRAM) THEN Cold reset: 00_003Fh. ELSE Cold reset:
1F_FFFFh. ENDIF.
D18F1x2[1C:00] DRAM Controller Base/Limit
The DRAM controller base and limit registers define a DRAM controller address range and specify the
mapping of physical DRAM addresses to a DCT as selected by DctSel or DctIntLvEn. The following
base/limit register pairs specify the address ranges:
Table 119: Register Mapping for D18F1x2[1C:00]
Function
Range 0
Reserved
Base Address
D18F1x200
D18F1x208,
D18F1x21[8,0]
Limit Address
D18F1x204
D18F1x20C,
D18F1x21[C,4]
BIOS should observe the following DCT configuration requirements:
• DRAM addresses are within the defined range if:
{DctBaseAddr[39:27], 000b, 00_0000h} <= address[39:0] <= {DctLimitAddr[39:27], 111b, FF_FFFFh}.
• DCT base/limit address ranges must not overlap each other.
• A maximum of two address ranges may be mapped to a single DCT.
Hoisting. When memory hoisting is enabled viaLegacyMmioHoleEn, the corresponding
DctBaseAddr/DctLimitAddr should be configured to account for the memory hoisted above the hole. A
contiguous memory hole should only be mapped by one DctBaseAddr/DctLimitAddr pair. See 2.9.10 [Memory Hoisting].
D18F1x2[1,0][8,0] DRAM Controller Base
IF (D18F2x118[LockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. Reset: 0000_0000h.
Table 120: Register Mapping for D18F1x2[1,0][8,0]
Register
D18F1x200
D18F1x208
D18F1x21[8,0]
Bits
Function
Range 0
Reserved
Reserved
Description
31:24 Reserved. Read-write.
23:11 DctBaseAddr[39:27]: DRAM controller base address [39:27]. Read-write. Specifies the base
physical address bits for this address range.
10:7 Reserved.
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DctSel: DRAM controller select. Read-write. Specifies the DCT mapped to this address range.
Bits
000b
111b-010b
Definition
DCT 0
Reserved
3
Reserved. Read-write.
2
Reserved. Read-write.
1
LgcyMmioHoleEn: legacy mmio hole enable. Read-write. BIOS: See 2.9.10 [Memory Hoisting].
1=Enable memory hoisting for this address range. BIOS sets this bit for an address range that spans
the 4GB boundary and contains a hole for addresses used by MMIO. 0=Memory hoisting is not
enabled.
0
DctAddrVal: DRAM controller address valid. Read-write. 1=Specifies this address range is valid
and enabled. 0=This address range is not enabled.
D18F1x2[1,0][C,4] DRAM Controller Limit
IF (D18F2x118[LockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. Reset: 0000_0000h.
Table 121: Register Mapping for D18F1x2[1,0][C,4]
Register
D18F1x204
D18F1x20C
D18F1x21[C,4]
Bits
Function
Range 0
Reserved
Reserved
Description
31:24 Reserved. Read-write.
23:11 DctLimitAddr[39:27]: DRAM controller limit address bits [39:27]. Read-write. Specifies the
limit physical address bits for this address range.
10:4 Reserved.
3:0
Reserved. Read-write.
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3.11 Device 18h Function 2 Configuration Registers
See 3.1 [Register Descriptions and Mnemonics]. See 2.7 [Configuration Space].
D18F2x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID. Read-only.
Value: 1532h.
15:0 VendorID: vendor ID. Read-only. Value: 1022h.
D18F2x08 Class Code/Revision ID
Reset: 0600_0000h.
Bits
Description
31:8 ClassCode. Read-only. Provides the host bridge class code as defined in the PCI specification.
7:0
RevID: revision ID. Read-only.
D18F2x0C Header Type
Reset: 0080_0000h.
Bits
Description
31:0 HeaderTypeReg. Read-only. These bits are fixed at their default values. The header type field indicates that there multiple functions present in this device.
D18F2x[5C:40]_dct[0] DRAM CS Base Address
IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Readwrite. ENDIF. IF (BootFromDRAM && REG==D18F2x40_dct[0]) THEN Cold reset: 0000_0001h. ELSE
Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT Configuration Registers].
These registers along with D18F2x[6C:60]_dct[0] [DRAM CS Mask], translate DRAM request addresses (to a
DRAM controller) into DRAM chip selects. Supported DIMM sizes are specified in D18F2x80_dct[0]
[DRAM Bank Address Mapping]. For more information on the DRAM controllers, see 2.9 [DRAM Controllers (DCTs)].
For each chip select, there is a DRAM CS Base Address register. For each CS pair there is a DRAM CS Mask
Register. For each CS pair, an even CS must be populated if the odd CS is populated.
Table 122: DIMM, Chip Select, and Register Mapping
Base Address Registers
D18F2x40_dct[x]
D18F2x44_dct[x]
Mask
Register
F2x60
Logical
DIMM
0
Chip Select1
BP_MEMCS[x]_L[0]
BP_MEMCS[x]_L[1]
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Table 122: DIMM, Chip Select, and Register Mapping
Base Address Registers
Mask
Register
F2x64
Logical
DIMM
1
D18F2x48_dct[x]
D18F2x4C_dct[x]
D18F2x[5C:50]_dct[x]
F2x6[C,8]
1. See 2.9.4 [DDR Pad to Processor Pin Mapping]
Chip Select1
BP_MEMCS[x]_L[2]
BP_MEMCS[x]_L[3]
Reserved
The DRAM controller operates on the normalized physical address of the DRAM request. The normalized
physical address includes all of the address bits that are supported by a DRAM controller. See 2.8 [Northbridge
(NB)].
Each base address register specifies the starting normalized address of the block of memory associated with the
chip select. Each mask register specifies the additional address bits that are consumed by the block of memory
associated with the chip selects. If both chip selects of a DIMM are used, they must be the same size; in this
case, a single mask register covers the address space consumed by both chip selects.
Lower-order address bits are provided in the base address and mask registers, as well. These allow memory to
be interleaved between chip selects, such that contiguous physical addresses map to the same DRAM page of
multiple chip selects. See 2.9.9.1 [Chip Select Interleaving]. The hardware supports the use of lower-order
address bits to interleave chip selects if (1) the each chip select of the memory system spans the same amount
of memory and (2) the number of chip selects of the memory system is a power of two.
System BIOS is required to assign the largest DIMM chip-select range to the lowest normalized address of the
DRAM controller. As addresses increase, the chip-select size is required to remain constant or decrease. This is
necessary to keep DIMM chip-select banks on aligned address boundaries, regardless as to the amount of
address space covered by each chip select.
For each normalized address for requests that enters a DRAM controller, a ChipSelect[i] is asserted if:
CSEnable[i] &
( {(InputAddr[38:27]
& ~AddrMask[i][38:27]),
(InputAddr[21:11]
& ~AddrMask[i][21:11])} ==
{(BaseAddr[i][38:27] & ~AddrMask[i][38:27]),
(BaseAddr[i][21:11] & ~AddrMask[i][21:11])} );
Bits
31
Description
Reserved.
30:19 BaseAddr[38:27]: normalized physical base address bits [38:27].
18:16 Reserved.
15:5 BaseAddr[21:11]: normalized physical base address bits [21:11].
4
Reserved.
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3
OnDimmMirror: on-DIMM mirroring (ODM) enabled. 1=Address and bank bits are swapped by
hardware for MRS commands sent to this chip select. This mode accounts for routing on the DIMM.
Hardware bit swapping does not occur for commands sent via D18F2x7C_dct[0][SendMrsCmd]
when D18F2x7C_dct[0][EnDramInit] = 0. This bit is expected to be set for the odd numbered rank of
unbuffered DDR3 DIMMs if SPD byte 63 indicates that address mapping is mirrored.
The following bits are swapped when enabled:
• BA0 and BA1.
• A3 and A4.
• A5 and A6.
• A7 and A8.
2
TestFail: memory test failed. Set by BIOS to indicate that a rank is present but has failed memory
training or a memory consistency test, indicating that the memory is bad. BIOS should treat
CSEnable=1 and TestFail=1 as mutually exclusive.
1
Reserved. Read-write.
0
CSEnable: chip select enable.
D18F2x[6C:60]_dct[0] DRAM CS Mask
IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Readwrite. ENDIF. IF (BootFromDRAM && (REG==D18F2x60_dct[0])) THEN Cold reset: 0038_FFE0h. ELSE
Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT Configuration Registers]. See D18F2x[5C:40]_dct[0].
Bits
31
Description
Reserved.
30:19 AddrMask[38:27]: normalized physical address mask bits [38:27].
18:16 Reserved.
15:5 AddrMask[21:11]: normalized physical address mask bits [21:11].
4
Reserved.
3:2
Reserved.
1:0
Reserved. Read-write.
D18F2x78_dct[0] DRAM Control
See 2.9.3 [DCT Configuration Registers].
Bits
Description
30:18 Reserved.
17
AddrCmdTriEn: address command tristate enable. Read-write. IF (BootFromDRAM) THEN
Cold reset: 0. ELSE Reset: 0. ENDIF. BIOS: See 2.9.7.7. 1=Tristate the address, command, and bank
buses when a Deselect command is issued.
15
Reserved. Read-write.
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14:11 Reserved.
10:0 Reserved.
D18F2x7C_dct[0] DRAM Initialization
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.7.8 [DRAM Device and Controller Initialization].
BIOS can directly control the DRAM initialization sequence using this register. To do so, BIOS sets EnDramInit to start DRAM initialization. BIOS should then complete the initialization sequence specified in the appropriate JEDEC specification. After completing the sequence, BIOS clears EnDramInit to complete DRAM
initialization. BIOS should not assert LDTSTOP_L while EnDramInit is set. Setting more than one of the command bits in this register (SendControlWord, SendMrsCmd, and SendAutoRefresh) at a time results in undefined behavior.
Bits
Description
31
EnDramInit: enable DRAM initialization. Read-write. 1=Place the DRAM controller in the BIOScontrolled DRAM initialization mode. The DCT deasserts CKE when this bit is set. BIOS must wait
until D18F2x98_dct[0][DctAccessDone] = 1 before programming AssertCke=1 and
DeassertMemRstX=1. BIOS must clear this bit after DRAM initialization is complete. BIOS must not
set this bit on a DCT with no attached DIMMs.
30
Reserved. Read; write-1-only; cleared-by-hardware.
29
SendZQCmd: send ZQ command. Read; write-1-only; cleared-by-hardware. 1=The DCT sends the
ZQ calibration command with either all even or all odd chip selects active. The first command targets
even chip selects. Subsequent commands alternate between even and odd chip selects. This bit is
cleared by the hardware after the command completes. This bit is valid only when EnDramInit=1. Rtl
hardcoded to send a ZQCL command, MrsAddress has no effect.
28
AssertCke: assert CKE. Read-write; S3-check-exclude. Setting this bit causes the DCT to assert the
CKE pins. This bit cannot be used to deassert the CKE pins.
27
DeassertMemRstX: deassert memory reset. Read-write; S3-check-exclude. Setting this bit causes
the DCT to deassert the memory reset. This bit cannot be used to assert the memory reset pin.
26
SendMrsCmd: send MRS command. Read; write-1-only; cleared-by-hardware.
1=The DCT sends the MRS commands defined by the MrsChipSel, MrsAddress, and MrsBank fields
of this register. This bit is cleared by hardware after the command completes. Reserved if
D18F2x78_dct[0][AddrCmdTriEn]=1.
25
SendAutoRefresh: send auto refresh command. Read; write-1-only; cleared-by-hardware. 1=The
DCT sends an auto refresh command. This bit is cleared by hardware after the command completes.
24
Reserved. Read-write.
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23:21 MrsChipSel: MRS command chip select. Read-write; S3-check-exclude. Specifies which DRAM
chip select is used for MRS commands. Defined only if (~EnDramInit | ~D18F2x90_dct[0][UnbuffDimm]); otherwise MRS commands are sent to all chip selects.
Description
Bits
000b
MRS command is sent to CS0
110b-001b
MRS command is sent to CS<MrsChipSel>
111b
MRS command is sent to CS7
20:18 MrsBank[2:0]: bank address for MRS commands. Read-write; S3-check-exclude. Specifies the
data driven on the DRAM bank pins for MRS commands.
17:0 MrsAddress[17:0]: address for MRS commands. Read-write; S3-check-exclude. Specifies the data
driven on the DRAM address pins for MRS commands.
D18F2x80_dct[0] DRAM Bank Address Mapping
IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Readwrite. ENDIF. IF (BootFromDRAM) THEN Cold reset: 0000_000Ah. ELSE Reset: 0000_0000h. ENDIF. See
2.9.3 [DCT Configuration Registers]. These fields specify DIMM configuration information. These fields are
required to be programmed based on the DRAM device size and with information of the DIMM. Table 123
shows the bit numbers for each position.
Bits
Description
31:16 Reserved.
15:8 Reserved. Read-write.
7:4
DimmAddrMap1: DIMM 1 address map.
3:0
DimmAddrMap0: DIMM 0 address map.
Table 123: DDR3 DRAM Address Mapping
Device size,
Bits
CS Size
0000b
width
Bank
2
1
Address
0
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row
Col
0001b 256MB
512Mb, x16
15
14
13
Row
x
x
x
x
17
16
27
26
25
24
23
22
21 20
19
18
0010b 512MB
512Mb, x8
Col
x
x
x
x
x
AP 12
11
10
9
8
7
6
5
4
3
15
14
13
Row
x
x
x
17
16
28
27
26
25
24
23
22
21
20
19
18
1Gb, x16
2Gb, x32
Col
x
x
x
x
x
AP 12
11
10
9
8
7
6
5
4
3
0011b
Reserved
Row
0100b
Reserved
Row
Row
x
x
17
16
29
28
27
26
25
24
23
22
21 20
19
18
Col
x
x
x
x
x
AP 12
11
10
9
8
7
6
4
3
1Gb, x32
Col
Col
0101b
1GB
1Gb, x8
2Gb, x16
4Gb, x32
0110b
15
14
13
5
Reserved
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Table 123: DDR3 DRAM Address Mapping
Device size,
Bits
CS Size
0111b
2GB
Bank
Address
width
2
1
0
2Gb, x8
15
14
13
4Gb, x16
8Gb, x32
1000b
Reserved
1001b
Reserved
1010b
4GB
4Gb, x8
15
14
13
8Gb, x16
1011b
1111b1100b
8GB
8Gb, x8
16
15
14
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row
x
17
16
30
Col
x
x
x
x
29
28
27
26
25
24
23
22
21 20
19
18
x
AP 12
11
10
9
8
7
6
5
4
3
Row
17
16
31
30
Col
x
x
x
x
29
28
27
26
25
24
23
22
21
20
19
18
x
AP 12
11
10
9
8
7
6
5
4
Row
17
32
31
3
30
29
28
27
26
25
24
23
22
21 20
19
18
Col
x
x
x
x
13 AP 12
11
10
9
8
7
6
4
3
5
Reserved
D18F2x84_dct[0] DRAM MRS
IF (BootFromDRAM) THEN Cold reset: 0000_0005h. ELSE Reset: 0000_0005h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. The fields of this register are applied to the MRS during HW DRAM initialization.
Bits
Description
31:24 Reserved.
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PchgPDModeSel: precharge power down mode select. Read-write. BIOS: 1. Specifies how a chip
select enters and exits power down mode. This mode is enabled by
D18F2x94_dct[0][PowerDownEn] and its behavior varies based on the setting of
D18F2x94_dct[0][PowerDownMode] and MR0[PPD] in D18F2x2E8_dct[0]_mp[1:0][MxMr0]. This
register is applied to the MRS during HW DRAM initialization.
PowerDownMode PchgPDModeSel MR0[PPD] Description
0b
0b
0b
Full channel slow exit (DLL off)
0b
0b
1b
Full channel fast exit (DLL on)
0b
1b
xb
Full channel dynamic fast exit/slow exit
1b
0b
0b
Reserved (Full channel slow exit)
1b
0b
1b
Partial channel fast exit (DLL on)
1b
1b
xb
Partial channel dynamic fast exit/slow exit
See D18F2x248_dct[0]_mp[1:0][Txpdll, Txp]. In dynamic fast exit/slow exit power down mode, the
DCT dynamically issues MRS command(s) to the DRAM to specify the powerdown mode; the DCT
specifies fast exit mode when chip selects on one of the two CKEs has recently been active; it specifies deep power down when chip selects on all CKEs have been idle. PchgPDModeSel=0 &&
MR0[PPD]=1 fast exit modes are reserved if S3 is also supported .
1:0
BurstCtrl: burst length control. Read-write. BIOS: 01b. Specifies the number of sequential beats of
DQ related to one read or write command. Requests from the processor are always 64-byte-length.
Requests generated by D18F2x250_dct[0] are always 64-byte-length. Requests from GMC may be
32-byte or 64-byte-length. Software must ensure that GMC requests are disabled to configure the
DCT and DRAMs for 8-beat burst length (e.g. during training). If this mode is changed, software
must issue a mode-register set command to MR0 of the DRAMs to place them in the same mode.
Description
Bits
00b
8 beats
01b
Dynamic 4 or 8 beats
11b-10b
Reserved
D18F2x88_dct[0] DRAM Timing Low
IF (BootFromDRAM) THEN Cold reset: 3E00_0000h. ELSE Reset: 3F00_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:30 Reserved.
29:24 MemClkDis: MEMCLK disable. Read-write. 1=Disable the MEMCLK. 0=Enable MEMCLK. All
enabled clocks should be 0; all no-connect and unused clocks should be 1.
Bit
Pad
[0]
BP_MEMCLK_H[0]
[1]
BP_MEMCLK_H[1]
[2]
BP_MEMCLK_H[2]
[3]
BP_MEMCLK_H[3]
[4]
BP_MEMCLK_H[4]
[5]
BP_MEMCLK_H[5]
23:0 Reserved.
D18F2x8C_dct[0] DRAM Timing High
IF (BootFromDRAM) THEN Cold reset: 0003_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
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Configuration Registers].
Bits
Description
31:19 Reserved.
18
DisAutoRefresh: disable automatic refresh. Read-write. BIOS: See 2.9.7.7. 1=Automatic refresh is
disabled.
17:16 Tref: refresh rate. Read-write. BIOS: See 2.9.7.5. This specifies the average time between refresh
requests to all DRAM devices.
Bits
Description
00b
Undefined behavior. This is only intended to be used for simulation. Refresh rows on average every X MEMCLKs, where X is a function of the maximum Trfc value for all DIMMs
in the system as follows:
if Trfc_max=000b, X=768
if Trfc_max=001b, X=768
if Trfc_max=010b, X=1024
if Trfc_max=011b, X=2048
if Trfc_max=1xxb, X=3072
01b
Reserved
10b
Every 7.8 us
11b
Every 3.9 us
15:0 Reserved.
D18F2x90_dct[0] DRAM Configuration Low
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31:28 IdleCycLimit: idle cycle limit. Read-write. IF (BootFromDRAM) THEN Cold reset: 8h. ELSE
Reset: 8h. ENDIF. BIOS: 8h. Specifies the number of MEMCLK cycles an idle page is open before it
is closed if DynPageCloseEn=0. This field is ignored if DynPageCloseEn=1. This field is an upper
limit for idle time whereas IdleCycLowLimit is a lower limit.
Description
Bits
0h
8 clocks
Fh-1h
<IdleCycLimit>*16 clocks
27
DisDllShutdownSR: disable DLL shutdown in self-refresh mode. Read-write. IF
(BootFromDRAM) THEN Cold reset: 1. ELSE Reset: 1. ENDIF. BIOS: See 2.9.7.7.
1=Disable the power saving features of shutting down DDR phy DLLs during DRAM self refresh and
memory P-states. 0=Shutdown DLLs during DRAM self refresh and allow memory P-state
transitions.
26
Reserved.
25
PendRefPaybackS3En: pending refresh payback S3 enable. Read-write. IF (BootFromDRAM)
THEN Cold reset: 0. ELSE Reset: 0. ENDIF. BIOS: 1. Specifies the S3 refresh payback behavior
when PendRefPayback=0. 1=Pending refreshes are paid back on S3 entry. 0=Pending refreshes are
not paid back on S3 entry.
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24
StagRefEn: Stagger Refresh Enable. Read-write. IF (BootFromDRAM) THEN Cold reset: 0. ELSE
Reset: 0. ENDIF. BIOS: 1. 1=The DRAM controller arbitrates refreshes among chip selects based on
the Tstag value (round robin algorithm). See D18F2x228_dct[0]. 0=DCT arbitrates among chip
selects using the Trfc value (linear sequential algorithm). See D18F2x208_dct[0].
23
ForceAutoPchg: force auto precharging. Read-write. IF (BootFromDRAM) THEN Cold reset: 0.
ELSE Reset: 0. ENDIF. BIOS: See 2.9.7.7.
1=Force auto-precharge cycles with every read or write command. In order to meet UMA traffic
bandwidth and latency performance targets in the CSRD, specific page hit ratios for display requests
must be realized. Setting ForceAutoPchg violates these CSRD targets, and therefore, should not be set
in UMA systems. Setting this bit may negatively impact non-UMA (generalized) stutter mode
performance as well.
22:21 IdleCycLowLimit: idle cycle low limit. Read-write. IF (BootFromDRAM) THEN Cold reset: 0.
ELSE Reset: 0. ENDIF. Specifies the number of MEMCLK cycles a page is allowed to be open
before it may be closed by the dynamic page close logic. This field is ignored if
D18F2x90_dct[0][DynPageCloseEn] = 0.
Bits
Description
00b
16 clocks
01b
32 clocks
10b
64 clocks
11b
96 clocks
20
DynPageCloseEn: dynamic page close enable. Read-write. IF (BootFromDRAM) THEN Cold
reset: 0. ELSE Reset: 0. ENDIF. See 2.9.7.7 [DCT Training Specific Configuration].
1=The DRAM controller dynamically determines when to close open pages based on the history of
that particular page and D18F2x90_dct[0][IdleCycLowLimit]. 0=Any open pages not auto-precharged by the DRAM controller are automatically closed after IdleCycLimit clocks of inactivity.
19
DimmEccEn: DIMM ECC enable. Read-write. IF (BootFromDRAM) THEN Cold reset: 0. ELSE
Reset: 0. ENDIF. 1=ECC checking is capable of being enabled for all DIMMs on the DRAM
controller by D18F3x44[DramEccEn]. This bit should not be set unless all populated DIMMs support
ECC check bits. 0=ECC checking is disabled on the DRAM controller.
18
PendRefPayback: pending refresh payback. Read-write. IF (BootFromDRAM) THEN Cold reset:
0. ELSE Reset: 0. ENDIF. BIOS: 0. 1=The DRAM controller executes all pending refresh commands
before entering the self refresh state. 0=The controller enters the self refresh state regardless of the
number of pending refreshes; applies to any self refresh entry if PendRefPaybackS3En=0, else any
non-S3 self refresh entry.
17
EnterSelfRef: enter self refresh command. Read, write-1-only; cleared-by-hardware. IF
(BootFromDRAM) THEN Cold reset: 0. ELSE Reset: 0. ENDIF. 1=The DRAM controller places the
DRAMs into self refresh mode. The DRAM interface is tristated 1 MEMCLK after the self refresh
command is issued to the DRAMs. Once entered, the DRAM interface must remain in self refresh
mode for a minimum of 5 MEMCLKs. This bit is read as a 1 while the enter-self-refresh command is
executing; it is read as 0 at all other times.
16
UnbuffDimm: unbuffered DIMM. IF (~Fuse[UnbDimmDis] & ~Fuse[RegDimmDis]) THEN
Read-write ELSE Read-only ENDIF. IF (BootFromDRAM) THEN Cold reset: 1. ELSE Reset:
(~Fuse[UnbDimmDis] & Fuse[RegDimmDis]). ENDIF. BIOS: 1. 1=The DRAM controller is connected to unbuffered DIMMs. 0=Reserved.
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15:12 Reserved. Read-write.
11
Reserved.
10
Reserved.
9
Reserved.
8
Reserved. Read-write.
7
Reserved.
6:2
Reserved.
1
ExitSelfRef: exit self refresh (after suspend to RAM or for DRAM training) command. Read,
write-1-only; cleared-by-hardware. IF (BootFromDRAM) THEN Cold reset: 0. ELSE Reset: 0.
ENDIF. Writing a 1 to this bit causes the DRAM controller to bring the DRAMs out of self refresh
mode. It also causes the DRAM controller to issue ZQCL and MRS MR0 commands (using DCT
internal versions of the MR0 state). This command should be executed by BIOS when returning from
the suspend to RAM state, after the DRAM controller configuration registers are properly initialized,
or when self refresh is used during DRAM training. This bit is read as a 1 while the exit-self-refresh
command is executing; it is read as 0 at all other times. This bit should not be set if the DCT is disabled.
D18F2x94_dct[0] DRAM Configuration High
See 2.9.3 [DCT Configuration Registers].
Bits
31
Description
DphyMemPsSelEn: Ddr phy MemPsSel enable. Read-write. IF (BootFromDRAM) THEN Cold
reset: 1h. ELSE Reset: 1h. ENDIF. BIOS: 1. 1=The DCT uses D18F1x10C[MemPsSel] to select the
memory P-state context of a phy register accessed by software with DctOffset[29:20]==0D0h.
DctOffset[6] is ignored. 0=Software accesses use DctOffset[6] to select context of those registers. If
DctOffset[29:20]!=0D0h then this register has no effect. See
D18F2x9C_x0D04_E008_dct[0][PStateToAccess].
30:29 Reserved.
28:24 DcqBypassMax: DRAM controller queue bypass maximum. Read-write. IF (BootFromDRAM)
THEN Cold reset: 0Fh. ELSE Reset: 0h. ENDIF. BIOS: 2.9.7.7. The DRAM controller arbiter
normally allows transactions to pass other transactions in order to optimize DRAM bandwidth. This
field specifies the maximum number of times that the oldest memory-access request in the DRAM
controller queue may be bypassed before the arbiter decision is overridden and the oldest memoryaccess request is serviced instead.
Bits
Description
0h
No bypass; the oldest request is never bypassed.
1Fh-1h
The oldest request may be bypassed no more than <DcqBypassMax> time.
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23
ProcOdtDis: processor on-die termination disable. Read-write. IF (BootFromDRAM) THEN Cold
reset: 0Fh. ELSE Reset: 0h. ENDIF. 1=The processor-side on-die termination is disabled.
0=Processor-side on-die termination enabled. Changes to this bit must be performed prior to setting
MemClkFreqVal.
22
BankSwizzleMode: bank swizzle mode. Read-write. IF (BootFromDRAM) THEN Cold reset: 0.
ELSE Reset: 0. ENDIF. BIOS: 2.9.7.7. 1=Remaps the DRAM device bank address bits as a function
of normalized physical address bits. Each of the bank address bits, as specified in D18F2x80_dct[0],
are remapped as follows:
• Define X as a bank address bit (e.g., X=15 if the bank bit is specified to be address bit 15).
• Define S(n) as the state of address bit n (0 or 1) and B as the remapped bank address bit. Then,
B= S(X) ^ S(X + 3) ^ S(X + 6); for an 8-bank DRAM.
For example, encoding 02h of Table 123 would be remapped from Bank[2:0]={A15, A14, A13} to
the following: Bank[2:0] = {A15^A18^A21, A14^A17^A20, A13^A16^A19}.
21
FreqChgInProg: frequency change in progress. Read-only. IF (BootFromDRAM) THEN Cold
reset: 0. ELSE Reset: 0. ENDIF. 1=A MEMCLK frequency change is in progress. The DDR phy
asserts this bit when it is in the process of locking the PLL. BIOS should not program the phy
registers while this bit is set. 0=DRAM-interface commands can be sent to the phy.
20
SlowAccessMode: slow access mode (a.k.a. 2T mode). Read-write. IF (BootFromDRAM) THEN
Cold reset: 0. ELSE Reset: 0. ENDIF. 1=One additional MEMCLK of setup time is provided on all
DRAM address and control signals (not including CS, CKE, and ODT); i.e., these signals are driven
for two MEMCLK cycles rather than one. 0=DRAM address and control signals are driven for one
MEMCLK cycle. 2T mode may be needed in order to meet electrical requirements of certain DIMM
speed and loading configurations. If memory P-states are enabled then BIOS must set this bit if 2T
timing is recommended for either memory P-state.
19
Reserved. Reset: 1.
18
Reserved. Read-write.
17
Reserved. Read-write.
16
PowerDownMode: power down mode. Read-write. IF (BootFromDRAM) THEN Cold reset: 0.
ELSE Reset: 0. ENDIF. BIOS: 1. Specifies how a chip select or group of chip selects enters power
down mode when enabled by D18F2x94_dct[0][PowerDownEn]. A chip select enters power down
mode when the DCT deasserts the CKE pin. The command and address signals tristate one
MEMCLK after CKE deasserts. The DCT behavior varies based on the setting of
D18F2x84_dct[0][PchgPDModeSel]. See also Table 122 [DIMM, Chip Select, and Register Mapping].
0=Channel CKE control mode; the DRAM channel is placed in power down mode when all chip
selects associated with the channel are idle; CKE pins for the channel operate in lock step in terms of
placing the channel in power down mode.
1=Chip select CKE control mode; the chip select group controlled by a CKE pin is placed in power
down mode when no transactions are pending.
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15
PowerDownEn: power down mode enable. Read-write. IF (BootFromDRAM) THEN Cold reset: 0.
ELSE Reset: 0. ENDIF.
BIOS: 2.9.7.7.
1=Power down mode is enabled. Only precharge power down mode is supported, not active power
down mode. See PowerDownMode, D18F2x84_dct[0][PchgPDModeSel],
D18F2xA8_dct[0][PrtlChPDEnhEn, AggrPDEn, PDPhyPSDis], and
D18F2x248_dct[0]_mp[1:0][PchgPDEnDelay].
14
DisDramInterface: disable the DRAM interface. Read-write. IF (BootFromDRAM) THEN Cold
reset: 0. ELSE Reset: 0. ENDIF. 1=The DRAM controller is disabled and the DRAM interface is
placed into a low power state. This bit must be set if there are no DIMMs connected to the DCT.
11:10 ZqcsInterval: ZQ calibration short interval. Read-write. IF (BootFromDRAM) THEN Cold reset:
00b. ELSE Reset: 00b. ENDIF. BIOS: See 2.9.7.7. This field specifies the programmable interval for
the controller to send out the DRAM ZQ calibration short command.
Bits
Description
00b
ZQ calibration short command is disabled
01b
64 ms
10b
128 ms
11b
256 ms
9:8
7
Reserved.
MemClkFreqVal: memory clock frequency valid. Read-write. Reset: 0. System BIOS should set
this bit after setting up D18F2x94_dct[0][MemClkFreq] to the proper value. This indicates to the
DRAM controller that it may start driving MEMCLK at the proper frequency. This bit should not be
set if the DCT is disabled. BIOS must change each DCT’s operating frequency in order.
See 2.9.7.4.2 [DRAM Channel Frequency Change].
6:5
Reserved. Reserved for future expansion of MemClkFreq.
4:0
MemClkFreq: memory clock frequency. Read-write. IF (BootFromDRAM) THEN Cold reset:
010b. ELSE Reset: 000b. ENDIF.
Specifies the frequency and rate of the DRAM interface (MEMCLK). See: Table 124 [Valid Values
for Memory Clock Frequency Value Definition]. The rate is twice the frequency. See
D18F5x84[DdrMaxRate] and D18F5x84[DdrMaxRateEnf]. See MemClkFreqVal.
Table 124: Valid Values for Memory Clock Frequency Value Definition
Bits
04h
06h
0Ah
0Eh
12h
16h
19h
1Ah
Description
333 MHz. (667 MT/s)
400 MHz. (800 MT/s)
533 MHz. (1066 MT/s)
667 MHz. (1333 MT/s)
800 MHz. (1600 MT/s)
933 MHz. (1866 MT/s)
1050 MHz. (2100 MT/s)
1066 MHz. (2133 MT/s)
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D18F2x98_dct[0] DRAM Controller Additional Data Offset
Reset: 8000_0000h. See 2.9.3 [DCT Configuration Registers].
Each DCT includes an array of registers that are used primarily to control DRAM-interface electrical parameters. Access to these registers is accomplished as follows:
Reads:
1. Write the register number to D18F2x98_dct[0][DctOffset] with D18F2x98_dct[0][DctAccessWrite]=0.
2. Read the register contents from D18F2x9C_dct[0].
Writes:
1. Write all 32 bits of register data to D18F2x9C_dct[0] (individual byte writes are not supported).
2. Write the register number to D18F2x98_dct[0][DctOffset] with D18F2x98_dct[0][DctAccessWrite]=1.
• The data will be delivered to the phy similar to a posted memory-write, and the write will complete without any further action. However, to ensure that the contents of the array register write have been delivered to the phy, software issues a subsequent configuration register read or write to any register in the
northbridge. For example, reading D18F2x98_dct[0] will accomplish this.
Registers for which there is one instance per memory P-state (listed with “_mp[1:0]” appended to the register
mnemonic) use D18F1x10C[MemPsSel], D18F2x94_dct[0][DphyMemPsSelEn], and
D18F2x9C_x0D04_E008_dct[0][PStateToAccess] for software accesses. BIOS programs these fields appropriately to ensure consistency of registers with controller fields and DDR phy fields.
• D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0] refers to all instances of the
D18F2x9C_x0000_0[3:0]0[3:1] register.
• D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1] refers to the register for memory P-state 1 of either or both
DCTs.
• It is recommended that BIOS program context sensitive registers in batches (training/restoring all registers of
a context before selecting a new context). BIOS should do the following prior to a new “batch”:
• Program D18F2x94_dct[0][DphyMemPsSelEn]=1.
• Program D18F2x9C_x0D04_E008_dct[0][PStateToAccess]=target.
• Program D18F1x10C[MemPsSel]=target.
Writes to any register in this additional address space causes the FIFO pointers to be reset. Therefore, it is recommended that only BIOS write these registers.
Reads or writes to any register in this additional address space collide with system self-refresh requests. Once
power management is enabled software should temporarily disable power management prior to accessing these
registers.
Bits
30
Description
DctAccessWrite: DRAM controller read/write select. RAZ; write. 0=Specifies a read access.
1=Specifies a write access.
29:0 DctOffset: DRAM controller offset. Read-write.
D18F2x9C_dct[0] DRAM Controller Additional Data Port
Reset: 0000_0000h. S3-check-exclude. See D18F2x98_dct[0] for register access information. See 2.9.3 [DCT
Configuration Registers]. Address: D18F2x98_dct[0][DctOffset].
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Description
31:0 Data. Read-write.
D18F2x9C_x0000_0000_dct[0]_mp[1:0] DRAM Output Driver Compensation Control
See 2.9.7.6.6 [DRAM Address Timing and Output Driver Compensation Control].
Bits
31
Description
Reserved.
30:28 ProcOdt: processor on-die termination. Read-write. Cold reset: 011b. Specifies the resistance of
the on-die termination resistors. This field is valid only when D18F2x94_dct[0][ProcOdtDis]=0.
Bits
Description
000b
240 ohms +/- 20%
001b
120 ohms +/- 20%
010b
80 ohms +/- 20%
011b
60 ohms +/- 20%
111b-100b
Reserved 80 ohms +/- 20%
27:23 Reserved.
22:20 DqsDrvStren: DQS drive strength. Read-write. Cold reset: 011b. Specifies the drive strength of the
DQS pins.
Bits
Description
000b
0.75x
001b
1.0x
010b
1.25x
011b
1.5x
100b
0.0x. Driver disabled.
101b
Reserved (0.5x)
110b
0.5x
111b
Reserved (0.75x)
19
Reserved.
18:16 DataDrvStren: data drive strength. Read-write. Cold reset: 011b. This field specifies the drive
strength of the DRAM data pins.
Bits
Description
000b
0.75x
001b
1.0x
010b
1.25x
011b
1.5x
100b
0.0x. Driver disabled.
101b
Reserved (0.5x)
110b
0.5x
111b
Reserved (0.75x)
This field is applied to DM signals as well.
15
Reserved.
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14:12 ClkDrvStren: MEMCLK drive strength. Read-write. Cold reset: 011b. This field specifies the
drive strength of the MEMCLK pins.
Bits
Description
000b
1.0x
001b
1.25x
010b
1.5x
011b
2.0x
100b
0.0x. Driver disabled.
101b
0.75x
110b
0.5x
111b
Reserved 1.0x
11
Reserved.
10:8 AddrCmdDrvStren: address/command drive strength. Read-write. Cold reset: 011b. This field
specifies the drive strength of the address, RAS, CAS, WE, bank and parity pins.
Bits
Description
000b
1.0x
001b
1.25x
010b
1.5x
011b
2.0x
100b
0.0x. Driver disabled.
101b
0.75x
110b
0.5x
111b
Reserved 1.0x
7
6:4
Reserved.
CsOdtDrvStren: CS/ODT drive strength. Read-write. Cold reset: 011b. This field specifies the
drive strength of the CS and ODT pins.
Bits
Description
000b
1.0x
001b
1.25x
010b
1.5x
011b
2.0x
100b
0.0x. Driver disabled.
101b
0.75x
110b
0.5x
111b
Reserved 1.0x
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Reserved.
CkeDrvStren: CKE drive strength. Read-write. Cold reset: 011b. This field specifies the drive
strength of the CKE pins.
Bits
Description
000b
1.0x
001b
1.25x
010b
1.5x
011b
2.0x
100b
0.0x. Driver disabled.
101b
0.75x
110b
0.5x
111b
Reserved 1.0x
D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0] DRAM Write Data Timing
BIOS: See 2.9.7.9.4 [DQS Position Training].
Table 125: Index Mapping for D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0000_0001h
0000_0002h
0000_0003h
0000_0101h
0000_0102h
0000_0103h
0000_0201h
0000_0202h
0000_0203h
0000_0301h
0000_0302h
0000_0303h
Function
DIMM/CS 0 Bytes 3-0
DIMM/CS 0 Bytes 7-4
DIMM/CS 0 ECC
DIMM/CS 1 Bytes 3-0
DIMM/CS 1 Bytes 7-4
DIMM/CS 1 ECC
Reserved/CS 2 Bytes 3-0
Reserved/CS 2 Bytes 7-4
Reserved/CS 2 ECC
Reserved/CS 3 Bytes 3-0
Reserved/CS 3 Bytes 7-4
Reserved/CS 3 ECC
Table 126: Byte Lane Mapping for D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0]
Register
Bits
31:24
23:16
15:8
7:0
D18F2x9C_x0000_0[3:0]01_dct[0]_mp[1:0]
Byte3
Byte2
Byte1
Byte0
D18F2x9C_x0000_0[3:0]02_dct[0]_mp[1:0]
Byte7
Byte6
Byte5
Byte4
D18F2x9C_x0000_0[3:0]03_dct[0]_mp[1:0]
Reserved Reserved Reserved
ECC
If D18F2xA8_dct[0][PerRankTimingEn]=1 then the function is CS. Otherwise the function is DIMM.
These registers control the timing of write DQ with respect to MEMCLK and allow transmit DQS to be centered in the data eye. The delay starts 1 UI before the rising edge of MEMCLK corresponding to the CASwrite-latency. See 2.9.7.9 [DRAM Training]. WrDatGrossDly must be programmed for a given DIMM and
lane such that WrDatDly - WrDqsDly <= 0.5 MEMCLKs.
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Bits
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Description
31:29 WrDatGrossDly: write data gross delay. See:
D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0][7:5].
28:24 WrDatFineDly: write data fine delay. See: D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0][4:0].
23:21 WrDatGrossDly: write data gross delay. See:
D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0][7:5].
20:16 WrDatFineDly: write data fine delay. See: D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0][4:0].
15:13 WrDatGrossDly: write data gross delay. See:
D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0][7:5].
12:8 WrDatFineDly: write data fine delay. See: D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0][4:0].
7:5
WrDatGrossDly: write data gross delay. Read-write. Reset: 0.
Bits
Description
000b
No delay
001b
0.5 MEMCLK delay
110b-010b
<WrDatGrossDly>/2 MEMCLK delay
111b
3.5 MEMCLK delay
Verification constraints: WrDatGrossDly must be programmed to ensure that WrDatGrossDly D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][WrDqsGrossDly] <= 0.5 MEMCLKs.
4:0
WrDatFineDly: write data fine delay. Read-write. Cold reset: 0.
Description
Bits
00h
0/64 MEMCLK delay
1Eh-01h
<WrDatFineDly>/64 MEMCLK delay
1Fh
31/64 MEMCLK delay
D18F2x9C_x0000_0004_dct[0]_mp[1:0] DRAM Address/Command Timing Control
BIOS: 2.9.7.6.6.
MEMCLK
Command
Command
1 MEMCLK
½ MEMCLK
Coarse Setup = 1 (setup is one full MEMCLK) –
Fine delay is zero.
Coarse Setup = 0 (setup is one half MEMCLK) –
Fine delay is zero.
Command
Coarse Setup = 1 (setup is one full MEMCLK) plus a
non zero fine delay.
Command
Coarse Setup = 0 (setup is one half MEMCLK) – A
half MEMCLK setup plus a non-zero fine delay.
Figure 8: Address/Command Timing at the Processor Pins
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This register controls the timing of the address, command, chip select, ODT and clock enable pins with respect
to MEMCLK as shown in Figure 8. See 2.9.7.4.2 [DRAM Channel Frequency Change] and 2.9.7.4.3 [Phy
Fence Programming]. 2T timing is controlled by D18F2x94_dct[0][SlowAccessMode]. If a setup time (coarse
delay) field is changed and D18F2x94_dct[0][MemClkFreqVal]=1, then software must toggle MemClkFreqVal
for the delay to take effect.
Bits
Description
31:22 Reserved.
21
AddrCmdSetup: address/command setup time. Read-write. Reset: 0. Selects the default setup time
for the address and command pins versus MEMCLK. 0=1/2 MEMCLK (1 1/2 MEMCLK for 2T timing). 1=1 MEMCLK (2 MEMCLKs for 2T timing).
20:16 AddrCmdFineDelay: address/command fine delay. Specifies the time that the address and command pins are delayed from the default setup time. See: CkeFineDelay.
15:14 Reserved.
13
CsOdtSetup: CS/ODT setup time. Selects the default setup time for the CS and ODT pins versus
MEMCLK. See: CkeSetup.
12:8 CsOdtFineDelay: CS/ODT fine delay. Specifies the time that the CS and ODT pins are delayed
from the default setup time. See: CkeFineDelay.
7:6
Reserved.
5
CkeSetup: CKE setup time. Read-write. Reset: 0. Selects the default setup time for the CKE pins
versus MEMCLK. 0=1/2 MEMCLK. 1=1 MEMCLK.
4:0
CkeFineDelay: CKE fine delay. Read-write. Cold reset: 00h. Specifies the time that the CKE pins
are delayed from the default setup time.
Bits
Description
00h
0/64 MEMCLK delay
1Eh-01h
<CkeFineDelay>/64 MEMCLK delay
1Fh
31/64 MEMCLK delay
D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0] DRAM Read DQS Timing
Table 127: Index Mapping for D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0000_0005h
0000_0006h
0000_0007h
0000_0105h
0000_0106h
0000_0107h
0000_0205h
0000_0206h
0000_0207h
0000_0305h
0000_0306h
0000_0307h
Function
DIMM/CS 0 Bytes 3-0
DIMM/CS 0 Bytes 7-4
DIMM/CS 0 ECC
DIMM/CS 1 Bytes 3-0
DIMM/CS 1 Bytes 7-4
DIMM/CS 1 ECC
Reserved/CS 2 Bytes 3-0
Reserved/CS 2 Bytes 7-4
Reserved/CS 2 ECC
Reserved/CS 3 Bytes 3-0
Reserved/CS 3 Bytes 7-4
Reserved/CS 3 ECC
328
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BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 128: Byte Lane Mapping for D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0]
Bits
Register
29:25
21:17
13:9
5:1
D18F2x9C_x0000_0[3:0]05_dct[0]_mp[1:0]
Byte3
Byte2
Byte1
Byte0
D18F2x9C_x0000_0[3:0]06_dct[0]_mp[1:0]
Byte7
Byte6
Byte5
Byte4
D18F2x9C_x0000_0[3:0]07_dct[0]_mp[1:0]
Reserved Reserved Reserved
ECC
If D18F2xA8_dct[0][PerRankTimingEn]=1 then the function is CS. Otherwise the function is DIMM.
These registers control the timing of read (input) DQS signals with respect to DQ. See 2.9.7.9 [DRAM Training]. Writes to D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0] set
D18F2x9C_x0D0F_0[F,8:0]2[3:0]_dct[0]_mp[1:0][RdDqsTimeU, RdDqsTimeL] = {RdDqsTime, RdDqsTime}. Reads from D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0] return
D18F2x9C_x0D0F_0[F,8:0]2[3:0]_dct[0]_mp[1:0][RdDqsTimeL].
The actual delay applied to the DQS input signal before sampling data includes an internal part dependent
(insertion) delay plus the nominal delay specified by the register setting.
Bits
Description
31:30 Reserved.
29:25 RdDqsTime: read DQS timing control. See: D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0][5:1].
24:22 Reserved.
21:17 RdDqsTime: read DQS timing control. See: D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0][5:1].
16:14 Reserved.
13:9 RdDqsTime: read DQS timing control. See: D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0][5:1].
8:6
Reserved.
5:1
RdDqsTime: read DQS timing control. Read-write. Cold reset: 0Fh.
Bits
Description
00h
0/64 MEMCLK delay
1Eh-01h
<RdDqsTime>/64 MEMCLK delay
1Fh
31/64 MEMCLK delay
0
Reserved.
D18F2x9C_x0000_0008_dct[0]_mp[1:0] DRAM Phy Control
Cold reset: 0208_0000h. See 2.9.7.9 [DRAM Training]. This register also provides access to the multiplier and
divider values used in the DDR phy. The default values for the given MEMCLK frequency of the PLL when
D18F2x94_dct[0][MemClkFreqVal]=1 can be found: [MACOREPLL Spec:1.4.3.1 Suggested DDR Phy Frequency Settings for 100Mhz RefClk].
Bits
Description
31
Reserved. Read-write.
30
DisAutoComp: disable automatic compensation. Read-write. BIOS: See 2.9.7.4.4. 1=Disable the
compensation control state machine. 0=The phy automatic compensation engine is enabled.
29
DisablePredriverCal: disable predriver calibration. Read-write. BIOS: See 2.9.7.4.4. 1=Disable
the update of predriver codes to all pads.
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13
DqsRcvTrEn: DQS receiver training enable. Read-write. 1=Initiate hardware assisted read DQS
receiver training. The phy waits for back to back read requests from the DCT (using the read pending
signal), discards the first 20 UI worth of DQS samples to account for asynchronous read return
latency, and enables the PRE for updating using subsequent samples until the read pipeline is interrupted with a deassertion of read pending. At that time, the PRE will stop updating regardless of the
state of this bit, and waits for another string of back to back read requests. During the time that the
PRE is enabled for sampling, the phy starts in high gain mode, where two samples contribute to one
LSB of phase change; this persists for 64 samples. The phy then changes to a low gain mode, where
32 samples contribute to one LSB of phase change. A minimum of 400 samples will assure convergence. This can be accomplished with multiple strings of reads of at least 56 UI. 0=Stop read DQS
receiver training. This allows BIOS to reliably read the DQS receiver training data.
12
WrLvOdtEn: write levelization ODT enabled. Read-write. 1=ODT specified by WrLvOdt is
enabled during write levelization training. 0=ODT is disabled during write levelization training.
11:8 WrLvOdt: write levelization ODT. Read-write; S3-check-exclude. Specifies the state of the ODT
pins when WrLvOdtEn is set. 1=ODT is enabled. 0=ODT is disabled. See 2.9.7.6.5 [DRAM ODT
Control]. Tri-state enable for ODT is turned off by the phy when WrLvOdtEn=1.
Bit
Pad
[0]
BP_MEMODT[0][0]
[1]
BP_MEMODT[0][1]
[2]
BP_MEMODT[0][2]
[3]
BP_MEMODT[0][3]
7:6
FenceTrSel: fence train select. Read-write; S3-check-exclude. Specifies the flop to be used for phy
based fence training. See PhyFenceTrEn. This field is shared by
D18F2x9C_x0000_0008_dct[0]_mp0 and D18F2x9C_x0000_0008_dct[0]_mp1.
Description
Bits
00b
PRE flop (legacy 45nm phy fence training)
01b
RxDll flop (applies to DqsRcvEn timing)
10b
TxDll flop (applies to RxValid timing only during DqsRcvEn training)
11b
TxPad flop (applies to WrDat, WrDqs, and Addr/Cmd/Cs/Odt/Cke timing)
5:4
TrChipSel: training DIMM select. Read-write; S3-check-exclude. Specifies a timing control for a
corresponding rank which is to be trained. If D18F2xA8_dct[0][PerRankTimingEn]=1 then the function is CS. Otherwise the function is DIMM.
This field also selects which bit of the x4DIMM field is used (which is then used to determine which
nibble is trained). To ensure complete consistency with 45nm product phy based training, if PerRankTimingEn=1 then x4DIMM[] must be zero.
Description
Bits
00b
DIMM/CS 0
01b
DIMM/CS 1
10b
DIMM:Reserved/CS 2
11b
DIMM:Reserved/CS 3
3
PhyFenceTrEn: phy fence training enable. Read-write. 1=Initiate phy based fence training. 0=Stop
the phy based fence training engine.
2
TrNibbleSel: training nibble select. Read-write. BIOS: 0. Specifies nibbles of each DIMM data byte
trained during write levelization training. 0=Lower nibbles. 1=Upper nibbles.
0
WrtLvTrEn: write levelization training enable. Read-write. 1=Initiate write levelization (tDQSS
margining) training. 0=The phy stops driving DQS and exits write levelization training.
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D18F2x9C_x0000_000B_dct[0] DRAM Phy Status Register
Bits
Description
31
DynModeChange: dynamic mode change. RAZ; write. Reset: 0. 1=Phy enters the state specified by
PhySelfRefreshMode. When writing a 1 to this bit, values written to bits [22:0] of the register are
ignored.
30
PhyPSReq: phy pstate request. RAZ; write. Reset: 0. 1=Phy enters the memory P-state specified by
PhyPS. When writing a 1 to this bit, values written to bits [22:0] of the register are ignored.
29:27 Reserved.
26
PhyPS: phy pstate. RAZ; write. Reset: 0. 1=M1. 0=M0. See PhyPSReq.
23
PhySelfRefreshMode: phy self refresh mode. RAZ; write. Reset: 0. 1=Enter self refresh mode.
0=Exit self refresh mode. See DynModeChange.
D18F2x9C_x0000_000C_dct[0] DRAM Phy Miscellaneous
Bits
31
Description
Reserved.
30:26 FenceThresholdTxDll: phy fence threshold transmit DLL. Read-write; S3-check-exclude. Cold
reset: 13h. BIOS: See 2.9.7.4.3. This field specifies the fence delay threshold value used to create the
fence bit in the DLL delay registers for DQS receiver valid. This field is only used during DQS
receiver enable training to time the internal phy signal RxValid. See FenceThresholdTxPad.
25:21 FenceThresholdRxDll: phy fence threshold DQS receiver enable. Read-write; S3-check-exclude.
Cold reset: 13h. BIOS: See 2.9.7.4.3. This field specifies the fence delay threshold value used to create the fence bit in the DLL delay registers for DQS receiver enable. See FenceThresholdTxPad.
20:16 FenceThresholdTxPad: phy fence threshold transmit pad. Read-write; S3-check-exclude. Cold
reset: 13h. BIOS: See 2.9.7.4.3. This field specifies the fence delay threshold value used to create the
fence bit in the DLL delay registers for write data, write DQS, Addr/Cmd, CS, ODT, and CKE. The
corresponding fence bit is set by hardware when the DLL delay register is written if DLL delay >=
FenceThresholdTxPad.
Bits
Description
00h
0/64 MEMCLK delay
1Eh-01h
<FenceThresholdTxPad>/64 MEMCLK delay
1Fh
31/64 MEMCLK delay
15:12 CKETri: CKE tri-state. Read-write. Cold reset: 0h. 0=The CKE signal is not tri-stated. 1=Tri-state
unconnected CKE signal from the processor. See 2.9.4 [DDR Pad to Processor Pin Mapping].
Bit
Pad
[0]
BP_MEMCKE[0][0]
[1]
BP_MEMCKE[0][1]
[2]
BP_MEMCKE[0][2]
[3]
BP_MEMCKE[0][3]
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11:8 ODTTri: ODT tri-state. Read-write. Cold reset: 0h. 0=The ODT signals are not tri-stated unless
directed to by the DCT. 1=Tri-state unconnected ODT signals from the processor. See 2.9.4 [DDR
Pad to Processor Pin Mapping].
Bit
Pad
[0]
BP_MEMODT[0][0]
[1]
BP_MEMODT[0][1]
[2]
BP_MEMODT[0][2]
[3]
BP_MEMODT[0][3]
7:0
ChipSelTri: chip select tri-state. Read-write. Cold reset: 00h. 0=The chip select signals are not tristated unless directed to by the DCT. 1=Tri-state unpopulated chip selects when motherboard termination is available. See 2.9.4 [DDR Pad to Processor Pin Mapping]. ChipSelTri must be programmed to
1b for each pad not connected to a processor pin when D18F2x250_dct[0][LoopbackBistReq]=1.
Bit
Pad
[0]
BP_MEMCS[0]_L[0]
[1]
BP_MEMCS[0]_L[1]
[2]
BP_MEMCS[0]_L[2]
[3]
BP_MEMCS[0]_L[3]
[4]
BP_MEMCS[0]_L[4]
[5]
BP_MEMCS[0]_L[5]
[6]
BP_MEMCS[0]_L[6]
[7]
BP_MEMCS[0]_L[7]
D18F2x9C_x0000_000D_dct[0]_mp[1:0] DRAM Phy DLL Control
Cold Reset: 0000_0000h. This register defines programmable options for the phy's DLLs for power savings.
There are two identical sets of configuration registers: one for the transmit DLLs (those running off of the phy's
internal PCLK which is running at rate of 2*MEMCLK) and receive DLLs (those running off of the DQS from
the DIMMs). These values are programmed by BIOS based on programmed DDR frequency. This register
must be programmed before DRAM device initialization.
Bits
Description
31:26 Reserved.
25:24 RxDLLWakeupTime: receive DLL wakeup time. Read-write. BIOS: See 2.9.7.10. Specifies the
number of PCLKs that the DLL standby signal must deassert prior to a DLL relock event or before
read traffic is sent to the receive DLLs.
23
Reserved.
22:20 RxCPUpdPeriod: receive charge pump period. Read-write. BIOS: See 2.9.7.10. Specifies the
number of DLL relocks required to keep the receive DLLs locked for the period where there is no
read traffic.
19:16 RxMaxDurDllNoLock: receive maximum duration DLL no lock. Read-write. BIOS: See 2.9.7.7.
Specifies the number of PCLK cycles that occur before the phy DLLs relock. A DLL relock occurs
every 2^RxMaxDurDllNoLock if there are no reads during the period. 0=DLL power saving(standby)
disabled. If RxMaxDurDllNoLock!=0 (standby is enabled),
D18F2x9C_x0D0F_0[F,8:0]0C_dct[0][DllRstRelock] must be set to 1 prior to writing this register
and then DllRstRelock must be cleared after the register write.
15:10 Reserved.
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9:8
7
BKDG for AMD Family 16h Models 00h-0Fh Processors
TxDLLWakeupTime: transmit DLL wakeup time. Read-write. BIOS: See 2.9.7.10. Specifies the
number of PCLK's that the DLL standby signal must deassert prior to a DLL relock event or before
write traffic is sent to transmit DLLs.
Reserved.
6:4
TxCPUpdPeriod: transmit charge pump DLL wakeup time. Read-write. BIOS: See 2.9.7.10.
Specifies the number of DLL relocks required to keep the TxDLLs locked for the period where there
is no write traffic.
3:0
TxMaxDurDllNoLock: transmit maximum duration DLL no lock. Read-write. BIOS: See
2.9.7.7. Specifies the number of PCLK cycles that occur before the phy DLLs relock. A DLL relock
occurs every 2^TxMaxDurDllNoLock if there are no writes during the period. 0=DLL power
saving(standby) disabled. If TxMaxDurDllNoLock!=0 (standby is enabled),
D18F2x9C_x0D0F_0[F,8:0]0C_dct[0][DllRstRelock] must be set to 1 prior to writing this register
and then DllRstRelock must be cleared after the register write.
D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0] DRAM DQS Receiver Enable Timing
Table 129: Index Mapping for D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0000_0010h
0000_0011h
0000_0012h
0000_0013h
0000_0014h
0000_0015h
0000_0016h
0000_0017h
0000_0018h
0000_0019h
0000_001Ah
0000_001Bh
0000_001[F:C]h
0000_0020h
0000_0021h
0000_0023h
0000_0024h
Function
DIMM/CS 0 Bytes 1-0
DIMM/CS 0 Bytes 3-2
DIMM/CS 0 ECC
DIMM
/CS 1 Bytes 1-0
DIMM
/CS 1 Bytes 3-2
DIMM
/CS 1 ECC
Reserved
/CS 2 Bytes 1-0
Reserved
/CS 2 Bytes 3-2
Reserved
/CS 2 ECC
Reserved
/CS 3 Bytes 1-0
Reserved
/CS 3 Bytes 3-2
Reserved
/CS 3 ECC
Reserved
DIMM/CS 0 Bytes 5-4
DIMM/CS 0 Bytes 7-6
DIMM
/CS 1 Bytes 5-4
DIMM
/CS 1 Bytes 7-6
333
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BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 129: Index Mapping for D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0]
0000_0025h
0000_0026h
Reserved
Reserved
/CS 2 Bytes 5-4
Reserved
/CS 2 Bytes 7-6
Reserved
/CS 3 Bytes 5-4
Reserved
/CS 3 Bytes 7-6
0000_0027h
0000_0029h
0000_002Ah
Table 130: Byte Lane Mapping for D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0]
Bits
Register
25:16
9:0
D18F2x9C_x0000_001[9,6,3,0]_dct[0]_mp[1:0]
Byte1
Byte0
D18F2x9C_x0000_001[A,7,4,1]_dct[0]_mp[1:0]
Byte3
Byte2
D18F2x9C_x0000_001[B,8,5,2]_dct[0]_mp[1:0]
Reserved
ECC
D18F2x9C_x0000_002[9,6,3,0]_dct[0]_mp[1:0]
Byte5
Byte4
D18F2x9C_x0000_002[A,7,4,1]_dct[0]_mp[1:0]
Byte7
Byte6
If D18F2xA8_dct[0][PerRankTimingEn]=1 then the function is CS. Otherwise the function is DIMM.
Each of these registers control the timing of the receiver enable from the start of the read preamble with respect
to MEMCLK. See 2.9.7.9 [DRAM Training]. These delay registers must be programmed such that across all
DIMMs and lanes MAX(DqsRcvEnDelay) - MIN(DqsRcvEnDelay) <= 7 UI.
Bits
Description
31:26 Reserved.
25:21 DqsRcvEnGrossDelay: DQS receiver enable gross delay. See:
D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][9:5].
20:16 DqsRcvEnFineDelay: DQS receiver enable fine delay. See:
D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][4:0].
15:10 Reserved.
9:5
DqsRcvEnGrossDelay: DQS receiver enable gross delay. Read-write. Reset: 01h. Rule: IF
((NBCOF / DdrRate < 1) && (D18F2x200_dct[0]_mp[1:0][Tcl]=5)) THEN DqsRcvEnGrossDelay
>= 1 ENDIF.
Bits
Description
00h
No delay
01h
0 MEMCLK delay
1Eh-02h
<DqsRcvEnGrossDelay>/2 MEMCLK delay
1Fh
15.5 MEMCLK delay
4:0
DqsRcvEnFineDelay: DQS receiver enable fine delay. Read-write. Cold reset: 00h.
Bits
Description
00h
0/64 MEMCLK delay
1Eh-01h
<DqsRcvEnFineDelay>/64 MEMCLK delay
1Fh
31/64 MEMCLK delay
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BKDG for AMD Family 16h Models 00h-0Fh Processors
D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0] DRAM DQS Write Timing
BIOS: See 2.9.7.9 [DRAM Training].
Table 131: Index Mapping for D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0000_0030h
0000_0031h
0000_0032h
0000_0033h
0000_0034h
0000_0035h
0000_0036h
0000_0037h
0000_0038h
0000_0039h
0000_003Ah
0000_003Bh
0000_0040h
0000_0041h
0000_0043h
0000_0044h
0000_0046h
0000_0047h
0000_0049h
0000_004Ah
Function
DIMM/CS 0 Bytes 1-0
DIMM/CS 0 Bytes 3-2
DIMM/CS 0 ECC
DIMM
/CS 1 Bytes 1-0
DIMM
/CS 1 Bytes 3-2
DIMM
/CS 1 ECC
Reserved
/CS 2 Bytes 1-0
Reserved
/CS 2 Bytes 3-2
Reserved
/CS 2 ECC
Reserved
/CS 3 Bytes 1-0
Reserved
/CS 3 Bytes 3-2
Reserved
/CS 3 ECC
DIMM/CS 0 Bytes 5-4
DIMM/CS 0 Bytes 7-6
DIMM
/CS 1 Bytes 5-4
DIMM
/CS 1 Bytes 7-6
Reserved
/CS 2 Bytes 5-4
Reserved
/CS 2 Bytes 7-6
Reserved
/CS 3 Bytes 5-4
Reserved
/CS 3 Bytes 7-6
335
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 132: Byte Lane Mapping for D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0]
Bits
Register
23:16
7:0
D18F2x9C_x0000_003[9,6,3,0]_dct[0]_mp[1:0]
Byte1
Byte0
D18F2x9C_x0000_003[A,7,4,1]_dct[0]_mp[1:0]
Byte3
Byte2
D18F2x9C_x0000_003[B,8,5,2]_dct[0]_mp[1:0]
Reserved
ECC
D18F2x9C_x0000_004[9,6,3,0]_dct[0]_mp[1:0]
Byte5
Byte4
D18F2x9C_x0000_004[A,7,4,1]_dct[0]_mp[1:0]
Byte7
Byte6
If D18F2xA8_dct[0][PerRankTimingEn]=1 then the function is CS. Otherwise the function is DIMM.
Each of these registers control the DQS timing delay for write commands relative to MEMCLK. The delay
starts at the rise edge of MEMCLK corresponding to the CAS-writelatency. Each control includes a gross timing field and a fine timing field, the sum of which is the total delay. See 2.9.7.9 [DRAM Training].
Bits
Description
31:29 Reserved. Read-write.
28:24 Reserved.
23:21 WrDqsGrossDly: DQS write gross delay. See: D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][7:5].
20:16 WrDqsFineDly: DQS write fine delay. See: D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0][4:0].
15:13 Reserved. Read-write.
12:8 Reserved.
7:5
WrDqsGrossDly: DQS write gross delay. Read-write. Reset: 0.
Bits
Description
000b
No delay
001b
0.5 MEMCLK delay
110b-010b
<WrDqsGrossDly>/2 MEMCLK delay
111b
3.5 MEMCLK delay
4:0
WrDqsFineDly: DQS write fine delay. Read-write. Cold reset: 0.
Bits
Description
00h
0/64 MEMCLK delay
1Eh-01h
<WrDqsFineDly>/64 MEMCLK delay
1Fh
31/64 MEMCLK delay
D18F2x9C_x0000_00[52:50]_dct[0] DRAM Phase Recovery Control
These registers are used by BIOS for hardware assisted DRAM training. Writes to these registers seed the
phase recovery engine prior to training. Reads from the registers indicate how much the phase recovery engine
has advanced to align the MEMCLK and DQS edges and is under hardware control. See 2.9.7.9 [DRAM
Training].
Table 133: Index Mapping for D18F2x9C_x0000_00[52:50]_dct[0]
D18F2x98_dct[0][31:0]
0000_0050h
0000_0051h
0000_0052h
Function
Bytes 3-0
Bytes 7-4
ECC
336
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BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 134: Byte Lane Mapping for D18F2x9C_x0000_00[52:50]_dct[0]
Bits
Register
31:24
23:16
15:8
7:0
D18F2x9C_x0000_0050_dct[0]
Byte3
Byte2
Byte1
Byte0
D18F2x9C_x0000_0051_dct[0]
Byte7
Byte6
Byte5
Byte4
D18F2x9C_x0000_0052_dct[0]
Bits
31
Reserved Reserved Reserved
ECC
Description
Reserved.
30:29 PhRecGrossDly: phase recovery gross delay. See: PhRecGrossDly.
28:24 PhRecFineDly: phase recovery fine delay. See: PhRecFineDly.
23
Reserved.
22:21 PhRecGrossDly: phase recovery gross delay. See: PhRecGrossDly.
20:16 PhRecFineDly: phase recovery fine delay. See: PhRecFineDly.
15
Reserved.
14:13 PhRecGrossDly: phase recovery gross delay. See: PhRecGrossDly.
12:8 PhRecFineDly: phase recovery fine delay. See: PhRecFineDly.
7
Reserved.
6:5
PhRecGrossDly: phase recovery gross delay. Read-write; S3-check-exclude. Reset: X. Gross timing indicates the number of half-MEMCLK periods that the phase recovery engine advanced while
aligning edges.
Bits
Description
00b
No delay
01b
0.5 MEMCLK delay
10b
1.0 MEMCLK delay
11b
1.5 MEMCLK delay
4:0
PhRecFineDly: phase recovery fine delay. Read-write; S3-check-exclude. Reset: X.
Bits
Description
00h
0/64 MEMCLK delay
1Eh-01h
<PhRecFineDly>/64 MEMCLK delay
1Fh
31/64 MEMCLK delay
D18F2x9C_x0D0F_0[F,8:0]02_dct[0] Data Byte Transmit PreDriver Calibration
Cold reset: xxxx_xxxxh. BIOS: See 2.9.7.4.4. DBYTE.
Table 135: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]02_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0802h 0702h 0602h 0502h 0402h 0302h 0202h 0102h 0002h
0D0Fh
ECC Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
337
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BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 136: Broadcast Mapping for D18F2x9C_x0D0F_0[F,8:0]02_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0F02h
0D0Fh
D18F2x9C_x0D0F_0[8:0]02
Table 137: Valid Values for D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]
Bits
0h
8h-1h
9h
11h-Ah
12h
1Ah-13h
1Bh
23h-1Ch
24h
2Ch-25h
2Dh
35h-2Eh
36h
3Eh-37h
3Fh
Bits
Description
Slew Rate 0 (slowest)
Reserved
Slew Rate 1
Reserved
Slew Rate 2
Reserved
Slew Rate 3
Reserved
Slew Rate 4
Reserved
Slew Rate 5
Reserved
Slew Rate 6
Reserved
Slew Rate 7 (fastest)
Description
31:16 Reserved.
15
ValidTxAndPre: predriver calibration code valid. Read-write; cleared-by-hardware. 1=Predriver
calibration codes are copied from this register and D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0] into the
associated transmit pad. Hardware clears this field after the copy is complete.
14:12 Reserved. Read-write.
11:6 TxPreP: PMOS predriver calibration code. Read-write; S3-check-exclude. Specifies the rising
edge slew rate of the transmit pad. See: Table 137 [Valid Values for
D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]]. After updating this value, BIOS must program
ValidTxAndPre=1 for the change to take effect.
5:0
TxPreN: NMOS predriver calibration code. Read-write; S3-check-exclude. Specifies the falling
edge slew rate of the transmit pad. See: Table 137 [Valid Values for
D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]]. After updating this value, BIOS must program
ValidTxAndPre=1 for the change to take effect.
D18F2x9C_x0D0F_0[F,8:0]0[B,7,3]_dct[0] Data Byte POdt Configuration
Cold reset: 0000_xxxxh. See D18F2x9C_x0D0F_1C00_dct[0]. DBYTE.
338
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BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 138: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]0[B,7,3]_dct[0]
D18F2x98_dct[0][31:0]
0D0F_000[B,7,3]h
0D0F_010[B,7,3]h
0D0F_020[B,7,3]h
0D0F_030[B,7,3]h
0D0F_040[B,7,3]h
0D0F_050[B,7,3]h
0D0F_060[B,7,3]h
0D0F_070[B,7,3]h
0D0F_080[B,7,3]h
0D0F_0F0[B,7,3]h
Bits
Function
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
ECC
D18F2x9C_x0D0F_0[8:0]0[B,7,3]
Description
31:16 Reserved.
15:14 Reserved. Read-write.
13:8 POdtD: pmos ODT calibration data. Read-write; S3-check-exclude.
7:6
Reserved. Read-write.
5:0
NOdtD: nmos ODT calibration data. Read-write; S3-check-exclude.
D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0] Data Byte 1.5X Pad Configuration
Cold reset: 0000_0033h. DBYTE.
Table 139: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_0004h
0D0F_0104h
0D0F_0204h
0D0F_0304h
0D0F_0404h
0D0F_0504h
0D0F_0604h
0D0F_0704h
0D0F_0804h
0D0F_0F04h
Bits
13
Function
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
ECC
D18F2x9C_x0D0F_0[8:0]04
Description
TriDM: tri-state DM. Read-write. BIOS: 2.9.7.10. Read-write. Specifies tri-state control for the
memory DM signal. 1=Signal is tri-stated. 0=Signal is not tri-stated.
339
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12
BKDG for AMD Family 16h Models 00h-0Fh Processors
POdtOff: processor ODT off. Read-write. BIOS: See 2.9.7.6.6. 1=Phy disables receiver pad termination. 0=Phy enables receiver pad termination. Hardware programs this field for the current M-state
(D18F2x9C_x0D00_E008_dct[0][PhyPS]) with the value in D18F2x94_dct[0][ProcOdtDis] (via
D18F2x9C_x0000_000B_dct[0][ProcOdtDis]) when the memory frequency is updated. See 2.9.7.4.2.
BIOS must reprogram this field after each frequency change if the target value differs from
D18F2x94_dct[0][ProcOdtDis].
11:0 Reserved. Read-write.
D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0] Data Byte Transmit PreDriver Calibration 2
Cold reset: xxxx_xxxxh. BIOS: See 2.9.7.4.4. DBYTE.
Table 140: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]06_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0806h 0706h 0606h 0506h 0406h 0306h 0206h 0106h 0006h
0D0Fh
ECC Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Table 141: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]0A_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
080Ah 070Ah 060Ah 050Ah 040Ah 030Ah 020Ah 010Ah 000Ah
0D0Fh
ECC Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Table 142: Broadcast Mapping for D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0F0Ah
0D0Fh
Bits
D18F2x9C_x0D0F_0[8:0]0A
0F06h
D18F2x9C_x0D0F_0[8:0]06
Description
11:6 TxPreP: PMOS predriver calibration code. Read-write. This field specifies the rising edge slew
rate of the transmit pad. See: D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]. After updating this
value, BIOS must program D18F2x9C_x0D0F_0[F,8:0]02_dct[0][ValidTxAndPre]=1 for the change
to take effect.
5:0
TxPreN: NMOS predriver calibration code. Read-write. This field specifies the falling edge slew
rate of the transmit pad. See: D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreN]. After updating this
value, BIOS must program D18F2x9C_x0D0F_0[F,8:0]02_dct[0][ValidTxAndPre]=1 for the change
to take effect.
D18F2x9C_x0D0F_0[F,8:0]10_dct[0]_mp[1:0] Data Byte DLL Power Management
Cold reset: 0000_0000h. DBYTE.
Table 143: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]10_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_0010h
0D0F_0110h
Function
Byte 0
Byte 1
340
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BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 143: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]10_dct[0]_mp[1:0]
0D0F_0210h
0D0F_0310h
0D0F_0410h
0D0F_0510h
0D0F_0610h
0D0F_0710h
0D0F_0810h
0D0F_0F10h
Bits
12
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 8-0
Description
EnRxPadStandby: enable receiver pad standby. Read-write. BIOS: See 2.9.7.7. 1=Phy receiver
standby mode is enabled to save power when not receiving data. 0=Phy receiver standby mode is disabled.
D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0] Data Byte DLL Configuration
Table 144: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_0013h
0D0F_0113h
0D0F_0213h
0D0F_0313h
0D0F_0413h
0D0F_0513h
0D0F_0613h
0D0F_0713h
0D0F_0813h
0D0F_0F13h
Bits
Function
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 8-0
Description
14
ProcOdtAdv: ProcOdt advance. Read-write. Cold reset: 1. BIOS: IF ((Solder-down DRAM ||
SODIMM) && DdrRate <= 1333) THEN 0 ELSE 1 ENDIF. 0=ProcOdt is asserted 1.5 PCLK before
DqsEn (pipeline, untimed). 1=If preceding write, ProcOdt is asserted 2.5 PCLK before DqsEn, else,
ProcOdt is asserted 5.0 PCLK before DqsEn. 45nm DDR phy asserted ProcOdt 1.0 PCLK before
DqsEn.
13
ExtraProcOdtAdv: extra ProcOdt advance. Read-write. Cold reset: 0. BIOS: 0. Reserved if ProcOdtAdv=0. 1=For a read without preceding read or write commands, ProcOdt is asserted with the
CAS command (rising edge of TxActive). 0=Extra ProcOdt is disabled.
12:9 Reserved. Read-write.
341
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BKDG for AMD Family 16h Models 00h-0Fh Processors
8
RxSsbMntClkEn: receive channel maintenance clock enable. Read-write. Cold reset: 0. BIOS:
2.9.7.10. 1=Enable receive channel maintenance clocks to improve internal timing margin at the cost
of some extra power. To enable clock generation, BIOS must first enable maintenance clocks in the
DCT (see D18F2x248_dct[0]_mp[1:0][RxChMntClkEn]). 0=Disable clocks. The maintenance clock
period is fixed at 8 PCLKs when no traffic occurs.
1
DllDisEarlyU: DLL disable early upper. Read-write. Cold reset: 0. BIOS: See 2.9.7.10. 1=Disable
upper receiver DQS DLL early timing for power savings.
0
DllDisEarlyL: DLL disable early lower. Read-write. Cold reset: 0. BIOS: See 2.9.7.10. 1=Disable
lower receiver DQS DLL early timing for power savings.
D18F2x9C_x0D0F_0[F,8:0]1C_dct[0]_mp[1:0] Data Byte DLL Power Management
Cold reset: 0000_0000h. DBYTE.
Table 145: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1C_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_001Ch
0D0F_011Ch
0D0F_021Ch
0D0F_031Ch
0D0F_041Ch
0D0F_051Ch
0D0F_061Ch
0D0F_071Ch
0D0F_081Ch
0D0F_0F1Ch
Bits
Function
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 8-0
Description
15
RxDllStggrEn: Rx DLL stagger enable. Read-write. BIOS: 2.9.7.10. 1=Insert RxDllStggrDly delay
prior to waking the receive DLLs from standby. 0=DLLs wake from standby at the default pendingactivity reference point.
14
Reserved.
13:8 RxDllStggrDly[5:0]: Rx DLL stagger delay. Read-write. BIOS: 2.9.7.10. Specifies the delay in
PCLK cycles from a CAS command or an internal DLL maintenance lock timing event before the
receive DLLs exit standby if the data bus is still idle. If data bus traffic is pending and the DLLs are in
standby then they wake immediately regardless of the delay value.
7
TxDllStggrEn: Tx DLL stagger enable. Read-write. BIOS: 2.9.7.10. 1=Insert TxDllStggrDly delay
prior to waking the transmit DLL from standby. 0=DLL wakes from standby at the default pendingactivity reference point.
6
Reserved.
5:0
TxDllStggrDly[5:0]: Tx DLL stagger delay. Read-write. BIOS: 0. BIOS: 2.9.7.10. Specifies the
delay in PCLK cycles from a CAS command or an internal DLL maintenance lock timing event
before the transmit DLL exits standby if the data bus is still idle. If data bus traffic is pending and the
DLL is in standby then it wakes immediately regardless of the delay value.
342
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BKDG for AMD Family 16h Models 00h-0Fh Processors
D18F2x9C_x0D0F_0[F,8:0]1E_dct[0]_mp[1:0] Data Byte Receiver Bias Current Control
Cold reset: 0000_5220h. DBYTE.
Table 146: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1E_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_001Eh
0D0F_011Eh
0D0F_021Eh
0D0F_031Eh
0D0F_041Eh
0D0F_051Eh
0D0F_061Eh
0D0F_071Eh
0D0F_081Eh
0D0F_0F1Eh
Bits
Function
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 8-0
Description
14:12 DllCSRBiasTrim: dll csr biast trim. Read-write. BIOS: 001b. The MSB bit adjusts the DAC current
profile that is used only by the delayline, which adjusts the tuning curve of the delayline. The remaining two bits affect the global bias current.
Bits
Description
000b
-25%
001b
Nominal
010b
+50%
011b
+100
100b
-25% + delayline adjust
101b
Nominal + delayline adjust
110b
+50% + delayline adjust
111b
+100 + delayline adjust
11:8 Reserved. Read-write.
7
Reserved. Read-write.
6:0
Reserved. Read-write.
D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0] Data Byte Receiver Configuration
Cold reset: 0000_2003h. DBYTE.
Table 147: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_001Fh
0D0F_011Fh
0D0F_021Fh
0D0F_031Fh
0D0F_041Fh
0D0F_051Fh
Function
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
343
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 147: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0]
0D0F_061Fh
0D0F_071Fh
0D0F_081Fh
0D0F_0F1Fh
Byte 6
Byte 7
Byte 8
Byte 8-0
Bits
Description
7:5
RxDqInsDly: receive DQ insertion delay. Read-write. BIOS: 2.9.7.9.4. This control adds insertion
delay to the Rx DQ path so that the delay through RxDqs+DLL insertion delay+Clk distribution better matches the DQ data propagation delay. Each stage expected to add 25 to 50 ps to DQ.
Bits
Description
000b
Min delay
001b
Delay 1
010b
Delay 2
011b
Max delay
111b-100b
Reserved
4:3
RxVioLvl: receiver voltage level. Read-write. BIOS: 2.9.7.4.1. Specifies the VDDIO voltage level.
Bits
Description
00b
1.5 V
01b
1.35 V
10b
1.25 V (Phy spec:1.2 V)
11b
Reserved
2:0
Reserved. Read-write.
D18F2x9C_x0D0F_0[F,8:0]2[3:0]_dct[0]_mp[1:0] Data Byte RxDqs DLL Configuration
Cold reset: 0000_0F0Fh. See D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0].
Table 148: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]2[3:0]_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_0020h
0D0F_0120h
0D0F_0220h
0D0F_0320h
0D0F_0420h
0D0F_0520h
0D0F_0620h
0D0F_0720h
0D0F_0820h
0D0F_0F20h
0D0F_0021h
0D0F_0121h
0D0F_0221h
0D0F_0321h
0D0F_0421h
Function
DIMM/CS 0 Byte 0
DIMM/CS 0 Byte 1
DIMM/CS 0 Byte 2
DIMM/CS 0 Byte 3
DIMM/CS 0 Byte 4
DIMM/CS 0 Byte 5
DIMM/CS 0 Byte 6
DIMM/CS 0 Byte 7
DIMM/CS 0 Byte 8
DIMM/CS 0 Byte 8-0
DIMM/CS 1 Byte 0
DIMM/CS 1 Byte 1
DIMM/CS 1 Byte 2
DIMM/CS 1 Byte 3
DIMM/CS 1 Byte 4
344
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 148: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]2[3:0]_dct[0]_mp[1:0]
0D0F_0521h
0D0F_0621h
0D0F_0721h
0D0F_0821h
0D0F_0F21h
0D0F_0022h
0D0F_0122h
0D0F_0222h
0D0F_0322h
0D0F_0422h
0D0F_0522h
0D0F_0622h
0D0F_0722h
0D0F_0822h
0D0F_0F22h
0D0F_0023h
0D0F_0123h
0D0F_0223h
0D0F_0323h
0D0F_0423h
0D0F_0523h
0D0F_0623h
0D0F_0723h
0D0F_0823h
0D0F_0F23h
DIMM/CS 1 Byte 5
DIMM/CS 1 Byte 6
DIMM/CS 1 Byte 7
DIMM/CS 1 Byte 8
DIMM/CS 1 Byte 8-0
Reserved/CS 2 Byte 0
Reserved/CS 2 Byte 1
Reserved/CS 2 Byte 2
Reserved/CS 2 Byte 3
Reserved/CS 2 Byte 4
Reserved/CS 2 Byte 5
Reserved/CS 2 Byte 6
Reserved/CS 2 Byte 7
Reserved/CS 2 Byte 8
Reserved/CS 2 Byte 8-0
Reserved/CS 3 Byte 0
Reserved/CS 3 Byte 1
Reserved/CS 3 Byte 2
Reserved/CS 3 Byte 3
Reserved/CS 3 Byte 4
Reserved/CS 3 Byte 5
Reserved/CS 3 Byte 6
Reserved/CS 3 Byte 7
Reserved/CS 3 Byte 8
Reserved/CS 3 Byte 8-0
If D18F2xA8_dct[0][PerRankTimingEn]=1 then the function is CS. Otherwise the function is DIMM.
Bits
Description
12:8 RdDqsTimeU: read DQS timing control upper nibble. Read-write.
Bits
Description
1Fh-00h
<RdDqsTimeU>/64 MEMCLK delay
7:5
Reserved. Read-write.
4:0
RdDqsTimeL: read DQS timing control lower nibble. Read-write.
Bits
Description
1Fh-00h
<RdDqsTimeL>/64 MEMCLK delay
D18F2x9C_x0D0F_0[8:0]2[9:4]_dct[0]_mp[1:0] Data Byte DLL Configuration
Cold reset: 0000_0000h. Updated by hardware during 2.9.7.4.3 [Phy Fence Programming].
Bits
Description
31:16 Reserved.
15
FenceBitO: fence bit odd. Read-write.
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BKDG for AMD Family 16h Models 00h-0Fh Processors
Fence2BitO: fence2 bit odd. Read-write.
13:8 Reserved. Read-write.
7
FenceBitE: fence bit even. Read-write.
6
Fence2BitE: fence2 bit even. Read-write.
5:0
Reserved. Read-write.
D18F2x9C_x0D0F_0[F,8:0]30_dct[0] Data Byte DLL Configuration and Power Down
Cold reset: 0000_0001h. DBYTE.
Table 149: Index Addresses for D18F2x9C_x0D0F_0[F,8:0]30_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0830h 0730h 0630h 0530h 0430h 0330h 0230h 0130h 0030h
0D0Fh
ECC
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Table 150: Broadcast Write Index Address for D18F2x9C_x0D0F_0[F,8:0]30_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0F30h
0D0Fh
Bits
D18F2x9C_x0D0F_0[8:0]30
Description
9
TxPclkGateEn: tx pclk gating enable. Read-write. BIOS: 2.9.7.10. 1=DQS TX data pipe PCLK
gating is enabled. 0=PCLK gating disabled.
8
BlockRxDqsLock: block rx dqs lock. Read-write. BIOS: 2.9.7.9.3. Specifies how the receive DLLs
lock. 1=Lock on PCLK. 0=Lock on both PCLK and the received DQS
7
PchgPdPClkGateEn: precharge powerdown pclk gating enable. Read-write. BIOS: 2.9.7.10.
1=DByte datapipe PCLK gating is enabled. 0=PCLK gating disabled.
6
DataCtlPipePclkGateEn: data control pipe pclk gating enable. Read-write. BIOS: 2.9.7.10.
1=Data control pipe PCLK gating is enabled. 0=PCLK gating disabled.
4
PwrDn: power down. Read-write. BIOS: 2.9.7.10. 1=Turn off DLL circuitry (DLLs, pads, bias macros, regulator).
3:0
Reserved. Read-write.
D18F2x9C_x0D0F_0[F,8:0]31_dct[0] Data Byte Fence2 Threshold
BIOS: 2.9.7.4.3. DBYTE.
Table 151: Index addresses for D18F2x9C_x0D0F_0[F,8:0]31_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0831h 0731h 0631h 0531h 0431h 0331h 0231h 0131h 0031h
0D0Fh
ECC Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
346
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 152: Broadcast write index address for D18F2x9C_x0D0F_0[F,8:0]31_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0F31h
0D0Fh
Bits
D18F2x9C_x0D0F_0[8:0]31
Description
31:10 Reserved.
9
Fence2EnableTxDll: phy fence2 enable transmit DLL. Read-write. Cold reset: 0. 1=Enable the use
of Fence2ThresholdTxDll for transmit DLL fence threshold. 0=Use
D18F2x9C_x0000_000C_dct[0][FenceThresholdTxDll].
8:5
Fence2ThresholdTxDll: phy fence2 threshold transmit DLL. Read-write. Cold reset: 0. If
Fence2EnableTxDll=1, this field specifies the fence delay threshold value used to create the fence bit
in the DLL delay registers for DQS receiver valid. This field is only used during DQS receiver enable
training to time the internal phy signal RxValid. See Fence2ThresholdTxPad.
4
3:0
Fence2EnableTxPad: fence2 enable transmit pad. Read-write; S3-check-exclude. Cold reset: 0.
1=Enable the use of Fence2ThresholdTxPad for transmit pad fence threshold. 0=Use
D18F2x9C_x0000_000C_dct[0][FenceThresholdTxPad].
Fence2ThresholdTxPad: phy fence2 threshold transmit pad. Read-write; S3-check-exclude. Cold
reset: 0. If Fence2EnableTxPad=1, this field specifies the fence delay threshold value used to create
the fence bit in the DLL delay registers for write data and write DQS. This field is only used during
write levelization training. The corresponding fence bit is set by hardware when the DLL delay register is written if DLL delay >= FenceThresholdTxPad.
Bits
Definition
0h
No delay
1h
1/64 MEMCLK delay
Eh-2h
<Fence2ThresholdTxPad> MEMCLK delay
Fh
15/64 MEMCLK delay
D18F2x9C_x0D0F_0[F,8:0]38_dct[0] Data Byte DLL Control Register
DBYTE.
Table 153: Index addresses for D18F2x9C_x0D0F_0[F,8:0]38_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0838h 0738h 0638h 0538h 0438h 0338h 0238h 0138h 0038h
0D0Fh
ECC Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
Table 154: Broadcast write index address for D18F2x9C_x0D0F_0[F,8:0]38_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
0F38h
0D0Fh
D18F2x9C_x0D0F_0[8:0]38
347
48751 Rev 3.00 - May 30, 2013
Bits
BKDG for AMD Family 16h Models 00h-0Fh Processors
Description
31:16 Reserved.
15
Reserved. Read-write.
14:13 ReducedLoop: reduced loop. Read-write. Cold reset: 0. Specifies additional delay imposed before
the phase comparator, which has the effect of locking the DLL to a shorter period.
Bits
Description
00b
No delay.
01b
1/3 maximum additional delay
10b
2/3 maximum additional delay
11b
Maximum additional delay
12:0 Reserved. Read-write.
D18F2x9C_x0D0F_1C00_dct[0] Clock Transmit PreDriver Calibration
Cold reset: xxxx_xxxxh. D3DBYTE.
Table 155: Broadcast write index address for D18F2x9C_x0D0F_1C00_dct[0]
D18F2x98_dct[0][31:16]
D18F2x98_dct[0][15:0]
1C00h
0D0Fh
Bits
D18F2x9C_x0D0F_0[F,8:0]0[B,7,
3]_dct[0]
Description
13:8 POdtD: pmos ODT calibration data. Write-only.
7:6
Reserved.
5:0
NOdtD: nmos ODT calibration data. Write-only.
D18F2x9C_x0D0F_2[2:0]02_dct[0] Clock Transmit PreDriver Calibration
Cold reset: xxxx_xxxxh. BIOS: See 2.9.7.4.4. D3CLK.
Table 156: Index Mapping for D18F2x9C_x0D0F_2[2:0]02_dct[0]
D18F2x98_dct[0][31:0]
0D0F_2002h
0D0F_2102h
0D0F_2202h
Bits
Function
Clock 0 Pad Group 0
Clock 1 Pad Group 0
Reserved
Description
31:16 Reserved.
15
ValidTxAndPre: predriver calibration code valid. Read-write; cleared-by-hardware. 1=Predriver
calibration codes are copied from this register into the associated transmit pad. Hardware clears this
field after the copy is complete.
14:12 Reserved. Read-write.
348
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BKDG for AMD Family 16h Models 00h-0Fh Processors
11:6 TxPreP: PMOS predriver calibration code. Read-write. This field specifies the rising edge slew
rate of the transmit pad. See: D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]. After updating this
value, BIOS must program ValidTxAndPre=1 for the change to take effect.
5:0
TxPreN: NMOS predriver calibration code. Read-write. This field specifies the falling edge slew
rate of the transmit pad. See: D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreN]. After updating this
value, BIOS must program ValidTxAndPre=1 for the change to take effect.
D18F2x9C_x0D0F_[C,8,2][2:0]1E_dct[0]_mp[1:0] Phy Control
Cold reset: 0000_5020h. ABYTE2, D3CSODT, D3CLK.
Table 157: Index address mapping for D18F2x9C_x0D0F_[C,8,2][2:0]1E_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_201Eh
0D0F_211Eh
0D0F_221Eh
0D0F_801Eh
0D0F_811Eh
0D0F_821Eh
0D0F_C01Eh
0D0F_C11Eh
0D0F_C21Eh
Bits
7
6:0
Function
Clock 0
Clock 1
Reserved
Cmd/Addr 0
Cmd/Addr 1
Reserved
Address
Reserved
Reserved
Description
Reserved.
Reserved. Read-write.
D18F2x9C_x0D0F_[C,8,2][2:0]1F_dct[0] Receiver Configuration
Cold reset: 0000_2000h. ABYTE2, D3CSODT, D3CLK.
Table 158: Index address mapping for D18F2x9C_x0D0F_[C,8,2][2:0]1F_dct[0]
D18F2x98_dct[0][31:0]
0D0F_201Fh
0D0F_211Fh
0D0F_221Fh
0D0F_801Fh
0D0F_811Fh
0D0F_821Fh
0D0F_C01Fh
0D0F_C11Fh
0D0F_C21Fh
Function
Clock 0
Clock 1
Reserved
Cmd/Addr 0
Cmd/Addr 1
Reserved
Address
Reserved
Reserved
349
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Bits
Description
4:3
RxVioLvl: receiver voltage level. Read-write. BIOS: See 2.9.7.4.1. Specifies the VDDIO voltage
level.
Description
Bits
00b
1.5 V
01b
1.35 V
10b
1.25 V (Phy spec:1.2 V)
11b
Reserved
2:0
Reserved. Read-write.
D18F2x9C_x0D0F_[C,8,2][2:0]20_dct[0]_mp[1:0] DLL Delay and Configuration
Cold reset: 0000_8000h. ABYTE2, D3CSODT, D3CLK. Updated by hardware during 2.9.7.4.3 [Phy Fence
Programming].
Table 159: Index Addresses for D18F2x9C_x0D0F_[C,8,2][2:0]20_dct[0]_mp[1:0]
D18F2x98_dct[0][31:0]
0D0F_2020h
0D0F_2120h
0D0F_2220h
0D0F_8020h
0D0F_8120h
0D0F_8220h
0D0F_C020h
0D0F_C120h
0D0F_C220h
Bits
Function
Clock 0
Clock 1
Reserved
Cmd/Addr 0
Cmd/Addr 1
Reserved
Address
Reserved
Reserved
Description
31:16 Reserved.
15
Reserved. Read-write.
13:8 Reserved. Read-write.
7
FenceBit: fence bit. Read-write.
6
Fence2Bit: fence2 bit. Read-write.
5:0
Reserved. Read-write.
D18F2x9C_x0D0F_2[F,2:0]30_dct[0] Clock DLL Configuration and Power Down
Cold reset: 0000_0001h. D3CLK.
Table 160: Index Addresses for D18F2x9C_x0D0F_2[F,2:0]30_dct[0]
D18F2x98_dct[0][31:0]
0D0F_2030h
0D0F_2130h
0D0F_2230h
0D0F_2F30h
Function
Clock 0
Clock 1
Reserved
Clock 1-0
350
48751 Rev 3.00 - May 30, 2013
Bits
BKDG for AMD Family 16h Models 00h-0Fh Processors
Description
31:16 Reserved.
15:5 Reserved. Read-write.
4
3:0
PwrDn: power down. Read-write. 1=Turn off DLL circuitry (DLLs, pads, bias macros, regulator).
Reserved. Read-write.
D18F2x9C_x0D0F_4006_dct[0] DRAM Phy MemVref Observation Configuration
Cold reset: 0000_0002h. D3CMP.
Bits
Description
31:16 Reserved.
15:9 Reserved. Read-write.
2:0
VrefSel: vref selection. Read-write.
Bits
Description
000b
Connections to the bump and internal VREF bus are driven tri-state.
001b
Internal Rx. VrefDAC is sent to the DQ receivers; pad connection is tri-state.
010b
External Rx. External Vref from the pad is sent to the DQ receivers.
011b
Internal Tx. VrefDAC is sent out on the pad; internal connection is tri-state.
110b-100b
Reserved.
111b
Internal Rx & Tx. VrefDAC is sent to all the DQ receivers and pad.
D18F2x9C_x0D0F_4007_dct[0] DRAM Phy MemVref Configuration
Cold reset: 0000_0002h. D3CMP.
Bits
Description
31:16 Reserved.
15:9 Reserved. Read-write.
8:3
VrefDAC: vref DAC. Read-write. Controls the relative offset for the internal generated Vref from
nominal VDDIO/2.
Bits
Description
1Eh-00h
<VrefDAC>%
20h-1Fh
Reserved
3Eh-21h
20h - <VrefDAC>%
3Fh
Reserved
2:0
VrefSel: vref selection. Read-write.
Bits
Description
000b
Reseved.
001b
Internal Rx. VrefDAC is sent to the DQ receivers; pad connection is tri-state.
010b
External Rx. External Vref from the pad is sent to the DQ receivers.
011b
Internal Tx. VrefDAC is sent out on the pad; internal connection is tri-state.
110b-100b
Reserved.
111b
Internal Rx & Tx. VrefDAC is sent to all the DQ receivers and pad.
351
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
D18F2x9C_x0D0F_4009_dct[0] Phy Cmp MemReset Configuration
Cold reset: 0000_2000h. D3CMP.
Bits
Description
31:16 Reserved.
15:14 CmpVioLvl: cmp voltage level. Read-write. BIOS: See 2.9.7.4.1. This field specifies the VDDIO
voltage level.
Bits
Description
00b
1.5 V
01b
1.35 V
10b
1.25 V (Phy spec:1.2 V)
11b
Reserved
13:4
Reserved. Read-write.
3:2
ComparatorAdjust: comparator adjust. Read-write. BIOS:
D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0][RxVioLvl]. This field specifies the adjustment signals for the comparator differential amplifier in madpcmpana.
1:0
Reserved. Read-write.
D18F2x9C_x0D0F_[C,8][1:0]02_dct[0] Transmit PreDriver Calibration
Cold reset: xxxx_xxxxh. BIOS: See 2.9.7.4.4. ABYTE2, D3CSODT.
Table 161: Index Mapping for D18F2x9C_x0D0F_[C,8][1:0]02_dct[0]
D18F2x98_dct[0][31:0]
0D0F_8002h
0D0F_8102h
0D0F_C002h
Bits
Function
Cmd/Addr 0 Pad Group 0
Cmd/Addr 1 Pad Group 0
Address Pad Group 0
Description
31:16 Reserved.
15
ValidTxAndPre: predriver calibration code valid. Read-write; cleared-by-hardware. 1=Predriver
calibration codes are copied from this register and
D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0] into the associated transmit pad. Hardware
clears this field after the copy is complete.
14:12 Reserved. Read-write.
11:6 TxPreP: PMOS predriver calibration code. Read-write. This field specifies the rising edge slew
rate of the transmit pad. See: D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]. After updating this
value, BIOS must program ValidTxAndPre=1 for the change to take effect.
5:0
TxPreN: NMOS predriver calibration code. Read-write. This field specifies the falling edge slew
rate of the transmit pad. See: D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreN]. After updating this
value, BIOS must program ValidTxAndPre=1 for the change to take effect.
D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0] Transmit PreDriver Calibration 2
Cold reset: xxxx_xxxxh. BIOS: See 2.9.7.4.4. ABYTE2, D3CSODT.
352
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
Table 162: Index Mapping for D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0]
D18F2x98_dct[0][31:0]
0D0F_8006h
0D0F_800Ah
0D0F_8106h
0D0F_810Ah
0D0F_C006h
0D0F_C00Ah
0D0F_C00Eh
0D0F_C012h
Bits
Function
Cmd/Addr 0 Pad Group 1
Cmd/Addr 0 Pad Group 2
Cmd/Addr 1 Pad Group 1
Cmd/Addr 1 Pad Group 2
Address Pad Group 1
Address Pad Group 2
Address Pad Group 3
Address Pad Group 4
Description
11:6 TxPreP: PMOS predriver calibration code. Read-write. This field specifies the rising edge slew
rate of the transmit pad. See: D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]. After updating this
value, BIOS must program D18F2x9C_x0D0F_[C,8][1:0]02_dct[0][ValidTxAndPre]=1 for the
change to take effect.
5:0
TxPreN: NMOS predriver calibration code. Read-write. This field specifies the falling edge slew
rate of the transmit pad. See: D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreN]. After updating this
value, BIOS must program D18F2x9C_x0D0F_[C,8][1:0]02_dct[0][ValidTxAndPre]=1 for the
change to take effect.
D18F2x9C_x0D0F_812F_dct[0] Tristate Configuration
Reset: 0000_00A0h. BIOS: See 2.9.7.10. D3CSODT.
Bits
Description
7
Add16Tri: MEMADD[16] tri-state. Read-write. Specifies tri-state control for the memory
address[16] signal. 1=Signal is tri-stated. 0=Signal is not tri-stated.
6
Reserved. Read-write.
5
Add17Tri: MEMADD[17] tri-state. Read-write. Specifies tri-state control for the memory
address[17] signal. 1=Signal is tri-stated. 0=Signal is not tri-stated.
4:1
0
Reserved. Read-write.
PARTri: MEMPAR tri-state. Read-write. Specifies tri-state control for the memory parity signal.
1=Signal is tri-stated. 0=Signal is not tri-stated.
D18F2x9C_x0D0F_[C,8][F:0]30_dct[0] Cmd/Addr DLL Configuration and Power Down
Cold reset: 0000_0001h. BIOS: See 2.9.7.4.4. ABYTE2, D3CSODT.
Table 163: Index Mapping for D18F2x9C_x0D0F_[C,8][F:0]30_dct[0]
D18F2x98_dct[0][31:0]
Function
0D0F_8030h
Cmd/Addr 0
0D0F_8130h
Cmd/Addr 1
0D0F_8F30h
Cmd/Addr 0 and Cmd/Addr 1
0D0F_C030h
Address 2
353
48751 Rev 3.00 - May 30, 2013
Bits
BKDG for AMD Family 16h Models 00h-0Fh Processors
Description
31:16 Reserved.
15:5 Reserved. Read-write.
4
3:0
PwrDn: power down. Read-write. 1=Turn off DLL circuitry (DLLs, pads, bias macros, regulator).
Reserved. Read-write.
D18F2x9C_x0D0F_C021_dct[0]_mp[1:0] DLL Delay and Configuration
Cold reset: 0000_0000h. ABYTE2. Updated by hardware during 2.9.7.4.3 [Phy Fence Programming].
Bits
Description
31:16 Reserved.
15:8 Reserved. Read-write.
7
FenceBit: fence bit. Read-write.
6
Fence2Bit: fence2 bit. Read-write.
5:0
Reserved. Read-write.
D18F2x9C_x0D0F_E000_dct[0]_mp[1:0] Phy Master Configuration
Cold reset: 0000_0002h. MASTER.
Bits
Description
31:16 Reserved.
15:14 Rate[4:3]. See: Rate[2:0].
13:4 Reserved. Read-write.
3
FreqValid: Frequency valid. Read-write. 1=The memory frequency specified with the Rate field is
valid. software must set this bit when programming Rate for the setting to take effect. Regardless of
this bit, a new rate does not take effect unless the target register context is of the current memory Pstate, or until the memory P-state is changed to the target Rate context.
2:0
Rate[2:0]. Read-write. Rate[4:0] = {Rate[4:3], Rate[2:0]}. Rate[4:0] is the 5-bit DDR data rate that
the phy uses to configure the PLL. See Table 124 [Valid Values for Memory Clock Frequency Value
Definition]. Software must set FreqValid=1 when programming this field. If memory P-states are
enabled then software must program the M1 context. It is not necessary for software to program the
M0 context when using D18F2x94_dct[0][MemClkFreqVal].
D18F2x9C_x0D0F_E006_dct[0] Phy PLL Lock Time
Cold reset: 0000_0190h. MASTER.
Bits
Description
31:16 Reserved.
15:0 PllLockTime: pll lock time. Read-write. Specifies the number of 5ns periods the phy waits for PLLs
to lock during a frequency change. See 2.9.7.4.2 [DRAM Channel Frequency Change].
354
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
D18F2x9C_x0D00_E008_dct[0] Phy Master Configuration
Cold reset: 0000_0013h. MASTER.
Bits
Description
31:13 Reserved.
12
PhyPS: Phy memory P-state. Read-only; updated-by-hardware. Indicates the current memory Pstate for the phy (not the DCT/NB). 0=M0. 1=M1. Writes to this nibble cause a PhyPS change.
11:5 Reserved.
4:0
FenceValue: fence value. Read-only; updated-by-hardware. Indicates the fence value used to create
the fence bit in the DLL delay registers. See 2.9.7.4.3 [Phy Fence Programming].
D18F2x9C_x0D04_E008_dct[0] Phy Master Configuration
Cold reset: 0000_0013h. MASTER.
Bits
Description
31:9 Reserved.
8
7:0
PStateToAccess: P-state to access. Read-write. Specifies the memory P-state context for context
sensitive DDR phy CSR accesses using D18F2x98_dct[0] when DctOffset[29:20]!=0D0h. 0=M0,
1=M1. The processor updates this field during a memory P-state change with the target state. See
D18F2x94_dct[0][DphyMemPsSelEn].
Reserved. Read-write; S3-check-exclude.
D18F2x9C_x0D0F_E00A_dct[0] Phy Dynamic Power Mode
Cold reset: 0000_0000h. MASTER.
Bits
Description
4
Reserved. Read-write.
3:0
Reserved. Read-write.
D18F2x9C_x0D0F_E013_dct[0] Phy PLL Regulator Wait Time
Cold reset: 0000_0118h. MASTER.
Bits
Description
31:16 Reserved.
15:0 PllRegWaitTime: PLL regulator wait time. Read-write. BIOS: 2.9.7.4. 1=Specifies the number of
5 ns periods the phy waits for the PLL to become stable when coming out of PLL regulator off power
down mode.
D18F2x9C_x0D0F_E019_dct[0] Fence2
Cold reset: 0000_0000h. BIOS: 2.9.7.4.3. MASTER.
355
48751 Rev 3.00 - May 30, 2013
Bits
BKDG for AMD Family 16h Models 00h-0Fh Processors
Description
31:15 Reserved.
14
Fence2EnableRxDll: phy fence2 enable receive DLL. Read-write. 1=Enable the use of
Fence2ThresholdRxDll for DQS receiver enable second fence threshold. 0=Disable second fence. See
D18F2x9C_x0000_000C_dct[0][FenceThresholdRxDll] for first fence.
13:10 Fence2ThresholdRxDll: phy fence2 threshold DQS receiver enable. Read-write. If
Fence2EnableRxDll=1, this field specifies the fence delay threshold value used to create the second
fence bit in the DLL delay registers for DQS receiver enable. See Fence2ThresholdTxPad.
9:5
4
3:0
Reserved.
Fence2EnableTxPad: fence2 enable transmit pad. Read-write. 1=Enable the use of
Fence2ThresholdTxPad for transmit pad second fence threshold. 0=Disable second fence. See
D18F2x9C_x0000_000C_dct[0][FenceThresholdTxPad] for first fence.
Fence2ThresholdTxPad: phy fence2 threshold transmit pad. Read-write. If
Fence2EnableTxPad=1, this field specifies the second fence delay threshold value used to create the
second fence bit (fence2) in the DLL delay registers for CLK, command, address, write data and write
DQS. The corresponding fence2 bit is set by hardware when the DLL delay register is written if DLL
delay >={1’b1, Fence2ThresholdTxPad}.
Bits
Definition
0h
16/64 MEMCLK delay
1h
17/64 MEMCLK delay
Eh-2h
{1,<Fence2ThresholdTxPad>}/64 MEMCLK delay
Fh
31/64 MEMCLK delay
D18F2x9C_x0D0F_E01A_dct[0] M1 Fence Value
Cold reset: 0000_0000h. BIOS: 2.9.7.4.3. MASTER. This register is used by BIOS to temporarily store the
trained fence values for the M1 memory P-state, and has no effect on the operation of the hardware. See
2.9.7.4.3. Note: fence2 value is recomputed by BIOS based on the fence value saved here.
Bits
Description
31:16 Reserved.
15
Reserved. Read-write.
14:10 TxDll: Transmit dll fence value. Read-write; S3-check-exclude. BIOS saves the trained TxDll to
this field until such time as it is able to write the value to NVRAM.
9:5
RxDll: Receiver dll fence value. Read-write; S3-check-exclude. BIOS saves the trained RxDll to this
field until such time as it is able to write the value to NVRAM.
4:0
TxPad: Transmit pad fence value. Read-write; S3-check-exclude. BIOS saves the trained TxPad to
this field until such time as it is able to write the value to NVRAM.
356
48751 Rev 3.00 - May 30, 2013
BKDG for AMD Family 16h Models 00h-0Fh Processors
D18F2xA4 DRAM Controller Temperature Throttle
See 2.9.3 [DCT Configuration Registers]. Writes to any DCT will be broadcast to all DCTs since this logic is
per DCT instance. Reads will return DCT0 result.
See 2.9.12 [DRAM On DIMM Thermal Management and Power Capping]. Independent channel throttling
may still be observed by having separate EVENT_L values.
Bits
Description
31:24 Reserved.
23:20 BwCapCmdThrottleMode: bandwidth capping command throttle mode. Read-write. Reset: 0.
Specifies the command throttle mode when BwCapEn=1. The DCT throttles commands over a rolling
window of 100 clock cycles, maintaining the average throttling as specified by this field.
MSRC001_0079[BwCapCmdThrottleMode] is an alias of D18F2xA4[BwCapCmdThrottleMode].
Description
Bits
0000b
Command throttling is disabled
0001b
Throttle commands by 30%
0010b
Throttle commands by 40%
0011b
Throttle commands by 50%
0100b
Throttle commands by 55%
0101b
Throttle commands by 60%
0110b
Throttle commands by 65%
0111b
Throttle commands by 70%
1000b
Throttle commands by 75%
1001b
Throttle commands by 80%
1010b
Throttle commands by 85%
1011b
Throttle commands by 90%
1100b
Throttle commands by 95%
1101b
Reserved
1110b
Throttle commands as specified by CmdThrottleMode
1111b
Reserved
Throttling should not be enabled until after DRAM initialization (D18F2x110[DramEnable]=1) and
training (see 2.9.7.9 [DRAM Training]) are complete. See MSRC001_0079.
19:15 Reserved.
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14:12 CmdThrottleMode: command throttle mode. Read-write. Reset: 0. BIOS: See 2.9.7.7 [DCT Training Specific Configuration]. Specifies the command throttle mode when ODTSEn=1 and the
EVENT_L pin is asserted. The DCT throttles commands over a rolling window of 100 clock cycles,
maintaining the average throttling as specified by this field.
Description
Bits
000b
Command throttling is disabled.
001b
Throttle commands by 30%.
010b
Throttle commands by 50%.
011b
Throttle commands by 60%.
100b
Throttle commands by 70%.
101b
Throttle commands by 80%.
110b
Throttle commands by 90%.
111b
Place the DRAM devices in powerdown mode (see D18F2x94_dct[0][PowerDownMode]) when EVENT_L is asserted. This mode is not valid if
D18F2x94_dct[0][PowerDownEn]=0.
Throttling should not be enabled until after DRAM initialization (D18F2x110[DramEnable]=1) and
training (See 2.9.7.9 [DRAM Training]) are complete. See also BwCapEn.
11
BwCapEn: bandwidth capping enable. Read-write. Reset: 0. 1=The memory command throttle
mode specified by BwCapCmdThrottleMode is applied.
This bit is used by software to enable command throttling independent of the state of the EVENT_L
pin. If this bit is set, ODTSEn=1, and the EVENT_L pin is asserted, the larger of the two throttle percentages specified by CmdThrottleMode and BwCapCmdThrottleMode is used.
See MSRC001_0079.
10:9 Reserved.
8
7:0
ODTSEn: on DIMM temperature sensor enable. Read-write. Reset: 0.
BIOS: See 2.9.7.7 [DCT Training Specific Configuration].
Enables the monitoring of the EVENT_L pin and indicates whether the on DIMM temperature sensors of the DIMMs on a channel are enabled. 0=Disabled. 1=Enabled. While the EVENT_L pin is
asserted, the controller (a) doubles the refresh rate (if Tref=7.8 us), and (b) throttles the address bus
utilization as specified by CmdThrottleMode[2:0].
Reserved.
D18F2xA8_dct[0] DRAM Controller Miscellaneous 2
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31
PerRankTimingEn: per rank timing enable. Read-write. Reset: 0. BIOS: 1. Specifies the mapping
between chip selects and a set of programmable timing delays. 1=Each chip select is controlled by a
set of timing delays. A maximum of 4 chip selects are supported per channel. 0=Each chip select pair
is controlled by a set timing delays.
30
Reserved. Read-write. Defined as ExtAddrEn.
29
Reserved. Read-write. Defined as RefChCmdMgmtDis.
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FastSelfRefEntryDis: fast self refresh entry disable. Read-write; Same-for-all. Reset: 1. BIOS:
~D18F2x1B4[FlushWrOnS3StpGnt]. 1=DCT pushes outstanding transactions to memory prior to
entering self refresh. 0=DCT enters self refresh immediately unless instructed to push outstanding
transactions to memory by D18F2x11C[FlushWrOnStpGnt] or D18F2x1B4[FlushWrOnS3StpGnt].
27:26 Reserved. Read-write.
25:24 Reserved.
22
PrtlChPDEnhEn: partial channel power down enh enable. Read-write. Reset: 0. BIOS: 0. Selects
the channel idle hysteresis for fast exit/slow exit mode changes when (D18F2x94_dct[0][PowerDownMode] & D18F2x84_dct[0][PchgPDModeSel]). 1=Hysteresis specified by
D18F2x244_dct[0][PrtlChPDDynDly]. 0=256 clock hysteresis.
21
AggrPDEn: aggressive power down enable. Read-write. Reset: 0. BIOS: 1. 1=The DCT places the
DRAM devices in precharge power down mode when pages are closed as specified by
D18F2x248_dct[0]_mp[1:0][AggrPDDelay]. 0=The DCT places the DRAM devices in precharge
power down mode when pages are closed as specified by D18F2x90_dct[0][DynPageCloseEn].
20
BankSwap: swap bank address. Read-write. Reset: 0. BIOS: See 2.9.7.7. 1=Swap the DRAM bank
address bits. The normalized address bits used for bank address are swapped with lower order address
bits. If D18F2x114[DctSelBankSwap]==1 then normalized address bits 10:8 are swapped else normalized address bits 11:9 are swapped. See D18F2x80_dct[0]. This swap happens before
D18F2x94_dct[0][BankSwizzleMode] is applied.
17:16 MemPhyPllPdMode: memory phy PLL powerdown mode. Read-write; Same-for-all. Reset: 00b.
BIOS: 10b. These bits control how the memory PLL powers down during self-refresh. If self-refresh
is requested for an NB p-state change, then thememory PLL is not powered down. These bits are sent
to phy 0x0B[25:24] by SR SM. Memory phy PLL powerdown can only be enabled if NB PLL power
down is enabled. See D18F5x128[NbPllPwrDwnRegEn].
Bits
Description
00b
PLL powerdown is disabled
01b
PLL VCO powerdown during SR
10b
PLL regulator powerdown during SR
11b
PLL VCO and regulator powerdown during SR
15:8 Reserved. Read-write.
7:6
Reserved. Read-write.
5
Reserved. Read-write.
4
Reserved. Read-write..
3:2
Reserved. Read-write.
1:0
Reserved.
D18F2xAC DRAM Controller Temperature Status
Cold reset: 0000_0000h.
Bits
Description
31:8 Reserved.
7:4
Reserved.
3:2
Reserved.
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1
Reserved. Read-write. Deprecated MemTrip0.
0
MemTempHot0: Memory temperature hot, DCT0. Read; Write-1-to-clear. 1=The EVENT_L pin
was asserted indicating the memory temperature exceeded the normal operating limit; the DCT may
be throttling the interface to aid in cooling. See D18F2xA4.
D18F2xF8 P-state Power Information 1
Read-only.
Bits
Description
31:24 PwrValue3: P3 power value. See PwrValue0. Value: Fuse[PwrValue[3][7:0]].
23:16 PwrValue2: P2 power value. See PwrValue0. Value: Fuse[PwrValue[2][7:0]].
15:8 PwrValue1: P1 power value. See PwrValue0. Value: Fuse[PwrValue[1][7:0]].
7:0
PwrValue0: P0 power value. PwrValue and PwrDiv together specify the expected power draw of a
single core in P0 and 1/NumCores of the Northbridge in the NB P-state as specified by
MSRC001_00[6B:64][NbPstate]. NumCores is defined to be the number of cores per node at cold
reset. Value: Fuse[PwrValue[0][7:0]].
PwrDiv
Description
00b
PwrValue / 1 W, Range: 0 to 255 W
01b
PwrValue / 10 W, Range: 0 to 25.5 W
10b
PwrValue / 100 W, Range: 0 to 2.55 W
11b
Reserved
D18F2xFC P-state Power Information 2
Read-only.
Bits
Description
31:24 Reserved.
23:22 PwrDiv7: P7 power divisor. See D18F2xF8[PwrValue0]. Value: Fuse[PwrDiv[7][1:0]].
21:20 PwrDiv6: P6 power divisor. See D18F2xF8[PwrValue0]. Value: Fuse[PwrDiv[6][1:0]].
19:18 PwrDiv5: P5 power divisor. See D18F2xF8[PwrValue0]. Value: Fuse[PwrDiv[5][1:0]].
17:16 PwrDiv4: P4 power divisor. See D18F2xF8[PwrValue0]. Value: Fuse[PwrDiv[4][1:0]].
15:14 PwrDiv3: P3 power divisor. See D18F2xF8[PwrValue0]. Value: Fuse[PwrDiv[3][1:0]].
13:12 PwrDiv2: P2 power divisor. See D18F2xF8[PwrValue0]. Value: Fuse[PwrDiv[2][1:0]].
11:10 PwrDiv1: P1 power divisor. See D18F2xF8[PwrValue0]. Value: Fuse[PwrDiv[1][1:0]].
9:8
PwrDiv0: P0 power divisor. See D18F2xF8[PwrValue0]. Value: Fuse[PwrDiv[0][1:0]].
7:0
PwrValue4: P4 power value. See D18F2xF8[PwrValue0]. Value: Fuse[PwrValue[4][7:0]].
D18F2x104 P-state Power Information 3
Read-only.
Bits
Description
31:24 Reserved.
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23:16 PwrValue7: P7 power value. See D18F2xF8[PwrValue0]. Value: Fuse[PwrValue[7][7:0]].
15:8 PwrValue6: P6 power value. See D18F2xF8[PwrValue0]. Value: Fuse[PwrValue[6][7:0]].
7:0
PwrValue5: P5 power value. See D18F2xF8[PwrValue0]. Value: Fuse[PwrValue[5][7:0]].
D18F2x110 DRAM Controller Select Low
IF (BootFromDRAM) THEN Cold reset: 0000_0004h. ELSE Reset: 0000_0000h. ENDIF.
Bits
Description
31:11 Reserved.
10
MemCleared: memory cleared. Read-only; updated-by-hardware. 1=Memory has been cleared
since the last warm reset. This bit is set by MemClrInit. See MemClrInit.
9
MemClrBusy: memory clear busy. Read-only; updated-by-hardware. 1=The memory clear operation in either of the DCTs is in progress. Reads or writes to DRAM while the memory clear operation
is in progress result in undefined behavior.
8
DramEnable: DRAM enabled. Read-only. 1=All of the used DCTs are initialized (see 2.9.7.8
[DRAM Device and Controller Initialization]) or have exited from self refresh
(D18F2x90_dct[0][ExitSelfRef] transitions from 1 to 0). A DCT is considered to be used if
D18F2x94_dct[0][DisDramInterface]=0 and the corresponding bit in D18F5x84[DctEn]=1.
7:6
Reserved. Read-write. DctSelIntLvAddr[1:0]. This field must be remain zero or the address bit
selection in D18F2xA8[BankSwap] does not function correctly.
5
DctDatIntLv: DRAM controller data interleave enable. IF (D18F2x118[LockDramCfg] &
~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. BIOS:
D18F3x44[DramEccEn]. 1=DRAM data bits from every two consecutive 64-bit DRAM lines are
interleaved in the ECC calculation such that a dead bit of a DRAM device is correctable.
4
Reserved.
3
MemClrInit: memory clear initialization. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. 1=The node writes 0’s to all locations of system memory attached to the node and sets the MemCleared bit. The status of the memory
clear operation can be determined by reading the MemClrBusy and MemCleared bits. This command
is ignored if MemClrBusy=1 when the command is received. DramEnable must be set before setting
MemClrInit. The memory prefetcher must be disabled by setting D18F2x11C[PrefIoDis] and
D18F2x11C[PrefCpuDis] before memory clear initialization and then can be re-enabled when MemCleared=1. Memory hole remapping must be disabled before setting MemClrInit. See
D18F1x2[1,0][8,0][LgcyMmioHoleEn]. Software may then reenable memory hole remapping when
the memory clear is complete.
2:0
Reserved.[2]: Read-write.
D18F2x114 DRAM Controller Select High
IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Readwrite. ENDIF. IF (BootFromDRAM) THEN Cold reset: 0000_0200h. ELSE Reset: 0000_0000h. ENDIF.
Bits
Description
31:10 Reserved.
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DctSelBankSwap: select DRAM bank swap address. BIOS: 1. See D18F2xA8_dct[0][BankSwap].
This bit is DctSelIntLvAddr[2] in the hardware.
Reserved.
D18F2x118 Memory Controller Configuration Low
Fields in this register (bits[17:0]) indicate priority of request types. Variable priority requests enter the memory
controller as medium priority and are promoted to high priority if they have not been serviced in the time specified by MctVarPriCntLmt. This feature may be useful for isochronous IO traffic. If isochronous traffic is specified to be high priority, it may have an adverse effect on the bandwidth and performance of the devices
associated with the other types of traffic. However, if isochronous traffic is specified as medium priority, the
processor may not meet the isochronous bandwidth and latency requirements. The variable priority allows the
memory controller to optimize DRAM transactions until isochronous traffic reaches a time threshold and must
be serviced more quickly.
Bits
Description
31:28 MctVarPriCntLmt: variable priority time limit. Read-write. Reset: 0000b. Temp.BIOS: 0001b.
Description
Bits
Description
Bits
0000b
80ns
1000b
720ns
0001b
160ns
1001b
800ns
0010b
240ns
1010b
880ns
0011b
320ns
1011b
960ns
0100b
400ns
1100b
1040ns
0101b
480ns
1101b
1120ns
0110b
560ns
1110b
1200ns
0111b
640ns
1111b
1280ns
27
Reserved.
26:24 McqHiPriByPassMax: memory controller high priority bypass max. Read-write. Reset: 100b.
Specifies the number of times a medium- or low-priority DRAM request may be bypassed by highpriority DRAM requests.
23
Reserved.
22:20 McqMedPriByPassMax: memory controller medium bypass low priority max. Read-write.
Reset: 100b. Specifies the number of times a low-priority DRAM request may be bypassed by
medium-priority DRAM requests.
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19
LockDramCfg. Write-1-only. Reset: 0. BIOS: See 2.9.11 [DRAM CC6/PC6 Storage], 2.5.3.2.3.3
[Core C6 (CC6) State].
The following registers are read-only if (LockDramCfg=1 & D18F3x12C[OverrideLockDramCfg]=0); otherwise the access type is specified by the register:
• D18F1xF0 [DRAM Hole Address]
• D18F2x[5C:40]_dct[0] [DRAM CS Base Address]
• D18F2x[6C:60]_dct[0] [DRAM CS Mask]
• D18F2x80_dct[0] [DRAM Bank Address Mapping]
• D18F2xB8 [Trace Buffer Base/Limit Address]
• D18F2xBC [Trace Buffer Address Pointer]
• D18F2xC0 [Trace Buffer Control]
• D18F2x110 [DRAM Controller Select Low]
• D18F2x114 [DRAM Controller Select High]
• D18F2x120 [Trace Buffer Extended Address]
• D18F2x250_dct[0] [DRAM Loopback and Training Control]
• D18F4x128[CoreStateSaveDestNode]
The following registers are read-only if LockDramCfg=1; otherwise the access type is specified by
the register:
• D18F1x[17C:140,7C:40] [DRAM Base/Limit]
• D18F1x120 [DRAM Base System Address]
• D18F1x124 [DRAM Limit System Address]
• D18F2x118[CC6SaveEn]
18
CC6SaveEn. IF (D18F2x118[LockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. Reset:
0. 1=CC6 save area is enabled; CC6 save area is initialized by microcode when the patch is loaded.
See 2.5.3.2.7 [BIOS Requirements for Initialization] and 2.4.13.2.1 [Microcode Patch Procedure
Overview]. BIOS: (D18F4x118[PwrGateEnCstAct0] | D18F4x118[PwrGateEnCstAct1] |
D18F4x11C[PwrGateEnCstAct2] | D18F4x118[PwrOffEnCstAct0] | D18F4x118[PwrOffEnCstAct1]
| D18F4x11C[PwrOffEnCstAct2]).
17:16 MctPriScrub: scrubber priority. Read-write. Reset: 00b.
Description
Bits
00b
Medium
01b
Reserved
10b
High
11b
Variable
15:14 MctPriTrace: trace-mode request priority. See: MctPriCpuRd. Read-write. Reset: 10b. This must
be set to high.
13:12 MctPriIsoc: display refresh read priority. See: MctPriCpuRd. Read-write. Reset: 10b.
11:10 MctPriWr: default write priority. See: MctPriCpuRd. Read-write. Reset: 01b.
9:8
MctPriDefault: default non-write priority. See: MctPriCpuRd. Read-write. Reset: 00b.
7:6
MctPriIsocWr: IO write with the isoch bit set priority. See: MctPriCpuRd. Read-write. Reset:
00b. This does not apply to isochronous traffic that is classified as display refresh.
5:4
MctPriIsocRd: IO read with the isoch bit set priority. See: MctPriCpuRd. Read-write. Reset: 10b.
This does not apply to isochronous traffic that is classified as display refresh.
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3:2
MctPriCpuWr: CPU write priority. See: MctPriCpuRd. Read-write. Reset: 01b.
1:0
MctPriCpuRd: CPU read priority. Read-write. Reset: 00b.
Description
Bits
00b
Medium
01b
Low
10b
High
11b
Variable
D18F2x11C Memory Controller Configuration High
The two main functions of this register are to control write bursting and memory prefetching.
Write bursting. DctWrLimit and MctWrLimit specify how writes may be burst from the MCT into the DCT to
improve DRAM efficiency. When the number of writes in the MCT reaches the value specified in MctWrLimit, then they are all burst to the DCTs at once. Prior to reaching the watermark, a limited number of
writes can be passed to the DCTs (specified by DctWrLimit), tagged as low priority, for the DCTs to complete
when otherwise idle. Rules regarding write bursting:
• Write bursting mode only applies to low-priority writes. Medium and high priority writes are not withheld
from the DCTs for write bursting.
• If write bursting is enabled, writes stay in the MCQ until the threshold specified by MctWrLimit is reached.
• Once the threshold is reached, all writes in MCQ are converted to medium priority.
• Any write in MCQ that matches the address of a subsequent access is promoted to either medium priority or
the priority of the subsequent access, whichever is higher.
• DctWrLimit only applies to low-priority writes.
Memory prefetching. The MCT prefetcher detects stride patterns in the stream of requests and then, for predictable stride patterns, generates prefetch requests. A stride pattern is a pattern of requests through system
memory that are the same number of cachelines apart. The prefetcher supports strides of -4 to +4 cachelines,
which can include alternating patterns (e.g. +1, +2, +1, +2), and can prefetch 1, 2, 3, 4, or 5 cachelines ahead,
depending on the confidence. In addition, a fixed stride mode (non-alternating) may be used for IO requests
which often have fixed stride patterns. This mode bypasses the stride predictor such that CPU-access stride
predictions are not adversely affected by IO streams.
The MCT tracks several stride patterns simultaneously. The prefetch table size is 32. Each of these has a confidence level associated with it that varies as follows:
• Each time a request is received that matches the stride pattern, the confidence level increases by one.
• Each time a request is received within +/- 4 cachelines of the last requested cacheline in the pattern that does
not match the pattern, then the confidence level decreases by one.
• When the confidence level reaches the saturation point specified by PrefConfSat, then it no-longer increments.
Each request that is not within +/- 4 cachelines of the last requested cacheline line of all the stride patterns
tracked initiates a new stride pattern by displacing one of the existing least-recently-used stride patterns.
The memory prefetcher uses an adaptive prefetch scheme to adjust the prefetch distance based upon the buffer
space available for prefetch request data. The adaptive scheme counts the total number of prefetch requests and
the number of prefetch requests that cannot return data because of buffer availability. After every 16 prefetch
requests, the prefetcher uses the following rules to adjust the prefetch distance:
• If the ratio of prefetch requests that cannot return data to total prefetch requests is greater than or equal to
D18F2x1B0[AdapPrefMissRatio] then the prefetch distance is reduced by D18F2x1B0[AdapPrefNega-
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tiveStep].
• If the ratio of prefetch requests that cannot return data to total prefetch requests is less than
D18F2x1B0[AdapPrefMissRatio] then the prefetch distance is increased by D18F2x1B0[AdapPrefPositiveStep].
• If the adjusted prefetch distance is greater than the prefetch distance defined for the current confidence level,
the prefetch distance for the current confidence level is used.
The adaptive prefetch scheme supports fractional prefetch distances by alternating between two whole number
prefetch distances. For example a prefetch distance of 1.25 causes a prefetch distance sequence of: 1, 1, 1, 2, 1,
1, 1, 2.
Bits
Description
31
MctScrubEn: MCT scrub enable. Read-write. Reset: 0. 1=Enables periodic flushing of prefetches
and writes based on the DRAM scrub rate. This is used to ensure that prefetch and write data aging is
not so long that soft errors accumulate and become uncorrectable. When enabled, each DRAM scrub
event causes a single prefetch to be de-allocated (the oldest one) and all queued writes to be flushed to
DRAM.
30
FlushWr: flush writes command. Read; write-1-only; cleared-by-hardware. Reset: 0. Setting this bit
causes write bursting to be canceled and all outstanding writes to be flushed to DRAM. This bit is
cleared when all writes are flushed to DRAM.
29
FlushWrOnStpGnt: flush writes on stop-grant. Read-write. Reset: 0. BIOS:
~D18F2x1B4[FlushWrOnS3StpGnt]. 1=Causes write bursting to be canceled and all outstanding
writes to be flushed to DRAM when in the stop-grant state.
28
Reserved. Read-write. Defined as PrefDramTrainMode for previous projects.
27:25 PrefThreeConf: prefetch three-ahead confidence. Read-write. Reset: 100b. Temp.BIOS: 110b.
Confidence level required in order to prefetch three cachelines ahead (same encoding as PrefTwoConf
below).
24:22 PrefTwoConf: prefetch two-ahead confidence. Read-write. Reset: 011b. Temp.BIOS: 011b. Confidence level required in order to prefetch two cachelines ahead.
Bits
Description
000b
0
110b-001b
[PrefTwoConf*2]
111b
14
21:20 PrefOneConf: prefetch one-ahead confidence. Read-write. Reset: 10b. Temp.BIOS: 10b. Confidence level required in order to prefetch one ahead (0 through 3).
19:18 PrefConfSat: prefetch confidence saturation. Read-write. Reset: 00b. Temp.BIOS: 00b. Specifies
the point at which prefetch confidence level saturates and stops incrementing.
Bits
Description
00b
15
01b
7
10b
3
11b
Reserved
17:16 PrefFixDist: prefetch fixed stride distance. Read-write. Reset: 00b. Specifies the distance to
prefetch ahead if in fixed stride mode. 00b=1 cacheline; 01b=2 cachelines; 10b=3 cachelines; 11b=4
cachelines.
15
PrefFixStrideEn: prefetch fixed stride enable. Read-write. Reset: 0. 1=The prefetch stride for all
requests (CPU and IO) is fixed (non-alternating).
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14
PrefIoFixStrideEn: Prefetch IO fixed stride enable. Read-write. Reset: 0. 1=The prefetch stride for
IO requests is fixed (non-alternating).
13
PrefIoDis: prefetch IO-access disable. Read-write. Reset: 1. BIOS: 0. 1=Disables IO requests from
triggering prefetch requests.
12
PrefCpuDis: prefetch CPU-access disable. Read-write. Reset: 1. BIOS: 0. 1=Disables CPU
requests from triggering prefetch requests.
11:7 MctPrefReqLimit: memory controller prefetch request limit. Read-write. Reset: 1Eh. Specifies
the maximum number of outstanding prefetch requests allowed. See D18F3x78 for restrictions on this
field.
6:2
MctWrLimit: memory controller write-burst limit. Read-write. Reset: 1Fh. BIOS:0Ch. Specifies
the number of writes in the memory controller queue before they are burst into the DCTs.
Bits
Description
00h
32
1Dh-01h
[32-MctWrLimit]
1Eh
2
1Fh
Write bursting disabled
1:0
DctWrLimit: DRAM controller write limit. Read-write. Reset: 00b. Temp.BIOS: 00b. Specifies the
maximum number of writes allowed in the DCT queue when write bursting is enabled, prior to when
the number of writes in MCQ exceeds the watermark specified by MctWrLimit.
Description
Bits
00b
0
01b
2
10b
4
11b
Reserved
D18F2x1B0 Extended Memory Controller Configuration Low
The main function of this register is to control the memory prefetcher. See D18F2x11C [Memory Controller
Configuration High] about the adaptive prefetch scheme.
Table 164: BIOS Recommendations for D18F2x1B[4:0]
Condition
DdrRate
667
800
1066
1333
1600
1866
2133
D18F2x1B0
DcqBwThrotWm
0h
0h
0h
0h
0h
0h
0h
D18F2x1B4
DcqBwThrotWm1 DcqBwThrotWm2
3h
4h
3h
5h
4h
6h
5h
8h
6h
9h
7h
Ah
8h
Ch
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Description
31:28 DcqBwThrotWm: dcq bandwidth throttle watermark. Read-write. Reset: 3h. BIOS: Table 164.
Specifies the number of outstanding DRAM read requests before new DRAM prefetch requests and
speculative prefetch requests are throttled. 0h=Throttling is disabled. Legal values are 0h through Ch.
Programming this field to a non-zero value disables D18F2x1B4[DcqBwThrotWm1,
DcqBwThrotWm2].
Rule: D18F2x1B0[DcqBwThrotWm]<=Ch. See D18F3x18C[DcqDepthCtl].
The percentage of DCQ occupancy affected by this field varies with memory speed as follows:
Memory Speed 100%
150%
200%
DDR3-667
3h
4h
5h
DDR3-800
3h
5h
6h
DDR3-1066
4h
6h
8h
DDR3-1333
5h
8h
Ah
DDR3-1600
6h
9h
Ch
DDR3-1866
7h
Ah
Eh
DDR3-2133
8h
Ch
10h
The BIOS recommended values are based off the 150% column.
27:25 PrefFiveConf: prefetch five-ahead confidence. Read-write. Reset: 110b. BIOS: 111b. Confidence
level required in order to prefetch five cachelines ahead.
Description
Bits
000b
0
110b-001b
[PrefFiveConf*2]
111b
14
24:22 PrefFourConf: prefetch four-ahead confidence. Read-write. Reset: 101b. BIOS: 111b. Confidence
level required in order to prefetch four cachelines ahead.
Bits
Description
000b
0
110b-001b
[PrefFourConf*2]
111b
14
21
Reserved.
20
DblPrefEn: double prefetch enable. Read-write. Reset: 0. 1=The memory prefetcher only generates
prefetch requests when it is able to generate a pair of prefetch requests to consecutive cache lines.
19:18 Reserved.
17:13 Reserved. Reset: 11100b. Read-write.
12
EnSplitDctLimits: split DCT write limits enable. Read-write. Reset: 0. BIOS: 1. 1=The number of
writes specified by D18F2x11C[DctWrLimit, MctWrLimit] is per DCT. 0=The number of writes
specified by D18F2x11C[DctWrLimit, MctWrLimit] is for the even[0,2] or odd[1,3] DCT channels.
0=The number of writes specified by D18F2x11C[DctWrLimit, MctWrLimit] is total writes independent of DCT. Setting this bit also affects the encoding of D18F2x11C[DctWrLimit].
11
DisIoCohPref: disable coherent prefetched for IO. IF (Fuse[DisCohIOPref]) THEN Read-only.
ELSE Read-write. ENDIF. IF (Fuse[DisCohIOPref]) THEN Reset: 1 ELSE Reset: 0 ENDIF.
1=Probes are not generated for prefetches generated for reads from IO devices.
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10:8 CohPrefPrbLmt: coherent prefetch probe limit. IF (Fuse[DisCohPref]) THEN Read-only. ELSE
Read-write. ENDIF. Reset: 000b. BIOS: 000b. Specifies the maximum number of probes that can be
outstanding for memory prefetch requests.
Description
Bits
000b
Probing disabled for memory prefetch requests
111b-001b
Reserved.
7:6
Reserved.
5:4
AdapPrefNegativeStep: adaptive prefetch negative step. Read-write. Reset: 00b. BIOS: 00b. Specifies the step size that the adaptive prefetch scheme uses when decreasing the prefetch distance.
Bits
Description
00b
2/16
01b
4/16
10b
8/16
11b
16/16
3:2
AdapPrefPositiveStep: adaptive prefetch positive step. Read-write. Reset: 00b. BIOS: 00b. Specifies the step size that the adaptive prefetch scheme uses when increasing the prefetch distance.
Bits
Description
00b
1/16
01b
2/16
10b
4/16
11b
8/16
1:0
AdapPrefMissRatio: adaptive prefetch miss ratio. Read-write. Reset: 00b. BIOS: 01b. Specifies
the ratio of prefetch requests that do not have data buffer available to the total number of prefetch
requests at which the adaptive prefetch scheme begins decreasing the prefetch distance.
Description
Bits
00b
1/16
01b
2/16
10b
4/16
11b
8/16
D18F2x1B4 Extended Memory Controller Configuration High Register
Bits
31
Description
FlushOnMmioWrEn: flush on mmio write enable. Read-write. Reset: 0. 1=Any CPU-sourced
MMIO write that matches D18F1x[2CC:2A0,1CC:180,BC:80] causes the memory controller data
buffers to be flushed to memory.
30:28 S3SmafId: S3 SMAF id. Read-write. Reset: 100b. SMAF encoding of D18F3x[84:80] corresponding to the ACPI S3 state when FlushWrOnS3StpGnt=1. Reserved when FlushWrOnS3StpGnt=0.
27
FlushWrOnS3StpGnt: flush write on S3 stop grant. Read-write. Reset: 0. BIOS: 1. 1=Write bursting is canceled and all outstanding writes are flushed to DRAM when in the stop-grant state and the
SMAF code is equal to S3SmafId, indicating entry into the ACPI S3 state. See
D18F2xA8_dct[0][FastSelfRefEntryDis], D18F2x11C[FlushWrOnStpGnt].
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26
EnSplitMctDatBuffers: enable split MCT data buffers. Read-write. Reset: 0. BIOS: 1. 1=Enable
resource allocation into the split buffer resources (a single DCT allocates into MCD_HI and
MCD_LO). This field was intended to be set only if NCLK frequency < 2 * MEMCLK frequency for
any P-state, but has no impact on operation when the ratio above is false. BIOS must program this bit
before any DRAM memory accesses are issued from the processor (including CAR initialization; if
accesses are carefully controlled, this may be programmed after CAR initialization but before DCT
initialization).
25
SmuCfgLock: SMU configuration lock. Read-write; updated-by-hardware. (SMU). Reset: 0.
This field should never be cleared by software. The following registers are read-only if
(LockSmuCfg=1 && D18F3x12C[OverrideLockDramCfg]=0); otherwise the access type is specified
by the register:
• D18F4x10C [TDP Limit 2]
• D18F4x15C [Core Performance Boost Control]
• D18F5x12C [Clock Power/Timing Control 4]
• D18F5x170 [Northbridge P-state Control]
• D18F5x188 [Clock Power/Timing Control 5]
SMU accesses are not locked by this field, only software accesses limited. This bit is set when BAPM
or NB DPM are enabled by SMU.
22
SpecPrefDisWm1: speculative prefetch disable watermark 1. Read-write. Reset: 0. 0=Disable
speculative prefetches at the DcqBwThrotWm2 limit. 1=Disable speculative prefetches at the
DcqBwThrotWm1 limit. See also D18F2x1B0[SpecPrefDis].
21
RegionAlloWm2: region prefetch allocate watermark 2. Read-write. Reset: 0. See
DemandAlloWm2.
20
RegionPropWm2: region prefetch propagate watermark 2. Read-write. Reset: 0. See
DemandPropWm2.
19
StrideAlloWm2: stride prefetch allocate watermark 2. Read-write. Reset: 1. See
DemandAlloWm2.
18
StridePropWm2: stride prefetch propagate watermark 2. Read-write. Reset: 1. See
DemandPropWm2.
17
DemandAlloWm2: demand request allocate watermark 2. Read-write. Reset: 1. Specifies the
behavior from the DcqBwThrotWm1 limit to the DcqBwThrotWm2 limit. 0=Requests do not allocate
a new MPT entry. 1=Requests allocate a new MPT entry; defined only if (DemandAlloWm1 &
DemandPropWm2).
16
DemandPropWm2: demand request propagate watermark 2. Read-write. Reset: 1. Specifies the
behavior from the DcqBwThrotWm1 limit to the DcqBwThrotWm2 limit. 0=Requests do not update
existing MPT entries. 1=Requests update existing MPT entries with new address and stride info;
defined only if (DemandPropWm1=1).
15
RegionAlloWm1: region prefetch allocate watermark 1. Read-write. Reset: 0. See
DemandAlloWm1.
14
RegionPropWm1: region prefetch propagate watermark 1. Read-write. Reset: 1. See
DemandPropWm1.
13
StrideAlloWm1: stride prefetch allocate watermark 1. Read-write. Reset: 1. See
DemandAlloWm1.
12
StridePropWm1: stride prefetch propagate watermark 1. Read-write. Reset: 1. See
DemandPropWm1.
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11
DemandAlloWm1: demand request allocate watermark 1. Read-write. Reset: 1. Specifies the
behavior prior to the DcqBwThrotWm1 limit. 0=Requests do not allocate a new MPT entry.
1=Requests allocate a new MPT entry; defined only if (DemandPropWm1=1).
10
DemandPropWm1: demand request propagate watermark 1. Read-write. Reset: 1. Specifies the
behavior prior to the DcqBwThrotWm1 limit. 0=Requests do not update existing MPT entries.
1=Requests update existing MPT entries with new address and stride info.
9:5
DcqBwThrotWm2: DCQ bandwidth throttle watermark 2. Read-write. Reset: 06h. BIOS:
Table 164. Specifies a prefetch throttling watermark based on the number of outstanding DRAM read
requests. This field is reserved when D18F2x1B0[DcqBwThrotWm] != 0. When throttling is enabled,
if the number of outstanding DRAM read requests exceeds DcqBwThrotWm2 both request allocate
and propagate are blocked and new prefetches are disabled. When throttling is enabled,
DcqBwThrotWm2 should be programmed to a value greater than DcqBwThrotWm1. 0h=Throttling
is disabled. Legal values are 0h through 18h. Rule: D18F2x1B4[DcqBwThrotWm2]<=18h. See
D18F3x18C[DcqDepthCtl].
The BIOS recommended values are based off the 150% column of D18F2x1B0[DcqBwThrotWm].
4:0
DcqBwThrotWm1: DCQ bandwidth throttle watermark 1. Read-write. Reset: 03h. BIOS:
Table 164. Specifies a prefetch throttling watermark based on the number of outstanding DRAM read
requests. This field is reserved when D18F2x1B0[DcqBwThrotWm] != 0. 0h=Throttling is disabled.
Legal values are 0h through 18h. Rule: D18F2x1B4[DcqBwThrotWm1]<=18h. See
D18F3x18C[DcqDepthCtl].
The BIOS recommended values are based off the 100% column of D18F2x1B0[DcqBwThrotWm].
D18F2x1BC_dct[0] DRAM CKE to CS Map
IF (BootFromDRAM) THEN Cold reset: Reset: 0000_AA55h ELSE Reset: 0000_AA55h. ENDIF. See 2.9.3
[DCT Configuration Registers].
Table 165: Field Mapping for D18F2x1BC_dct[0]
Register
D18F2x1BC_dct[0]
Bits
31:24
23:16
15:8
7:0
CKE3
CKE2
CKE1
CKE0
Table 166: BIOS Recommendations for D18F2x1BC_dct[0]
Condition:
Package
FT3
Bits
D18F2x1BC_dct[0]
NumDimmSlots
1, 2
08040201h
Description
31:24 CSMapCKE: CS map CKE. See: D18F2x1BC_dct[0][7:0].
23:16 CSMapCKE: CS map CKE. See: D18F2x1BC_dct[0][7:0].
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15:8 CSMapCKE: CS map CKE. See: D18F2x1BC_dct[0][7:0].
7:0
CSMapCKE: CS map CKE. Read-write. BIOS: See Table 166 [BIOS Recommendations for
D18F2x1BC_dct[0]]. Maps the CS to CKE relationship, which varies by platform and DIMM. 1=This
CKE is associated with the listed chip select. 0=This CKE is not associated with the listed chip select.
See also D18F2x9C_x0000_000C_dct[0][CKETri].
E.g. D18F2x1BC_dct[0]=0000_AA55h means that CKE0 controls all the even CSes, CKE1 controls
all the odd CSes, and CKE2 & CKE3 are unused. Only 1 CKE may be assigned to a CS across
D18F2x1BC_dct[0]. Only even CKEs may be assigned to even CSes. Only odd CKEs may be
assigned to odd CSes.
Bit
Description
[0]
CS0
[1]
CS1
[2]
CS2
[3]
CS3
[7:4]
Reserved
D18F2x200_dct[0]_mp[1:0] DDR3 DRAM Timing 0
IF (BootFromDRAM) THEN Cold reset: 1505_0505h. ELSE Reset: 0F05_0505h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:30 Reserved.
29:24 Tras: row active strobe. Read-write. BIOS: See 2.9.7.5 [SPD ROM-Based Configuration]. Specifies
the minimum time in memory clock cycles from an activate command to a precharge command, both
to the same chip select bank.
Description
Bits
07h-00h
Reserved
2Ah-08h
<Tras> clocks
3Fh-2Bh
Reserved
23:21 Reserved.
20:16 Trp: row precharge time. Read-write. BIOS: See 2.9.7.5 [SPD ROM-Based Configuration]. Specifies the minimum time in memory clock cycles from a precharge command to an activate command or
auto refresh command, both to the same bank.
Rule: D18F2x200_dct[0]_mp[1:0][Trp] > D18F2x24C_dct[0][Tpd].
Bits
Description
04h-00h
Reserved
13h-05h
<Trp> clocks
1Fh-14h
Reserved
15:13 Reserved.
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12:8 Trcd: RAS to CAS delay. Read-write. BIOS: See 2.9.7.5 [SPD ROM-Based Configuration]. Specifies the time in memory clock cycles from an activate command to a read/write command, both to the
same bank.
Description
Bits
04h-00h
Reserved
13h-05h
<Trcd> clocks
1Fh-14h
Reserved
7:5
Reserved.
4:0
Tcl: CAS latency. Read-write. BIOS: See 2.9.7.5 [SPD ROM-Based Configuration]. Specifies the
time in memory clock cycles from the CAS assertion for a read cycle until data return (from the perspective of the DRAM devices).
Bits
Description
04h-00h
Reserved
13h-05h
<Tcl> clocks
1Fh-14h
Reserved
D18F2x204_dct[0]_mp[1:0] DDR3 DRAM Timing 1
IF (BootFromDRAM) THEN Cold reset: 040A_040Dh. ELSE Reset: 0400_040Bh. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:28 Reserved.
27:24 Trtp: read CAS to precharge time. Read-write. BIOS: See 2.9.7.5. Specifies the earliest time in
memory clock cycles a page can be closed after having been read. Satisfying this parameter ensures
read data is not lost due to a premature precharge.
Bits
Description
3h-0h
Reserved
Bh-4h
<Trtp> clocks
Fh-Ch
Reserved
23:22 Reserved.
21:16 FourActWindow: four bank activate window. Read-write. BIOS: See 2.9.7.5. Specifies the rolling
tFAW window in memory clock cycles during which no more than 4 banks in an 8-bank device are
activated.
Bits
Description
00h
No tFAW window restriction
05h-01h
Reserved
2Ch-06h
[FourActWindow] clocks
3Fh-2Dh
Reserved
15:12 Reserved.
11:8 Trrd: row to row delay (or RAS to RAS delay). Read-write. BIOS: See 2.9.7.5. Specifies the minimum time in memory clock cycles between activate commands to different chip select banks.
Bits
Description
0h
Reserved
9h-1h
<Trrd> clocks
Fh-Ah
Reserved
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7:6
Reserved.
5:0
Trc: row cycle time. Read-write. BIOS: See 2.9.7.5. Specifies the minimum time in memory clock
cycles from and activate command to another activate command or an auto refresh command, all to
the same chip select bank.
Bits
Description
09h-00h
Reserved
3Ah-0Ah
<Trc> clocks
3Fh-3Bh
Reserved
D18F2x208_dct[0] DDR3 DRAM Timing 2
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31:27 Reserved.
26:24 Trfc3: auto refresh row cycle time for CS 6 and 7. See: Trfc0.
23:19 Reserved.
18:16 Trfc2: auto refresh row cycle time for CS 4 and 5. See: Trfc0.
15:11 Reserved.
10:8 Trfc1: auto refresh row cycle time for CS 2 and 3. See: Trfc0.
7:3
Reserved.
2:0
Trfc0: auto refresh row cycle time for CS 0 and 1. Read-write. IF (BootFromDRAM) THEN Cold
reset: 100b. ELSE Reset: 100b. ENDIF. BIOS: 2.9.7.5. Specifies the minimum time from a refresh
command to the next valid command, except NOP or DES. The recommended programming of this
register varies based on DRAM density and speed.
Bits
Description
000b
Reserved
001b
90 ns (all speeds, 512 Mbit)
010b
110 ns (all speeds, 1 Gbit)
011b
160 ns (all speeds, 2 Gbit)
100b
300 ns (all speeds, 4 Gbit)
101b
350 ns (all speeds, 8 Gbit)
111b-110b
Reserved
D18F2x20C_dct[0]_mp[1:0] DDR3 DRAM Timing 3
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31:18 Reserved.
17:16 WrDqDqsEarly: DQ and DQS write early. Read-Write. Reset: 0. Specifies the DQ and DQS launch
timing for write commands relative to the Tcwl MEMCLK.
Bits
Description
00b
0 MEMCLK early (aligned with Tcwl MEMCLK rising edge)
01b
0.5 MEMCLK early
10b
Reserved ;1.0 MEMCLK early
11b
Reserved
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15:12 Reserved. [15:12] are reserved for Twtr.
11:8 Twtr: internal DRAM write to read command delay. Read-write. IF (BootFromDRAM) THEN
Cold reset: 7h. ELSE Reset: 4h. ENDIF. BIOS: See 2.9.7.5. Specifies the minimum number of memory clock cycles from a write operation to a read operation, both to the same chip select. This is measured from the rising clock edge following last non-masked data strobe of the write to the rising clock
edge of the next read command.
Description
Bits
3h-0h
Reserved
Bh-4h
<Twtr> clocks
Fh-Ch
Reserved
7:5
Reserved.
4:0
Tcwl: CAS write latency. Read-write. IF (BootFromDRAM) THEN Cold reset: 5h. ELSE Reset: 5h.
ENDIF. BIOS: See 2.9.7.5. Specifies the number of memory clock cycles from internal write command to first write data in at the DRAM. This register is applied to the MRS during HW DRAM initialization. See 2.9.7.8 [DRAM Device and Controller Initialization].
Bits
Description
04h-00h
Reserved
0Ah-05h
<Tcwl> clocks
1Fh-0Bh
Reserved
D18F2x210_dct[0]_nbp[3:0] DRAM NB P-state
See 2.9.3 [DCT Configuration Registers]. For D18F2x210_dct[0]_nbp[x], x=D18F1x10C[NbPsSel]; see
D18F1x10C[NbPsSel].
Table 167: BIOS Recommendations for RdPtrInit
Condition
NBCOF >= DdrRate
D18F2x210_dct[0]_nbp[3:0]
DdrRate
RdPtrInit
0
-
0010b
1
667, 800, 1066, 1333,
1600
0110b
1
1866, 2133
0101b
Bits
Description
31:22 MaxRdLatency: maximum read latency. Read-write. IF (BootFromDRAM) THEN Cold reset:
Fuse[PA_MaxRdLatency[9:0]]. ELSE Reset: 000h. ENDIF. BIOS: See 2.9.7.9.5 [Calculating
MaxRdLatency]. Specifies the maximum round-trip latency in the system from the processor to the
DRAM devices and back. The DRAM controller uses this to help determine when the first two beats
of incoming DRAM read data can be safely transferred to the NCLK domain. The time includes the
asynchronous and synchronous latencies.
Bits
Description
000h
0 NCLKs
3FEh-001h
<MaxRdLatency> NCLKs
3FFh
1023 NCLKs
21:19 Reserved.
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18:16 DataTxFifoWrDly: data transmit FIFO write delay. Read-write. IF (BootFromDRAM) THEN
Cold reset: 0h. ELSE Reset: 0. ENDIF. BIOS: 0h. Specifies the DCT to phy write data FIFO delay.
Bits
000b
001b
010b
011b
100b
101b
110b
111b
Description
0 MEMCLK
0.5 MEMCLK
1.0 MEMCLK
1.5 MEMCLKs
2.0 MEMCLKs
2.5 MEMCLKs
3.0 MEMCLKs
Reserved
15:4 Reserved.
3:0
RdPtrInit: read pointer initial value. Read-write. IF (BootFromDRAM) THEN Cold reset: 4h.
ELSE Reset: 6h. ENDIF. BIOS: Table 167. There is a synchronization FIFO between the NB clock
domain and memory clock domain. Each increment of this field positions the read pointer one half
clock cycle closer to the write pointer thereby reducing the latency through the FIFO. BIOS must program this field for the current or target NB P-state prior to a frequency change or NB P-state change.
Bits
Description
0001b-0000b
Reserved
0010b
3 MEMCLK
0011b
2.5 MEMCLK
0100b
2 MEMCLKs
0101b
1.5 MEMCLKs
0110b
1 MEMCLKs
1111b-0111b
Reserved
D18F2x214_dct[0]_mp[1:0] DDR3 DRAM Timing 4
IF (BootFromDRAM) THEN Cold reset: 0001_0304h. ELSE Reset: 0001_0202h. ENDIF.
Bits
Description
31:20 Reserved.
19:16 TwrwrSdSc: write to write timing same DIMM same chip select. Read-write. BIOS: See 2.9.7.6.2
[TwrwrSdSc, TwrwrSdDc, TwrwrDd (Write to Write Timing)]. Specifies the minimum number of
cycles from the last clock of virtual CAS of the first write-burst operation to the clock in which CAS
is asserted for a following write-burst operation.
Description
Bits
0h
Reserved
1h
1 clock
Ah-2h
<TwrwrSdSc> clocks
Bh
11 clocks
Fh-Ch
Reserved
e.g. TwrwrSdSc=1h, BL=8:
| WR | NOP | NOP | NOP (LVC) | WR | NOP | NOP | NOP (LVC) | …
e.g. TwrwrSdSc=2h, BL=8:
| WR | NOP | NOP | NOP (LVC) | NOP | WR | NOP | NOP | NOP (LVC) | …
15:12 Reserved.
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11:8 TwrwrSdDc: write to write timing same DIMM different chip select. See: TwrwrDd.
7:4
Reserved.
3:0
TwrwrDd: write to write timing different DIMM. Read-write. BIOS: See 2.9.7.6.2 [TwrwrSdSc,
TwrwrSdDc, TwrwrDd (Write to Write Timing)]. Specifies the minimum number of cycles from the
last clock of virtual CAS of the first write-burst operation to the clock in which CAS is asserted for a
following write-burst operation.
Description
Bits
1h-0h
Reserved
Bh-2h
<TwrwrDd> clocks
Fh-Ch
Reserved
D18F2x218_dct[0]_mp[1:0] DDR3 DRAM Timing 5
IF (BootFromDRAM) THEN Cold reset: 0102_0303h. ELSE Reset: 0103_0203h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:30 TrdrdBan: read to read timing ban. Read-write. BIOS: 00b. Bans the traffic for the specified cases
where the number of cycles from the last clock of virtual CAS of a first read-burst operation to the
clock in which CAS is asserted for a following read-burst operation.
Description
Bits
00b
Ban disabled, traffic allowed as specified by TrdrdSdSc, TrdrdSdDc, TrdrdDd.
01b
Ban Trdrd traffic at 2 MEMCLKs.
10b
Ban Trdrd traffic at 2 and 3 MEMCLKs.
11b
Reserved
e.g. TrdrdSdSc=1h, TrdrdSdScBan=1h, BL=8:
Allowed: | RD | NOP | NOP | NOP (LVC) | RD | NOP | NOP | NOP (LVC) | …
Allowed: | RD | NOP | NOP | NOP (LVC) | NOP | NOP | RD | NOP | NOP | NOP (LVC) | …
Banned: | RD | NOP | NOP | NOP (LVC) | NOP | RD | NOP | NOP | NOP (LVC) | …
29:28 Reserved.
27:24 TrdrdSdSc: read to read timing same DIMM same chip select. Read-write. BIOS: See 2.9.7.6.1
[TrdrdSdSc, TrdrdSdDc, and TrdrdDd (Read to Read Timing)]. Specifies the minimum number of
cycles from the last clock of virtual CAS of a first read-burst operation to the clock in which CAS is
asserted for a following read-burst operation.
Bits
Description
0h
Reserved
Bh-1h
<TrdrdSdSc> clocks
Fh-Ch
Reserved
e.g. TrdrdSdSc=1h, BL=8:
| RD | NOP | NOP | NOP (LVC) | RD | NOP | NOP | NOP (LVC) | …
e.g. TrdrdSdSc=2h, BL=8:
| RD | NOP | NOP | NOP (LVC) | NOP | RD | NOP | NOP | NOP (LVC) | …
23:20 Reserved.
19:16 TrdrdSdDc: read to read timing same DIMM different chip select. See: TrdrdDd.
15:12 Reserved.
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11:8 Twrrd: write to read DIMM termination turnaround. Read-write. BIOS: See 2.9.7.6.3 [Twrrd
(Write to Read DIMM Termination Turn-around)]. Specifies the minimum number of cycles from the
last clock of virtual CAS of the first write-burst operation to the clock in which CAS is asserted for a
following read-burst operation, both to different chip selects.
Bits
Description
0h
Reserved
Bh-1h
<Twrrd> clocks
Fh-Ch
Reserved
e.g. Twrrd=1h, BL=8:
| WR | NOP | NOP | NOP (LVC) | RD | NOP | NOP | NOP (LVC) | …
7:4
Reserved.
3:0
TrdrdDd: read to read timing different DIMM. Read-write. BIOS: See 2.9.7.6.1 [TrdrdSdSc,
TrdrdSdDc, and TrdrdDd (Read to Read Timing)]. Specifies the minimum number of cycles from the
last clock of virtual CAS of a first read-burst operation to the clock in which CAS is asserted for a following read-burst operation.
Bits
Description
1h-0h
Reserved
Bh-2h
<TrdrdDd> clocks
Fh-Ch
Reserved
D18F2x21C_dct[0]_mp[1:0] DDR3 DRAM Timing 6
IF (BootFromDRAM) THEN Cold reset: 0005_0500h. ELSE Reset: 0004_0300h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:21 Reserved. [23:21] are reserved for TrwtWB.
20:16 TrwtWB: read to write turnaround for opportunistic write bursting. Read-write. BIOS: TrwtTO
+ 1. Specifies the minimum number of clock cycles from the last clock of virtual CAS of a first readburst operation to the clock in which CAS is asserted for a following write-burst operation. The purpose of this field is to hold off write operations until several cycles have elapsed without a read cycle;
this may result in performance benefits.
Description
Bits
02h-00h
Reserved
1Ch-03h
<TrwtWB> clocks
1Fh-1Dh
Reserved
15:13 Reserved.
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12:8 TrwtTO: read to write turnaround. Read-write. BIOS: See 2.9.7.6.4 [TrwtTO (Read-to-Write
Turnaround for Data, DQS Contention)]. Specifies the minimum number of clock cycles from the last
clock of virtual CAS of a first read-burst operation to the clock in which CAS is asserted for a following write-burst operation.
Description
Bits
01h-00h
Reserved
1Bh-02h
<TrwtTO> clocks
1Fh-1Ch
Reserved
e.g. TrwtTO=2h, BL=8:
| RD | NOP | NOP | NOP (LVC) | NOP | WR | NOP | NOP | NOP (LVC) | …
7:0
Reserved.
D18F2x220_dct[0] DDR3 DRAM Timing 7
IF (BootFromDRAM) THEN Cold reset: 0000_0505h. ELSE Reset: 0000_0C04h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:13 Reserved. [15:13] are reserved for Tmod.
12:8 Tmod: mode register command delay. Read-write. BIOS: See 2.9.7.5. Specifies the minimum time
in memory clock cycles from an MRS command to another non-MRS command (excluding NOP and
DES), all to the same chip select.
Description
Bits
1h-0h
Reserved
14h-2h
<Tmod> clocks
1Fh-15h
Reserved
7:4
Reserved.
3:0
Tmrd: mode register command cycle time. Read-write. BIOS: See 2.9.7.5. Specifies the minimum
time in memory clock cycles from an MRS command to another MRS command, all to the same chip
select.
Bits
Description
1h-0h
Reserved
8h-2h
<Tmrd> clocks
Fh-9h
Reserved
D18F2x224_dct[0] DDR3 DRAM Timing 8
IF (BootFromDRAM) THEN Cold reset: 0000_0408h. ELSE Reset: 0000_0408h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:11 Reserved. [15:11] are reserved for Tzqcs.
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10:8 Tzqcs: Zq short cal command delay. Read-write. BIOS: See 2.9.7.5. Specifies the minimum time in
memory clock cycles from a ZQCS command to any other command (excluding NOP and DES) on
the channel.
Description
Bits
Description
Bits
000b
Reserved
100b
64 clocks
001b
16 clocks
101b
80 clocks
010b
32 clocks
110b
96 clocks
011b
48 clocks
111b
Reserved
7:4
Reserved.
3:0
Tzqoper: Zq long cal command delay. Read-write. BIOS: See 2.9.7.5. Specifies the minimum time
in memory clock cycles from a ZQCL command to any other command (excluding NOP and DES) on
the channel.
Bits
Description
Bits
Description
0000b
Reserved
1000b
256 clocks
0001b
32 clocks
1001b
288 clocks
0010b
64 clocks
1010b
320 clocks
0011b
96 clocks
1011b
352 clocks
0100b
128 clocks
1100b
384 clocks
0101b
160 clocks
1111b-1101b Reserved
0110b
192 clocks
0111b
224 clocks
D18F2x228_dct[0] DDR3 DRAM Timing 9
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31:24 Tstag3: auto refresh stagger time for logical DIMM 3. See: Tstag0.
23:16 Tstag2: auto refresh stagger time for logical DIMM 2. See: Tstag0.
15:8 Tstag1: auto refresh stagger time for logical DIMM 1. See: Tstag0.
7:0
Tstag0: auto refresh stagger time for logical DIMM 0. Read-write. IF (BootFromDRAM) THEN
Cold reset: 14h. ELSE Reset: 00h. ENDIF. BIOS: MAX(D18F2x204_dct[0]_mp[1:0][Trrd],
CEIL(D18F2x204_dct[0]_mp[1:0][FourActWindow]/4)).
Specifies the number of clocks between auto refresh commands to different ranks of a DIMM when
D18F2x90_dct[0][StagRefEn]=1.
For UDIMM and RDIMMs, the assumption is that the worst Trrd/Tfaw spec is a best available proxy
for a minimum stagger value.
Tstagmax = D18F2x8C_dct[0][Tref] clocks /# of physical ranks present, such that all ranks can be
refreshed within a Tref period.
Bits
00h
FEh-01h
FFh
Description
0 clocks
<Tstag0> clocks
255 clocks
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D18F2x22C_dct[0]_mp[1:0] DDR3 DRAM Timing 10
IF (BootFromDRAM) THEN Cold reset: 0000_000Ch. ELSE Reset: 0000_000Ch. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:5 Reserved.
4:0
Twr: write recovery. Read-write. BIOS: See 2.9.7.5. Specifies the minimum time from the last data
write until the chip select bank precharge.
Bits
Description
4h-0h
Reserved
8h-5h
8 to 5 clocks
9h
Reserved
Ah
10 clocks
Bh
Reserved
Ch
12 clocks
Dh
Reserved
Eh
14 clocks
Fh
Reserved
10h
16 clocks
11h
Reserved
12h
18 clocks
1Fh-13h
Reserved
D18F2x[234:230]_dct[0] DDR3 DRAM Read ODT Pattern [High:Low]
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. This register is used by BIOS to specify the state of the ODT pins during DDR reads.
F2x230 is used to control chip selects 0-3. F2x234 is used to control chip selects 4-7.
See 2.9.7.6.5 [DRAM ODT Control] and Table343 [DIMM, Chip Select, and Register Mapping] for more
information.
Bits
Description
31:28 Reserved.
27:24 RdOdtPatCs73: read ODT pattern chip select [7,3]. See: RdOdtPatCs40.
23:20 Reserved.
19:16 RdOdtPatCs62: read ODT pattern chip select [6,2]. See: RdOdtPatCs40.
15:12 Reserved.
11:8 RdOdtPatCs51: read ODT pattern chip select [5,1]. See: RdOdtPatCs40.
7:4
Reserved.
3:0
RdOdtPatCs40: read ODT pattern chip select [4,0]. Read-write. Specifies the state of ODT[3:0]
pins when a read occurs to the specified chip select.
D18F2x[23C:238]_dct[0] DDR3 DRAM Write ODT Pattern [High:Low]
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. This register is used by BIOS to specify the state of the ODT pins during DDR
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writes. F2x238 is used to control chip selects 0-3. F2x23C is used to control chip selects 4-7.
See 2.9.7.6.5 [DRAM ODT Control] and Table343 [DIMM, Chip Select, and Register Mapping] for more
information.
Bits
Description
31:28 Reserved.
27:24 WrOdtPatCs73: write ODT pattern chip select [7,3]. See: WrOdtPatCs40.
23:20 Reserved.
19:16 WrOdtPatCs62: write ODT pattern chip select [6,2]. See: WrOdtPatCs40.
15:12 Reserved.
11:8 WrOdtPatCs51: write ODT pattern chip select [5,1]. See: WrOdtPatCs40.
7:4
Reserved.
3:0
WrOdtPatCs40: write ODT pattern chip select [4,0]. Read-write. Specifies the state of ODT[3:0]
pins when a write occurs to the specified chip select.
D18F2x240_dct[0]_mp[1:0] DDR3 DRAM ODT Control
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31:15 Reserved.
14:12 WrOdtOnDuration: write ODT on duration. Read-write. BIOS: 6. Specifies the number of memory clock cycles that ODT is asserted for writes. Normally, WrOdtOnDuration = BL/2 + 2.
Bits
Description
0h
0 clocks (Don’t assert ODT)
5h-1h
<WrOdtOnDuration> clocks
7h-6h
<WrOdtOnDuration> clocks
11
Reserved.
10:8 WrOdtTrnOnDly: Write ODT Turn On Delay. Read-write. BIOS: 0. Specifies the number of
memory clock cycles that ODT assertion is delayed relative to write CAS. (0h = ODT asserted with
internal CAS).
Bits
Description
0h
0 clocks
7h-1h
<WrOdtTrnOnDly> clocks, Reserved if (WrOdtOnDuration=0)
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7:4
RdOdtOnDuration: Read ODT On Duration. Read-write. BIOS: 6. Specifies the number of memory clock cycles that ODT is asserted for an eight-beat read burst. The controller will shorten the ODT
pulse duration by two clock cycles if the burst is chopped. Normally, RdOdtOnDuration = BL/2 + 2.
Bits
Description
0h
0 clocks (Don’t assert ODT)
5h-1h
<RdOdtOnDuration> clocks
9h-6h
<RdOdtOnDuration> clocks
Fh-Ah
Reserved
3:0
RdOdtTrnOnDly: Read ODT Turn On Delay. Read-write. BIOS: MAX(0,
D18F2x200_dct[0]_mp[1:0][Tcl] - D18F2x20C_dct[0]_mp[1:0][Tcwl]). Specifies the number of
clock cycles that ODT assertion is delayed relative to read CAS. (0h = ODT asserted with internal
CAS).
Description
Bits
0h
0 clocks
Fh-0h
<RdOdtTrnOnDly> clocks, Reserved if (RdOdtOnDuration=0)
D18F2x244_dct[0] DRAM Controller Miscellaneous 3
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
7:4
Reserved.
3:0
PrtlChPDDynDly: partial channel power down dynamic delay. Read-write. BIOS:4h. Specifies
the channel idle hysteresis for fast exit/slow exit mode changes when D18F2xA8_dct[0][PrtlChPDEnhEn]=1.
Bits
Description
0h
0 clocks
7h-1h
<PrtlChPDDynDly*32> clocks
8h
256 clocks
Fh-9h
Reserved
D18F2x248_dct[0]_mp[1:0] DRAM Power Management 0
IF (BootFromDRAM) THEN Cold reset: 0000_0C05h. ELSE Reset: 0000_0A03h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
Bits
Description
31
RxChMntClkEn: Receive channel maintenance clocks. Read-Write. BIOS: 0.
1=Enable receive channel maintenance clocks to improve internal timing margin at the cost of some
extra power. 0=Disable clocks. To disable clocks, BIOS must first disable clock generation in the phy
(see D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0][RxSsbMntClkEn]).
30
Reserved.
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29:24 AggrPDDelay: aggressive power down delay. Read-Write. BIOS: 20h. Specifies a hysteresis count
from the last DRAM activity for the DCT to close pages prior to precharge power down. The counter
does not start until the DCQ, RDQ, and WDQ are empty. The counter runs orthogonal to the page policy specified by D18F2x90_dct[0][DynPageCloseEn]. Reserved if D18F2xA8_dct[0][AggrPDEn]==0. See PchgPDEnDelay and D18F2x94_dct[0][PowerDownEn].
Description
Bits
00h
64 clocks
01h
1 clock
3Eh-02h
<AggrPDDelay> clocks
3Fh
63 clocks
23:22 Reserved.
21:16 PchgPDEnDelay: precharge power down entry delay. Read-write.
BIOS: IF (D18F2xA8_dct[0][AggrPDEn]) THEN (D18F2x200_dct[0]_mp[1:0][Tcl] + 5 +
CEIL((MAX(D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay]) + 0.5) / 2))
ELSE 00h ENDIF.
Specifies the power down entry delay. If D18F2xA8_dct[0][AggrPDEn]==0, this delay behaves as a
hysteresis. This field must satisfy the minimum power down entry delay requirements. See also
D18F2x94_dct[0][PowerDownEn].
Rule: PchgPDEnDelay == 0 || PchgPDEnDelay >= D18F2x200_dct[0]_mp[1:0][Tcl] + 5 +
CEIL((MAX(D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0][DqsRcvEnGrossDelay]) + 0.5) / 2).
Bits
00h
01h
3Eh-02h
3Fh
Description
64 clocks
1 clock
<PchgPDEnDelay> clocks
63 clocks
15:13 Reserved.
12:8 Txpdll: exit DLL and precharge powerdown to command delay. Read-write. Specifies the minimum time that the DCT waits to issue a command after exiting precharge powerdown mode if the
DLL was also disabled.
Bits
Description
09h-00h
Reserved
1Dh-0Ah
<Txpdll> clocks
1Fh-1Eh
Reserved
7:4
Reserved.
3:0
Txp: exit precharge PD to command delay. Read-write. Specifies the minimum time that the DCT
waits to issue a command after exiting precharge powerdown mode.
Bits
Description
2h-0h
Reserved
8h-3h
<Txp> clocks
Fh-9h
Reserved
D18F2x24C_dct[0] DDR3 DRAM Power Management 1
IF (BootFromDRAM) THEN Cold reset: 0214_0803h. ELSE Reset: 0214_0803h. ENDIF.See 2.9.3 [DCT
Configuration Registers].
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Bits
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Description
31:30 Reserved.
29:24 Tcksrx: clock stable to self refresh exit delay. Read-write. Specifies the minimum time in memory
clock cycles that the DCT waits to assert CKE after clock frequency is stable.
Bits
Description
01h-00h
Reserved
0Eh-02h
<Tcksrx> clocks
3Fh-0Fh
Reserved
23:22 Reserved.
21:16 Tcksre: self refresh to command delay. Read-write. Specifies the minimum time in memory clock
cycles that the DCT waits to remove external clocks after entering self refresh or powerdown.
Bits
Description
04h-00h
Reserved
27h-05h
<Tcksre> clocks
3Fh-28h
Reserved
15:14 Reserved.
13:8 Tckesr: self refresh to command delay. Read-write. Specifies the minimum time in memory clock
cycles that the DCT waits to issue a command after entering self refresh.
Bits
Description
01h-00h
Reserved
2Bh-02h
<Tckesr> clocks
3Fh-2Ch
Reserved
7:4
Reserved.
3:0
Tpd: minimum power down entry to exit. Read-write. Specifies minimum time in memory clock
cycles for powerdown entry to exit timing.
Bits
Description
0h
Reserved
Ah-1h
<Tpd> clocks
Fh-Bh
Reserved
D18F2x250_dct[0] DRAM Loopback and Training Control
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
20:18 DataPatGenSel: data pattern generator select. IF (D18F2x118[LockDramCfg] &
~D18F3x12C[OverrideLockDramCfg]) THEN Read-only; S3-check-exclude. ELSE Read-write; S3check-exclude. ENDIF.
Description
Bits
000b
PRBS23 I.
001b
PRBS23 II. Within a byte lane, the DQ[n] value is offset 8n bit times from DQ[0].
010b
Configurable data pattern. See D18F2x2[B4,B0,AC,A8]_dct[0].
011b
Configurable data pattern with circular lane shift. See D18F2x2[B4,B0,AC,A8]_dct[0].
100b
PRBS23 III. Within a byte lane, each DQ[n] value is equal to DQ[0].
111b-101b Reserved.
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17
ActPchgGenEn: activate precharge generation enable. IF (D18F2x118[LockDramCfg] &
~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. 1=The DCT
generates ACT and PRE traffic in the available command bandwidth from SendCmd. 0=Traffic generation is not enabled. Reserved if ~CmdTestEnable.
15
Reserved. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Readonly. ELSE Read; write-1-only; cleared-by-hardware. ENDIF.
13
LfsrRollOver: LFSR roll over. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. Specifies the behavior of DataPrbsSeed and
the data comparison logic if the generated address wraps around to equal
D18F2x25[8,4]_dct[0][TgtAddress]. 0=The PRBS will not be re-seeded. 1=The PRBS will be reseeded.
12
CmdSendInProg: command in progress. Read-only; updated-by-hardware. 0=DCT is idle. 1=DCT
is busy.
11
SendCmd: send command. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. 0=Stop command generation. 1=Begin command
generation as specified in CmdTgt, CmdType, and D18F2x260_dct[0][CmdCount]. BIOS must set
this field to a 0 after a command series is completed. Reserved if ~CmdTestEnable.
10
TestStatus: test status. Read-only. 0=Command generation is in progress. 1=Command generation
has completed. Reserved if ~(SendCmd & (D18F2x260_dct[0][CmdCount] > 0 | StopOnErr)).
9:8
CmdTgt: command target. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. Specifies the SendCmd command target address
mode. See D18F2x25[8,4]_dct[0].
Bits
Description
00b
Issue commands to address Target A
01b
Issue alternating commands to address Target A and Target B
11b-10b
Reserved
7:5
CmdType: command type. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. Specifies the SendCmd command type.
Bits
Description
000b
Read
001b
Write
010b
Alternating write and read
111b-011b
Reserved
4
StopOnErr: stop on error. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. Specifies the DCT behavior if a data comparison
error occurs. 1=Stop command generation. DCT behavior is imprecise, depending on when an error is
detected vs. in-flight commands. 0=Continue command generation. If StopOnErr=1, BIOS must program ResetAllErr=1 when programming SendCmd=1.
3
ResetAllErr: reset all errors. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read; write-1-only; cleared-by-hardware. ENDIF. 1=Clear error status
bits and error counters in D18F2x264_dct[0], D18F2x268_dct[0], and D18F2x26C_dct[0]. This bit
may be written along with SendCmd.
2
CmdTestEnable: command test enable. IF (D18F2x118[LockDramCfg] & ~D18F3x12C[OverrideLockDramCfg]) THEN Read-only. ELSE Read-write. ENDIF. 0=Disable the command generation
mode. 1=Enable the command generation mode. See SendCmd. Enabling this mode disables the DCT
speculative precharge logic. Reserved if D18F2x250_dct[0][LoopbackBistEn].
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D18F2x25[8,4]_dct[0] DRAM Target [B, A] Base
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Table 168: Register Mapping for D18F2x25[8,4]_dct[0]
Register
D18F2x254_dct[0]
D18F2x258_dct[0]
Bits
Function
Target A
Target B
Description
31:27 Reserved.
26:24 TgtChipSelect: target chip select. Read-write; S3-check-exclude. Specifies the chip select.
Bits
Description
111b-000b
CS<TgtChipSelect>
23:21 TgtBank: target bank [2:0]. Read-write; S3-check-exclude. Specifies the bank address.
20:16 Reserved.
15:10 TgtAddress[15:10]: target address [15:10]. Read-write; S3-check-exclude. Specifies the upper column address bits [15:10]. Software must always program bit 10 and bit 12 equal to 0.
9:0
TgtAddress[9:0]: target address [9:0]. Read-write; S3-check-exclude. Specifies the column address
bits [9:0]. Column address bits [15:10] = 0. The address sequencing in a command series occurs as
follows: TgtAddress[9:3] is incremented by one with wrap around. The increment occurs after each
command if D18F2x250_dct[0][CmdType] = 00xb or if (D18F2x250_dct[0][CmdType] = 010b and
D18F2x250_dct[0][CmdTgt] = 01b). The increment occurs after each command pair if
(D18F2x250_dct[0][CmdType] = 010b and D18F2x250_dct[0][CmdTgt] = 00b). The value of
TgtAddress is not updated by hardware.
D18F2x25C_dct[0] DRAM Command 0
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0001h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:22 BubbleCnt2: bubble count 2. See: BubbleCnt. Specifies the number of NOP commands inserted
after the last clock of virtual CAS of each read-burst operation in alternating write and read mode.
Defined only if (D18F2x250_dct[0][CmdType] == 010b); otherwise reserved.
21:12 BubbleCnt: bubble count. Read-write; S3-check-exclude. Specifies the number of NOP commands
inserted after the last clock of virtual CAS of the last command of the command stream specified by
CmdStreamLen.
Bits
Description
000h
0 command bubbles
3FEh-001h
<BubbleCnt> command bubbles
3FFh
3FFh command bubbles
11:9 Reserved.
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8
CmdTimingEn: command timing enable. Read-write; S3-check-exclude. 1=Forces DCT to schedule RRW commands initiated by D18F2x250_dct[0][SendCmd] to adhere to the same DRAM timing
parameters as normal traffic. 0=Commands initiated by D18F2x250_dct[0][SendCmd] ignore DRAM
timing parameters.
7:0
CmdStreamLen: command stream length. Read-write; S3-check-exclude. Specifies the number of
commands(CAS’s on the bus) generated before BubbleCnt bubbles are inserted.
Bits
Description
00h
Reserved
01h
1 command
FEh-02h
<CmdStreamLen> commands; defined only if ~(D18F2x250_dct[0][CmdType]=010b)
FFh
255 commands; defined only if ~(D18F2x250_dct[0][CmdType]=010b)
The following two examples apply for DDR3:
e.g. CmdType=000b, BubbleCnt=3, CmdStreamLen=2:
| RD | NOP | NOP | NOP (LVC) | RD | NOP | NOP | NOP (LVC) | NOP | NOP | NOP | RD | …
e.g. CmdType=010b, BubbleCnt=2 CmdStreamLen=1:
| WR | NOP | NOP | NOP (LVC) | NOP | NOP | RD | NOP | NOP | NOP (LVC) | NOP | NOP | …
D18F2x260_dct[0] DRAM Command 1
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:21 Reserved.
20:0 CmdCount: command count. Read-write; S3-check-exclude. Specifies the maximum number of
commands to generate when D18F2x250_dct[0][SendCmd]=1. See also D18F2x250_dct[0][StopOnErr].
Description
Bits
0h
Infinite commands.
1F_FFFFh-1h
<CmdCount> commands
D18F2x264_dct[0] DRAM Status 0
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
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31:25 ErrDqNum: error DQ number. Read-only; S3-check-exclude. Indicates the DQ bit of the first error
occurrence when D18F2x264_dct[0][ErrCnt] > 0. Cleared by D18F2x250_dct[0][ResetAllErr].
Bits
Description
3Fh-00h
Data[<ErrDqNum>]
47h-40h
ECC[7:0]
7Fh-48h
Reserved
24:0 ErrCnt: error count. Read; set-by-hardware; write-1-to-clear. Specifies a saturating counter indicating the number of DQ bit errors detected. Counts a maximum of 1 error per bit-lane per each bit-time.
Status is accumulated until cleared by D18F2x250_dct[0][ResetAllErr].
Errors can be masked on per-bit basis by programming D18F2x274_dct[0], D18F2x278_dct[0], and
D18F2x27C_dct[0].
IF D18F2x250_dct[0][LoopbackBistEn] = 1, Mx_RESET_L can be used as an external trigger when
an error event occurs. In this mode, a pulse at least 1 MEMCLK wide is asserted on the
Mx_RESET_L pin when an error is counted. If D18F2x250_dct[0][StopOnErr]=1, Mxx_RESET_L
will be asserted until cleared by D18F2x250_dct[0][ResetAllErr]. In this mode, if any LFSR seed is
detected as all 0’s then hardware writes all 1’s to this field.
Description
Bits
0h
0 errors
1FF_FFFDh-1h
<ErrCnt> errors
1FF_FFFEh
1FF_FFFEh errors
1FF_FFFFh
1FF_FFFFh or more errors, or any LFSR seed is zero when in loopback mode
D18F2x268_dct[0] DRAM Status 1
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:20 Reserved.
19:0 NibbleErrSts: nibble error status. Read-only; S3-check-exclude. Indicates error detection status on
a per nibble basis when D18F2x264_dct[0][ErrCnt] > 0. Status is accumulated until cleared by
D18F2x250_dct[0][ResetAllErr].
Description
Bit
[15:0]
Data[<(NibbleErrSts*4)+3>:<NibbleErrSts*4>]
[16]
ECC[3:0]
[17]
ECC[7:4]
[19:18]
Reserved
D18F2x26C_dct[0] DRAM Status 2
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
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31:18 Reserved.
17:0 NibbleErr180Sts: nibble error 180 status. Read-only; S3-check-exclude. Indicates error detection
status on a per nibble basis when D18F2x264_dct[0][ErrCnt] > 0, comparing read data against data
shifted 1-bit time earlier. I.e. Hardware compares an incoming bit time 180 degrees out of phase, N=0,
1, …, 6 read to bit time N=1, 2, …, 7 written. Status is accumulated until cleared by
D18F2x250_dct[0][ResetAllErr].
Bit
Description
[15:0]
Data[<(NibbleErr180Sts]*4)+3>:<NibbleErr180Sts*4>]
[16]
ECC[3:0]
[17]
ECC[7:4]
D18F2x270_dct[0] DRAM PRBS
See 2.9.3 [DCT Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
31
Description
Reserved.
23:19 Reserved.
18:0 DataPrbsSeed: data PRBS seed. Read-write; S3-check-exclude. IF (BootFromDRAM) THEN Cold
reset: 7FFFFh. ELSE Reset: 7FFFFh. ENDIF. Specifies the seed value used for creating pseudo random traffic on the data bus. This register must be written with a non-zero seed value. PRBS23 is
based on a 23 bit LFSR with polynomial G(x) = x^23 + x^18 + 1. The LFSR for each byte lane is
seeded as follows: {DataPrbsSeed, 4-bit byte lane index}. PRBS bits [7:0] map to byte lane bits [7:0].
Recommended BIOS values for DRAM training:
DataPrbsSeed
CmdCount
32
62221h
64
66665h
128
26666h
256
44443h
D18F2x274_dct[0] DRAM DQ Mask Low
See D18F1x10C[DctCfgSel]. See 2.9.3 [DCT Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:0 DQMask[31:0]: DQ mask. Read-write; S3-check-exclude. DQMask[63:0] =
{D18F2x278_dct[0][DQMask[63:32]], DQMask[31:0]}. IF (BootFromDRAM) THEN Cold reset:
0000_0000_0000_0000h. ELSE Reset: 0000_0000_0000_0000h. ENDIF. 1=The corresponding DQ
bit will not be compared. 0=The corresponding DQ bit will be compared. See
D18F2x264_dct[0][ErrCnt].
Bit
Description
[0]
Data[0]
[62:1]
Data[<DQMask>]
[63]
Data[63]
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D18F2x278_dct[0] DRAM DQ Mask High
Bits
Description
31:0 DQMask[63:32]: DQ mask. See: D18F2x274_dct[0][DQMask[31:0]].
D18F2x27C_dct[0] DRAM ECC and EDC Mask
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:20 Reserved.
19:16 Reserved.
15:8 Reserved.
7:0
EccMask: ECC mask. Read-write; S3-check-exclude. 1=The corresponding ECC DQ bit will not be
compared. 0=The corresponding ECC DQ bit will be compared. See D18F2x264_dct[0][ErrCnt].
Bit
[0]
[6:1]
[7]
Description
ECC[0]
ECC[<EccMask>]
ECC[7].
D18F2x280_dct[0] DRAM DQ Pattern Override 0
See D18F1x10C[DctCfgSel]. See 2.9.3 [DCT Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:0 DQPatOvrEn[31:0]: DQ pattern override enable. Read-write; S3-check-exclude. DQPatOvrEn[63:0] = {D18F2x284_dct[0][DQPatOvrEn[63:32]], DQPatOvrEn[31:0]}. IF
(BootFromDRAM) THEN Cold reset: 0000_0000_0000_0000h. ELSE Reset:
0000_0000_0000_0000h. ENDIF. 1=The pattern on this DQ bit lane will be overridden with a static
value specified by D18F2x288_dct[0][PatOvrVal]. 0=The pattern on this DQ bit lane will not be overridden. Reserved if D18F2x250_dct[0][DataPatGenSel] != 10b.
Bit
Description
[0]
Data[0]
[62:1]
Data[<DQPatOvrEn[31:0]>]
[63]
Data[63]
D18F2x284_dct[0] DRAM DQ Pattern Override 1
Bits
Description
31:0 DQPatOvrEn[63:32]: DQ pattern override enable. See: D18F2x280_dct[0][DQPatOvrEn[31:0]].
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D18F2x288_dct[0] DRAM DQ Pattern Override 2
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See
D18F1x10C[DctCfgSel]. See 2.9.3 [DCT Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:24 XorPatOvr: xor pattern override. Read-write; S3-check-exclude. Specifies the override data
pattern used.
for creating traffic on the data bus. The output data for each DQ of each byte lane will be XOR’d with
the specified values. Reserved if D18F2x250_dct[0][DataPatGenSel] != 100b.
Description
Bit
[0]
DQ[0]
[1]
DQ[1]
[6:2]
DQ[<XorPatOvr>]
[7]
DQ[7]
23:9 Reserved.
8
PatOvrVal: pattern override value. Read-write; S3-check-exclude. Specifies the override data
7:0
pattern used.
for creating traffic on the data bus. 1=Static 1’s. 0=Static 0’s. Reserved if
D18F2x250_dct[0][DataPatGenSel] != 10b.
EccPatOvrEn: ECC pattern override enable. Read-write; S3-check-exclude. See
D18F2x280_dct[0][DQPatOvrEn]
Description
Bit
[0]
ECC[0]
[1]
ECC[1]
[6:2]
ECC[<EccPatOvr>]
[7]
ECC[7].
D18F2x28C_dct[0] DRAM Command 2
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation]. This register may only be used when
D18F2x250_dct[0][CmdTestEnable]=1.
Bits
Description
31
SendActCmd: send activate command. Read; write-1-only; cleared-by-hardware. 1=The DCT
sends an activate command as specified by ChipSelect, Bank, and Address. This bit is cleared by
hardware after the command completes.
30
SendPchgCmd: send precharge all command. Read; write-1-only; cleared-by-hardware. The DCT
sends a precharge command based on CmdAddress[10]. This bit is cleared by hardware after the command completes. 0=Command has completed. 1=If (CmdAddress[10]=1) then send a precharge all
command as specified by CmdChipSelect; If (CmdAddress[10]=0) then send a precharge command
as specified by CmdChipSelect, CmdBank.
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29:22 CmdChipSelect: command chip select. Read-write; S3-check-exclude. Specifies the chip select.
Bit
[7:0]
Description
CS<CmdChipSelect>
21:19 CmdBank: command bank [2:0]. Read-write; S3-check-exclude. Specifies the bank address.
Bits
Description
7h-0h
Bank<CmdBank>
18
Reserved.
17:0 CmdAddress: command address [17:0]. Read-write; S3-check-exclude. Specifies the row address.
D18F2x290_dct[0] DRAM Status 3
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:27 Reserved.
26:24 ErrBeatNum: error beat number. Read-only. Indicates the data beat of the first error occurrence in
the command reported by ErrCmdNum when D18F2x264_dct[0][ErrCnt] > 0 and
D18F2x260_dct[0][CmdCount] > 0. Cleared by D18F2x250_dct[0][ResetAllErr].
Bits
Description
7h-0h
<ErrBeatNum> beat
23:21 Reserved.
20:0 ErrCmdNum: error command number. Read-only. Indicates the command number of the first
error occurrence when D18F2x264_dct[0][ErrCnt] > 0 and D18F2x260_dct[0][CmdCount] > 0.
Cleared by D18F2x250_dct[0][ResetAllErr].
Bits
Description
1F_FFFFh-0h
<ErrCmdNum> command
D18F2x294_dct[0] DRAM Status 4
See 2.9.3 [DCT Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:0 DQErr[31:0]: DQ error. Read-only; S3-check-exclude. DQErr[63:0] =
{D18F2x298_dct[0][DQErr[63:32]], DQErr[31:0]}. IF (BootFromDRAM) THEN Cold reset:
0000_0000_0000_0000h. ELSE Reset: 0000_0000_0000_0000h. ENDIF. Indicates error detection
status on a per bit basis when D18F2x264_dct[0][ErrCnt] > 0. Status is accumulated until cleared by
D18F2x250_dct[0][ResetAllErr].
Description
Bit
[0]
Data[0]
[62:1]
Data[<DQErr>]
[63]
Data[63]
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D18F2x298_dct[0] DRAM Status 5
Bits
31:0
Description
DQErr[63:32]: DQ error. See: D18F2x294_dct[0][DQErr[31:0]].
D18F2x29C_dct[0] DRAM Status 6
IF (BootFromDRAM) THEN Cold reset: 0000_0000h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:20 Reserved.
19:16 Reserved.
15:8 Reserved.
7:0
EccErr: ECC error. Read-only; S3-check-exclude. Indicates ECC error detection status on a per bit
basis when D18F2x264_dct[0][ErrCnt] > 0. Status is accumulated until cleared by
D18F2x250_dct[0][ResetAllErr].
Bit
Description
[0]
ECC[0]
[6:1]
ECC[<EccErr>]
[7]
ECC[7]
D18F2x2[B4,B0,AC,A8]_dct[0] DRAM User Data Pattern
IF (BootFromDRAM) THEN Cold reset: 5555_5555h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Table 169: Register Mapping for D18F2x2[B4,B0,AC,A8]_dct[0]
Register
D18F2x2A8_dct[0]
D18F2x2AC_dct[0]
D18F2x2B0_dct[0]
D18F2x2B4_dct[0]
Function
Nibble Lanes 0, 4, 8, 12, 16
Nibble Lanes 1, 5, 9, 13, 17
Nibble Lanes 2, 6, 10, 14
Nibble Lanes 3, 7, 11, 15
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Table 170: Field Mapping for D18F2x2[B4,B0,AC,A8]_dct[0]
Register
Bits
Bits
31:24
23:16
15:8
7:0
D18F2x2A8_dct[0]
DQ3,
DQ19,
DQ35,
DQ51,
ECC3
DQ2,
DQ18,
DQ34,
DQ50,
ECC2
DQ1,
DQ17,
DQ33,
DQ49,
ECC1
DQ0,
DQ16,
DQ32,
DQ48,
ECC0
D18F2x2AC_dct[0]
DQ7,
DQ23,
DQ39,
DQ55,
ECC7
DQ6,
DQ22,
DQ38,
DQ54,
ECC6
DQ5,
DQ21,
DQ37,
DQ53,
ECC5
DQ4,
DQ20,
DQ36,
DQ52,
ECC4
D18F2x2B0_dct[0]
DQ11,
DQ27,
DQ43,
DQ59
DQ10,
DQ26,
DQ42,
DQ58
DQ9,
DQ25,
DQ41,
DQ57
DQ8,
DQ24,
DQ40,
DQ56
D18F2x2B4_dct[0]
DQ15,
DQ31,
DQ47,
DQ63
DQ14,
DQ30,
DQ46,
DQ62
DQ13,
DQ29,
DQ45,
DQ61
DQ12,
DQ28,
DQ44,
DQ60
Description
31:24 DataPattern: data pattern. See: D18F2x2[B4,B0,AC,A8]_dct[0][7:0].
23:16 DataPattern: data pattern. See: D18F2x2[B4,B0,AC,A8]_dct[0][7:0].
15:8 DataPattern: data pattern. See: D18F2x2[B4,B0,AC,A8]_dct[0][7:0].
7:0
DataPattern: data pattern. Read-write; S3-check-exclude. Specifies a data pattern used for creating
traffic on the data bus for the specified bit lanes. See D18F2x250_dct[0][DataPatGenSel].
Description
Bit
[0]
Pattern Data Beat 0
[6:1]
Pattern Data Beat 1 to Pattern Data Beat 6
[7]
Pattern Data Beat 7
D18F2x2B8_dct[0] DRAM Command 3
IF (BootFromDRAM) THEN Cold reset: 0000_0F00h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Bits
Description
31:16 ActPchgSeq: activate precharge sequence. Read-write; S3-check-exclude. Specifies the command
that will be generated in the sequence, corresponding to the sixteen target entries in
D18F2x2[C0,BC]_dct[0]. 1=Activate. 0=Precharge.
Bit
Description
[0]
ACT/PRE [0]
[14:1]
ACT/PRE [<ActPchgSeq>]
[15]
ACT/PRE [15]
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15:12 Reserved.
11:8 ActPchgCmdMin: activate precharge command minimum. Read-write; S3-check-exclude. Specifies the minimum time in memory clock cycles from an activate or precharge command to the next
activate or precharge command in the ActPchgSeq sequence.
Bits
Description
0
Reserved
Fh-1h
[<ActPchgCmdMin>] clocks
7:0
Reserved.
D18F2x2[C0,BC]_dct[0] DRAM Command 4 & 5
Reset: 0000_0000h. See 2.9.3 [DCT Configuration Registers]. See 2.9.8 [Continuous Pattern Generation].
Table 171: Field Mappings for D18F2x2[C0,BC]_dct[0]
Register
Bits
Bits
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
D18F2x2BC_dct[0]
ACT/PRE
7
ACT/PRE
6
ACT/PRE
5
ACT/PRE
4
ACT/PRE
3
ACT/PRE
2
ACT/PRE
1
ACT/PRE
0
D18F2x2C0_dct[0]
ACT/PRE
15
ACT/PRE
14
ACT/PRE
13
ACT/PRE
12
ACT/PRE
11
ACT/PRE
10
ACT/PRE
9
ACT/PRE
8
Description
31:28 ActPchgTgtBank: activate precharge target bank. See: D18F2x2[C0,BC]_dct[0][3:0].
27:24 ActPchgTgtBank: activate precharge target bank. See: D18F2x2[C0,BC]_dct[0][3:0].
23:20 ActPchgTgtBank: activate precharge target bank. See: D18F2x2[C0,BC]_dct[0][3:0].
19:16 ActPchgTgtBank: activate precharge target bank. See: D18F2x2[C0,BC]_dct[0][3:0].
15:12 ActPchgTgtBank: activate precharge target bank. See: D18F2x2[C0,BC]_dct[0][3:0].
11:8 ActPchgTgtBank: activate precharge target bank. See: D18F2x2[C0,BC]_dct[0][3:0].
7:4
ActPchgTgtBank: activate precharge target bank. See: D18F2x2[C0,BC]_dct[0][3:0].
3:0
ActPchgTgtBank: activate precharge target bank. Read-write; S3-check-exclude. Specifies the
bank address used for this command of the sequence.
Description
Bits
7h-0h
Bank [<ActPchgTgtBank>]
Fh-8h
Reserved
D18F2x2E0_dct[0] Memory P-state Control and Status
See 2.9.3 [DCT Configuration Registers].
Bits
31
Description
Reserved.
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30
FastMstateDis: fast M-state change disable. Read-write. IF (BootFromDRAM) THEN Cold reset:
0. ELSE Reset: 0. ENDIF. 1=The DCT changes MEMCLK frequency only after the NCLK frequency
has changed. 0=The DCT changes MEMCLK frequency while the northbridge changes NCLK.
29
Reserved.
28:24 M1MemClkFreq: M1 memory clock frequency. Read-write. IF (BootFromDRAM) THEN Cold
reset: 00h. ELSE Reset: 00h. ENDIF. Specifies the frequency of the DRAM interface (MEMCLK) for
memory P-state 1. See Table 124 [Valid Values for Memory Clock Frequency Value Definition]. The
hardware enforces D18F5x84[DdrMaxRateEnf] when writes to this field occur. See
D18F5x84[DdrMaxRate] and D18F5x84[DdrMaxRateEnf]. Hardware does not generate a x0B write
for this register. BIOS must also program D18F2x9C_x0D0F_E000_dct[0]_mp[1:0][Rate] for M1.
23
Reserved. Reserved for MxMrs3En.
22:20 MxMrsEn: Mx Mrs enable. Read-write. IF (BootFromDRAM) THEN Cold reset: 0h. ELSE
Reset:0h. ENDIF. 1=The DCT writes to the DRAM MR after a memory P-state change. 0=The DCT
does not write to the DRAM MR.
Bit
Description, MR value
[0]
MR0, D18F2x2E8_dct[0]_mp[1:0][MxMr0]
[1]
MR1, D18F2x2E8_dct[0]_mp[1:0][MxMr1]
[2]
MR2, D18F2x2EC_dct[0]_mp[1:0][MxMr2]
19:1 Reserved.
0
CurMemPstate: current memory P-state. Reset: 0h. Read-only; updated-by-hardware. Specifies
the current memory P-state. 0=M0. 1=M1.
D18F2x2E8_dct[0]_mp[1:0] MRS Buffer
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31:16 MxMr1: Mx MR1. Read-write. IF (BootFromDRAM) THEN Cold reset: 0000h. ELSE Reset:
0000h. ENDIF. Specifies the value written to DRAM MR1 after a memory P-state change. If the M1
value is the same as the M0 value, then BIOS should optimize P-state switching latency by programming D18F2x2E0_dct[0][MxMrsEn]=0.
15:0 MxMr0: Mx MR0. Read-write. IF (BootFromDRAM) THEN Cold reset: 0000h. ELSE Reset:
0000h. ENDIF. Specifies the value written to DRAM MR0 after a memory P-state change. If the M1
value is the same as the M0 value, then BIOS should optimize P-state switching latency by programming D18F2x2E0_dct[0][MxMrsEn]=0.
D18F2x2EC_dct[0]_mp[1:0] MRS Buffer
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31:16 Reserved.
15:0 MxMr2: Mx MR2. Read-write. IF (BootFromDRAM) THEN Cold reset: 0000h. ELSE Reset:
0000h. ENDIF. Specifies the value written to DRAM MR2 after a memory P-state change. If the M1
value is the same as the M0 value, then BIOS should optimize P-state switching latency by programming D18F2x2E0_dct[0][MxMrsEn]=0.
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D18F2x2F0_dct[0]_mp[1:0] DRAM Controller Misc 3
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31:1 Reserved.
0
EffArbDis: Efficient arbitration disable. Read-write. IF (BootFromDRAM) THEN Cold reset: 0.
ELSE Reset: 0. ENDIF. BIOS: 0. 0=The DCT optimizes the arbitration phases to improve performance (in addition to EarlyArbEn=1, this applies to non-page-hit DRAM commands) under certain
traffic conditions whenever the NCLK to MEMCLK ratio is less than 2:1. The DCT arbitrates normally with other ratios. 1=The DCT arbitrates normally, requiring 3 NCLKs, at all NCLK:MEMCLK
ratios. If the NCLK to MEMCLK ratio is less than 2:1, the DCT issues non-PH commands at most
every other MEMCLK cycle.
D18F2x400_dct[0] GMC to DCT Control 0
IF (BootFromDRAM) THEN Cold reset: 0000_0404h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
The GMC to DCT interface (GARLIC) controls how DRAM bus resources are allocated and arbitrated
between the MCT and the GMC. A token is the unit of available resource and is equivalent to a DCQ entry. A
minimum count ensures a number of available DCQ entries. A token limit for MCT or GMC ensures resources
are not all allocated to the GMC, or MCT respectively. Limits are configured bimodal: for normal GMC traffic
and for when urgent (nominally display refresh) GMC traffic is occurring.
Rule: D18F2x400_dct[0][MctTokenLimit] + D18F2x400_dct[0][GmcTokenLimit] <= 16.
Rule: D18F2x400_dct[0][GmcTokenLimit] >= 1.
Rule: D18F2x400_dct[0][MctTokenLimit] >= 1.
Rule: D18F2x404_dct[0][UrGmcTokenLimit] + D18F2x404_dct[0][UrMctTokenLimit] <= 16.
Rule: D18F2x404_dct[0][UrGmcMinTokens] + D18F2x404_dct[0][UrMctMinTokens] <= 16.
Rule: D18F2x400_dct[0][MctTokenLimit] == D18F2x404_dct[0][UrMctTokenLimit].
Bits
Description
31:16 Reserved.
15:12 Reserved.
11:8 GmcTokenLimit: GMC token limit. Read-write.BIOS: 4h. Limit of outstanding GMC tokens.
Bits
Description
Fh-0h
<GmcTokenLimit> tokens
7:4
Reserved.
3:0
MctTokenLimit: MCT token limit. Read-write. BIOS: 4h. Limit of outstanding MCT tokens.
Bits
Description
Fh-0h
<MctTokenLimit> tokens
D18F2x404_dct[0] GMC to DCT Control 1
IF (BootFromDRAM) THEN Cold reset: 0004_0004h. ELSE Reset: 0000_0000h. ENDIF. See 2.9.3 [DCT
Configuration Registers].
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Bits
31
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Description
UrgentTknDis: Urgent token disable. Read-write. BIOS: 0. 0=When urgent GMC traffic is
requested (GarlicTokUrg), override the programmed values in D18F2x400_dct[0] and force the token
scheme to heavily weight towards graphics by using the programmable token limits in
D18F2x404_dct[0]. 1=Token scheme remains at the previously programmed non-urgent token limits
in D18F2x400_dct[0] regardless of urgent GMC traffic.
30:28 Reserved.
27:24 UrGmcMinTokens: Display refresh GMC minimum tokens. Read-write. BIOS: 4. Urgent mode
minimum number of tokens assigned to the GMC.
Bits
Description
Fh-0h
<UrGmcMinTokens> tokens
23:21 Reserved.
20:16 UrGmcTokenLimit: Display refresh GMC token limit. Read-write. BIOS: 04h. Urgent mode limit
of outstanding GMC tokens.
Bits
Description
10h-0h
<UrGmcTokenLimit> tokens
1Fh-11h
Reserved
15:12 Reserved.
11:8 UrMctMinTokens: Display refresh MCT minimum tokens. Read-write. BIOS: 4. Urgent mode
minimum number of tokens assigned to the MCT.
Bits
Description
Fh-0h
<UrMctMinTokens> tokens
7:5
Reserved.
4:0
UrMctTokenLimit: Display refresh MCT token limit. Read-write. BIOS: 04h. Urgent mode limit
of outstanding MCT tokens. Rule: IF (!(D18F2x404_dct[0][UrgentTknDis])) THEN
D18F2x404_dct[0][UrMctTokenLimit] <= D18F2x400_dct[0][MctTokenLimit].
Bits
Description
10h-0h
<UrMctTokenLimit> tokens
1Fh-11h
Reserved
D18F2x408_dct[0] GMC to DCT Control 2
See 2.9.3 [DCT Configuration Registers].
Bits
Description
28:24 CpuElevPrioPeriod: Cpu elevate priority period. Read-write. Reset: 0. BIOS: Ch. Specifies the
hysteresis of how often a new MCT read can be elevated to high priority if no other MCT reads currently exist in the DCQ. If CpuElevPrioPeriod==0, MCT will continuously elevate the priority of a
new lone MCT read to high. Reserved if CpuElevPrioDis==1. Since this field controls internal timing
in the NCLK domain, external bus equivalence is approximate.
Bits
Description
00h
hysteresis counter disabled
1Fh-01h
<CpuElevPrioPeriod*32> MEMCLKs (*32 CmdOut, +/- NCLK)
23:3 Reserved.
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2
NonP0UrgentTknDis: non-P0 urgent token disable. Read-write. Reset: 0. BIOS: 0. 0=Switch from
normal GMC traffic token scheme defined by D18F2x400_dct[0] to urgent GMC traffic token scheme
defined by D18F2x404_dct[0] when all processors are not in software P0 state. 1=Use normal GMC
traffic token scheme when all processors are not in software P0 state.
1
TokenAllocSelect: Token allocation select. Read-write. IF (BootFromDRAM) THEN Cold reset: 0.
ELSE Reset: 0. ENDIF. BIOS: 0. 0=When both the MCT and GMC have less than their maximum
outstanding tokens, tokens are allocated by alternating between each. 1= When both the MCT and
GMC have less than their maximum outstanding tokens, tokens are allocated to whichever has less
(DCQ entries + current outstanding).
0
CpuElevPrioDis: Cpu elevate priority disable. Read-write. IF (BootFromDRAM) THEN Cold
reset: 0. ELSE Reset: 0. ENDIF. BIOS: 0. 1=Reads from MCT arbitrate with GMC traffic normally.
0=Elevate the priority of a new MCT read to high if no other MCT reads currently exist in the DCQ.
This can alleviate CPU stalls during very long graphics requests.
D18F2x420_dct[0] GMC to DCT FIFO Config 1
See 2.9.3 [DCT Configuration Registers].
Bits
Description
31:12 Reserved.
7:4
Reserved.
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3.12 Device 18h Function 3 Configuration Registers
See 3.1 [Register Descriptions and Mnemonics]. See 2.7 [Configuration Space].
D18F3x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID. Read-only.
Value: 1533h.
15:0 VendorID: vendor ID. Read-only. Value: 1022h.
D18F3x04 Status/Command
Bits
Description
31:16 Status. Read-only. Reset: 0000h, except bit[20]. Bit[20] is set to indicate the existence of a PCIdefined capability block, if one exists.
15:0 Command. Read-only. Reset: 0000h.
D18F3x08 Class Code/Revision ID
Bits
Description
31:8 ClassCode. Read-only. Reset: 060000h. Provides the host bridge class code as defined in the PCI
specification.
7:0
RevID: revision ID. Read-only. Reset: 00h.
D18F3x0C Header Type
Reset: 0080_0000h.
Bits
Description
31:0 HeaderTypeReg. Read-only. These bits are fixed at their default values. The header type field indicates that there are multiple functions present in this device.
D18F3x34 Capability Pointer
Bits
Description
31:8 Reserved.
7:0
CapPtr. Read-only. Value: 00h. DEV not implemented.
D18F3x40 MCA NB Control
Read-write. Reset: 0000_0000_0000_0000h. MSR0000_0410[31:0] is an alias of D18F3x40. See
MSR0000_0410[31:0].
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Bits Description
63:32 Unused.
31
McaCpuDatErrEn: L2 complex data error. 1=Enables MCA reporting of CPU data errors sent to
the NB.
29:28 Unused. Read-write.
27
Unused. Read-write.
26
NbArrayParEn: northbridge array parity error reporting enable. 1=Enables reporting of parity
errors in the NB arrays.
25
UsPwDatErrEn: upstream data error enable. Read-write. 1=Enables MCA reporting of upstream
posted writes in which the EP bit is set as indicated by the ONION error bits.
24:18 Unused. Read-write.
17
CpPktDatEn: completion packet error reporting enable. Read-write. 1=Enables MCA reporting of
completion packets with the EP bit set. Any response packet with data errors detected by ONION will
generate this error.
16
NbIntProtEn: northbridge internal bus (ONION) protocol error reporting enable. Read-write.
1=Enables MCA reporting of protocol errors detected on the northbridge internal bus (ONION). When
possible, this enable should be cleared before initiating a warm reset to avoid logging spurious errors
due to RESET_L signal skew.
15:13 Unused. Read-write.
12
WDTRptEn: watchdog timer error reporting enable. 1=Enables MCA reporting of watchdog timer
errors. The watchdog timer checks for NB system accesses for which a response is expected but no
response is received. See D18F3x44 [MCA NB Configuration] for information regarding
configuration of the watchdog timer duration. This bit does not affect operation of the watchdog timer
in terms of its ability to complete an access that would otherwise cause a system hang. This bit only
affects whether such errors are reported through MCA.
11
AtomicRMWEn: atomic read-modify-write error reporting enable. 1=Enables MCA reporting of
atomic read-modify-write (RMW) commands received from an IO link. Atomic RMW commands are
not supported. An atomic RMW command results in a link error response being generated back to the
requesting IO device. The generation of the link error response is not affected by this bit.
10
Unused. Read-write.
9
TgtAbortEn: target abort error reporting enable. 1=Enables MCA reporting of target aborts to a
link. The NB returns an error response back to the requestor with any associated data all 1s
independent of the state of this bit.
8
MstrAbortEn: master abort error reporting enable. 1=Enables MCA reporting of master aborts to
a link. The NB returns an error response back to the requestor with any associated data all 1s
independent of the state of this bit.
7:6
5
Unused. Read-write.
SyncPktEn: link sync packet error reporting enable. 1=Enables MCA reporting of link-defined
sync error packets detected on link. The NB floods its outgoing link with sync packets after detecting a
sync packet on the incoming link independent of the state of this bit.
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Unused. Read-write.
1
UECCEn: uncorrectable ECC error reporting enable. 1=Enables MCA reporting of DDR3 DRAM
uncorrectable ECC errors which are detected in the NB. In some cases data may be forwarded to the
core prior to checking ECC in which case the check takes place in one of the other error reporting
banks.
0
CECCEn: correctable ECC error reporting enable. 1=Enables MCA reporting of DDR3 DRAM
correctable ECC errors which are detected in the NB.
D18F3x44 MCA NB Configuration
See D18F3x180 [Extended NB MCA Configuration]. It is expected that all fields of this register are
programmed to the same value in all nodes, except for the fields used for link error injection: GenLinkSel,
GenSubLinkSel, GenCrcErrByte1, GenCrcErrByte0.
Bits
Description
31
NbMcaLogEn: northbridge MCA log enable. Read-write. Reset: 0. 1=Enables logging (but not
reporting) of NB MCA errors even if MCA is not globally enabled.
30
SyncFloodOnDramAdrParErr: sync flood on DRAM address parity error. Read-write. Reset: 0.
BIOS: 1. 1=Enable sync flood on detection of a DRAM address parity error.
29
DisMstAbortCpuErrRsp: master abort CPU error response disable. Read-write. Reset: 0.
1=Disables master abort reporting through the CPU MCA error-reporting banks; Suppresses sending
of RDE to CPU; Does not log any MCA information in the NB.
28
DisTgtAbortCpuErrRsp: target abort CPU error response disable. Read-write. Reset: 0. 1=Disables target abort reporting through the CPU MCA error-reporting banks; Suppresses sending of RDE
to CPU; Does not log any MCA information in the NB.
27
NbMcaToMstCpuEn: machine check errors to master CPU only. Read-write. Reset: 0. BIOS: 1.
1=NB MCA errors in CMP device are only reported to the node base core (NBC), and the NB MCA
registers in MSR space (MSR0000_0410, MSR0000_0411, MSR0000_0412, MSR0000_0413,
MSR0000_0408, and MSRC001_0048) are only accessible from the NBC; reads of these MSRs from
other cores return 0’s and writes are ignored. This allows machine check handlers running on different
cores to avoid coordinating accesses to the NB MCA registers. This field does not affect PCI-defined
configuration space accesses to these registers, which are accessible from all cores. See 3.1 [Register
Descriptions and Mnemonics] for a description of MSR space and 3 [Registers] for PCI-defined configuration space. 0=NB MCA errors may be reported to the core that originated the request, if applicable and known, and the NB MCA registers in MSR space are accessible from any core.
Note:
• When the CPU which originated the request is known, it is stored in MSR0000_0411[ErrCoreId],
regardless of the setting of NbMcaToMstCpuEn. See Table 206 for errors where ErrCoreId is
known.
• If IO originated the request, then the error is reported to the NBC, regardless of the setting of NbMcaToMstCpuEn.
26
FlagMcaCorrErr: correctable error MCA exception enable. Read-write. Reset: 0. 1=Raise a
machine check exception for correctable and deferred machine check errors which are enabled in
D18F3x40.
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25
DisPciCfgCpuErrRsp: PCI configuration CPU error response disable. Read-write. Reset: 0.
1=Disables generation of an error response to the core on detection of a master abort, target abort, or
data error condition, and disables logging and reporting through the MCA error-reporting banks for
PCI configuration accesses. For NB WDT errors on PCI configuration accesses, this prevents sending
an error response to the core, but does not affect logging and reporting of the NB WDT error. See
D18F3x180[DisPciCfgCpuMstAbortRsp], which applies only to master aborts.
24
IoRdDatErrEn: IO read data error log enable. Read-write. Reset: 0. 1=Enables MCA loggingand
reporting of errors on transactions from IO devices upon detection of a target abort, master abort, or
data error condition. 0=Errors on transactions from IO devices are not logged in MCA, although error
responses to the requesting IO device may still be generated.
Errors include the following for requests sourced from IO:
• Target abort, master abort, or data error
• P2P compatibility space error (either request or response)
• Extended addressing error
23
ChipKillEccCap: chip-kill ECC mode. Read-only; updated-by-hardware. Reset: 0. 1=Chipkill ECC
mode capable; ECC checking is based on x8 ECC symbols (D18F3x180[EccSymbolSize]) and can be
used for chipkill. 0=Chipkill ECC mode not capable; ECC checking is based on two interleaved,
unganged 64/8-bit data/ECC lines and x4 ECC symbols and cannot be used for chipkill. See 2.14.2
[DRAM ECC Considerations].
22
DramEccEn: DRAM ECC enable. Read-write. Reset: 0. 1=Enables ECC check/correct mode. This
bit must be set in order for ECC checking/correcting by the NB to be enabled. If set, ECC is checked
and correctable errors are corrected irrespective of whether machine check ECC reporting is enabled.
The hardware only allows values to be programmed into this field which are consistent with the ECC
capabilities of the device as specified in D18F3xE8 [Northbridge Capabilities]. Attempts to write values inconsistent with the capabilities results in this field not being updated. This bit does not affect
ECC checking in the northbridge arrays.
21
SyncFloodOnAnyUcErr: sync flood on any UC error. Read-write. Reset: 0. BIOS: 1. 1=Enable
sync flood of all links with sync packets on detection of any NB MCA error that is uncorrectable,
including northbridge array errors and link protocol errors.
20
SyncFloodOnWDT: sync flood on watchdog timer error. Read-write. Reset: 0. BIOS: 1. 1=Enable
sync flood of all links with sync packets on detection of a watchdog timer error. See D18F3x18C[DisSrqReqCompOnWDT].
19:18 GenSubLinkSel: sublink select for CRC error generation. Read-write. Reset: 0. Selects the sublink of a link selected by GenLinkSel to be used for CRC error injection through GenCrcErrByte0 and
GenCrcErrByte1. When the link is ganged, GenSubLinkSel must be 00b. When the link is unganged,
the following values indicate which sublink is selected:
Bits
Description
00b
Sublink 0
01b
Sublink 1
10b
Reserved
11b
Reserved
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17
GenCrcErrByte1: generate CRC error on byte lane 1. Read-Write. Reset: 0. 1=For ganged links
(see GenSubLinkSel), a CRC error is injected on byte lane 1 of the link specified by GenLinkSel. For
ganged links in retry mode or unganged links, this field is reserved, and GenCrcErrByte0 must be
used. The data carried by the link is unaffected. This bit is cleared after the error has been generated.
For ganged links in retry mode, GenCrcErrByte1 has no effect; only GenCrcErrByte0 may be used.
16
GenCrcErrByte0: generate CRC error on byte lane 0. Read-Write. Reset: 0. 1=Causes a CRC
error to be injected on byte lane 0 of the link specified by GenLinkSel and the sublink specified by
GenSubLinkSel. The data carried by the link is unaffected. This bit is cleared after the error has been
generated. For ganged links in retry mode, GenCrcErrByte1 has no effect; only GenCrcErrByte0 may
be used.
15:14 GenLinkSel: link select for CRC error generation. Read-Write. Reset: 00b. Selects the link to be
used for CRC error injection through GenCrcErrByte1/GenCrcErrByte0.
Bits
Description
00b
link 0
01b
link 1
10b
link 2
11b
link 3
13:12 WDTBaseSel: watchdog timer time base select. Read-write. Reset: 0. Selects the time base used by
the watchdog timer. The counter selected by WDTCntSel determines the maximum count value in the
time base selected by WDTBaseSel.
Bits
Description
00b
1.31 ms
01b
1.28 us
10b
Reserved.
11b
Reserved. (WDT disabled)
11:9 WDTCntSel[2:0]: watchdog timer count select bits[2:0]. Read-write. Reset: 0. Selects the count
used by the watchdog timer. WDTCntSel = {D18F3x180[WDTCntSel[3]], D18F3x44[WDTCntSel[2:0]]}. The counter selected by WDTCntSel determines the maximum count value in the time
base selected by WDTBaseSel. WDTCntSel is encoded as:
Bits
Description
0000b
4095
0001b
2047
0010b
1023
0011b
511
0100b
255
0101b
127
0110b
63
0111b
31
1000b
8191
1001b
16383
1111b-1010b
Reserved
Because WDTCntSel is split between two registers, care must be taken when programming WDTCntSel to ensure that a reserved value is never used by the watchdog timer or undefined behavior could
result.
8
WDTDis: watchdog timer disable. Read-write. Cold reset: 0. 1=Disables the watchdog timer. The
watchdog timer is enabled by default and checks for NB system accesses for which a response is
expected and where no response is received. If such a condition is detected the outstanding access is
completed by generating an error response back to the requestor. An MCA error may also be generated if enabled in D18F3x40 [MCA NB Control].
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7
IoErrDis: IO error response disable. Read-write. Reset: 0. 1=Disables setting either Error bit in link
response packets to IO devices on detection of a target or master abort error condition.
6
CpuErrDis: CPU error response disable. Read-write. Reset: 0. BIOS: 1. 1=Disables generation of a
read data error response to the core on detection of a target or master abort error condition.
5
IoMstAbortDis: IO master abort error response disable. Read-write. Reset: 0. 1=Signals target
abort instead of master abort in link response packets to IO devices on detection of a master abort
error condition.When IoMstAbortDis and D18F3x180[ChgMstAbortToNoErr] are both set,
D18F3x180[ChgMstAbortToNoErr] takes precedence.
4
SyncPktPropDis: sync packet propagation disable. Read-write. Reset: 0. BIOS: 0. 1=Disables
flooding of all outgoing links with sync packets when a sync packet is detected on an incoming link.
Sync packets are propagated by default.
3
SyncPktGenDis: sync packet generation disable. Read-write. Reset: 0. BIOS: 0. 1=Disables flooding of all outgoing links with sync packets when a CRC error is detected on an incoming link. By
default, sync packet generation for CRC errors is controlled through D18F0x[E4,C4,A4,84] [Link
Control].
2
SyncFloodOnDramUcEcc: sync flood on uncorrectable DRAM ECC error. Read-write. Reset: 0.
BIOS: 1.
1=Enable sync flood of all links with sync packets on detection of an uncorrectable DRAM ECC
error.
1
CpuRdDatErrEn: CPU read data error log enable. Read-write. Reset: 0. 1=Enables reporting of
read data errors (master aborts and target aborts) for data destined for the CPU on this node. This bit
should be clear if read data error logging is enabled for the remaining error reporting blocks in the
CPU. Logging the same error in more than one block may cause a single error event to be treated as a
multiple error event and cause the CPU to enter shutdown.
0
Reserved.
D18F3x48 MCA NB Status Low
Bits
Description
31:0 MSR0000_0411[31:0] is an alias of D18F3x48. See MSR0000_0411.
D18F3x4C MCA NB Status High
Bits
Description
31:0 MSR0000_0411[63:32] is an alias of D18F3x4C. See MSR0000_0411.
D18F3x50 MCA NB Address Low
Bits
Description
31:0 MSR0000_0412[31:0] is an alias of D18F3x50. See MSR0000_0412[31:0].
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D18F3x54 MCA NB Address High
Bits
Description
31:0 MSR0000_0412[63:32] is an alias of D18F3x54. See MSR0000_0412[63:32].
D18F3x58 Scrub Rate Control
This register specifies the ECC sequential scrubbing rate for lines of memory and cache. See 2.8.3 [Memory
Scrubbers]. Scrub rates are a platform consideration. See 2.14.1.8 [Scrub Rate Considerations].
Bits
Description
31:29 Reserved.
28:24 Reserved. Read-write.
23:5 Reserved.
4:0
DramScrub: DRAM scrub rate. Specifies time between 64 B scrub events. See D18F3x5C and
D18F3x60.
Bits
Description
Bits
Description
00h
Disable sequential scrubbing
10h
1.31 ms
1
11h
2.62 ms
01h
40 ns
1
12h
5.24 ms
02h
80 ns
13h
10.49 ms
03h
160 ns1
14h
20.97 ms
04h
320 ns1
05h
640 ns
15h
42 ms
06h
1.28 us
16h
84 ms
07h
2.56 us
1Eh-17h
Reserved
08h
5.12 us
1Fh
20 ns
09h
10.2 us
0Ah
20.5 us
0Bh
41.0 us
0Ch
81.9 us
0Dh
163.8 us
0Eh
327.7 us
0Fh
655.4 us
Note:
1. This setting is not supported (and is not verified) except as a DRAM scrub rate when no other
memory accesses are being performed.
D18F3x5C DRAM Scrub Address Low
In addition to sequential DRAM scrubbing, the DRAM scrubber has a redirect mode for scrubbing DRAM
locations accessed during normal operation. This is enabled by setting D18F3x5C[ScrubReDirEn]. When a
DRAM read is generated by any agent other than the DRAM scrubber, correctable ECC errors are corrected as
the data is passed to the requestor, but the data in DRAM is not corrected if redirect scrubbing mode is
disabled. In scrubber redirect mode, correctable errors detected during normal DRAM read accesses redirect
the scrubber to the location of the error. After the scrubber corrects the location in DRAM, it resumes
scrubbing from where it left off. DRAM scrub address registers are not modified by the redirect scrubbing
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mode. Sequential scrubbing and scrubber redirection can be enabled independently or together. ECC errors
detected by the scrubber are logged in the MCA registers (See D18F3x40 [MCA NB Control]).
Bits
Description
31:6 ScrubAddr[31:6]: DRAM scrubber address bits[31:6]. Read-write; updated-by-hardware.
ScrubAddr[47:6] = {D18F3x60[ScrubAddr[47:32]], ScrubAddr[31:6]}. Reset: 0. ScrubAddr points
to a DRAM cacheline in physical address space. BIOS should initialize the scrubber address register
to the base address of the node specified by D18F1x[17C:140,7C:40] [DRAM Base/Limit] prior to
enabling sequential scrubbing through D18F3x58[DramScrub]. When sequential scrubbing is
enabled: it starts at the address that the scrubber address registers are initialized to; it increments
through address space and updates the scrubber address registers as it does so; when the scrubber
reaches the DRAM limit address specified by D18F1x[17C:140,7C:40], it wraps around to the base
address. Reads of the scrubber address registers provide the next cacheline to be scrubbed.
5:1
0
Reserved.
ScrubReDirEn: DRAM scrubber redirect enable. Read-write. Reset: 0. BIOS: See Table 47 [DCT
Training Specific Register Values]. If a correctable error is discovered from a non-scrubber DRAM
read, then the data is corrected before it is returned to the requestor; however, the DRAM location
may be left in a corrupted state (until the next time the scrubber address counts up to that location, if
sequential scrubbing is enabled through D18F3x58[DramScrub]). 1=Enables the scrubber to
immediately scrub any address in which a correctable error is discovered. This bit and sequential
scrubbing can be enabled independently or together; if both are enabled, the scrubber jumps from the
scrubber address to where the correctable error was discovered, scrubs that location, and then jumps
back to where it left off; the scrubber address register is not affected during scrubber redirection.
D18F3x60 DRAM Scrub Address High
Bits
Description
31:16 Reserved.
15:0 ScrubAddr[47:32]: DRAM scrubber address bits[47:32]. See: D18F3x5C[ScrubAddr[31:6]].
Reset: 0.
D18F3x64 Hardware Thermal Control (HTC)
See 2.10.3.1 [PROCHOT_L and Hardware Thermal Control (HTC)]. If Fuse[HtcMsrLock]=1, then
HtcPstateLimit, HtcHystLmt, HtcTmpLmt, HtcClkInact, HtcClkAct, HtcPstateSel, and HtcEn fields are
reserved. MSRC001_003E is an alias of D18F3x64. If D18F3xE8[HtcCapable]=0 then this register is reserved.
Bits
31
Description
Reserved.
30:28 HtcPstateLimit: HTC P-state limit select. IF (~Fuse[HtcMsrLock]) THEN Read-write. ELSE
Read-only. ENDIF. Reset: Fuse[HtcStcPstateLimit]. Specifies the P-state limit of all cores when in
the P-state based HTC-active state. This field uses hardware P-state numbering and is not changed on
a write if the value written is greater than D18F3xDC[HwPstateMaxVal] or less than
D18F4x15C[NumBoostStates]. See 2.10.3.1 [PROCHOT_L and Hardware Thermal Control (HTC)]
and 2.5.3.1.1.2 [Hardware P-state Numbering].
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27:24 HtcHystLmt: HTC hysteresis. IF (~Fuse[HtcMsrLock]) THEN Read-write. ELSE Read-only.
ENDIF. Reset: Fuse[HtcHystLmt[3:0]]. The processor exits the HTC-active state when (Tctl or Tctlm
< (HtcTmpLmt - HtcHystLmt). Modifying HtcHystLmt via BIOS should be done early in POST.
Description
Bits
0h
0
1h
0.5
Eh-2h
<HtcHystLmt*0.5>
Fh
7.5
23
HtcSlewSel: HTC slew-controlled temperature select. Read-write. Reset: 0. 1=HTC logic is
driven by the slew-controlled temperature, Tctl, specified in D18F3xA4 [Reported Temperature Control]. 0=HTC logic is driven by the measured control temperature, Tctlm, with no slew controls.
22:16 HtcTmpLmt: HTC temperature limit. IF (~Fuse[HtcMsrLock]) THEN Read-write. ELSE Readonly. ENDIF. Reset: Fuse[HtcTmpLmt[6:0]]. The processor enters the HTC-active state when Tctl or
Tctlm reaches or exceeds the temperature limit defined by this register. Modifying HtcTmpLmt via
BIOS should be done early in POST. Increasing above the default value is not supported.
Bits
Description
00h
52
01h
52.5
7Eh-02h
<(HtcTmpLmt*0.5) + 52>
7Fh
115.5
7
PslApicLoEn: P-state limit lower value change APIC interrupt enable. Read-write. Reset: 0.
PslApicLoEn and PslApicHiEn enable interrupts using APIC330 [LVT Thermal Sensor] of each core
when the active P-state limit in MSRC001_0061[CurPstateLimit] changes. PslApicLoEn enables the
interrupt when the limit value becomes lower (indicating higher performance). PslApicHiEn enables
the interrupt when the limit value becomes higher (indicating lower performance). 1=Enable interrupt. See D18F5x88[EnAllPstateLimitEnterIntr, EnAllPstateLimitExitIntr].
6
PslApicHiEn: P-state limit higher value change APIC interrupt enable. Read-write. Reset: 0.
See PslApicLoEn.
5
HtcActSts: HTC-active status. Read; set-by-hardware; write-1-to-clear. Reset: 0. This bit is set by
hardware when the processor enters the HTC-active state. It is cleared by writing a 1 to it.
4
HtcAct: HTC-active state. Read-only, updated-by-hardware. Reset: X. (Can be asserted out of reset
when Fuse[HtcMsrLock]=1 and the processor immediately goes into the HTC-active state). 1=The
processor is currently in the HTC-active state. 0=The processor is not in the HTC-active state.
0
HtcEn: HTC enable. IF (~Fuse[HtcMsrLock]) THEN Read-write. ELSE Read-only. ENDIF. Reset:
Fuse[HtcMsrLock]. BIOS: IF (D18F3x64[HtcTmpLmt]==0) THEN 0 ELSE 1 ENDIF. 1=HTC is
enabled; the processor is capable of entering the HTC-active state.
D18F3x68 Software P-state Limit
See 2.10.3.3 [Software P-state Limit Control]. MSRC001_003F is an alias of D18F3x68. If
D18F3xE8[HtcCapable]=0 then this register is reserved.
Bits
31
Description
Reserved.
30:28 SwPstateLimit: software P-state limit select. Read-write. Reset: Fuse[HtcStcPstateLimit]. Specifies
a P-state limit for all cores. Uses hardware P-state numbering; see 2.5.3.1.1.2 [Hardware P-state Numbering]. Not changed on a write if the value written is greater than D18F3xDC[HwPstateMaxVal] or
less than D18F4x15C[NumBoostStates]. See SwPstateLimitEn.
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27:6 Reserved. Read-write.
5
4:0
SwPstateLimitEn: software P-state limit enable. Read-write. Reset: 0. 1=SwPstateLimit is
enabled.
Reserved. Read-write.
D18F3x6C Data Buffer Count
Out of cold reset, the processor allocates a minimal number of buffers that is smaller than the default values in
the register. BIOS must use D18F0x6C[RlsLnkFullTokCntImm] or D18F0x6C[RlsLnkFullTokCntOnRst] for
the values in the register to take effect. This is necessary even if the values are unchanged from the default
values.
• To ensure deadlock free operation the following minimum buffer allocations are required:
• Rule: D18F3x6C[UpRspDBC] >= 1.
• Rule: D18F3x6C[DnReqDBC] >= 1.
• Rule: D18F3x6C[UpReqDBC] >= 1.
• Rule: D18F3x6C[DnRspDBC] >= 1.
• If D18F0x[E4,C4,A4,84][IsocEn]=1: IsocRspDBC >= 1.
• The total number of data buffers allocated in this register and D18F3x7C must satisfy the following equation:
• Rule: D18F3x6C[UpReqDBC] + D18F3x6C[UpRspDBC] + D18F3x6C[DnReqDBC] +
D18F3x6C[DnRspDBC] + D18F3x6C[IsocRspDBC] + (IF (D18F3x7C[Sri2XbarFreeRspDBC]==0)
THEN (D18F3x7C[Sri2XbarFreeXreqDBC]*2) ELSE D18F3x7C[Sri2XbarFreeXreqDBC] ENDIF) +
D18F3x7C[Sri2XbarFreeRspDBC] <= 16.
Bits
31
Description
Reserved.
30:28 IsocRspDBC: isochronous response data buffer count. Read-write. Reset: 3. BIOS: 1.
27:19 Reserved.
18:16 UpRspDBC: upstream response data buffer count. Read-write. Reset: 2. BIOS: 1.
15
Reserved. Read-write.
14:8 Reserved.
7:6
DnRspDBC: downstream response data buffer count. Read-write. Reset: 2. BIOS: 1.
5:4
DnReqDBC: downstream request data buffer count. Read-write. Reset: 1. BIOS: 1.
3
2:0
Reserved.
UpReqDBC: upstream request data buffer count. Read-write. Reset: 2. BIOS: 2.
D18F3x70 SRI to XBAR Command Buffer Count
Reset: 1111_2153h. Out of cold reset, the processor allocates a minimal number of buffers that is smaller than
the default values in the register. BIOS must use D18F0x6C[RlsLnkFullTokCntImm] or
D18F0x6C[RlsLnkFullTokCntOnRst] for the values in the register to take effect. This is necessary even if the
values are unchanged from the default values.
• To ensure deadlock free operation the following minimum buffer allocations are required:
• Rule: D18F3x70[UpRspCBC] >= 1.
• Rule: D18F3x70[UpPreqCBC] >= 1.
• Rule: D18F3x70[DnPreqCBC] >= 1.
• Rule: D18F3x70[UpReqCBC] >= 1.
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• Rule: D18F3x70[DnReqCBC] >= 1.
• Rule: D18F3x70[DnRspCBC] >= 1.
• If any of the D18F0x[E4,C4,A4,84][IsocEn] bits are set:
IsocReqCBC >= 1
IsocRspCBC >= 1
• If D18F0x[E4,C4,A4,84][IsocEn]=1 and isochronous posted requests may be generated by the system:
IsocPreqCBC >= 1
• The total number of SRI to XBAR commandbuffers allocated in this register and D18F3x7C must satisfy the
following equation:
• Rule: D18F3x70[IsocRspCBC] + D18F3x70[IsocPreqCBC] + D18F3x70[IsocReqCBC] +
D18F3x70[UpRspCBC] + D18F3x70[DnPreqCBC] + D18F3x70[UpPreqCBC] +
D18F3x70[DnReqCBC] + D18F3x70[DnRspCBC] + D18F3x70[UpReqCBC] +
D18F3x7C[Sri2XbarFreeRspCBC] + D18F3x7C[Sri2XbarFreeXreqCBC] <= 24.
Bits
31
Description
Reserved.
30:28 IsocRspCBC: isoc response command buffer count. Read-write. BIOS: 1.
27
Reserved.
26:24 IsocPreqCBC: isoc posted request command buffer count. Read-write. BIOS: 0.
23
Reserved.
22:20 IsocReqCBC: isoc request command buffer count. Read-write. BIOS: 1.
19
Reserved.
18:16 UpRspCBC: upstream response command buffer count. Read-write. BIOS: 3.
15
Reserved.
14:12 DnPreqCBC: downstream posted request command buffer count. Read-write. BIOS: 1.
11
Reserved.
10:8 UpPreqCBC: upstream posted request command buffer count. Read-write. BIOS: 1.
7:6
DnRspCBC: downstream response command buffer count. Read-write. BIOS: 1.
5:4
DnReqCBC: downstream request command buffer count. Read-write. BIOS: 1.
3
2:0
Reserved.
UpReqCBC: upstream request command buffer count. Read-write. BIOS: 3
D18F3x74 XBAR to SRI Command Buffer Count
Reset: 0007_1111h. Out of cold reset, the processor allocates a minimal number of buffers that is smaller than
the default values in the register. BIOS must use D18F0x6C[RlsLnkFullTokCntImm] or
D18F0x6C[RlsLnkFullTokCntOnRst] for the values in the register to take effect. This is necessary even if the
values are unchanged from the default values.
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Table 172: Buffer Definitions
Term
SpqSize
Definition
Probe command queue size.
SpqSize = 20.
SrqSize
SRQ (XBAR command and probe response to SRI) queue size.
SrqSize = 36.
PrbRsp
MpbcSize
SRQ entries hard allocated to probe responses. PrbRsp = 4.
MPB command buffer size.
MpbcSize = 24.
McqSize
MCT command queue size.
McqSize = 36.
• To ensure deadlock free operation the following minimum buffer allocations are required:
• Rule: D18F3x74[ProbeCBC] >= 2.
• Rule: D18F3x74[UpReqCBC] >= 1.
• Rule: D18F3x74[UpPreqCBC] >= 1.
• (IsocReqCBC + IsocPreqCBC + DRReqCBC) <= 31 .
• (IsocReqCBC + IsocPreqCBC + DRReqCBC) <= (McqSize - 16).
• If any of D18F0x[E4,C4,A4,84][IsocEn] bits are set, then IsocReqCBC >= 1.
• If any of the D18F0x[E4,C4,A4,84][IsocEn] bits are set and isochronous posted requests may be generated
by the system:
IsocPreqCBC >= 1
• The total number of XBAR to SRI commandbuffers allocated in this register and D18F3x7C must satisfy the
following equation:
• Rule: D18F3x74[UpReqCBC] + D18F3x74[UpPreqCBC] + D18F3x74[DnReqCBC] +
D18F3x74[DnPreqCBC] + D18F3x74[IsocReqCBC] + D18F3x74[IsocPreqCBC] +
D18F3x74[DRReqCBC] + D18F3x7C[Xbar2SriFreeListCBC] + (D18F3x1A0[CpuCmdBufCnt] *
NumOfCompUnitsOnNode) + D18F3x1A0[CpuToNbFreeBufCnt] + PrbRsp <= SrqSize
• The total number of SPQ (probe command) buffers allocated must satisfy the following equation:
• Rule: (D18F3x17C[SPQPrbFreeCBC] + D18F3x74[ProbeCBC]) <= SpqSize.
Bits
Description
31:28 DRReqCBC: display refresh request command buffer count. Read-write. BIOS: 0.
27
Reserved.
26:24 IsocPreqCBC: isochronous posted request command buffer count. Read-write.
BIOS: 1.
23:20 IsocReqCBC: isochronous request command buffer count. Read-write.
BIOS: 1.
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19:16 ProbeCBC: probe command buffer count. Read-write.
BIOS: Ch.
Description
Bits
0h
0 buffers
Ch-1h
<ProbeCBC> buffers
Fh-Dh
Reserved.
15
Reserved.
14:12 DnPreqCBC: downstream posted request command buffer count. Read-write.
BIOS: 0.
11
Reserved.
10:8 UpPreqCBC: upstream posted request command buffer count. Read-write.
BIOS: 1.
7
6:4
3
2:0
Reserved.
DnReqCBC: downstream request command buffer count. Read-write.
BIOS: 0.
Reserved.
UpReqCBC: upstream request command buffer count. Read-write.
BIOS: 1.
D18F3x78 MCT to XBAR Buffer Count
Reset: 0024_0519h. Out of cold reset, the processor allocates a minimal number of buffers that is smaller than
the default values in the register. BIOS must use D18F0x6C[RlsLnkFullTokCntImm] or
D18F0x6C[RlsLnkFullTokCntOnRst] for the values in the register to take effect. This is necessary even if the
values are unchanged from the default values.
• To ensure deadlock free operation the following minimum buffer allocations are required:
ProbeCBC >= 1
RspCBC >= 1
RspDBC >= 2
RspDBC >= D18F2x11C[MctPrefReqLimit]+2
• The total number of command buffers allocated in this register must satisfy the following equation:
Rule: (D18F3x78[ProbeCBC] + D18F3x78[RspCBC]) <= MpbcSize.
Bits
Description
31:22 Reserved.
21:16 RspDBC: response data buffer count. Read-write.
Bits
Description
01h-00h
Reserved
02h
2 Buffers
1Fh-03h
<RspDBC> Buffers
20h
32 Buffers
3Fh-21h
Reserved
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15:13 Reserved.
12:8 ProbeCBC: probe command buffer count. Read-write.
BIOS: 8h.
7:6
Reserved.
5:0
RspCBC: response command buffer count. Read-write.
BIOS: 10h.
D18F3x7C Free List Buffer Count
Reset: 0003_660Ch. Out of cold reset, the processor allocates a minimal number of buffers that is smaller than
the default values in the register. BIOS must use D18F0x6C[RlsLnkFullTokCntImm] or
D18F0x6C[RlsLnkFullTokCntOnRst] for the values in the register to take effect. This is necessary even if the
values are unchanged from the default values. See D18F3x6C and D18F3x70.
• To ensure deadlock free operation the following minimum buffer allocations are required:
• Rule: IF (D18F3x7C[Sri2XbarFreeRspCBC]==0) THEN (D18F3x7C[Sri2XbarFreeXreqCBC]>2).
• Rule: IF (D18F3x7C[Sri2XbarFreeRspCBC]!=0) THEN (D18F3x7C[Sri2XbarFreeRspCBC]>2).
• Rule: IF (D18F3x7C[Sri2XbarFreeRspDBC]==0) THEN (D18F3x7C[Sri2XbarFreeXreqDBC]>2).
• Rule: IF (D18F3x7C[Sri2XbarFreeRspDBC]!=0) THEN (D18F3x7C[Sri2XbarFreeRspDBC]>2).
• Rule: D18F3x7C[Xbar2SriFreeListCBC] >= (D18F3x1A0[CpuToNbFreeBufCnt] *
NumOfCompUnitsOnNode) + 2.
Bits
31
Description
Reserved.
30:28 Xbar2SriFreeListCBInc: XBAR to SRI free list command buffer increment. Read-write. This
field is use to add buffers to the free list pool if they are reclaimed from hard allocated entries without
having to go through warm reset. This field may only be programmed after buffers have been allocated and released via D18F0x6C[RlsLnkFullTokCntImm] or D18F0x6C[RlsLnkFullTokCntOnRst].
27:23 Reserved.
22:20 Sri2XbarFreeRspDBC: SRI to XBAR free response data buffer count. Read-write. BIOS: 0.
19:16 Sri2XbarFreeXreqDBC: SRI to XBAR free request and posted request data buffer count. Readwrite.
BIOS: 5h.
If Sri2XbarFreeRspDBC=0h, then these buffers are shared between requests, responses and posted
requests and the number of buffers allocated is two times the value of this field.
15:12 Sri2XbarFreeRspCBC: SRI to XBAR free response command buffer count. Read-write. BIOS:
0h.
11:8 Sri2XbarFreeXreqCBC: SRI to XBAR free request and posted request command buffer count.
Read-write.
BIOS: 6h.
If Sri2XbarFreeRspCBC=0h, then these buffers are shared between requests, responses and posted
requests and the number of buffers allocated is two times the value of this field.
7:6
Reserved.
5:0
Xbar2SriFreeListCBC: XBAR to SRI free list command buffer count. Read-write.
BIOS: 1Bh.
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D18F3x[84:80] ACPI Power State Control
This block consists of eight identical 8-bit registers, one for each System Management Action Field (SMAF)
code associated with STPCLK assertion commands from the link. Refer to the descriptions below for the
associated ACPI state and system management actions for each of the 8 SMAF codes. The SmafAct fields
specify the system management actions taken when the corresponding SMAF code is received. For instance, a
SMAF code of 5 results in the power management actions specified by SmafAct5. Some ACPI states and
associated SMAF codes may not be supported in certain conditions. See 2.5 [Power Management] for which
states are supported.
When a link STPCLK assertion command is received by the processor, the power management commands
specified by the register with the corresponding SMAF code are invoked. When the STPCLK deassertion
command is received by the processor, the processor returns into the operational state. However, had the NB
COF-change command been issued (NbCofChg), the NB returns in the new NB P-state.
In multi-node systems, these registers should be programmed identically in all nodes.
Table 173: SMAF Action Definition
Register
SmafAct
D18F3x84[31:24] SmafAct7
ACPI state
C1
D18F3x84[23:16] SmafAct6
S4/S5
D18F3x84[15:8]
SmafAct5
Throttling
D18F3x84[7:0]
SmafAct4
S3
D18F3x80[31:24] SmafAct3
S1
Description
Initiated when a Halt instruction is executed by processor.
This does not involve the interaction with the SMC, therefore the SMC is required to never send STPCLK assertion
commands with SMAF=7h.
Initiated by a processor access to the ACPI-defined
PM1_CNTa register.
Occurs based upon SMC hardware-initiated throttling.
Refer to section 1.5.4 [Supported Feature Variations] for
package-specific support. AMD recommends using
PROCHOT_L for thermal throttling and notimplementing
stop clock based throttling.
Initiated by a processor access to the ACPI-defined
PM1_CNTa register.
Initiated by a processor access to the ACPI-defined
PM1_CNTa register.
D18F3x80[23:16] SmafAct2
D18F3x80[15:8] SmafAct1 C3, C1E, or Link Initiated by an access to the ACPI-defined P_LVL3 regisinit.
ter.
D18F3x80[7:0] SmafAct0
C2
Initiated by a processor access to the ACPI-defined
P_LVL2 register.
D18F3x80 ACPI Power State Control Low
Reset: 0000_0000h. Read-write.
Bits
Description
31:29 ClkDivisorSmafAct3. See: ClkDivisorSmafAct0.
26
NbGateEnSmafAct3. See: NbGateEnSmafAct0.
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25
NbLowPwrEnSmafAct3. See: NbLowPwrEnSmafAct0.
24
CpuPrbEnSmafAct3. See: CpuPrbEnSmafAct0.
23:21 ClkDivisorSmafAct2. See: ClkDivisorSmafAct0.
18
NbGateEnSmafAct2. See: NbGateEnSmafAct0.
17
NbLowPwrEnSmafAct2. See: NbLowPwrEnSmafAct0.
16
CpuPrbEnSmafAct2. See: CpuPrbEnSmafAct0.
15:13 ClkDivisorSmafAct1. See: ClkDivisorSmafAct0.
10
NbGateEnSmafAct1. See: NbGateEnSmafAct0.
9
NbLowPwrEnSmafAct1. See: NbLowPwrEnSmafAct0.
8
CpuPrbEnSmafAct1. See: CpuPrbEnSmafAct0.
7:5
ClkDivisorSmafAct0: clock divisor. Read-write.
Specifies the core clock frequency while in the low-power state. This divisor is relative to the current
FID frequency, or:
• 100 MHz * (10h + MSRC001_00[6B:64][CpuFid]) of the current P-state specified by
MSRC001_0063[CurPstate].
If MSRC001_00[6B:64][CpuDid] of the current P-state indicates a divisor that is deeper than specified by this field, then no frequency change is made when entering the low-power state associated
with this register.
Bits
Description
Bits
Description
000b
/1
100b
/16
001b
/2
101b
/128
010b
/4
110b
/512
011b
/8
111b
Turn off clocks
2
NbGateEnSmafAct0: northbridge gate enable. Read-write. This bit does not control hardware.
NbLowPwrEn is required to be set if this bit is set. Regardless of this bit, NB coarse gaters are always
enabled in the low-power state and MEMCLK is always tristated when DRAM is in self-refresh
mode.
1
NbLowPwrEnSmafAct0: Northbridge low-power enable. Read-write. 1=The NB clock is ramped
down to the divisor specified by D18F3xD4[NbClkDiv] and DRAM is placed into self-refresh mode
when LDTSTOP_L is asserted while in the low-power state.
0
CpuPrbEnSmafAct0: CPU direct probe enable. Read-write. Specifies how probes are handled
while in the low-power state. 0=When the probe request comes into the NB, the core clock is brought
up to the COF (based on the current P-state), all outstanding probes are completed, the core waits for
a hysteresis time based on D18F3xD4[ClkRampHystSel], and then the core clock is brought down to
the frequency specified by ClkDivisor. 1=The core clock does not change frequency; the probe is handled at the frequency specified by ClkDivisor; this may only be set if:
• ClkDivisor specifies a divide-by 1, 2, 4, 8, or 16 and NbCof <= 3.2 GHz
• ClkDivisor specifies a divide-by 1, 2, 4, or 8 and NbCof >= 3.4 GHz
This bit also specifies functionality of the timer used for cache flushing during halt. See
D18F3xDC[CacheFlushOnHaltTmr].
• If ((D18F3x84[CpuPrbEnSmafAct7]==0) && (D18F3xDC[IgnCpuPrbEn]==0)), only the time
when the core is halted and has its clocks ramped up to service probes is counted.
• If ((D18F3x84[CpuPrbEnSmafAct7]==1) or (D18F3xDC[IgnCpuPrbEn]==1)), all of the time the
core is halted is counted.
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D18F3x84 ACPI Power State Control High
Reset: 0000_0000h. Read-write.
Bits
Description
31:29 ClkDivisorSmafAct7. See: D18F3x80[ClkDivisorSmafAct0].
26
NbGateEnSmafAct7. See: D18F3x80[NbGateEnSmafAct0].
25
NbLowPwrEnSmafAct7. See: D18F3x80[NbLowPwrEnSmafAct0].
24
CpuPrbEnSmafAct7. See: D18F3x80[CpuPrbEnSmafAct0].
23:21 ClkDivisorSmafAct6. See: D18F3x80[ClkDivisorSmafAct0].
18
NbGateEnSmafAct6. See: D18F3x80[NbGateEnSmafAct0].
17
NbLowPwrEnSmafAct6. See: D18F3x80[NbLowPwrEnSmafAct0].
16
CpuPrbEnSmafAct6. See: D18F3x80[CpuPrbEnSmafAct0].
15:13 ClkDivisorSmafAct5. See: D18F3x80[ClkDivisorSmafAct0].
10
NbGateEnSmafAct5. See: D18F3x80[NbGateEnSmafAct0].
9
NbLowPwrEnSmafAct5. See: D18F3x80[NbLowPwrEnSmafAct0].
8
CpuPrbEnSmafAct5. See: D18F3x80[CpuPrbEnSmafAct0].
7:5
ClkDivisorSmafAct4. See: D18F3x80[ClkDivisorSmafAct0].
2
NbGateEnSmafAct4. See: D18F3x80[NbGateEnSmafAct0].
1
NbLowPwrEnSmafAct4. See: D18F3x80[NbLowPwrEnSmafAct0]. Char.Temp.BIOS: 1.
0
CpuPrbEnSmafAct4. See: D18F3x80[CpuPrbEnSmafAct0].
D18F3x88 NB Configuration 1 Low (NB_CFG1_LO)
Bits
Description
31:0 MSRC001_001F[31:0], MSRC001_101F[31:0] are an alias of D18F3x88. See MSRC001_001F.
D18F3x8C NB Configuration 1 High (NB_CFG1_HI)
Bits
Description
31:0 MSRC001_001F[63:32], MSRC001_101F[63:32] are an alias of D18F3x8C. See MSRC001_001F.
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D18F3xA0 Power Control Miscellaneous
Bits
31
Description
CofVidProg: COF and VID of P-states programmed. Read-only. Reset: Fuse[CofVidProg]. 1=Out
of cold reset, the VID, FID, and DID values of the P-state registers specified by
MSRC001_0071[StartupPstate] and D18F5x174[StartupNbPstate] have been applied to the processor. 0=Out of cold reset, the boot VID is applied to all processor power planes, the NB clock plane is
set to 800 MHz (with a FID of 00h=800 MHz and a DID of 0b) and core CPU clock planes are set to
800 MHz (with a FID of 00h=1.6 GHz and a DID of 1h). Registers containing P-state information
such as FID, DID, and VID values are valid out of cold reset independent of the state of
D18F3xA0[CofVidProg]. BIOS must transition the processor to a valid P-state out of cold reset when
D18F3xA0[CofVidProg]=0. See 2.5.3.1.6 [BIOS Requirements for Core P-state Initialization and
Transitions].
27:16 ConfigId: Configuration identifier. Read-only. Reset: Fuse[ConfigId]. Specifies the configuration
ID associated with the product. This field indicates the fuse recipe (PSDD source) used to generate
the part. The ConfigId namespace is unique within a specific value for D18F4x160 [Native Die
CPUID Family/Model/Stepping].
14
Svi2HighFreqSel: SVI2 high frequency select. Read-write. Cold reset: 0. IF (SVI1) THEN BIOS:
0. ELSE BIOS: 1. ENDIF. 0=3.4 MHz. 1=20 MHz. Writes to this field take effect at the next SVI
command boundary. If 20 MHz is supported by the VRM, BIOS should program this to 1 prior to any
VID transitions. Once this bit is set, it should not be cleared until the next cold reset.
13:11 PllLockTime: PLL synchronization lock time. Read-write. Reset: 0. BIOS: 001b. If a P-state
change occurs that applies a new FID to the PLL, this field specifies the time required for the PLL to
lock to the new frequency.
Bits
Description
Bits
Description
000b
1 us
100b
8 us
001b
2 us
101b
16 us
010b
3 us
110b
Reserved
011b
4 us
111b
Reserved
10
Reserved.
9
Reserved.
8
PsiVid[7]. Read-write. Reset: 0. BIOS: 2.5.1.3.1.1. See PsiVid[6:0].
7
PsiVidEn: PSI_L VID enable. Read-write. Reset: 0. BIOS: 2.5.1.3.1.1. This bit specifies how PSI_L
is controlled. This signal may be used by the voltage regulator to improve efficiency while in reduced
power states. 1=Control over the PSI_L signal is as specified by the PsiVid field of this register.
0=PSI_L is always high. See 2.5.1.3.1 [PSIx_L Bit].
6:0
PsiVid[6:0]: PSI_L VID threshold. Read-write. Reset: 0. BIOS: 2.5.1.3.1.1. PsiVid[7:0] =
{PsiVid[7], PsiVid[6:0]}. When enabled by PsiVidEn, PsiVid[7:0] specifies the threshold value of the
VID code generated by the processor, which in turn determines the state of PSI0_L. When the VID
code generated by the processor is less than PsiVid[7:0] (i.e., the VID code is specifying a higher voltage level than the PsiVid-specified voltage level), then PSI0_L is high; when the VID code is greater
than or equal to PsiVid[7:0], PSI0_L is driven low. See 2.5.1.3.1 [PSIx_L Bit].
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D18F3xA4 Reported Temperature Control
The slew rate controls in this register are used to filter processor temperature measurements. Separate controls
are provided for a measured temperature, Tctlm, that is higher or lower than Tctl. The per-step timer counts as
long as the measured temperature stays either above or below Tctl. Each time the measured temperature
changes to the other side of Tctl, the step timer resets, and Tctl is not changed. If, for example, step times are
enabled in both directions, Tctl=62.625, and the measured temperature keeps jumping quickly between 62.5
and 63.0, then (assuming the step times are long enough) Tctl would not change. However, once the measured
temperature settles on one side of Tctl, Tctl can step toward the measured temperature. If the difference of
measured temperature minus Tctl is greater than the value set by MaxTmpDiffUp, then Tctl is set equal to the
measured temperature. See 2.10 [Thermal Functions].
Bits
Description
31:21 CurTmp: current temperature.
IF (D18F3xA4[CurTmpTjSel]==11b) THEN Read-write. ELSE Read-only, updated-by-hardware.
ENDIF. Reset: X. Provides the current control temperature, Tctl, after the slew-rate controls have
been applied.
RangeUnajusted = ((D18F3xA4[CurTmpTjSel]!=11b) && (D18F3xA4[CurTmpRangeSel]==0)).
RangeUnajusted
Description
Bits
000h
0
-49
001h
0
-48.875
7FEh-002h
0
<(CurTmp*0.125)-49>
7FFh
0
206.875
000h
1
0
001h
1
0.125
7FEh-002h
1
<CurTmp*0.125>
7FFh
1
255.875
20
Reserved.
17:16 CurTmpTjSel: Current temperature select. Read-write. Reset: 00. These bits may be used to provide the current temperature or control the temperature for diagnostic software. See 2.10 [Thermal
Functions].
Description
Bits
00b
CurTmp provides the read-only Tctl value.
01b
Reserved.
10b
Reserved.
11b
CurTmp is a read-write register that specifies a value used to create Tctl. The two LSB’s are
read-only zero (provides 0.5 degree resolution). Value in CurTmp is passed through slew
control logic. That result is used for HTC and SB-TSI. However, the value reported through
CurTmp is the same as the input value and is unaffected by the slew control logic.
15:13 Reserved.
12:8 PerStepTimeDn: per step time down. Read-write. Cold reset: 18h. BIOS: 0Fh. Specifies the time
that Tctlm must remain below Tctl before applying a 0.125 downward step. See: PerStepTimeUp.
7
TmpSlewDnEn: temperature slew downward enable. Read-write. Cold reset: 0. BIOS: 1.
1=Downward slewing enabled. 0=Downward slewing disabled.
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6:5
TmpMaxDiffUp: temperature maximum difference up. Read-write. Cold reset: 00b. BIOS: 11b.
Specifies the maximum difference, (Tctlm - Tctl), when Tctl immediatly updates to Tctlm.
Description
Bits
00b
0.0 (disable upward slew)
01b
1.0
10b
3.0
11b
9.0
4:0
PerStepTimeUp: per 1/8th degree step time up. Read-write. Cold reset: 00h. BIOS: 0Fh. Specifies
the time that Tctlm must remain above Tctl before applying a 0.125 upward step.
Bits
Definition
1Fh-00h
<(PerStepTimeUp[2:0] + 1) * 10^PerStepTimeUp[4:3]> ms, ranging from 1 ms
to 8000 ms.
D18F3xA8 Pop Up and Down P-states
Bits
Description
31:29 PopDownPstate. Read-write. Reset: D18F3xDC[HwPstateMaxVal]. BIOS: D18F3xDC[HwPstateMaxVal]. Specifies the pop-down P-state number. This field uses hardware P-state numbering.
See 2.5.3.2.3.3 [Core C6 (CC6) State]. This field must be set to D18F3xDC[HwPstateMaxVal]
D18F3xB8 NB Array Address
S3-check-exclude. Reset: xxxx_xxxxh. D18F3xB8 [NB Array Address] and D18F3xBC [NB Array Data Port]
provide a mechanism to inject errors into DRAM and data read from internal NB arrays.
D18F3xB8 should first be written with the target array and address within the array. Read and write accesses to
D18F3xBC then access the target address within the target array.
Bits
Description
9:0
ArrayAddress. Read-write. Selects the location to access within the selected array. This format of
this field is a function of ArraySelect.
Description
ArraySelect
1h
LPB. See Table 450 [Format of D18F3xB8[ArrayAddress] for LPB].
8h
DRAM ECC. See Table 454 [Format of D18F3xB8[ArrayAddress] for DRAM
ECC].
Ah
TCB. See Table 453 [Format of D18F3xB8[ArrayAddress] for TCB].
All others
Reserved
D18F3xBC NB Array Data Port
S3-check-exclude. See D18F3xB8 for register access information. Address: D18F3xB8[ArraySelect].
Bits
Description
31:0 Data.
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D18F3xBC_x8 DRAM ECC
This register controls injection of errors in writes to DRAM. See 2.14.3.1 [DRAM Error Injection].
Bits
Description
31:29 Reserved.
28:20 ErrInjEn: enable error injection to word. Read-write. Reset: 0. Each bit in this field corresponds to
a 16-bit DRAM word and enables injecting errors in that word.
Bit
Description
[0]
Data[15:0]
[1]
Data[31:16]
[2]
Data[47:32]
[3]
Data[63:48]
[4]
Data[79:64]
[5]
Data[95:80]
[6]
Data[111:96]
[7]
Data[127:112]
[8]
ECC[15:0]
19
Reserved.
18
DramErrEn. Read-write. Reset: 0. 1=Errors are continually injected on DRAM writes. The error
injection takes place only on DRAM write accesses and should be initiated by a non-cacheable store.
Errors continue to be injected on writes until this bit is cleared to a 0 by software.
17
EccWrReq. Read; write-1-only; cleared-by-hardware. Reset: 0. 1=Error is injected on DRAM write
at the bits enabled by ErrInjEn and EccVector. A single error injection takes place on the next DRAM
write access and should be initiated by a non-cacheable store. This bit is cleared by hardware after the
write.
16
EccRdReq. Read; write-1-only; cleared-by-hardware. Reset: 0. 1=Indicates a DRAM ECC read is
requested. The read takes place on the next DRAM read access and should be initiated by a noncacheable load. The ECC bits read from DRAM are stored in EccVector. This bit is cleared by hardware after the read.
15:0 EccVector: error injection vector. Read-write; S3-check-exclude. Reset: x. When used in conjunction with EccWrReq, each bit of EccVector enables injecting errors to the corresponding bit within
each word enabled by ErrInjEn. When used in conjunction with EccRdReq, EccVector holds the contents of the DRAM ECC bits after the read.
D18F3xD4 Clock Power/Timing Control 0
Bits
31
Description
NbClkDivApplyAll. Read-write. Cold reset: 0. BIOS: 1. See NbClkDiv.
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30:28 NbClkDiv: NB clock divisor. Read-write. Cold reset: Fuse[NbDivAltVid].
BIOS: 001b.
Specifies the NB CLK divisor associated with D18F3x80/D18F3x84[NbLowPwrEn]. This divisor is
applied while LDTSTOP_L is asserted if the corresponding core CLK divisor,
D18F3x80/D18F3x84[ClkDivisor], is set to “turn off clocks” or if NBClkDivApplyAll=1; otherwise,
the divisor specified by D18F3x80/D18F3x84[ClkDivisor] is applied. This divisor is relative to the
current NB FID frequency, or:
100 MHz * (4 + D18F5x16[C:0][NbFid]).
If D18F5x16[C:0][NbDid] of the current NB P-state indicates a divisor that is lower than specified by
this field, then no NB frequency change is made when entering the low-power state associated with
this register (i.e., if this field specifies a divide-by 1 and the DID is divide-by 2, then the divisor
remains 2 while in the low-power state). This field is encoded as follows:
Bits
Description
Bits
Description
000b
Divide-by 1
100b
Divide-by 16
001b
Divide-by 2
101b
Reserved Divide-by 128
010b
Divide-by 4
110b
Reserved Divide-by 512
011b
Divide-by 8
111b
Reserved
27:24 PowerStepUp. Read-write. Reset: 0000b. Specifies the rate at which blocks of compute unit and NB
logic are gated on while the processor transitions from a quiescent state to an active state as part of a
power management state transition. There are about 15 steps in this transition for each compute unit
and about 5 steps for the NB for the PowerStepDown and PowerStepUp transitions. So the total transition time for a single compute unit is about 15 times the time specified by PowerStepDown and
PowerStepUp and the transition time for the NB is about 5 times the time specified by PowerStepDown and PowerStepUp. Use of longer transition times may help reduce voltage transients associated
with power state transitions. The bits for PowerStepUp and PowerStepDown are encoded as follows:
Description
Bits
Description
Bits
0000b
Reserved. 400 ns
1000b
50 ns
0001b
Reserved. 300 ns
1001b
Reserved. 45 ns
0010b
Reserved. 200 ns
1010b
Reserved. 40 ns
0011b
100 ns
1011b
Reserved. 35 ns
0100b
90 ns
1100b
Reserved. 30 ns
0101b
80 ns
1101b
Reserved. 25 ns
0110b
70 ns
1110b
Reserved. 20 ns
0111b
60 ns
1111b
Reserved. 15 ns
• If PowerStepDown or PowerStepUp are programmed to greater than 50 ns, then the value applied to
the NB is clipped to 50 ns. The compute unit steps are not clipped.
• PowerStepDown and PowerStepUp should always be configured to less than or equal to 50 ns in
client systems. This restriction is to satisfy display refresh and isoc bandwidth requirements.
• BIOS: 1000b.
23:20 PowerStepDown. Read-write. Reset: 0000b. BIOS: 1000b. This specifies the rate at which blocks of
compute unit and NB logic are gated off while the processor transitions from an active state to a quiescent state as part of a power management state transition.
19:18 Reserved.
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14
CacheFlushImmOnAllHalt: cache flush immediate on all halt. Read-write. Reset: 0. 1=Flush the
caches immediately when all cores in a package have halted. One of the following conditions must be
true in order for the caches to be flushed:
• D18F4x128[CoreCstateMode]=0 and D18F4x118/D18F4x11C[CacheFlushEn]=1 for the corresponding C-state action field on all cores.
• D18F4x128[CoreCstateMode]=1 and D18F3xDC[CacheFlushOnHaltCtl] !=0.
13
Reserved.
12
ClkRampHystCtl: clock ramp hysteresis control. Read-write. Reset: 0. Specifies the time base for
ClkRampHystSel when (D18F4x128[CoreCstateMode] ? (D18F3x80/D18F3x84[CpuPrbEn]==0) :
(D18F4x118/D18F4x11C[CpuPrbEn]==0)). 0=320 ns. 1=1.28 us.
11:8 ClkRampHystSel: clock ramp hysteresis select. Read-write. Reset: 0h. Char.BIOS: Fh. When the
core(s) are in the stop-grant or halt state and a probe request is received, the core clock may need to be
brought up to service the probe.
• If (D18F4x128[CoreCstateMode] ? (D18F3x80/D18F3x84[CpuPrbEn]==0) :
(D18F4x118/D18F4x11C[CpuPrbEn]==0)) then this field specifies how long the core clock is left
up to service additional probes before being brought back down. Each time a probe request is
received, the hysteresis timer is reset such that the period of time specified by this field must expire
with no probe request before the core clock is brought back down. The hysteresis time is encoded as
(the time base specified by D18F3xD4[ClkRampHystCtl]) * (1 + ClkRampHystSel).
• If (D18F4x128[CoreCstateMode] ? (D18F3x80/D18F3x84[CpuPrbEn]==1) :
(D18F4x118/D18F4x11C[CpuPrbEn]==1)) then this field specifies a fixed amount of time to allow
for probes to be serviced after completing the transition of each core. If, for example, two cores
enter stop-grant or halt at the same time, then (1) the first core would complete the transition to the
low power state, (2) probe traffic would be serviced for the time specified by this field, (3) the
second core would complete the transition to the low power state, and (4) probe traffic would be
seviced for the time specified by this field (and afterwards, until the next power state transition). For
this purpose, values range from 0h=40 ns to Fh=640 ns, encoded as 40 ns * (1 + ClkRampHystSel).
7:6
Reserved.
5:0
MaxSwPstateCpuCof: maximum software P-state core COF. Read-only. Cold reset:
Fuse[MaxSwPstateCof]. Specifies the maximum CPU COF supported by the processor in a software
P-state. The maximum frequency is 100 MHz * MaxSwPstateCpuCof, if MaxSwPstateCpuCof is
greater than zero; if MaxSwPstateCpuCof = 00h, then there is no frequency limit. Any attempt to
change a software P-state CPU COF to a frequency greater than specified by this field is ignored. Processors that support core performance boost must fuse this field to the software P0 frequency or
higher. See 2.5.3.1.1.1 [Software P-state Numbering] and 2.5.3.1.5 [Core P-state Transition Behavior].
D18F3xD8 Clock Power/Timing Control 1
See 2.5.1.4 [Voltage Transitions].
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Bits
Description
6:4
VSRampSlamTime. Read-write. Cold reset: 000b. BIOS: 100b. Specifies the time the processor
waits for voltage transitions to complete before beginning an additional voltage change or a frequency
change.
IF (SVI1) THEN
Wait time = (VSRampSlamTime / 12.5mV) * ABS(destination voltage - current voltage).
ELSE
Wait time = (VSRampSlamTime / 15mV) * ABS(destination voltage - current voltage).
ENDIF.
IF (SVI1) THEN
Description
Bits
000b
6.25 us
001b
5.00 us
010b
4.17 us
011b
3.13 us
ELSE
Description
Bits
000b
5.00 us
001b
3.75 us
010b
3.00 us
011b
2.40 us
ENDIF.
Bits
100b
101b
110b
111b
Description
2.50 us
1.67 us
1.25 us
1.00 us
Bits
100b
101b
110b
111b
Description
2.00 us
1.50 us
1.20 us
1.00 us
D18F3xDC Clock Power/Timing Control 2
Bits
Description
31:30 NbsynPtrAdjPstate[2:1]: NB/core synchronization FIFO pointer adjust P-state[2:1]. Read-write.
Reset: Fuse[NumBoostStates[2:1]]. See NbsynPtrAdj.
29:27 NbsynPtrAdjLo: NB/core synchronization FIFO pointer adjust low. Read-write. Cold reset:
000b.
BIOS: 101b.
See NbsynPtrAdj.
26
IgnCpuPrbEn: ignore CPU probe enable. Read-write. Cold reset: 0.
BIOS: 0.
See D18F3x80/D18F3x84[CpuPrbEn] and D18F4x118/D18F4x11C[CpuPrbEn].
25:19 CacheFlushOnHaltTmr: cache flush on halt timer. Read-write. Cold reset: 00h.
IF (BatteryPower) THEN BIOS: 4h. ELSE BIOS: Fh. ENDIF.
Specifies how long each core needs to stay in a C-state before it flushes its caches. See CacheFlushOnHaltCtl, D18F3x80/D18F3x84[CpuPrbEn], [CoreCstateMode], and
D18F4x118/D18F4x11C[CacheFlushTmrSel].
Bits
Description
00h
5.12 us
7Fh-01h
(<CacheFlushOnHaltTmr> * 10.24us) - 5.12us <= Time <= <CacheFlushOnHaltTmr> * 10.24 us
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18:16 CacheFlushOnHaltCtl: cache flush on halt control. Read-write. Reset: 000b.
BIOS: 000b.
Enables cache flush on halt when ((D18F4x128[CoreCstateMode]==1) && (CacheFlushOnHaltCtl
!= 0)). Specifies what core clock divisor is used after the caches have been flushed, regardless of
D18F4x128[CoreCstateMode]. See D18F4x118/D18F4x11C[CacheFlushTmrSel].
Bits
Description
000b
IF (D18F4x128[CoreCstateMode]) THEN Disabled. ELSE Divide-by 1. ENDIF.
001b
Divide-by 2
010b
Divide-by 4
011b
Divide-by 8
100b
Divide-by 16
101b
Reserved Divide-by 128
110b
Reserved Divide-by 512
111b
Turn off clocks
Values of /128 and /512 should be not be used. See D18F3x[84:80] and D18F4x11[C:8] for clock
divisor specifications that are in effect during a C-state before the caches have been flushed. See
2.5.3.2.3.1 [C-state Probes and Cache Flushing].
15
NbsynPtrAdjPstate[0]: NB/core synchronization FIFO pointer adjust P-state[0]. Read-write.
Reset: Fuse[NumBoostStates[0]]. See NbsynPtrAdj.
14:12 NbsynPtrAdj: NB/core synchronization FIFO pointer adjust. Read-write. Cold reset: 000b.
BIOS: 110b.
Changes to this field take effect after any of the following events :
• Warm reset.
• At least one core on all compute units perform a P-state transition.
• An NB P-state transition.
There is a synchronization FIFO between the NB clock domain and core clock domains. At cold reset,
the read pointer and write pointer for each of these FIFOs is positioned conservatively, such that FIFO
latency may be greater than is necessary.
NbsynPtrAdj and NbsynPtrAdjLo may be used to position the read pointer and write pointer of each
FIFO closer to each other such that latency is reduced. Each increment of NbsynPtrAdj and
NbsynPtrAdjLo represents one clock cycle of whichever is the slower clock (longer period) between
the NB clock and the core clock. NbsynPtrAdj is used when the core P-state is less than or equal to
NbsynPtrAdjPstate, otherwise NbsynPtrAdjLo is used.
Values less than the recommended value are allowed; values greater than the recommended value are
illegal.
Description
Bits
6h-0h
Position the read pointer <NbsynPtrAdj, NbsynPtrAdjLo> clock cycles closer to the
write pointer.
7h
Position the read pointer 7 clock cycles closer to the write pointer
11
Reserved.
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10:8 HwPstateMaxVal: P-state maximum value. Read-write. IF ((D18F3xE8[HtcCapable]==1) &&
(D18F3x64[HtcTmpLmt]!=0) && (D18F3x64[HtcPstateLimit] > HwPstateMaxVal)) THEN BIOS:
D18F3x64[HtcPstateLimit]. ENDIF. Cold reset: specified by the reset state of
MSRC001_00[6B:64][PstateEn]; the cold reset value is the highest P-state number corresponding to
the MSR in which PstateEn is set (e.g., if MSRC001_0064 and MSRC001_0065 have this bit set and
the others do not, then HwPstateMaxVal=1; if MSRC001_0064 has this bit set and the others do not,
then HwPstateMaxVal=0). This specifies the highest P-state value (lowest performance state) supported by the hardware. This field must not be written to a value less (higher performance) than
MSRC001_0071[CurPstateLimit].
See MSRC001_0061[PstateMaxVal]. This field uses hardware P-state numbering. See 2.5.3.1.1.2
[Hardware P-state Numbering].
7:0
Reserved.
D18F3xE4 Thermtrip Status
Bits
Description
31
SwThermtp: software THERMTRIP. Write-1-only; cleared-by-hardware. Reset: 0. Writing a 1 to
this bit position induces a THERMTRIP event. This bit returns 0 when read. This is a diagnostic bit,
and it should be used for testing purposes only.
5
ThermtpEn: THERMTRIP enable. Read-only. Reset: Fuse[ThermTripEn]. 1=The THERMTRIP
state is supported. See 2.10.3.4 [THERMTRIP].
4
Reserved.
3
ThermtpSense: THERMTRIP sense. Read-only. Cold reset: 0. The processor temperature could
exceeded the THERMTRIP value prior to cold reset. 1=The processor temperature exceeded the
THERMTRIP value (regardless as to whether the THERMTRIP state is enabled). This bit is also set
when the diagnostic bit SwThermtp = 1.
2
Reserved.
1
Thermtp: THERMTRIP. Read-only. Cold reset: 0. The processor temperature could exceeded the
THERMTRIP value prior to cold reset. 1=The processor has entered the THERMTRIP state.
0
Reserved.
D18F3xE8 Northbridge Capabilities
Read-only. Unless otherwise specified, 1=The feature is supported by the processor; 0=The feature is not
supported.
Bits
Description
31:29 Reserved.
28
SUCCOR. Read-only. See CPUID Fn8000_0007_EBX[SUCCOR].
Value: 0.
27:26 Reserved.
25
Reserved.
24
MemPstateCap: memory P-state capable. Value: ~Fuse[MemPstateDis].
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23:20 Reserved.
19
x2Apic: x2APIC capability.
Value: 0.
18:16 Reserved.
15
Reserved.
14
MultVidPlane: multiple VID plane capable. Value: 1.
13:12 Reserved.
11
Reserved. Value: 0.
10
HtcCapable: HTC capable. Value: ~Fuse[HtcDis]. This affects D18F3x64 and D18F3x68.
9
SvmCapable: SVM capable. Value: ~Fuse[SvmDis].
8
MctCap: memory controller (on the processor) capable. Value: (D18F5x84[DctEn[1:0]]!=00b).
7:5
Reserved.
4
ChipKill: chipkill ECC capable. Value: ~Fuse[EccDis].
3
ECC: ECC capable. Value: ~Fuse[EccDis].
2
EightNode: Eight-node multi-processor capable. Value: (Fuse[DisableMP][2:0]==100b).
1
DualNode: Dual-node multi-processor capable. Value: (Fuse[DisableMP][2:0]==110b).
0
Reserved.
D18F3xFC CPUID Family/Model/Stepping
CPUID Fn0000_0001_EAX, CPUID Fn8000_0001_EAX are an alias of D18F3xFC.
Bits
Description
31:28 Reserved.
27:20 ExtFamily: extended family. Read-only.
Value: 07h.
19:16 ExtModel: extended model. Read-only. IF (Fuse[CpuIDFused]) THEN Reset: Fuse[CpuIdExtModel[3:0]] ELSE Reset: Metal[CpuIdExtModel[3:0]] ENDIF.
15:12 Reserved.
11:8 BaseFamily. Read-only. Reset: Fh.
7:4
BaseModel. Read-only. IF (Fuse[CpuIDFused]) THEN Reset: Fuse[CpuIdModel[3:0]] ELSE Reset:
Metal[CpuIdModel[3:0]] ENDIF.
3:0
Stepping. Read-only. IF (Fuse[CpuIDFused]) THEN Reset: Fuse[CpuIdStepping[3:0]] ELSE Reset:
Metal[CpuIdStepping[3:0]] ENDIF.
D18F3x138 DCT0 Bad Symbol Identification
Bits
Description
31:0 Reserved.
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D18F3x13C DCT1 Bad Symbol Identification
Bits
Description
31:0 Reserved.
D18F3x140 SRI to XCS Token Count
Out of cold reset, the processor allocates a minimal number of buffers that is smaller than the default values in
the register. BIOS must use D18F0x6C[RlsLnkFullTokCntImm] or D18F0x6C[RlsLnkFullTokCntOnRst] for
the values in the register to take effect. This is necessary even if the values are unchanged from the default
values.
D18F3x140, D18F3x144, and D18F3x1[54:48] specify the number of XCS (XBAR command scheduler)
entries assigned to each virtual channel within each source port. See 2.8 [Northbridge (NB)].
The default totals are:
Buffer allocation rules:
• The totals of SRI, MCT and the links must not exceed the number of XCS entries. XcsSize = 44.
• Rule: SUM(D18F3x140[UpReqTok, UpPreqTok, UpRspTok, DnReqTok, DnPreqTok, DnRspTok,
IsocReqTok, IsocPreqTok, IsocRspTok, FreeTok]) + SUM(D18F3x144[ProbeTok, RspTok]) +
SUM(D18F3x148[ReqTok0, PReqTok0, RspTok0, ProbeTok0, {FreeTok[3:2],FreeTok[1:0]},
IsocReqTok0, IsocPReqTok0, IsocRspTok0, ReqTok1, PReqTok1, RspTok1, ProbeTok1,
IsocReqTok1, IsocPReqTok1, IsocRspTok1]) + SUM(D18F3x14C[ReqTok0, PReqTok0, RspTok0,
ProbeTok0, {FreeTok[3:2],FreeTok[1:0]}, IsocReqTok0, IsocPReqTok0, IsocRspTok0, ReqTok1,
PReqTok1, RspTok1, ProbeTok1, IsocReqTok1, IsocPReqTok1, IsocRspTok1])<= XcsSize. See
D18F3x1[54:48].
The defaults for D18F3x140 and D18F3x1[54:48] do not allocate any tokens in the isochronous channel.
If isochronous flow control mode (IFCM) is enabled (D18F0x[E4,C4,A4,84][IsocEn]), then the XCS token
counts must be changed.
• If IFCM is enabled, then D18F3x140[IsocReqTok, IsocRspTok] must each be non-zero. If isochronous
posted requests may be generated in the system, then D18F3x140[IsocPreqTok] must also be non-zero. Or, in
display refresh mode, D18F3x140[IsocReqTok, IsocRspTok] must be non-zero.
Bits
Description
31:25 Reserved.
24:20 FreeTok: free tokens. Read-write.
Reset: 0Ch.
BIOS: Fh.
The number of free tokens must always be greater than or equal to 2 to ensure deadlock free
operation.
19:18 Reserved.
17:16 IsocRspTok: isochronous response tokens. Read-write.
Reset: 0.
BIOS: 1.
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15:14 IsocPreqTok: isochronous posted request tokens. Read-write.
Reset: 0.
BIOS: 0.
13:12 IsocReqTok: isochronous request tokens. Read-write.
Reset: 0.
BIOS: 1.
11:10 DnRspTok: downstream response tokens. Read-write.
Reset: 1.
BIOS: 1.
9:8
UpRspTok: upstream response tokens. Read-write.
Reset: 3. BIOS: 1.
7:6
DnPreqTok: downstream posted request tokens. Read-write. Reset: 1. BIOS: 1.
5:4
UpPreqTok: upstream posted request tokens. Read-write. Reset: 1. BIOS: 2.
3:2
DnReqTok: downstream request tokens. Read-write.
Reset: 1. BIOS: 1.
1:0
UpReqTok: upstream request tokens. Read-write.
Reset: 3.
BIOS: 2.
D18F3x144 MCT to XCS Token Count
See D18F3x140.
Bits
Description
31:8 Reserved.
7:4
ProbeTok: probe tokens. Read-write.
Reset: 7h.
BIOS: 4h.
3:0
RspTok: response tokens. Read-write.
Reset: 7h.
BIOS: 7h.
D18F3x1[54:48] Link to XCS Token Count
See D18F3x140.
Table 174: Register Mapping for D18F3x1[54:48]
Register
D18F3x148
D18F3x1[54:4C]
Function
ONION Link
Reserved
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Bits
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Description
31:30 FreeTok[3:2]: free tokens. Read-write. Cold reset: 00b.
BIOS: 0.
See FreeTok[1:0].
29
Reserved.
28
IsocRspTok1: isochronous response tokens sublink 1. Read-write. Cold reset: 0. BIOS: 0.
27
Reserved.
26
IsocPreqTok1: isochronous posted request tokens sublink 1. Read-write. Cold reset: 0. BIOS: 0.
25
Reserved.
24
IsocReqTok1: isochronous request tokens sublink 1. Read-write. Cold reset: 0. BIOS: 0.
23:22 ProbeTok1: probe tokens sublink 1. Read-write. Cold reset: 0. BIOS: 0.
21:20 RspTok1: response tokens sublink 1. Read-write. Cold reset: 0. BIOS: 0.
19:18 PReqTok1: posted request tokens sublink 1. Read-write. Cold reset: 0. BIOS: 0.
17:16 ReqTok1: request tokens sublink 1. Read-write. Cold reset: 0. BIOS: 0.
15:14 FreeTok[1:0]: free tokens. Read-write. Cold reset: 00b. FreeTok[3:0] = {FreeTok[3:2],
FreeTok[1:0]}.
BIOS: 00b.
13:12 IsocRspTok0: isochronous response tokens sublink 0. Read-write. Cold reset: 0.BIOS: 0.
11:10 IsocPreqTok0: isochronous posted request tokens sublink 0. Read-write. Cold reset: 0.
BIOS: IF (REG==D18F3x148) THEN 1 ELSE 0 ENDIF.
See D18F0x6C[ApplyIsocModeEnNow].
9:8
IsocReqTok0: isochronous request tokens sublink 0. Read-write. Cold reset: 0.
BIOS: IF (REG==D18F3x148) THEN 1 ELSE 0 ENDIF.
7:6
ProbeTok0: probe tokens sublink 0. Read-write. Cold reset: 2.
BIOS: 0.
5:4
RspTok0: response tokens sublink 0. Read-write. Cold reset: 2. BIOS: IF (REG==D18F3x148)
THEN 2 ELSE 0 ENDIF.
3:2
PReqTok0: posted request tokens sublink 0. Read-write. Cold reset: 2. BIOS: IF
(REG==D18F3x148) THEN 2 ELSE 0 ENDIF.
1:0
ReqTok0: request tokens sublink 0. Read-write. Cold reset: 2. BIOS: IF (REG==D18F3x148)
THEN 2 ELSE 3 ENDIF.
D18F3x160 NB Machine Check Misc (DRAM Thresholding) 0 (MC4_MISC0)
See 2.14.1.7 [Error Thresholding]. D18F3x160 is associated with the DRAM error type. See MSR0000_0413.
Bits
Description
31
Valid. Read-only. Reset: 1.
30
CntP: counter present. Read-only. Reset: 1.
29
Locked. Read-only. Reset: 0.
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28:24 Reserved.
23:20 LvtOffset: LVT offset. IF (Locked) THEN Read-only. ELSE Read-write. ENDIF. Reset: 0h. BIOS:
1h.
19
CntEn: counter enable. IF (Locked) THEN Read-only. ELSE Read-write. ENDIF. Reset: 0.
18:17 IntType: interrupt type. IF (Locked) THEN Read-only. ELSE Read-write. ENDIF. Cold reset: 0.
16
Ovrflw: overflow. IF (Locked) THEN Read-only; set-by-hardware. ELSE Read-write; set-by-hardware. ENDIF. Cold reset: 0.
15:12 Reserved.
11:0 ErrCnt: error counter. IF (Locked) THEN Read-only; updated-by-hardware. ELSE Read-write;
updated-by-hardware. ENDIF. Cold reset: 0.
D18F3x168 NB Machine Check Misc (Link Thresholding) 1 (MC4_MISC1)
See 2.14.1.7 [Error Thresholding]. D18F3x168 is associated with the link error type. See MSRC000_0408.
Bits
Description
31
Valid. Read-only. Reset: 1.
30
CntP: counter present. Read-only. Reset: 1.
29
Locked. Read-only. Reset: 0.
28:24 Reserved.
23:20 LvtOffset: LVT offset. IF (Locked) THEN Read-only. ELSE Read-write. ENDIF. Reset: 0h. BIOS:
1h.
19
CntEn: counter enable. IF (Locked) THEN Read-only. ELSE Read-write. ENDIF. Reset: 0.
18:17 IntType: interrupt type. IF (Locked) THEN Read-only. ELSE Read-write. ENDIF. Cold reset: 0.
16
Ovrflw: overflow. IF (Locked) THEN Read-only; set-by-hardware. ELSE Read-write; set-by-hardware. ENDIF. Cold reset: 0.
15:12 Reserved.
11:0 ErrCnt: error counter. IF (Locked) THEN Read-only; updated-by-hardware. ELSE Read-write;
updated-by-hardware. ENDIF. Cold reset: 0.
D18F3x17C Extended Freelist Buffer Count
Out of cold reset, the processor allocates a minimal number of buffers that is smaller than the default values in
the register. BIOS must use D18F0x6C[RlsLnkFullTokCntImm] or D18F0x6C[RlsLnkFullTokCntOnRst] for
the values in the register to take effect. This is necessary even if the values are unchanged from the default
values.
Bits
Description
31:4 Reserved.
3:0
SPQPrbFreeCBC: XBAR to SRI Probe command buffer freelist.
Reset: 8h.
Read-write.
BIOS: 8h.
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D18F3x180 Extended NB MCA Configuration
Reset: 0000_0000h. This register is an extension of D18F3x44 [MCA NB Configuration].
Bits
Description
31
Reserved.
30
Reserved. Read-write.
29
Reserved. Read-write. SyncFloodOnG5CrcErr.
28
SyncFloodOnCC6DramUcErr. Read-write. BIOS: 1. 1=Enable generation of SyncFlood when we
hit an Uncorrectable ECC error on C6 restore reads.
27
Reserved. Read-write.
26
ConvertUnCorToCorErrEn: convert uncorrectable error to correctable error enable. Readwrite. 1=The status of uncorrectable errors is changed to appear as correctable errors;
MSR0000_0411[UC, PCC] are cleared and a machine check exception will not be raised. For
uncorrectable ECC errors, MSR0000_0411[UECC] is cleared and MSR0000_0411[CECC] is set.
Deferred errors are not affected. This field is intended for debug observability.
25
EccSymbolSize: ECC symbol size and code selection. Read-write. BIOS: See 2.14.2 [DRAM ECC
Considerations]. 0=x4 symbol size and code used.1=reserved
24
McaLogErrAddrWdtErr: log error address on WDT errors. Read-write. BIOS: 1. 1=When a
watchdog timeout error occurs (see MSR0000_0410[WDTRptEn]), the associated address is logged
and MSR0000_0411[AddrV] is set. 0=When a watchdog timeout error occurs, NB state information
is saved and MSR0000_0411[AddrV] is cleared. See D18F3x50 for details on saved information.
23
Reserved. Read-write.
22
Reserved. Read-write.
21
SyncFloodOnCpuLeakErr: sync flood on CPU leak error. Read-write. BIOS: 1. 1=Enable sync
flood when one of the cores encounters an uncorrectable error which cannot be contained to the process on the core.
20
Reserved. Read-write.
19
PwP2pDatErrRmtPropDis: posted write for remote peer-to-peer data error propagation disable. Read-write.
1= A peer-to-peer posted write with a data error is not propagated to the target IO link chain if the target IO link chain is not attached to the local node (the same node as the source IO link chain). Instead,
the write is dropped by the host bridge. This bit can be used in conjunction with DatWrErrDeferEn to
cause a machine check exception and SyncFloodOnDeferErrToIO to cause a sync flood. The state of
this field is ignored if SyncFloodOnUsPwDatErr==1.
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18
PwP2pDatErrLclPropDis: posted write for local peer-to-peer data error propagation disable.
Read-write. 1=A peer-to-peer posted write with a data error is not propagated to the target IO link
chain if the target IO link chain is attached to the local node (the same node as the source IO link
chain). Instead, the write is dropped by the host bridge. This bit can be used in conjunction with DatWrErrDeferEn to cause a machine check exception and SyncFloodOnDeferErrToIO to cause a sync
flood. The state of this field is ignored if SyncFloodOnUsPwDatErr==1.
17
SyncFloodOnDeferErrToIO: convert deferred error for an IO link to sync flood enable. Readwrite.
BIOS: 1.
1=A deferred error which targets an IO link device is turned into a sync flood.
• When DramErrDeferEn is set and the read response is for a DMA read with a data error, setting
SyncFloodOnDeferErrToIO causes a sync flood.
• When DatWrErrDeferEn is set and the write is peer-to-peer, setting SyncFloodOnDeferErrToIO
causes a sync flood.
16
DeferDatErrNcHtMcaEn: convert deferred error for an IO link to machine check exception
enable. IF (D18F3xE8[SUCCOR]) THEN Read-write. ELSE Read-only. ENDIF.
1=A deferred error which targets an IO link device is turned into a machine check exception.
• When DramErrDeferEn is set and the read response is for a DMA read with a data error, setting
DeferDatErrNcHtMcaEn causes an uncorrected error to be logged and a machine check exception
to be generated. An error response is returned to the IO device irrespective of the setting of DeferDatErrNcHtMcaEn.
• When DatWrErrDeferEn is set and the write is peer-to-peer, setting DeferDatErrNcHtMcaEn
causes an uncorrected error to be logged and a machine check exception to be generated. An error
indication is sent to the target IO device irrespective of the setting of DeferDatErrNcHtMcaEn.
15
Reserved.
10
Reserved. Read-write.
9
SyncFloodOnUCNbAry: sync flood on UC NB array error. Read-write. BIOS: 1. 1=Enable sync
flood on detection of an UC error in an NB array.
8
SyncFloodOnProtErr: sync flood on protocol error. Read-write. BIOS: 1. 1=Enable sync flood on
detection of link protocol error, L3 protocol error, and probe filter protocol error.
7
SyncFloodOnTgtAbortErr. Read-write. BIOS: 1. 1=Enable sync flood on generated or received link
responses that indicate target aborts.
6
SyncFloodOnDatErr. Read-write.
BIOS: 1.
1=Enable sync flood on generated or received link responses that indicate data error.
5
DisPciCfgCpuMstAbortRsp. Read-write. BIOS: 1. 1=For master abort responses to CPU-initiated
configuration accesses, disables MCA error reporting and generation of an error response to the core.
It is recommended that this bit be set in order to avoid MCA exceptions being generated from master
aborts for PCI configuration accesses, which are common during device enumeration.
4
ChgMstAbortToNoErr. Read-write. 1=Signal no errors instead of master abort in link response
packets to IO devices on detection of a master abort condition. When ChgMstAbortToNoErr and
D18F3x44[IoMstAbortDis] are both set, ChgMstAbortToNoErr takes precedence.
3
ChgDatErrToTgtAbort. Read-write. 1=Signal target abort instead of data error in link response
packets to IO devices (for Gen1 link compatibility).
2
WDTCntSel[3]: watchdog timer count select bit[3]. Read-write. See D18F3x44[WDTCntSel].
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1
SyncFloodOnUsPwDatErr: sync flood on upstream posted write data error. Read-write.
BIOS: 1.
1=Enable sync flood generation when an upstream posted write data error is detected; setting of
PwP2pDatErrRmtPropDis and PwP2pDatErrLclPropDis are ignored.
0
McaLogUsPwDatErrEn: MCA log of upstream posted write data error enable. Read-write.
BIOS: 1. 1=Enable logging of upstream posted write data errors in MCA (if NB MCA registers are
appropriately enabled and configured).
D18F3x188 NB Configuration 2 (NB_CFG2)
Same-for-all.
Bits
Description
27
DisCpuWrSzDw64ReOrd: disable streaming store reorder. Read-write. Reset: 1. BIOS: 1. 1=Disable reordering of streaming store commands.
9
DisL3HiPriFreeListAlloc. Read-write. Reset: 0. BIOS: 1. 1=Disables normal SRQ entry scheme
which gives higher priority to L3 than XBAR.
D18F3x190 Downcore Control
Cold reset: 0000_0000h. See 2.4.4 [Processor Cores and Downcoring] and 2.4.4.1 [Software Downcoring
using D18F3x190[DisCore]].
Bits
Description
31:0 DisCore. Read-write; reset-applied. 0=Logical Core enabled. 1=Logical Core disabled.
Bit
Description
[0]
Logical Core 0.
[2:1]
Logical Core <BIT>.
[3]
Logical Core 3.
[31:4]
Reserved.
D18F3x1A0 Core Interface Buffer Count
Out of cold reset, the processor allocates a minimal number of buffers that is smaller than the default values in
the register. BIOS must use D18F0x6C[RlsLnkFullTokCntImm] or D18F0x6C[RlsLnkFullTokCntOnRst] for
the values in the register to take effect. This is necessary even if the values are unchanged from the default
values.
• The following buffer allocations rules must be satisfied:
• CpuCmdBufCnt >= 2.
Bits
31
Description
Reserved.
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30:26 NbToCpuPrbLmt. Read-write. Reset: 10h. Maximum number of outstanding probes to the
compute-unit.
Bits
Description
02h-00h
Reserved
0Fh-03h
Maximum of <NbToCpuPrbLmt> probes.
1Fh-10h
Reserved
25:24 Reserved.
23:20 NbToCpuDatReqLmt. Read-write. Reset: Ch. Octword outstanding per core limit.
Bits
Description
Ch-0h
Octword outstanding per core limit
Fh-Dh
Reserved
19
Reserved.
18:16 CpuToNbFreeBufCnt. Read-write. Reset: 2h. Provides the number of tokens which can released to
each compute unit from the freelist pool. This field can be updated at any time by BIOS and does not
require a warm reset to take effect.
BIOS: 11b.
Bits
Description
3h-0h
Number of tokens released to each compute unit from the freelist pool.
7h-4h
Reserved
15:12 Reserved. Read-write; Reset-applied. Cold reset: 4h.
11:10 Reserved.
9:4
3
2:0
Reserved. Read-write; Reset-applied. Cold reset: IF (NumOfCompUnitsOnNode==1) THEN 1Ch
ELSEIF (NumOfCompUnitsOnNode==2) THEN 18h ENDIF.
Reserved.
CpuCmdBufCnt: CPU to SRI command buffer count. Read-write; reset-applied. Each compute
unit is allocated the number of buffers specified by this field.
Reset: 2h.
BIOS: 1h.
D18F3x1CC IBS Control
Reset: 0000_0000h. MSRC001_103A is an alias of D18F3x1CC. D18F3x1CC is programmed by BIOS; The
OS reads the LVT offset from MSRC001_103A.
Bits
Description
31:9 Reserved.
8
LvtOffsetVal: local vector table offset valid. Read-write. BIOS: 1. 1=The offset in LvtOffset is
valid. 0=The offset in LvtOffset is not valid and IBS interrupt generation is disabled.
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7:4
Reserved.
3:0
LvtOffset: local vector table offset. Read-write. BIOS: 0h. Specifies the address of the IBS LVT
entry in the APIC registers. See APIC[530:500].
Bits
Description
3h-0h
LVT address = <500h + LvtOffset<<4>
Fh-4h
Reserved
D18F3x1FC Product Information Register 1
Bits
Description
31:1 Reserved. Value: Fuse[ScratchFuses[31:1]].
0
DcTdpSupport. Value: Fuse[ScratchFuses[0]]. 1=Dynamic Configurable TDP supported. See
2.5.11.8 [Dynamic Configurable TDP (DcTDP)].
D18F3x200 Performance Mode Control Register
Reset: 0000_0000h.
Bits
Description
31:8 Reserved.
7:4
EnCpuSkidBufFull. Read-write. Enables optimal use of the CPU skid buffers, in the presence of
multiple data movement requests from the same core. This value shouldbe set based on the number of
CPU skid buffers instantiated in the design.
3
EnMcqPrbPickThrottle. Read-write. BIOS: 0. 1=Enabling throttling the MCQ to ensure the bypass
path is taken by the probes instead of allocating in to the XCS.
2
EnDctOddToNcLnkDatXfr. Read-write. BIOS: 0. 1=Enables direct transfer of data from oddnumbered DRAM channels (1,3,..) to non-coherent links on the local node.
1
EnDctEvnToNcLnkDatXfr. Read-write.
BIOS: 0.
1=Enables direct transfer of data from even-numbered DRAM channels (0,2,..) to non-coherent links
on the local node.
0
Reserved. Read-write.
D18F3x238 DCT2 Bad Symbol Identification
Bits
Description
31:0 Reserved.
D18F3x23C DCT3 Bad Symbol Identification
Bits
Description
31:0 Reserved.
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D18F3x2B4 DCT and Fuse Power Gate Control
Cold reset: 0000_0000h.
Bits
Description
31:27 Reserved.
26:12 Reserved.
11:0 Reserved.
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3.13 Device 18h Function 4 Configuration Registers
See 3.1 [Register Descriptions and Mnemonics]. See 2.7 [Configuration Space].
D18F4x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID. Read-only.
Value: 1534h.
15:0 VendorID: vendor ID. Read-only. Value: 1022h.
D18F4x04 Status/Command
Bits
Description
31:16 Status. Read-only. Reset: 0000_0000_000X_0000b. Only Status[4] may be set to indicate the existence of a PCI-defined capability block. 0=No supported links are unganged. 1=At least one link may
be unganged, in which case there is a capability block associated with sublink one of the link in this
function.
15:0 Command. Read-only. Value: 0000h.
D18F4x08 Class Code/Revision ID
Reset: 0600_0000h.
Bits
Description
31:8 ClassCode. Read-only. Provides the host bridge class code as defined in the PCI specification.
7:0
RevID: revision ID. Read-only.
D18F4x0C Header Type
Reset: 0080_0000h.
Bits
Description
31:0 HeaderTypeReg. Read-only. These bits are fixed at their default values. The header type field indicates that there are multiple functions present in this device.
D18F4x34 Capabilities Pointer
Bits
Description
31:8 Reserved.
7:0
CapPtr: capabilities pointer. Read-only. Value: 00h.
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D18F4x110 Sample and Residency Timers
Bits
Description
31:21 Reserved.
20:13 MinResTmr: minimum residency timer. IF D18F4x15C[BoostLock] THEN Read-only. ELSE
Read-write. ENDIF. Cold reset: Fuse[MinResTmr].
Specifies the minimum amount of time required between APM TDP-initiated P-state transitions. The
minimum amount of time is defined as MinResTmr * CSampleTimer * FastCSampleTimer. In addition to the MinResTmr, the requirements in D18F5xB4[NodeTdpAccThrottleThreshold],
D18F5xB0[NodeTdpAccBoostThreshold] or D18F5xBC[CmpUnitTdpAccThrottleThreshold] for a
given compute unit must be met prior to an APM TDP-initiated P-state transition. See 2.5.9.3 [Bidirectional Application Power Management (BAPM)].
12
Reserved.
11:0 CSampleTimer.
Read-write.
Cold reset: 0.
BIOS: 14h.
Specifies the value that the internal CSampleTimer counter must increment to before expiring. When
the internal CSampleTimer counter expires, it is reset to 0. This is the rate at which the northbridge
samples the power monitor. A value of 0 disables the power monitor sampling. See FastCSampleTimer and 2.5.9 [Application Power Management (APM)].
When the Northbridge is in a low power state (D18F3x80/D18F3x84[NbLowPwrEn]=1) and NbCof
>= RefClk, the Northbridge updates power information at the following rate:
CSampleTimer * FastCSampleTimer <= Time <= (CSampleTimer * FastCSampleTimer + (9 *
(CLKIN / NbCof)) / CLKIN).
When the Northbridge is in a low power state and NbCof < RefClk, the Northbridge updates power
information at the following rate:
CSampleTimer * FastCSampleTimer <= Time <= (CSampleTimer * FastCSampleTimer + (9 *
(CLKIN / NbCof) + 4) / CLKIN).
When the Northbridge is not in a low power state, the Northbridge samples the power monitor at the
following rate:
CSampleTimer * FastCSampleTimer <= Time <= (CSampleTimer * FastCSampleTimer + (9 * (1 /
CLKIN).
D18F4x11[C:8] C-state Control
D18F4x11[C:8] consist of three identical 16-bit registers, one for each C-state Action Field (CAF) associated
with an IO address that is read to enter C-states. Refer to 2.5.3.2 [Core C-states].
• D18F4x118[15:0] specifies the actions attempted by the core when software reads from the IO address
specified by MSRC001_0073[CstateAddr].
• D18F4x118[31:16] specifies the actions attempted by the core when software reads from the IO address
specified by MSRC001_0073[CstateAddr]+1.
• D18F4x11C[15:0] specifies the actions attempted by the core when software reads from the IO address
specified by MSRC001_0073[CstateAddr]+2.
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D18F4x118 C-state Control 1
Bits
Description
31:30 Reserved.
29
SelfRefrEarly1. Read-write. Reset: 0. See: SelfRefrEarly0. Temp.BIOS: 0.
28
SelfRefr1. Read-write. Reset: 0. See: SelfRefr0.
Temp.BIOS: 1.
27
NbClkGate1. Read-write. Reset: 0. See: NbClkGate0.
Temp.BIOS: 1.
26
NbPwrGate1. Read-write. Reset: 0. See: NbPwrGate0.
25
PwrOffEnCstAct1. Read-write; updated-by-SMU. Reset: 0. See: PwrOffEnCstAct0.
BIOS: 1.
24
PwrGateEnCstAct1. Read-write. Reset: 0. See: PwrGateEnCstAct0. Temp.BIOS: 1.
23:21 ClkDivisorCstAct1. Read-write. Reset: 0. See: ClkDivisorCstAct0.
BIOS: 000b.
20
Reserved.
19:18 CacheFlushTmrSelCstAct1. Read-write. Reset: 0. See: CacheFlushTmrSelCstAct0.
Char.Temp.BIOS: 10b.
17
CacheFlushEnCstAct1. Read-write. Reset: 0. See: CacheFlushEnCstAct0. Char.Temp.BIOS: 1.
16
CpuPrbEnCstAct1. Read-write. Reset: 0. See: CpuPrbEnCstAct0. Char.Temp.BIOS: 1.
15:14 Reserved.
13
SelfRefrEarly0: allow early self-refresh. Read-write. Reset: 0. Temp.BIOS: 0. 1=Allow self-refresh
while cores in PC1 or CC1 are waiting for the cache flush timer to expire. 0=Wait for cache flush
timer to expire before allowing self-refresh. The usage of this bit depends on D18F4x128[CoreCstateMode]. See 2.5.7.2 [DRAM Self-Refresh] and 2.5.3.2.3.1 [C-state Probes and Cache Flushing].
12
SelfRefr0: self-refresh. Read-write. Reset: 0.
Temp.BIOS: 1.
1=Allow DRAM self-refresh while in NB C-states. 0=Prevent DRAM self-refresh while in NB Cstates. NbClkGate0 must be equal to SelfRefr0. The usage of this bit depends on D18F4x128[CoreCstateMode]. See 2.5.7.2 [DRAM Self-Refresh] and 2.5.4.2 [NB C-states].
11
NbClkGate0: NB clock-gating. Read-write. Reset: 0.
Temp.BIOS: 1.
1=Allow clock-gating of the NB. 0=Prevent clock-gating of the NB. NbClkGate0 must be equal to
SelfRefr0. The usage of this bit depends on D18F4x128[CoreCstateMode]. See 2.5.4.2 [NB C-states].
10
NbPwrGate0: NB power-gating. Read-write. Reset: 0.
1=Allow power-gating of the NB. 0=Prevent power-gating of the NB. NbPwrGate0 can only be programmed to 1 if NbClkGate0 and SelfRefr0 are programmed to 1. The usage of this bit depends on
D18F4x128[CoreCstateMode]. See 2.5.4.2 [NB C-states].
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9
PwrOffEnCstAct0: power off enable. Read-write; updated-by-SMU. Reset: 0.
Char.Temp.BIOS: 1.
1=Package power off enable. CacheFlushEnCstAct0 is required to be set if this bit is set.
PwrGateEnCstAct0 is required to be set if this bit is set. See 2.5.3.2.3.4 [Package C6 (PC6) State].
8
PwrGateEnCstAct0: power gate enable. Read-write. Reset: 0. Char.Temp.BIOS: 1. 1=Core power
gating is enabled. CacheFlushEnCstAct0 is required to be set if this bit is set. See 2.5.3.2.3.3 [Core C6
(CC6) State].
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ClkDivisorCstAct0: clock divisor. Read-write. Reset: 0.
BIOS: 000b.
Specifies the core clock frequency while in the low-power state before the caches are flushed. This
divisor is relative to the current FID frequency, or:
• 100 MHz * (10h + MSRC001_00[6B:64][CpuFid]) of the current P-state specified by
MSRC001_0063[CurPstate].
If MSRC001_00[6B:64][CpuDid] of the current P-state indicates a divisor that is deeper than specified by this field, then no frequency change is made when entering the low-power state associated
with this register.
DescriptionBits
Description
Bits
000b
/1
100b
/16
001b
/2
101b
/128
010b
/4
110b
/512
011b
/8
111b
Turn off clocks.
See CacheFlushTmrSelCstAct0.
Reserved.
CacheFlushTmrSelCstAct0: cache flush timer select. Read-write. Reset: 0. Char.Temp.BIOS: 10b.
Specifies the timer to use for cache flush.
Bits
Cache flush timer
00b
0 us
01b
D18F3xDC[CacheFlushOnHaltTmr]
10b
D18F4x128[CacheFlushTmr]
11b
Reserved
Each core has one timer.
D18F3xDC[CacheFlushOnHaltCtl] specifies the core clock divisor to use after the caches are flushed.
Writing values greater than 10b result in 10b. See CacheFlushEnCstAct0 and CpuPrbEnCstAct0.
1
CacheFlushEnCstAct0: cache flush enable. Read-write. Reset: 0. Char.Temp.BIOS: 1. 1=Cache
flush enable. The cache flush timer starts counting when the C-state is entered. See
CacheFlushTmrSelCstAct0 and 2.5.3.2.3.1 [C-state Probes and Cache Flushing].
PwrGateEnCstAct0 is required to be set if this bit is set.
0
CpuPrbEnCstAct0: core direct probe enable. Read-write. Reset: 0. Char.Temp.BIOS: 1. Specifies
how probes are handled while in the low-power state. 0=When the probe request comes into the NB,
the core clock is brought up to the COF (based on the current P-state), all outstanding probes are completed, the core waits for a hysteresis time based on D18F3xD4[ClkRampHystSel], and then the core
clock is brought down to the frequency specified by ClkDivisorCstAct0. 1=The core clock does not
change frequency; the probe is handled at the frequency specified by ClkDivisorCstAct0; this may
only be set if:
• ClkDivisorCstAct0 specifies a divide-by 1, 2, 4, 8, or 16 and NbCof <= 3.2 GHz
• ClkDivisorCstAct0 specifies a divide-by 1, 2, 4, or 8 and NbCof >= 3.4 GHz
This bit also specifies functionality of the timer used for cache flushing. See
CacheFlushTmrSelCstAct0.
• If CpuPrbEnCstAct0=0 and D18F3xDC[IgnCpuPrbEn]=0, only the time when the core is in a nonC0 state and has its clocks ramped up to service probes is counted.
• If CpuPrbEnCstAct0=1 or D18F3xDC[IgnCpuPrbEn]=1, all of the time the core is in a non-C0
state is counted.
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D18F4x11C C-state Control 2
Reset: 0000_0000h. Read-write.
Bits
Description
31:14 Reserved.
13
SelfRefrEarly2. See: D18F4x118[SelfRefrEarly0].
12
SelfRefr2. See: D18F4x118[SelfRefr0].
11
NbClkGate2. See: D18F4x118[NbClkGate0].
10
NbPwrGate2. See: D18F4x118[NbPwrGate0].
9
PwrOffEnCstAct2. See: D18F4x118[PwrOffEnCstAct0].
8
PwrGateEnCstAct2. See: D18F4x118[PwrGateEnCstAct0].
7:5
ClkDivisorCstAct2. See: D18F4x118[ClkDivisorCstAct0].
4
3:2
Reserved.
CacheFlushTmrSelCstAct2. See: D18F4x118[CacheFlushTmrSelCstAct0].
1
CacheFlushEnCstAct2. See: D18F4x118[CacheFlushEnCstAct0].
0
CpuPrbEnCstAct2. See: D18F4x118[CpuPrbEnCstAct0].
D18F4x124 C-state Interrupt Control
Bits
Description
31:0 Reserved.
D18F4x128 C-state Policy Control 1
Reset: 0080_0000h.
Bits
31
Description
CstateMsgDis: C-state messaging disable. Read-write.
Specifies whether any messages are sent to the FCH when a core enters or exits a C-state. 0=Messages are sent. 1=Messages are not sent. See 2.5.3.2.4.1 [FCH Messaging].
24:23 CacheFlushSucMonMispredictAct: cache flush success monitor mispredict action. Read-write.
Char.Temp.BIOS: 01b.
Specifies the cache flush success monitor decrement when non-C0 residency is shorter than duration
specified by CacheFlushSucMonTmrSel. See D18F4x130[CacheFlushSuccessMonitor].
This applies for all cores.
Bits
Description
00b
reset counter to zero
01b
decrement by 1
10b
decrement by 2
11b
decrement by 2
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22:21 CacheFlushSucMonTmrSel: cache flush success monitor timer select. Read-write.
Char.Temp.BIOS: 01b.
Specifies the non-C0 duration used to increment the cache flush success monitor. See
D18F4x130[CacheFlushSuccessMonitor].
This threshold applies for all cores.
Bits
Duration
00b
Use cache flush timer specified by D18F4x11[C:8]
01b
D18F3xDC[CacheFlushOnHaltTmr]
10b
D18F4x128[CacheFlushTmr]
11b
Reserved
20:18 CacheFlushSucMonThreshold: cache flush success monitor threshold. Read-write.
BIOS: 100b.
Flush the caches immediately if cache flushing is enabled and the cache flush success monitor count
(D18F4x130[CacheFlushSuccessMonitor]) == CacheFlushSucMonThreshold. A value of 0 disables
the cache flush success monitor. See D18F4x118/D18F4x11C[CacheFlushEn].
This threshold applies for all cores.
17:12 Reserved. Read-write.
11:5 CacheFlushTmr: cache flush timer. Read-write.
IF (BatteryPower) THEN BIOS: 3Ch. ELSE BIOS: 7Fh. ENDIF.
Specifies how long each core needs to stay in a C-state before it flushes its caches. See CoreCstateMode and D18F4x118/D18F4x11C[CacheFlushTmrSel].
Bits
Description
00h
<= 5.12 us
7Fh-01h
(<CacheFlushTmr> * 10.24us) - 5.12us <= Time <= <CacheFlushTmr> * 10.24 us
4:2
HaltCstateIndex. Read-write. Char.Temp.BIOS: 0. Specifies the IO-based C-state that is invoked by
a HLT instruction. See CoreCstateMode.
1
Reserved. Read-write.
0
Reserved.
D18F4x13C SMU P-state Control
Reset: 0000_0000h. Read-only, updated-by-SMU.
Bits
Description
31:4 Reserved.
3:1
0
SmuPstateLimit. Specifies the highest-performance P-state (lowest value) allowed. SmuPstateLimit
is always bounded by MSRC001_0061[PstateMaxVal]. This field uses hardware P-state numbering.
See MSRC001_0071[CurPstateLimit] and 2.5.3.1.1.2 [Hardware P-state Numbering].
SmuPstateLimitEn.
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D18F4x15C Core Performance Boost Control
Bits
31
Description
BoostLock. Read-only. Reset: Fuse[BoostLock]. Specifies whether the following registers are Readwrite, read-only, or have special requirements related to writability. See individual register definitions
for details.
• MSRC001_00[6B:64][CpuFid, CpuDid, CpuVid].
• D18F4x10C[CmpUnit0TdpLimit].
• D18F4x110[MinResTmr]
• D18F4x200.
• D18F4x204.
• D18F4x148.
• D18F4x14C.
• D18F4x150.
• D18F4x154.
• D18F4x15C[NumBoostStates].
• D18F4x16C[CstateCnt, CstateBoost, TdpLimitDis, NodeTdpLimitEn].
• D18F5xB0[NodeTdpAccBoostThreshold]
• D18F5xB4[NodeTdpAccThrottleThreshold]
• D18F5xBC[CmpUnitTdpAccThrottleThreshold]
• D18F5xC0[NodeTdpMarginAcc]
• D18F5x[268:264,D8:C4][CmpUnitTdpMarginAcc]
• D18F4x250[NodeTdpLimit].
30:9 Reserved.
8
CstatePowerEn: C-state power enable. If D18F2x1B4[SmuCfgLock] THEN Read-only; updatedby-hardware. (SMU) ELSE Read-write. ENDIF Reset: 0. BIOS: 1. 1=Enable
D18F4x150[CstatePowerP1, CstatePowerP2].
7
ApmMasterEn: APM master enable. If D18F2x1B4[SmuCfgLock] THEN Read-only; updated-byhardware. (SMU) ELSE Read-write. ENDIF Reset: 0.
BIOS: IF(D18F4x15C[NumBoostStates]==0) THEN 0. ELSE 1. ENDIF.
1=Enables the ability to turn on features associated with APM when used in conjunction with the
individual feature enable bits. Enables the Northbridge-to-core power monitor request interface. This
bit is the master enable bit for all APM related features. Programming this bit to 0 disables all APM
related features and disables the Northbridge-to-core power monitor request interface. See 2.5.9
[Application Power Management (APM)].
BIOS must not set D18F4x15C[ApmMasterEn] until after MSRC001_1073[ConfigLocked] is set.
6:5
Reserved.
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4:2
NumBoostStates: number of boosted states.
IF (D18F4x15C[BoostLock] | ApmMasterEn | D18F2x1B4[SmuCfgLock]) THEN Read-only. ELSE
Read-write. ENDIF. Reset: Fuse[NumBoostStates]. Specifies the number of P-states that are considered boosted P-states. See 2.5.9 [Application Power Management (APM)]. See
MSRC001_0072[NumBoostStates].
1:0
BoostSrc: boost source.
If D18F2x1B4[SmuCfgLock] THEN Read-only; updated-by-hardware. (SMU) ELSE Read-write.
ENDIF Reset: 0.
BIOS: 2.5.3.1.6.
Specifies whether CPB is enabled or disabled. See 2.5.5.1.6 [Modification of P-state Requests and
Visibility].
Bits
Description
00b
Boosting disabled Sets P-state limit to NumBoostStates on all cores.
01b
Boosting enabled APM boosting.
10b
Reserved defined as SBB enable.
11b
Reserved
D18F4x164 Fixed Errata
Bits
Description
31:0 FixedErrata. Value: {000000h, Fuse[FixedErrata[7:0]]}. See the Revision Guide for the definition of
this field. See 1.2 [Reference Documents].
D18F4x16C APM TDP Control
Bits
Description
31:15 Reserved.
14
CacUpC1. IF D18F4x15C[BoostLock] THEN Read-only. ELSE Read-write. ENDIF.
Reset: 1.
BIOS: 0.
1=Cac interface is up on C1 (non XC6) state. 0=Cac interface is down and Cstate scalers are used in
place of Cac reads.
13
CstateCores. IF D18F4x15C[BoostLock] THEN Read-only. ELSE Read-write. ENDIF.
Reset: 1.
Specifies how CstateCnt determines Cstate boost conditions.
Description
Bit
0h
CstateCnt specifies the number of cores.
1h
CstateCnt specifies the number of compute units (or CPCs).
11:9 CstateCnt: C-state count. IF D18F4x15C[BoostLock] THEN Read-only. ELSE Read-write. ENDIF.
Reset: Fuse[CStateCnt]. Specifies the number of cores or compute units (see CstateCores) that must
be in CC6 before an APM transition can occur to a boosted P-state that is higher performance than the
P-state specified by CstateBoost. A value of 0 disables access to P-states above CstateBoost.
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8:6
CstateBoost. Read-write. Reset: Fuse[CstateBoost]. Specifies the P-state which requires the number
of cores or compute units (see CstateCores) specified in CstateCnt to be in CC6 before a transition to
a higher performance (lower numbered) boosted P-state is allowed. CstateBoost must be less than or
equal to D18F4x15C[NumBoostStates] otherwise undefined behavior results. If D18F4x15C[BoostLock]=1, CstateBoost can only be written with values that are greater than or equal to the reset value.
Attempts to write values less than the reset value are ignored. A value of 0 indicates that the C-state
boost feature is not supported. This field uses hardware P-state numbering. See 2.5.3.1.1.2 [Hardware
P-state Numbering].
5
ApmTdpLimitSts: APM TDP limit status. Read; set-by-hardware; write-1-to-clear. Reset: 0. This
bit is set by hardware when D18F5xE8[ApmTdpLimit] changes.
4
ApmTdpLimitIntEn: APM TDP limit interrupt enable. Read-write. Reset: 0. BIOS: 1. 1=Enables
the generation of an interrupt using APIC330 of each core when D18F5xE8[ApmTdpLimit] changes.
See ERBT-925 and ERBT-1049.
3
TdpLimitDis. IF D18F4x15C[BoostLock] THEN Read-only. ELSE Read-write. ENDIF. IF
D0F0xBC_xC010408C[2]==1(Fuse[BapmDisable]). THEN BIOS:1. ENDIF. Reset: 0. 1=Disables
TDP limit checking and allows the processor to transition to higher performance P-states. See 2.5.9.3
[Bidirectional Application Power Management (BAPM)].
D18F4x1C0 Node Cac Register 1
Bits
Description
11:0 NodeCacLatest. Read-only, updated-by-hardware. Reset: 0. Specifies the sum of all instantaneous
power credits on each compute unit. NodeCacLatest is reset to 0 when D18F4x15C[ApmMasterEn]=0. NodeCacLatest is the sum of all CmpUnitCacLatest values. CmpUnitCacLatest is an internal, non-software visible value.
D18F4x250 TDP Limit 8
Bits
31
Description
Reserved.
30:28 TdpLimitPstate. Read-write. Reset: 0. Specifies the highest performance P-state that has a power
consumption less than or equal to the APM TDP limit. This field is programmed by BIOS and uses
software P-state numbering.
See 2.5.3.1.1.1 [Software P-state Numbering] and 2.5.5.1.6 [Modification of P-state Requests and
Visibility].
27:12 Reserved.
11:0 NodeTdpLimit. Read-write; Same-for-all. Reset: Fuse[ChipTdpLimit]. Specifies the maximum
allowed sum of TDPs from all cores on a node. If the consumed power exceeds the NodeTdpLimit, a
P-state limit is applied to all cores on the processor to reduce the power consumption so that it
remains within the TDP limit. If D18F4x15C[BoostLock]=1, NodeTdpLimit can only be written with
values that are less than or equal to the reset value. Attempts to write an invalid value are ignored. See
D18F4x16C[NodeTdpLimitEn] and 2.5.9.2 [TDP Limiting].
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3.14 Device 18h Function 5 Configuration Registers
See 3.1 [Register Descriptions and Mnemonics]. See 2.7 [Configuration Space].
D18F5x00 Device/Vendor ID
Bits
Description
31:16 DeviceID: device ID. Read-only. Value: 1535h.
15:0 VendorID: vendor ID. Read-only. Value: 1022h.
D18F5x04 Status/Command
Bits
Description
31:16 Status. Read-only. Value: 0000h.
15:0 Command. Read-only. Value: 0000h.
D18F5x08 Class Code/Revision ID
Bits
Description
31:8 ClassCode. Read-only. Value: 060000h. Provides the host bridge class code as defined in the PCI
specification.
7:0
RevID: revision ID. Read-only. Value: 00h.
D18F5x0C Header Type
Bits
Description
31:0 HeaderTypeReg. Read-only. Reset: 0080_0000h. These bits are fixed at their default values. The
header type field indicates that there are not multiple functions present in this device.
D18F5x34 Capabilities Pointer
Bits
Description
31:8 Reserved.
7:0
CapPtr: capabilities pointer. Read-only. Value: 00h.
D18F5x[70,60,50,40] Northbridge Performance Event Select Low
Bits
Description
31:0 MSRC001_024[6,4,2,0][31:0] is an alias of D18F5x[70,60,50,40].
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D18F5x[74,64,54,44] Northbridge Performance Event Select High
Bits
Description
31:0 MSRC001_024[6,4,2,0][63:32] is an alias of D18F5x[74,64,54,44].
D18F5x[78,68,58,48] Northbridge Performance Event Counter Low
Bits
Description
31:0 MSRC001_024[7,5,3,1][31:0] is an alias of D18F5x[78,68,58,48].
D18F5x[7C,6C,5C,4C] Northbridge Performance Event Counter High
Bits
Description
31:0 MSRC001_024[7,5,3,1][63:32] is an alias of D18F5x[7C,6C,5C,4C].
D18F5x80 Compute Unit Status 1
See 2.4.4 [Processor Cores and Downcoring].
Software associates logical core ID to the cores of the compute units according to the following table. All combinations not listed are reserved.
Table 175: D18F5x80[Enabled, DualCore, TripleCore, QuadCore] Definition
Enabled
1h
DualCore
xh
1h
xh
1h
1h
1h
0h
Bits
TripleCore QuadCore Definition
xh
1h
1 L2 complex is enabled; four cores of the L2 complex are
enabled.
1h
0h
1 L2 complex is enabled; three cores of the L2 complex
are enabled.
0h
0h
1 L2 complex is enabled; two cores of the L2 complex are
enabled.
0h
0h
1 L2 complex is enabled; one core of the L2 complex are
enabled.
Description
31:28 Reserved.
27:24 QuadCore: four cores of a L2 complex are enabled. Read-only. Reset: Reset is a function of
Fuse[CoreDis[7:0]], D18F3x190[DisCore[7:0]], and CLL; In CLL mode, the reset value is
0001_0001h. 1=Four cores of a L2 complex are enabled. See Table 175 [D18F5x80[Enabled, DualCore, TripleCore, QuadCore] Definition].
Bit
Description
[0]
Logical L2 complex 0
[1]
Reserved
[2]
Reserved
[3]
Reserved
23:20 Reserved.
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19:16 DualCore: two cores of a L2 complex are enabled. Read-only. Reset: Reset is a function of
Fuse[CoreDis[7:0]], D18F3x190[DisCore[7:0]], and CLL; In CLL mode, the reset value is
0001_0001h. 1=Both cores of a L2 complex are enabled. See Table 175 [D18F5x80[Enabled, DualCore, TripleCore, QuadCore] Definition].
Bit
Description
[0]
Logical L2 complex 0
[1]
Reserved
[2]
Reserved
[3]
Reserved
15:12 Reserved.
11:8 TripleCore: three cores of a L2 complex are enabled. Read-only. Reset: Reset is a function of
Fuse[CoreDis[7:0]], D18F3x190[DisCore[7:0]], and CLL; In CLL mode, the reset value is
0001_0001h. 1=Three cores of a L2 complex are enabled. See Table 175 [D18F5x80[Enabled, DualCore, TripleCore, QuadCore] Definition].
Bit
Description
[0]
Logical L2 complex 0
[1]
Reserved
[2]
Reserved
[3]
Reserved
7:4
Reserved.
3:0
Enabled: at least one core of a L2 complex is enabled. Read-only. Reset: Reset is a function of
Fuse[CoreDis[7:0]], D18F3x190[DisCore[7:0]], and CLL; In CLL mode, the reset value is
0001_0001h. 1=At least one core is enabled in a L2 complex. See Table 175 [D18F5x80[Enabled,
DualCore, TripleCore, QuadCore] Definition].
Description
Bit
[0]
Logical L2 complex 0
[1]
Reserved
[2]
Reserved
[3]
Reserved
D18F5x84 Northbridge Capabilities 2
Unless otherwise specified, 1=The feature is supported by the processor; 0=The feature is not supported.
Bits
Description
31:29 Reserved. Reserved for future expansion of DdrMaxRateEnf.
28:24 DdrMaxRateEnf: enforced maximum DDR rate. Read-only. Value: Fuse[DdrMaxRateEnf]. See:
DdrMaxRate. Specifies the maximum DRAM data rate that the processor is designed to support.
Writes to D18F2x94_dct[0][MemClkFreq] that specify a frequency greater than specified by
DdrMaxRateEnf will result in the D18F2x94_dct[0][MemClkFreq] being set to DdrMaxRateEnf.
23:21 Reserved.
20:16 DdrMaxRate: maximum DDR rate. Read-only. Value: Fuse[DdrMaxRate]. Specifies the maximum
DRAM data rate that the processor is designed to support. DdrMaxRate is defined by Table 124
[Valid Values for Memory Clock Frequency Value Definition]; except that 00h is defined as no limit.
See D18F2x94_dct[0][MemClkFreq], and DdrMaxRateEnf.
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15:12 DctEn[3:0]: DCT[3:0] enabled. Read-only. Value: ~Fuse[MemChanDis[3:0]]. Specifies which DCT
controllers are enabled. 1=Enabled. 0=Disabled.
Bit
Description
[0]
DCT 0
[3:1]
Reserved
11:8 Reserved.
7:0
CmpCap: CMP capable. Read-only. Value: (Number of physical cores on the node) - 1 - (the number of cores that are disabled by Fuse[CoreDis]). Number of fuse enabled cores on the internal node is
CmpCap+1. CmpCap does not reflect cores software disabled by D18F3x190[DisCore]. See 2.4.4
[Processor Cores and Downcoring].
D18F5x88 NB Configuration 4 (NB_CFG4)
Bits
Description
24
DisHbNpReqBusLock. Read-write. Reset: 0. BIOS: 1. 0=While bus locks are in progress, all nonposted commands from I/O, including atomics, are blocked until the core has completed the locked
transaction and releases the bus. 1=All non-posted commands except atomics do not honor bus locks
and are allowed to proceed. This bit may be set to achieve better DMA performance in the presence of
bus locks. This bit has no effect if MSRC001_001F[DisHbBusLock]=1.
18
EnCstateBoostBlockCC6Exit. Read-write. Reset: 0. If (EnCstateBoostBlockCC6Exit==1 &&
MSRC001_001F[DisCstateBoostBlockPstateUp]==0), cores cannot exit CC6 until VDD is less than
or equal to the voltage of the P-state indexed by D18F4x16C[CstateBoost]. This bit must be cleared if
CC6PstateLimitMaskDis is set. This bit must be cleared if D18F3x18C[DisC6StpGntExit] is set.
14
DisHldRegRdRspChk. Read-write. Reset: 0. 1=Disable primary holding register CPU or I/O read
response checks.
0
CC6PstateWakeUpDis. Read-write. Reset: 0. BIOS: 1. 1=Disable waking up cores in CC6 for Pstate changes. 0=Wakeup cores in CC6 for a P-state change to the PopDownPstate, and then return the
core to CC6. This is a chicken bit for the case where a core can enter CC6 and not be in the PopDownPstate.
D18F5x8C NB Configuration 5 (NB_CFG5)
Bits
15
Description
EnSrqAllocGt31. Read-write. Reset: 0b. BIOS: 1. 1=Enables allocation of SRA entries to above the
lower 32 entries.
D18F5xE0 Processor TDP Running Average
Bits
Description
3:0
RunAvgRange: running average range. Read-write; Same-for-all. Reset: 0. BIOS: 1h. Specifies the
interval over which the UNB averages power consumption estimates from the cores for boosting.
Time interval = 2^(RunAvgRange + 1) * FreeRunSampleTimer rate. A value of 0 disables the TDP
running average accumulator capture function. See 2.5.9 [Application Power Management (APM)]
and TdpRunAvgAccCap.
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D18F5xE8 TDP Limit 3
Bits
Description
31:29 Reserved.
28:16 ApmTdpLimit. Read-only; updated-by-hardware. Value: D18F4x250[NodeTdpLimit]. If the consumed node power exceeds the ApmTdpLimit on an single node processor or the ApmTdpLimit/2 on
a multi-node processor, a P-state limit is applied to all cores on all nodes to reduce the power consumption to remain within the TDP limit. See 2.5.9.2 [TDP Limiting] and MSRC001_0078[ApmTdpLimit]. See D18F4x16C[ApmlSwTdpLimitEn].
15:10 Tdp2Watt[5:0]. Read-only. Value: 000000b. See Tdp2Watt[15:6]. Read by ucode to produce
MSRC001_0077[Tdp2Watt[5:0]].
9:0
Tdp2Watt[15:6]. Read-only. Value: Fuse[Tdp2Watt]. Specifies in watts/TDP units the conversion
factor for converting TDP units to watts. Tdp2Watt[15:0] is a fixed point integer with 16 bits to the
right of the decimal point and 0 bits to the left of the decimal point. E.g. Tdp2Watt[15]==0.5 W;
Tdp2Watt[6]==0.976 mW; Tdp2Watt[0]==15.2 uW. Read by ucode to produce
MSRC001_0077[Tdp2Watt[15:6]].
D18F5xEC Load Step Throttle Control
Bits
Description
31:0 Reserved.
D18F5x128 Clock Power/Timing Control 3
Bits
Description
30
NbFidChgCpuOpEn. Read-write. Reset: 0b. 1=Explicitly clock gate a core prior to an NB P-state
operation.
27
SprSaveRestoreEn. Read-write. Cold Reset:0. Enables SPR save/restore for non-retention NB
power gating.
22
NbPllPwrDwnRegEn: NB PLL power down. Read-write. Cold reset: Fuse[NbPllPwrDnRegEn].
1=The NB PLL is powered down when the NB is power gated and DRAM is placed into self-refresh
(see 2.5.4.2 [NB C-states]). 0=The NB PLL is not powered down during NB C-states.
21
PC6Vid[7]. Read-write. Cold reset: Fuse[C6Vid[7]]. See PC6Vid[6:0].
15
CC6PwrDwnRegEn: CC6 power down regulator enable. Read-write. Cold reset:
Fuse[CC6PLLPwrDnRegEn]. 1=Power down the VDDA regulator on CC6 entry. If this bit is set to 1,
then CC6PwrDwnVcoEn must be 0. See PllRegTime.
14
PC6PwrDwnRegEn: PC6 power down regulator enable. Read-write. Cold reset:
Fuse[C6PLLPwrDnRegEn]. 1=Power down the VDDA regulator on PC6 entry. See PllRegTime.
Kabini PLL design always powers down regulator during PC6, irrespective of this setting.
PC6PwrDwnRegEn=0 has no effect.
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13:12 PwrGateTmr: power gate timer. Read-write. Cold reset: 01b. BIOS: Char.Temp.00b. Specifies the
minimum delay time required from the power gating or ungating of one Core to the power gating or
ungating of the same Coreor another Core.
Bits
Description
Bits
Description
00b
500 ns
10b
Reserved. (5 us)
01b
1 us
11b
Reserved. (10 us)
11:10 PllVddOutUpTime. Read-write. Reset: 0. The VDD regulator may be powered down when the processor transitions to PC6. If the regulator is powered down, this field specifies the time required to
initialize the core PLL logic once the regulator is powered back up.
Bits
Description
Bits
Description
00b
100 ns
10b
400 ns
01b
200 ns
11b
800 ns
9
FastSlamTimeDown. Read-write. Cold reset: 0. Temp.BIOS: 1. Specifies the time the processor
waits for downward voltage transitions to complete. This field only effects transitions from
D18F4x16C[CstateBoost] or lower performance P-states. 0=D18F3xD8[VSRampSlamTime] or
D18F3xD8[VSSlamTime], as specified by D18F3xD8[SlamModeSelect]. 1=10 us.
8:7
PllRegTime: Pll regulator time. Read-write. Cold reset: 10b. The VDDA regulator may be powered
down when the processor transitions to PC6 or CC6. See PC6PwrDwnRegEn and
CC6PwrDwnRegEn. If CC6PwrDwnRegEn=1, the VDDA regulator is powered down during CC6. If
PC6PwrDwnRegEn=1, the VDDA regulator is powered down during PC6. If the VDDA regulator is
powered down during CC6 and the core transitions from CC6 to PC6, the regulator remains powered
down during PC6 regardless of the PC6PwrDwnRegEn setting. This field specifies the time required
for the VDDA regulator to power back up and initialize the core PLL logic that is powered by the
VDDA regulator. The regulator does not support times less than 1.5us.
Bits
Description
Bits
Description
00b
0.5 us
10b
1.5 us
01b
1.0 us
11b
2.0 us
6:0
PC6Vid[6:0]: package C6 vid. Read-write. Cold reset: Fuse[C6Vid]. PC6Vid[7:0] = {PC6Vid[7],
PC6Vid[6:0]}. PC6Vid[7:0] specifies the VID driven in the PC6 state. See 2.5.3.2.3.4 [Package C6
(PC6) State] and 2.5.1.3.2 [Low Power Voltages].
D18F5x12C Clock Power/Timing Control 4
See the AMD Serial VID Interface 2.0 (SVI2) Specification.
Bits
31
Description
Svi2CmdBusy. Read-only, updated-by-hardware. Cold reset: 0. 1=SVI2 command in progress. This
bit is set by hardware when any SVI2 command is sent to the voltage regulator. Software must wait
for this bit to clear to 0 before writing any of the following fields: D18F5x12C[CorePsi1En, CoreLoadLineTrim, CoreOffsetTrim], D18F5x188[NbPsi1, NbLoadLineTrim, NbOffsetTrim],
D18F5x18C[CoreTfn, NbTfn]. This bit is cleared by hardware when the SVI2 command is complete.
On a voltage change, this bit is cleared when the voltage transition is completed. See 2.5.1.4.1 [Hardware-Initiated Voltage Transitions]. On a telemetry or PSIx_L change, this bit is cleared as soon as
the SVI2 command is sent to the voltage regulator. See 2.5.1.1.1 [SVI2 Features] and 2.5.1.3.1
[PSIx_L Bit].
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WaitVidCompDis: wait VID completion disable. IF (D18F2x1B4[SmuCfgLock]) THEN Readonly; updated-by-hardware. ELSE Read-write. ENDIF. Cold reset: 0. 0=Hardware waits for the
VOTF complete indicator from the voltage regulator before clearing Svi2CmdBusy or making additional voltage change requests. 1=Hardware clears Svi2CmdBusy 500us after changes to CoreLoadLineTrim, CoreOffsetTrim, or D18F5x188[NbLoadLineTrim, NbOffsetTrim] are made; hardware
clears Svi2CmdBusy and additional voltage changes are allowed after the time specified by
D18F3xD8[VSRampSlamTime] or D18F3xD8[VSSlamTime], as specified by D18F3xD8[SlamModeSelect]. See 2.5.1.4 [Voltage Transitions].
29:6 RAZ.
5
CorePsi1En: Core PSI1_L enable. If D18F2x1B4[SmuCfgLock] THEN Read-only; updated-byhardware. (SMU) ELSE Read-write. ENDIF Cold reset: 0. BIOS: IF (SVI1) THEN 0 ELSE 1 ENDIF.
0=PSI1_L for VDD is deasserted. 1=PSI1_L for VDD is asserted when all cores are in CC6. See
2.5.3.2.3.4 [Package C6 (PC6) State], 2.5.1.3.1 [PSIx_L Bit], and Svi2CmdBusy.
4:2
CoreLoadLineTrim: Core load line trim. IF (D18F2x1B4[SmuCfgLock]) THEN Read-only;
updated-by-hardware. ELSE Read-write. ENDIF. Cold reset: 011b. CoreLoadLineTrim and NbLoadLineTrim specify a percentage change relative to the initial load line slope for VDD and VDDNB,
respectively. See Svi2CmdBusy.
Bits
Description
Bits
Description
000b Load line disabled
100b +20%
001b -40%
101b +40%
010b -20%
110b +60%
011b 0%
111b +80%
1:0
CoreOffsetTrim: Core offset trim. IF (D18F2x1B4[SmuCfgLock]) THEN Read-only; updated-byhardware. ELSE Read-write. ENDIF. Cold reset: 10b. CoreOffsetTrim and NbOffsetTrim specify a
voltage offset relative to the initial load line offset for VDD and VDDNB, respectively. See
Svi2CmdBusy.
Bits
Description
Bits
Description
00b
Load line offset disabled
10b
0mV
01b
-25mV
11b
+25mV
D18F5x16[C:0] Northbridge P-state [3:0]
Each of these registers specify the frequency and voltage associated with each of the NB P-states.
Table 176: Register Mapping for D18F5x16[C:0]
Register
D18F5x160
D18F5x164
D18F5x168
D18F5x16C
Function
NB P-state 0
NB P-state 1
NB P-state 2
NB P-state 3
The NbVid field is allowed to be different between processors in a multi-processor system. All other fields are
required to be programmed to the same value for all processors in the coherent fabric. See 2.5.4.1 [NB P-states]
for more information about these registers.
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Table 177: NB P-state Definitions
Term
NBCOF
Definition
NB current operating frequency in MHz. NBCOF = 100 *
(D18F5x16[C:0][NbFid] + 4h) / (2^D18F5x16[C:0][NbDid]).
NBCOF[0]
NB current operating frequency in MHz for NB P-state 0.
NBCOF[0] = (100 * (D18F5x160[NbFid] + 4h) / (2^D18F5x160[NbDid])).
NBCOF[1]
NB current operating frequency in MHz for NB P-state 1.
NBCOF[1] = (100 * (D18F5x164[NbFid] + 4h) / (2^D18F5x164[NbDid])).
NBCOF[2]
NB current operating frequency in MHz for NB P-state 2.
NBCOF[2] = (100 * (D18F5x168[NbFid] + 4h) / (2^D18F5x168[NbDid])).
NBCOF[3]
NB current operating frequency in MHz for NB P-state 3.
NBCOF[3] = (100 * (D18F5x16C[NbFid] + 4h) / (2^D18F5x16C[NbDid])).
Bits
Description
31:24 NbIddValue: northbridge current value. Read-write. Cold reset: Fuse[NbIddValue[3:0][1:0]]. See
NbIddDiv.
23:22 NbIddDiv: northbridge current divisor. Read-write. Cold reset: Fuse[NbIddDiv[3:0][1:0]]. After
reset, NbIddDiv and NbIddValue combine to specify the expected maximum current drawn on the
VDDNB power plane at a given VDDNB voltage. These values are intended to be used by 2.5.1.3.1.1
[BIOS Requirements for PSI0_L]. These values are not intended to convey final product power levels
and may not match the power levels specified in the Power and Thermal Datasheet. These fields may
be subsequently altered by software; they do not affect the hardware behavior.
Bits
Description
00b
IddValue / 1 A, Range: 0 to 255 A.
01b
IddValue / 10 A, Range: 0 to 25.5 A.
10b
IddValue / 100 A, Range: 0 to 2.55 A.
11b
Reserved.
21
NbVid[7]. Read-write. Cold reset: Fuse[NbVid[3:0][7]]. See NbVid[6:0].
20
Reserved.
19
Reserved. Reserved for expansion of MemPstate.
18
MemPstate: Memory P-state. Read-write. Cold reset: Fuse[MemPstate[3:0]]. 1=The Northbridge Pstate specified by this register maps to memory P-state 1. 0=The Northbridge P-state specified by this
register maps to memory P-state 0. Memory P-states may be globally disabled by programming
D18F5x170[MemPstateDis]. See 2.5.7.1 [Memory P-states].
17
Reserved.
16:10 NbVid[6:0]: Northbridge VID. Read-write. Cold reset: Fuse[NbVid[3:0][6:0]]. NbVid[7:0] =
{NbVid[7], NbVid[6:0]}. NbVid[7:0] specifies the Northbridge voltage.
9:8
7
Reserved.
NbDid: Northbridge divisor ID. Read-write. Cold reset: Fuse[NbDid[3:0]]. Specifies the Northbridge frequency divisor; see NbFid.
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6:1
NbFid[5]: Northbridge frequency ID. Read-write. Cold reset: Fuse[NbFid[3:0][5:0]]. Specifies the
Northbridge frequency multiplier. The NB COF is a function of NbFid and NbDid, and defined by
NBCOF. NbFid and NbDid are not changed on a write if the value written results in a frequency
greater than MSRC001_0071[MaxNbCof]. See 2.5.3.1.5 [Core P-state Transition Behavior].
0
NbPstateEn: Northbridge P-state enable. Read-write. Cold reset: Fuse[NbPstateEn[3:0]]. 1=The
Northbridge P-state specified by this register is valid. 0=The Northbridge P-state specified by this
register is not valid. This bit must be set to 1 in order for the Northbridge P-state specified by this register to be programmed in D18F5x170[NbPstateHi, NbPstateLo]. This bit controls hardware and is
used to qualify the values written in D18F5x170[NbPstateHi, NbPstateLo].
D18F5x170 Northbridge P-state Control
See also 2.5.4.1 [NB P-states].
Bits
Description
31
MemPstateDis: memory P-state disable. IF (D18F3xE8[MemPstateCap] && D18F2x1B4[SmuCfgLock]==0) THEN Read-write, updated-by-hardware; Updated-by-SMU. ELSE Read-only, updatedby-hardware; Updated-by-SMU. Reset: Fuse[MemPstateDis]. 1=Memory P-state transitions are disabled. The current P-state is not changed by programming this bit. The memory P-state will be forced
to M0 on the next NB P-state transition. On processors where memory P-states are enabled, programming this bit may result in a violation of bandwidth requirements stated in 2.5.3.1.5 (M0.MemClkFreq>NBCOF). Software must ensure that NB P-states which violate those requirements are forced
disabled. 0=Memory P-state transitions are enabled if D18F2x90_dct[0][DisDllShutdownSR]=0.
30
NbPstateFidVidSbcEn. IF (D18F5x174[NbPstateDis] || D18F2x1B4[SmuCfgLock]) THEN Readonly. ELSE Read: Write-1-only. ENDIF. Reset: 0. BIOS: 1. NB P-state transitions are blocked until
this field is set to a 1. This field should only be set when all APs are launched.
29:27 NbPstateHiRes: NB P-state high residency timer. If D18F2x1B4[SmuCfgLock] THEN Read-only;
updated-by-hardware. (SMU) ELSE Read-write. ENDIF Reset: 0. Specifies the minimum time the
processor must spend in the high NB P-state before transitions to the low NB P-state are allowed. See
2.5.4.1 [NB P-states].
Bits
Description
Bits
Description
000b
0us
100b
1ms
001b
10us
101b
5ms
010b
100us
110b
10ms
011b
500us
111b
50ms
26:24 NbPstateLoRes: NB P-state low residency timer. If D18F2x1B4[SmuCfgLock] THEN Read-only;
updated-by-hardware. (SMU) ELSE Read-write. ENDIF Reset: 0. Specifies the minimum time the
processor must spend in the low NB P-state before transitions to the high NB P-state are allowed. See
2.5.4.1 [NB P-states]. See: NbPstateHiRes.
23
NbPstateGnbSlowDis. If D18F2x1B4[SmuCfgLock] THEN Read-only; updated-by-hardware.
(SMU) ELSE Read-write. ENDIF Reset: 0. Specifies whether NBP-state transitions take the GnbSlow signal into account. 0=Take GnbSlow into account. 1=Ignore GnbSlow. See 2.5.4.1 [NB Pstates].
14
SwNbPstateLoDis: software NB P-state low disable. IF (D18F5x174[NbPstateDis] |
D18F2x1B4[SmuCfgLock]) THEN Read-only. ELSE Read-write. ENDIF. Reset: 0. 1=Transition to
NbPstateHi and disable transitions to NbPstateLo.
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NbPstateDisOnP0: NB P-state disable on P0. IF (D18F5x174[NbPstateDis] | D18F2x1B4[SmuCfgLock]) THEN Read-only. ELSE Read-write. ENDIF. Reset: 0. 1=Transition to NbPstateHi and disable transitions to NbPstateLo if any compute unit is in P0 or a boosted P-state. This field uses
software P-state numbering. See 2.5.3.1.1.1 [Software P-state Numbering].
12:9 NbPstateThreshold: NB P-state threshold. If D18F2x1B4[SmuCfgLock] THEN Read-only;
updated-by-hardware. (SMU) ELSE Read-write. ENDIF Reset: COUNT(D18F5x80[Enabled]).
Char.Temp.BIOS: COUNT(D18F5x80[Enabled]) . Specifies the minimum number of compute units
that must be in a P-state with MSRC001_00[6B:64][NbPstate]=1 before transitions to lower performance NB P-states are allowed. See NbPstateLo and NbPstateHi.
8
7:6
5
4:3
2
1:0
Reserved. Reserved for future expansion of NbPstateHi.
NbPstateHi: NB P-state high. IF (D18F2x1B4[SmuCfgLock]) THEN Read-only; updated-by-hardware. ELSE Read-write. ENDIF. Cold reset: Fuse[NbPstateHi]. If NB P-states are enabled, this field
specifies the NB P-state that is used when the number of compute units in a P-state with
MSRC001_00[6B:64][NbPstate]=1 is less than NbPstateThreshold. This field must be programmed
to the same value for all processors in the coherent fabric. This field is not changed on a write if the
value written is greater than the NbPstateMaxVal value written or greater than the current NbPstateLo
value. See also NbPstateDisOnP0, SwNbPstateLoDis, NbPstateLo, D18F5x174[NbPstateDis], and
D18F5x16[C:0][NbPstateEn].
Reserved.
NbPstateLo: NB P-state low. IF (D18F2x1B4[SmuCfgLock]) THEN Read-only; updated-by-hardware. ELSE Read-write. ENDIF. Cold reset: Fuse[NbPstateLo]. If NB P-states are enabled, this field
specifies the NB P-state that is used when the number of compute units in a P-state with
MSRC001_00[6B:64][NbPstate]=1 is greater than or equal to NbPstateThreshold. NbPstateLo must
be greater than or equal to NbPstateHi. This field must be programmed to the same value for all processors in the coherent fabric. This field is not changed on a write if the value written is greater than
the NbPstateMaxVal value written or less than the current NbPstateHi value. See also
NbPstateDisOnP0, SwNbPstateLoDis, D18F5x174[NbPstateDis], and D18F5x16[C:0][NbPstateEn].
Reserved.
NbPstateMaxVal: NB P-state maximum value. IF (D18F2x1B4[SmuCfgLock]) THEN Read-only;
updated-by-hardware. ELSE Read-write. ENDIF. Cold reset: specified by the reset state of
D18F5x16[C:0][NbPstateEn]; the cold reset value is the highest NB P-state number corresponding to
the register in which NbPstateEn is set (e.g., if D18F5x160 and D18F5x164 have this bit set and the
others do not, then NbPstateMaxVal=1; if NbPstateEn is only set in D18F5x160, then NbPstateMaxVal=0). This specifies the highest NB P-state value (lowest performance state) supported by the hardware.
D18F5x174 Northbridge P-state Status
Bits
Description
24
CurMemPstate: current memory P-state. Read-only; updated-by-hardware. Reset: 0. Specifies the
current memory P-state. 1=Memory P-state 1. 0=Memory P-state 0. See 2.5.7.1 [Memory P-states].
23
CurNbVid[7]: current northbridge voltage ID[7]. MSRC001_0071[CurNbVid[7]] is an alias of
D18F5x174[CurNbVid[7]]. . VDDNB voltage.
22
CurNbPstateLo. Read-only; updated-by-hardware. Reset: 0. 1=Current NB Pstate maps to
D18F5x170[NbPstateLo]. 0=Current NB Pstate maps to D18F5x170[NbPstateHi].
21
Reserved.
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20:19 CurNbPstate: current northbridge P-state. Read-only; updated-by-hardware. Reset: 0. Provides
the NB P-state that corresponds to the current frequency component of the NB. The value of this field
is updated when the COF transitions to a new value associated with an NB P-state.
Description
Bits
00b
NB P0
01b
NB P1
10b
NB P2
11b
NB P3
18:12 CurNbVid[6:0]: current northbridge voltage ID. MSRC001_0071[CurNbVid[6:0]] is an alias of
D18F5x174[CurNbVid[6:0]]. VDDNB voltage.
11
Reserved.
10
Reserved.
9
CurNbDid: current northbridge divisor ID. Read-only, updated-by-hardware. Reset: 0.
8:3
CurNbFid[5:0]: current northbridge frequency ID. Read-only, updated-by-hardware. Reset: 0.
2:1
StartupNbPstate: startup northbridge P-state number. Read-only. Cold reset: Fuse[StartupNbPstate]. Specifies the cold reset VID, FID and DID for the Northbridge based on the NB P-state number
selected. If D18F3xA0[CofVidProg]=0, then the state of this field is ignored and the VID, FID and
DID are applied to the NB as specified by that bit. Hardware verifies that D18F5x16[C:0][NbVid,
NbFid, NbDid] for the NB P-state pointed to by StartupNbPstate are programmed as specified by
MSRC001_0071[MaxNbCof]. Hardware does not verify that NbPstateEn is set.
0
NbPstateDis: northbridge P-state disable. Read-only. Value: Fuse[NbPstateDis].
MSRC001_0071[NbPstateDis] is an alias of D18F5x174[NbPstateDis].
D18F5x178 Northbridge Fusion Configuration
Bits
Description
19
SwGfxDis. Read-write. Reset: 1. BIOS: IF (GpuEnabled) THEN 0 ELSE 1 ENDIF. 1=Hardware
handshakes for NB P-state transitions and DRAM self-refresh entry are ignored. See 2.5.4.1.1 [NB Pstate Transitions]. See 2.5.7.2 [DRAM Self-Refresh]. Causes UNB to ignore AllowSelfRefresh,
AllowNbTrans, ForceNbPs1, GnbSlow, and garlic flush.
18
CstateFusionHsDis: C-state fusion handshake disable. Read-write. Reset: 0. BIOS:1. 1=Ignore the
FCH handshake response for PC6 transitions. 0=Use the FCH handshake response for PC6 entry. See
2.5.3.2.4.1 [FCH Messaging].
17
Dis2ndGnbAllowPsWait. Read-write. Reset: 0. BIOS: 1. 1=Do not do a second check of AllowNbTrans after quiescing the cores when transitioning NB P-states. See 2.5.4.1.1 [NB P-state Transitions].
16
ProcHotToGnbEn. Read-write. Reset: 0. BIOS: 1. Specifies whether PROCHOT_L is distributed to
GNB. See Figure 44.
11
AllowSelfRefrS3Dis: allow self-refresh S3 disable. Read-write. Reset: 0. BIOS: 1. 1=The NB does
not wait for AllowSelfRefresh assertion before placing DRAM into self-refresh (see 2.5.7.2 [DRAM
Self-Refresh]) on S3 entry (see 2.5.8.1.1 [ACPI Suspend to RAM State (S3)]). 0=The NB waits for
AllowSelfRefresh assertion before placing DRAM into self-refresh on S3 entry.
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10
InbWakeS3Dis: InbWake S3 disable. Read-write. Reset: 0. BIOS: 1. 1= The NB does not wait for
InbWake de-assertion before placing DRAM into self-refresh (see 2.5.7.2 [DRAM Self-Refresh]) on
S3 entry (see 2.5.8.1.1 [ACPI Suspend to RAM State (S3)]). 0=The NB waits for InbWake de-assertion before placing DRAM into self-refresh on S3 entry.
3
CstateThreeWayHsEn: C-state three way handshake disable. Read-write. Reset: 0. 1=Enable the
three way handshake with the FCH when entering a C-state. 0=Only a two way handshake with FCH
is used. There is no message about the resulting package state sent to FCH. See 2.5.3.2.4.1 [FCH
Messaging].
2
CstateFusionDis: C-state fusion disable. Read-write. Reset: 0. 1=All HALT or C-state requests are
forwarded to the FCH. 0=HALT and C-state requests are forwarded to the FCH when each core has
made a request. See 2.5.3.2.4.1 [FCH Messaging].
D18F5x17C Miscellaneous Voltages
Bits
31
Description
NbPsi0VidEn: Northbridge PSI0_L VID enable. Read-write. Reset: 0. This bit specifies how
PSI0_L is controlled for VDDNB. See D18F3xA0[PsiVidEn] and 2.5.1.3.1 [PSIx_L Bit].
30:23 NbPsi0Vid[7:0]: Northbridge PSI0_L VID threshold. Read-write. Reset: 0. When enabled by
NbPsi0VidEn, NbPsi0Vid specifies the threshold value of the VID code generated by the Northbridge, which in turn determines the state of PSI0_L. See D18F3xA0[PsiVid[6:0]] and 2.5.1.3.1
[PSIx_L Bit].
22:18 Reserved.
17:10 MinVid: minimum voltage. Read-only. Reset: Fuse[MinVid]. Specifies the VID code corresponding
to the minimum voltage (highest VID code) that the processor drives. 00h indicates that no minimum
VID code is specified. See 2.5.1 [Processor Power Planes And Voltage Control].
9:8
Reserved.
7:0
MaxVid: maximum voltage. Read-only. Reset: Fuse[MaxVid]. Specifies the VID code
corresponding to the maximum voltage (lowest VID code) that the processor drives. 00h indicates
that no maximum VID code is specified. See 2.5.1 [Processor Power Planes And Voltage Control].
D18F5x188 Clock Power/Timing Control 5
See the AMD Serial VID Interface 2.0 (SVI2) Specification.
Bits
Description
31:6 RAZ.
5
NbPsi1: Northbridge PSI1_L. IF D18F2x1B4[SmuCfgLock] THEN Read-only; updated-by-hardware. (SMU) ELSE Read-write. ENDIF Cold reset: 0. Specifies how PSI1_L is controlled for
VDDNB. 1=PSI1_L is low. 0=PSI1_L is high. See 2.5.1.3.1 [PSIx_L Bit].
4:2
NbLoadLineTrim: Northbridge load line trim. IF D18F2x1B4[SmuCfgLock] THEN Read-only;
updated-by-hardware. (SMU) ELSE Read-write. ENDIF Cold reset: 011b. See D18F5x12C[CoreLoadLineTrim].
1:0
NbOffsetTrim: Northbridge offset trim. IF D18F2x1B4[SmuCfgLock] THEN Read-only; updatedby-hardware. ELSE Read-write. ENDIF. Cold reset: 10b. See D18F5x12C[CoreOffsetTrim].
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D18F5x18C Clock Power/Timing Control 6
See the AMD Serial VID Interface 2.0 (SVI2) Specification.
Bits
Description
31:2 RAZ. Reserved for expansion of Clock Power/Timing Control.
1
CoreTfn: Core telemetry functionality. If D18F2x1B4[SmuCfgLock] THEN Read-only; updatedby-hardware. (SMU) ELSE Read-write. ENDIF Cold reset: 0. See NbTfn.
0
NbTfn: Northbridge telemetry functionality. If D18F2x1B4[SmuCfgLock] THEN Read-only;
updated-by-hardware. (SMU) ELSE Read-write. ENDIF. Cold reset: 0. See
D18F5x12C[Svi2CmdBusy]. CoreTfn and NbTfn specify the telemetry mode as follows:
CoreTfn
NbTfn
Description
0
0
Telemetry enabled in voltage-only mode.
0
1
Telemetry enabled in voltage and current mode.
1
0
Telemetry disabled.
1
1
Reserved.
D18F5x194 Name String Address Port
D18F5x194 and D18F5x198 provide BIOS with a read-only (Fused) name string that may be copied to
MSRC001_00[35:30] at warm reset. Each of D18F5x198_x[B:0] is read as follows:
1. Write D18F5x194[Index].
2. Read D18F5x198.
Bits
Description
31:4 Reserved.
3:0
Index: name string register index. Read-write. Reset: 0.
Bits
Description
Bh-0h
Name String Registers. See D18F5x198_x[B:0].
Fh-Ch
Reserved
D18F5x198 Name String Data Port
See D18F5x194 for register access information. Address: D18F5x194[Index].
Bits
Description
31:0 Data.
D18F5x198_x[B:0] Name String Data
Bits
Description
31:24 NameStringByte3: name string ASCII character 3. Read-only. Value: Table 1188.
23:16 NameStringByte2: name string ASCII character 2. Read-only. Value: Table 1188.
15:8 NameStringByte1: name string ASCII character 1. Read-only. Value: Table 1188.
7:0
NameStringByte0: name string ASCII character 0. Read-only. Value: Table 1188.
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D18F5x240 ECC Exclusion Base Address Low
• Transaction addresses are within the defined range if:
{EccExclBaseAddr[47:6], 00_0000b} <= address[47:0] <= {EccExclLimitAddr[47:6], 00_0000b}.
• BIOS must quiesce all other forms of DRAM traffic when configuring this range. See MSRC001_001F[DisDramScrub].
• When initializing the base/limit pair, the BIOS must write the limit register before the EccExclEn bit is set.
BIOS should clear EccExclEn before changing the address range.
• BIOS should take care to re-initialize memory with valid ECC when resizing this region.
Bits
Description
31:6 EccExclBaseAddr[31:6]: ECC exclusion base address register bits[31:6]. Read-write. Reset: 0.
EccExclBaseAddr[47:6]={D18F5x244[EccExclBaseAddr[47:32]], EccExclBaseAddr[31:6]}. The
ECC Exclusion Base/Limit Address registers setup a contiguous range in DRAM where ECC check
and error reporting is disabled. BIOS configures the ECC exclusion range code to cover the frame
buffer region in ECC UMA systems with internal GPUs. The GPU is configured as
MC_SHARED:MC_VM_STEERING [DEFAULT_STEERING]=1 (system traffic to onion).
5:1
0
Reserved.
EccExclEn. Read-write. Reset: 0. 1=Enable ECC Exclusion Range. See D18F5x240[EccExclBaseAddr].
D18F5x244 ECC Exclusion Base Address High
Bits
Description
31:16 Reserved.
15:0 EccExclBaseAddr[47:32]: ECC exclusion base address register bits[47:32]. Read-write. Reset: 0.
See D18F5x240[EccExclBaseAddr].
D18F5x248 ECC Exclusion Limit Address Low
Bits
Description
31:6 EccExclLimitAddr[31:6]: ECC exclusion limit address register bits[31:6]. Read-write. Reset: 0.
EccExclLimitAddr[47:6]={D18F5x24C[EccExclLimitAddr[47:32]], EccExclLimitAddr[31:6]}. See
D18F5x240[EccExclBaseAddr].
5:0
Reserved.
D18F5x24C ECC Exclusion Limit Address High
Bits
Description
31:16 Reserved.
15:0 EccExclLimitAddr[47:32]: ECC exclusion limit address register bits[47:32]. Read-write. Reset:
0. See D18F5x240[EccExclBaseAddr].
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D18F5x260 Clock Power/Timing Control 8
Bits
Description
31:4 Reserved.
3:0
Reserved.
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3.15 GPU Memory Mapped Registers
3.16 Northbridge IOAPIC Registers
The Northbridge IOAPIC is accessed through the Northbridge IOAPIC base address specified by
D0F0xFC_x01 [IOAPIC Base Address Lower] and D0F0xFC_x02 [IOAPIC Base Address Upper].
NBIOAPICx00 IO Register Select
Bits
Description
31:8 Reserved.
7:0
IndirectAddressOffset. Read-write. Reset: 0. Specifies the indexed register accessed via
NBIOAPICx10 [IO Window].
NBIOAPICx10 IO Window
Bits
Description
31:0 IoapicData.
NBIOAPICx10_x00 IOAPIC ID
This register is not used in IOxAPIC PCI bus delivery mode.
Bits
Description
31:28 ExtendID: extended IOAPIC device ID. IF (D0F0xFC_x00[IoapicIdExtEn]==0) THEN Read-only.
ELSE Read-write. ENDIF. Reset: 0.
27:24 ID: IOAPIC device ID. Read-write. Reset: 0.
23:0 Reserved.
NBIOAPICx10_x01 IOAPIC Version
Bits
Description
31:24 Reserved.
23:16 MaxRedirectionEntries. Value: 1Fh. Indicates 32 entries [31:0].
15
PRQ. Value: 1. IRQ pin assertion supported
14:8 Reserved.
7:0
Version. Value: 21h. PCI 2.2 compliant
NBIOAPICx10_x02 IOAPIC Arbitration
Bits
Description
31:28 Reserved.
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27:24 ArbitrationID. Read-only. Reset: 0.
23:0 Reserved.
NBIOAPICx10_x[4E:10:step2] Redirection Table Entry [31:0]
Bits
Description
63:56 DestinationID. Read-write. Reset: 0. Bits [19:12] of the address field of the interrupt message.
55:32 Reserved.
31:17 Reserved.
16
Mask. Read-write. Reset: 1. 1=Mask the interrupt injection at the input of this device. 0=Unmask.
15
TriggerMode. Read-write. Reset: 0. 0=Edge. 1=Level
14
RemoteIRR. Read-only. Reset: 0. Used for level triggered interrupts only. It is cleared by EOI special
cycle transaction or write to EOI register. 1=Interrupt message is delivered.
13
InterruptPinPolarity. Read-write. Reset: 0. 0=High. 1=Low.
12
DeliveryStatus. Read-only. Reset: 0. 0=Idle. 1=Send Pending.
11
DestinationMode. Read-write. Reset: 0. 0=Physical. 1=Logical
10:8 DeliveryMode. Read-write. Reset: 0.
Bits
Definition
000b
Fixed
001b
Lowest Priority
010b
SMI/PMI
011b
Reserved
7:0
Bits
100b
101b
110b
111b
Definition
NMI
INIT
Reserved
ExtINT
Vector. Read-write. Reset: 0. Interrupt vector associated with this interrupt input
NBIOAPICx20 IRQ Pin Assertion
Bits
Description
31:8 Reserved.
7:0
InputIrq. Read-write. Reset: 0. IRQ number for the requested interrupt. A write to this register will
trigger an interrupt associated with the redirection table entry referenced by the IRQ number. Currently the redirection table has 24 entries. Writes with IRQ number greater than 17h have no effect.
NBIOAPICx40 EOI
Bits
Description
31:8 Reserved.
7:0
Vector. Write-only. Reset: 0. Interrupt vector. A write to this register will clear the remote IRR bit in
the redirection table entry found matching the interrupt vector. This provides an alternate mechanism
other than PCI special cycle for EOI to reach IOxAPIC.
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3.17 APIC Registers
See 2.4.8.1.2 [APIC Register Space].
MMIO local APIC space is accessible in xAPIC mode.
APIC20 APIC ID
Bits
Description
31:24 ApicId: APIC ID. Read-write.
Reset: Varies based on core number.
• The initial value of APIC20[ApicId[7:0]] is {0000b, CpuCoreNum[3:0]}.
See 2.4.8.1.3 [ApicId Enumeration Requirements]. See 2.4.4 [Processor Cores and Downcoring].
Intel defines as Read-only on some processors.
23:0 Reserved.
APIC30 APIC Version
Bits
31
Description
ExtApicSpace: extended APIC register space present. Read-only. Reset: 1. 1=Indicates the
presence of extended APIC register space starting at APIC400. Reserved on Intel processors.
30:25 RAZ.
24
DirectedEoiSupport: directed EOI support. Read-only. Reset: 0. 0=Directed EOI capability not
supported.
23:16 MaxLvtEntry. Read-only. Reset: IF (Fuse[HtcDis] | MSRC001_001F[DisApicThermLVT]) THEN
04h ELSE 05h ENDIF. Specifies the number of entries in the local vector table minus one.
15:8 RAZ.
7:0
Version. Read-only. Reset: 10h. Indicates the version number of this APIC implementation.
APIC80 Task Priority (TPR)
Bits
Description
31:8 RAZ.
7:0
Priority. Read-write. Reset: 0. This field is assigned by software to set a threshold priority at which
the core is interrupted.
APIC90 Arbitration Priority (APR)
Bits
Description
31:8 RAZ.
7:0
Priority. Read-only. Reset: 0. Indicates the current priority for a pending interrupt, or a task or interrupt being serviced by the core. The priority is used to arbitrate between cores to determine which
accepts a lowest-priority interrupt request.
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APICA0 Processor Priority (PPR)
Bits
Description
31:8 RAZ.
7:0
Priority. Reset: 0. Read-only. Indicates the core’s current priority servicing a task or interrupt, and is
used to determine if any pending interrupts should be serviced. It is the higher value of the task priority value and the current highest in-service interrupt.
APICB0 End of Interrupt
This register is written by the software interrupt handler to indicate the servicing of the current interrupt is
complete.
Bits
Description
31:0 Unused. Write-only.
APICC0 Remote Read
Bits
Description
31:0 RemoteReadData. Read-only. Reset: 0. The data resulting from a valid completion of a remote read
inter-processor interrupt.
APICD0 Logical Destination (LDR)
Bits
Description
31:24 Destination. Read-write. Reset: 0. This APIC’s destination identification. Used to determine which
interrupts should be accepted.
23:0 Reserved.
APICE0 Destination Format
Only supported in xAPIC mode.
Bits
Description
31:28 Format. Read-write. Reset: Fh. Controls which format to use when accepting interrupts with a logical
destination mode.
Bits
Definition
0h
Cluster destinations are used
Eh-1h
Reserved
Fh
Flat destinations are used
27:0 Reserved. Reset: FFF_FFFFh.
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APICF0 Spurious-Interrupt Vector (SVR)
Bits
Description
31:13 RAZ.
12
EoiBroadcastDisable: EOI broadcast disable. Read-only. Reset: 0. AMD-specific: Added by Intel
with x2APIC, not added by AMD.
11:10 RAZ.
9
FocusDisable. Read-write. Reset: 0. 1=Disable focus core checking during lowest-priority arbitrated
interrupts. AMD-specific: Deprecated by Intel with x2APIC, not deprecated by AMD.
8
APICSWEn: APIC software enable. Read-write. Reset: 0. 0=SMI, NMI, INIT, LINT[1:0], and
Startup interrupts may be accepted; pending interrupts in APIC[170:100] and APIC[270:200] are
held, but further fixed, lowest-priority, and ExtInt interrupts are not accepted. All LVT entry mask bits
are set and cannot be cleared.
See MSRC001_001F[DisApicSwEnFix].
7:0
Vector. Read-write. Reset: FFh. The vector that is sent to the core in the event of a spurious interrupt.
The behavior of bits 3:0 are controlled as specified by D18F0x68[ApicExtSpur].
APIC[170:100] In-Service (ISR)
The in-service registers provide a bit per interrupt to indicate that the corresponding interrupt is being serviced
by the core. APIC100[15:0] are reserved. Interrupts are mapped as follows:
Table 178: Register Mapping for APIC[170:100]
Register
APIC100
APIC110
APIC120
APIC130
APIC140
APIC150
APIC160
APIC170
Bits
Function
Interrupts [31:16]
Interrupts [63:32]
Interrupts [95:64]
Interrupts [127:96]
Interrupts [159:128]
Interrupts [191:160]
Interrupts [223:192]
Interrupts [255:224]
Description
31:0 InServiceBits. Reset: 0. Read-only. These bits are set when the corresponding interrupt is being serviced by the core.
APIC[1F0:180] Trigger Mode (TMR)
The trigger mode registers provide a bit per interrupt to indicate the assertion mode of each interrupt.
APIC180[15:0] are reserved. Interrupts are mapped as follows:
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Table 179: Register Mapping for APIC[1F0:180]
Register
APIC180
APIC190
APIC1A0
APIC1B0
APIC1C0
APIC1D0
APIC1E0
APIC1F0
Bits
Function
Interrupts [31:16]
Interrupts [63:32]
Interrupts [95:64]
Interrupts [127:96]
Interrupts [159:128]
Interrupts [191:160]
Interrupts [223:192]
Interrupts [255:224]
Description
31:0 TriggerModeBits. Reset: 0. Read-only. The corresponding trigger mode bit is updated when an interrupt is accepted. The values are: 0=Edge-triggered interrupt. 1=Level-triggered interrupt.
APIC[270:200] Interrupt Request (IRR)
The interrupt request registers provide a bit per interrupt to indicate that the corresponding interrupt has been
accepted by the APIC. APIC200[15:0] are reserved. Interrupts are mapped as follows:
Table 180: Register Mapping for APIC[270:200]
Register
APIC200
APIC210
APIC220
APIC230
APIC240
APIC250
APIC260
APIC270
Bits
Function
Interrupts [31:16]
Interrupts [63:32]
Interrupts [95:64]
Interrupts [127:96]
Interrupts [159:128]
Interrupts [191:160]
Interrupts [223:192]
Interrupts [255:224]
Description
31:0 RequestBits. Read-only. Reset: 0. The corresponding request bit is set when the an interrupt is
accepted by the APIC.
APIC280 Error Status
Writes to this register trigger an update of the register state. The value written by software is arbitrary. Each
write causes the internal error state to be loaded into this register, clearing the internal error state. Consequently, a second write prior to the occurrence of another error causes the register to be overwritten with
cleared data.
Bits
Description
31:8 RAZ.
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7
IllegalRegAddr: illegal register address. Read-write. Reset: 0. This bit indicates that an access to a
nonexistent register location within this APIC was attempted. Can only be set in xAPIC mode. Illegal
register accesses in x2APIC mode cause #GP fault.
6
RcvdIllegalVector: received illegal vector. Read-write. Reset: 0. This bit indicates that this APIC
has received a message with an illegal vector (00h to 0Fh for fixed and lowest priority interrupts).
5
SentIllegalVector. Read-write. Reset: 0. This bit indicates that this APIC attempted to send a message with an illegal vector (00h to 0Fh for fixed and lowest priority interrupts).
4
RAZ. Intel defined as Redirectable IPI. Intel dropped redirectable IPI with the addition of x2APIC.
Redirectable not deprecated by AMD.
3
RcvAcceptError: receive accept error. Read-write. Reset: 0. This bit indicates that a message
received by this APIC was not accepted by this or any other APIC. AMD-specific: Deprecated by
Intel with x2APIC, not deprecated by AMD.
2
SendAcceptError. Read-write. Reset: 0. This bit indicates that a message sent by this APIC was not
accepted by any APIC. AMD-specific: Deprecated by Intel with x2APIC, not deprecated by AMD.
1:0
RAZ. [1]: Previously defined as Receive Checksum Error. Only used by 3-wire interface. [0]: Previously defined as Send Checksum Error. Only used by 3-wire interface.
APIC300 Interrupt Command Low (ICR Low)
Not all combinations of ICR fields are valid. Only the following combinations are valid:
Table 181: ICR valid combinations
Message Type
Trigger Mode
Level
Destination Shorthand
Edge
x
x
Level
Assert
x
Edge
x
Lowest Priority, SMI,
NMI, INIT
Destination or all excluding self.
Level
Assert
Destination or all excluding self
Startup
x
x
Destination or all excluding self
Fixed
Note: x indicates a don’t care.
Bits
Description
31:20 RAZ.
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19:18 DestShrthnd: destination shorthand. Read-write. Reset: 0. Provides a quick way to specify a destination for a message.
Bits
Description
00b
No shorthand (Destination field)
01b
Self
10b
All including self
11b
All excluding self (This sends a message with a destination encoding of all 1s,
so if lowest priority is used the message could end up being reflected back to
this APIC.)
If all including self or all excluding self is used, then destination mode is ignored and physical is automatically used.
17:16 RemoteRdStat: remote read status. Read-only. Reset: 0. Deprecated by Intel.
Bits
Description
00b
Read was invalid
01b
Delivery pending
10b
Delivery complete and access was valid
11b
Reserved
15
TM: trigger mode. Read-write. Reset: 0. Indicates how this interrupt is triggered. 0=Edge triggered.
1=Level triggered.
14
Level. Read-write. Reset: 0. 0=Deasserted. 1=Asserted.
13
RAZ.
12
DS: interrupt delivery status. Read-only. Reset: 0. In xAPIC mode this bit is set to indicate that the
interrupt has not yet been accepted by the destination core(s). 0=Idle. 1=Send pending. Reserved in
x2APIC mode. Software may repeatedly write ICRL without polling the DS bit; all requested IPIs
will be delivered.
11
DM: destination mode. Read-write. Reset: 0. 0=Physical. 1=Logical.
10:8 MsgType. Read-write. Reset: 0. The message types are encoded as follows:
Bits
Description
000b
Fixed
001b
Lowest Priority. Deprecated by Intel with x2APIC.
010b
SMI
011b
Remote read. Deprecated by Intel with x2APIC.
100b
NMI
101b
INIT
110b
Startup
111b
External interrupt. Deprecated by Intel with x2APIC.
7:0
Vector. Read-write. Reset: 0. The vector that is sent for this interrupt source.
APIC310 Interrupt Command High (ICR High)
Bits
Description
31:24 DestinationField. Read-write. Reset: 0. The destination encoding used when APIC300[DestShrthnd]
is 00b.
23:0 RAZ.
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APIC320 LVT Timer
Bits
Description
31:18 RAZ.
17
Mode. Read-write. Reset: 0. 0=One-shot. 1=Periodic.
16
Mask. Read-write. Reset: 1. 0=Not masked. 1=Masked.
15:13 RAZ.
12
DS: interrupt delivery status. Read-only; updated-by-hardware. Reset: 0. 0=Idle. 1=Send pending.
(Indicates that the interrupt has not yet been accepted by the core.)
11
RAZ.
10:8 MsgType: message type. Read-write. Reset: 000b. See 2.4.8.1.14 [Generalized Local Vector Table].
7:0
Vector. Read-write. Reset: 00h. Interrupt vector number.
APIC330 LVT Thermal Sensor
Interrupts for this local vector table are caused by changes in MSRC001_0061[CurPstateLimit] due to SB-RMI
or HTC. This register is accessible if ((MSRC001_001F[DisApicThermLVT]==0) && (FUSE[HtcDis]==0)).
Bits
Description
31:17 RAZ.
16
Mask. Read-write. Reset: 1. 0=Not masked. 1=Masked.
15:13 RAZ.
12
DS: interrupt delivery status. Read-only; updated-by-hardware. Reset: 0. 0=Idle. 1=Send pending.
(Indicates that the interrupt has not yet been accepted by the core.)
11
RAZ.
10:8 MsgType: message type. Read-write. Reset: 000b. See 2.4.8.1.14 [Generalized Local Vector Table].
7:0
Vector. Read-write. Reset: 00h. Interrupt vector number.
APIC340 LVT Performance Monitor
Interrupts for this local vector table are caused by overflows of:
• MSRC001_00[07:04] [Performance Event Counter (PERF_CTR[3:0])].
• MSRC001_024[7,5,3,1] [Northbridge Performance Event Counter (NB_PERF_CTR[3:0])].
Bits
Description
31:17 RAZ.
16
Mask. Read-write. Reset: 1. 0=Not masked. 1=Masked.
15:13 RAZ.
12
DS: interrupt delivery status. Read-only; updated-by-hardware. Reset: 0. 0=Idle. 1=Send pending.
(Indicates that the interrupt has not yet been accepted by the core.)
11
RAZ.
10:8 MsgType: message type. Read-write. Reset: 000b. See 2.4.8.1.14 [Generalized Local Vector Table].
7:0
Vector. Read-write. Reset: 00h. Interrupt vector number.
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APIC3[60:50] LVT LINT[1:0]
Table 182: Register Mapping for APIC3[60:50]
Register
APIC350
APIC360
Bits
Function
LINT 0
LINT 1
Description
31:17 RAZ.
16
Mask. Read-write. Reset: 1. 0=Not masked. 1=Masked.
15
TM: trigger mode. Read-write. Reset: 0. 0=Edge. 1=Level.
14
RmtIRR. Read-only; updated-by-hardware. Reset: 0. If trigger mode is level, remote IRR is set when
the interrupt has begun service. Remote IRR is cleared when the end of interrupt has occurred.
13
Reserved. Read-write. Reset: 0. Intel defined as pin polarity. Not used by AMD because LINT interrupts are delivered by link messages instead of individual pins.
12
DS: interrupt delivery status. Read-only; updated-by-hardware. Reset: 0. 0=Idle. 1=Send pending.
(Indicates that the interrupt has not yet been accepted by the core.)
11
RAZ.
10:8 MsgType: message type. Read-write. Reset: 000b. See 2.4.8.1.14 [Generalized Local Vector Table].
7:0
Vector. Read-write. Reset: 00h. Interrupt vector number.
APIC370 LVT Error
Bits
Description
31:17 RAZ.
16
Mask. Read-write. Reset: 1. 0=Not masked. 1=Masked.
15:13 Reserved.
12
DS: interrupt delivery status. Read-only; updated-by-hardware. Reset: 0. 0=Idle. 1=Send pending.
(Indicates that the interrupt has not yet been accepted by the core.)
11
RAZ.
10:8 MsgType: message type. Read-write. Reset: 000b. See 2.4.8.1.14 [Generalized Local Vector Table].
7:0
Vector. Read-write. Reset: 00h. Interrupt vector number.
APIC380 Timer Initial Count
Bits
Description
31:0 Count. Read-write. Reset: 0. The value copied into the current count register when the timer is loaded
or reloaded.
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APIC390 Timer Current Count
Bits
Description
31:0 Count. Read-only. Reset: 0. The current value of the counter.
APIC3E0 Timer Divide Configuration
The Div bits are encoded as follows:
Table 183: Div[3,1:0] Value Table
Div[3] Div[1:0]
Resulting Timer Divide
0
00b
2
0
01b
4
0
10b
8
0
11b
16
1
00b
32
1
01b
64
1
10b
128
1
11b
1
Bits
Description
31:4 RAZ.
3
Div[3]. Read-write. Reset: 0. See Table 183.
2
RAZ.
1:0
Div[1:0]. Read-write. Reset: 0. See Table 183.
APIC400 Extended APIC Feature
Bits
Description
31:24 RAZ.
23:16 ExtLvtCount: extended local vector table count. Read-only. Reset: 04h. This specifies the number
of extended LVT registers (APIC[530:500]) in the local APIC.
15:3 RAZ.
2
ExtApicIdCap: extended APIC ID capable. Read-only. Reset: 1. 1=The processor is capable of
supporting an 8-bit APIC ID, as controlled by APIC410[ExtApicIdEn].
1
SeoiCap: specific end of interrupt capable. Read-only. Reset: 1. 1=The APIC420 [Specific End Of
Interrupt] is present.
0
IerCap: interrupt enable register capable. Read-only. Reset: 1. This bit indicates that the
APIC[4F0:480] [Interrupt Enable] are present. See 2.4.8.1.8 [Interrupt Masking].
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APIC410 Extended APIC Control
Bits
Description
31:3 RAZ.
2
ExtApicIdEn: extended APIC ID enable. Read-write. Reset: 0. 1=Enable 8-bit APIC ID;
APIC20[ApicId] supports an 8-bit value; an interrupt broadcast in physical destination mode requires
that the IntDest[7:0]=1111_1111b (instead of xxxx_1111b); a match in physical destination mode
occurs when (IntDest[7:0] == ApicId[7:0]) instead of (IntDest[3:0] == ApicId[3:0]). 4-bit APIC ID
support deprecated only when x2APIC mode is added.
If ExtApicIdEn=1 then program D18F0x68[ApicExtId]=1 and D18F0x68[ApicExtBrdCst]=1.
1
SeoiEn. Read-write. Reset: 0. 1=Enable SEOI generation when a write to APIC420 [Specific End Of
Interrupt] is received.
0
IerEn. Read-write. Reset: 0. 1=Enable writes to the interrupt enable registers.
APIC420 Specific End Of Interrupt
Bits
Description
31:8 RAZ.
7:0
EoiVec: end of interrupt vector. Read-write. Reset: 0. A write to this field causes an end of interrupt
cycle to be performed for the vector specified in this field. The behavior is undefined if no interrupt is
pending for the specified interrupt vector.
APIC[4F0:480] Interrupt Enable
AMD-Specific. Interrupt enables range is mapped as follows:
Table 184: Register Mapping for APIC[4F0:480]
Register
APIC480
APIC490
APIC4A0
APIC4B0
APIC4C0
APIC4D0
APIC4E0
APIC4F0
Bits
Function
IntEn[31:0]
IntEn[63:32]
IntEn[95:64]
IntEn[127:96]
IntEn[159:128]
IntEn[191:160]
IntEn[223:192]
IntEn[255:224]
Description
31:0 InterruptEnableBits. Read-write. Reset: FFFF_FFFFh. The interrupt enable bits can be used to
enable each of the 256 interrupts. See above table.
APIC[530:500] Extended Interrupt [3:0] Local Vector Table
AMD-Specific. APIC500 provides a local vector table entry for IBS; See D18F3x1CC. APIC510 provides a
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local vector table entry for error thresholding. The APIC[530:520] registers are unused. APIC[530:500] interrupts disabled by (MSRC001_001F[DisApicExtReg]==1).
Table 185: Register Mapping for APIC[530:500]
Register
APIC500
APIC510
APIC520
APIC530
Bits
Function
Extended Interrupt 0 (IBS)
Extended Interrupt 1 (Thresholding)
Extended Interrupt 2
Extended Interrupt 3
Description
31:17 RAZ.
16
Mask. IF (MSRC001_001F[DisApicExtReg]) THEN RAZ. ELSE Read-write. ENDIF. Reset: 1.
0=Not masked. 1=Masked.
15:13 RAZ.
12
DS: interrupt delivery status. IF (MSRC001_001F[DisApicExtReg]) THEN RAZ. ELSE Readonly; updated-by-hardware. ENDIF. Reset: 0. 0=Idle. 1=Send pending. (Indicates that the interrupt
has not yet been accepted by the core.)
11
RAZ.
10:8 MsgType: message type. IF (MSRC001_001F[DisApicExtReg]) THEN RAZ. ELSE Read-write.
ENDIF. Reset: 000b. See 2.4.8.1.14 [Generalized Local Vector Table].
7:0
Vector. IF (MSRC001_001F[DisApicExtReg]) THEN RAZ. ELSE Read-write. ENDIF. Reset: 00h.
Interrupt vector number.
3.18 CPUID Instruction Registers
Processor feature capabilities and configuration information are provided through the CPUID instruction. The
information is accessed by (1) selecting the CPUID function setting EAX and optionally ECX for some functions, (2) executing the CPUID instruction, and (3) reading the results in the EAX, EBX, ECX, and EDX registers. The syntax CPUID FnXXXX_XXXX_EiX[_xYYY] refers to the function where EAX==X, and optionally
ECX==Y, and the registers specified by EiX. EiX can be any single register such as {EAX, EBX, ECX, and
EDX}, or a range of registers, such as E[C,B,A]X. Undefined function numbers return 0’s in all 4 registers. See
2.4.10 [CPUID Instruction].
Unless otherwise specified, single-bit feature fields are encoded as 1=Feature is supported by the processor;
0=Feature is not supported by the processor.
The following provides processor specific details about CPUID.
CPUID Fn0000_0000_EAX Processor Vendor and Largest Standard Function Number
Bits
Description
31:0 LFuncStd: largest standard function. Value: 0000_000Dh. The largest CPUID standard function
input value supported by the processor implementation.
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CPUID Fn0000_0000_E[D,C,B]X Processor Vendor
CPUID Fn0000_0000_E[D,C,B]X and CPUID Fn8000_0000_E[D,C,B]X return the same value.
Table 186: Reset Mapping for CPUID Fn8000_0000_E[D,C,B]X
Register
CPUID Fn0000_0000_EBX
CPUID Fn0000_0000_ECX
CPUID Fn0000_0000_EDX
Bits
Value
6874_7541h
444D_4163h
6974_6E65h
Description
The ASCII characters “h t u A”.
The ASCII characters “D M A c”.
The ASCII characters “i t n e”.
Description
31:0 Vendor. The 12 8-bit ASCII character codes to create the string “AuthenticAMD”.
CPUID Fn0000_0001_EAX Family, Model, Stepping Identifiers
Also see CPUID Fn8000_0001_EAX [Family, Model, Stepping Identifiers].
Family is an 8-bit value and is defined as: Family[7:0] = ({0000b,BaseFamily[3:0]} + ExtendedFamily[7:0]).
E.g. If BaseFamily[3:0]=Fh and ExtendedFamily[7:0]=07h, then Family[7:0]=16h.
Model is an 8-bit value and is defined as: Model[7:0] = {ExtendedModel[3:0], BaseModel[3:0]}. E.g. If
ExtendedModel[3:0]=Eh and BaseModel[3:0]=8h, then Model[7:0] = E8h. Model numbers vary with product.
Bits
Description
31:28
Reserved.
27:20
ExtFamily: extended family. CPUID Fn0000_0001_EAX[ExtFamily] is an alias of
D18F3xFC[ExtFamily].
19:16
ExtModel: extended model. CPUID Fn0000_0001_EAX[ExtModel] is an alias of
D18F3xFC[ExtModel].
15:12
Reserved.
11:8
BaseFamily. CPUID Fn0000_0001_EAX[BaseFamily] is an alias of D18F3xFC[BaseFamily].
7:4
BaseModel. CPUID Fn0000_0001_EAX[BaseModel] is an alias of D18F3xFC[BaseModel].
3:0
Stepping. CPUID Fn0000_0001_EAX[Stepping] is an alias of D18F3xFC[Stepping].
CPUID Fn0000_0001_EBX LocalApicId, LogicalProcessorCount, CLFlush
Bits
Description
31:24 LocalApicId: initial local APIC physical ID. Value: The initial APIC20[ApicId] value.
See 2.4.4 [Processor Cores and Downcoring].
23:16 LogicalProcessorCount: logical processor count. Specifies the number of cores in the processor
as CPUID Fn8000_0008_ECX[NC] + 1. Value: CPUID Fn8000_0008_ECX[NC] + 1.
15:8
CLFlush: CLFLUSH size in quadwords. Value: 08h.
7:0
8BitBrandId: 8 bit brand ID. Value: 00h. Indicates that the brand ID is in CPUID
Fn8000_0001_EBX.
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CPUID Fn0000_0001_ECX Feature Identifiers
These values can be over-written by MSRC001_1004.
Bits
Description
31
RAZ. Reserved for use by hypervisor to indicate guest status.
30
RDRAND: RDRAND instruction support.
Value: 0.
29
F16C: half-precision convert instruction support.
Value: ~(Fuse[XCoreLateBits[88]] || MSRC001_102E[DisF16c]).
28
AVX: AVX instruction support. Value: 1.
Value: ~(Fuse[XCoreLateBits[87]] || MSRC001_102E[DisAvx]).
27
OSXSAVE: OS enabled support for XGETBV/XSETBV. Value: CR4[OSXSAVE]. 1=The OS has
enabled support for XGETBV/XSETBV instructions to query processor extended states.
26
XSAVE: XSAVE (and related) instruction support.
Value: ~(Fuse[XCoreLateBits[85]] || MSRC001_102E[DisXsave]).
1=Support provided for the XSAVE, XRSTOR, XSETBV, and XGETBV instructions and the
XFEATURE_ENABLED_MASK register.
25
AES: AES instruction support.
Value: ~(Fuse[XCoreLateBits[84]] || MSRC001_102E[DisAes]).
24
Reserved.
23
POPCNT: POPCNT instruction. Value: 1.
22
MOVBE: MOVBE instruction support.
Value: ~(Fuse[XCoreLateBits[83]] || MSRC001_102E[DisMovbe]