RD74LVC138B 3-to-8-line Decoder / Demultiplexer REJ03D0502–0200 Rev.2.00 Jan. 14, 2005 Description The RD74LVC138B has three binary select inputs in a 16 pin package. If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables are provided to ease the cascading of decoders. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • • • • • VCC = 1.65 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±12 mA (@VCC = 2.7 V) ±24 mA (@VCC = 3.0 V to 5.5 V) • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) RD74LVC138BFPEL SOP–16 pin (JEITA) FP–16DAV FP EL (2,000 pcs/reel) RD74LVC138BTELL TSSOP–16 pin TTP–16DAV T ELL (2,000 pcs/reel) Function Table Inputs Enable Outputs Select G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H L L H H H H H H H H H H L H H: High level L: Low level X: Immaterial Rev.2.00 Jan. 14, 2005 page 1 of 7 RD74LVC138B Pin Arrangement 16 VCC A 1 B 2 B C 3 A Y0 15 Y0 C Y1 14 Y1 G2A 4 G2A Y2 13 Y2 G2B 5 G2B Y3 12 Y3 G1 6 G1 Y4 11 Y4 Y7 7 Y7 Y6 Y5 10 Y5 9 Y6 GND 8 (Top view) Absolute Maximum Ratings Item Supply voltage Symbol Ratings Unit VCC –0.5 to 7.0 Input diode current IIK –50 mA Input voltage VI –0.5 to 7.0 V Output diode current IOK –50 mA Output voltage VO –0.5 to VCC +0.5 V Output current IO ±50 mA VCC, GND current / pin ICC or IGND 100 mA Storage temperature Tstg –65 to +150 °C Conditions V 50 VI = –0.5 V VO = –0.5 V VO = VCC +0.5 V Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00 Jan. 14, 2005 page 2 of 7 RD74LVC138B Recommended Operating Conditions Item Supply voltage Symbol VCC Ratings 1.5 to 5.5 Unit V 1.65 to 5.5 Conditions Data retention At operation VI 0 to 5.5 V A, B, C, G1, G2A, G2B VO 0 to VCC V Y0 to Y7 Operating temperature Ta –40 to 85 °C Output current IOH –4 mA Input / output voltage VCC = 2.3 V –12 VCC = 2.7 V –24 IOL Input rise / fall time *1 tr, tf 4 VCC = 3.0 V to 5.5 V mA VCC = 1.65 V 8 VCC = 2.3 V 12 VCC = 2.7 V 24 VCC = 3.0 V to 5.5 V 20 10 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Jan. 14, 2005 page 3 of 7 VCC = 1.65 V –8 ns/V VCC = 1.65 V to 2.7 V VCC = 3.0 V to 5.5 V RD74LVC138B Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VIH VIL Output voltage VOH VOL VCC (V) Min Unit Max 1.65 to 1.95 VCC×0.65 — 2.3 to 2.7 1.7 — 2.7 to 3.6 2.0 — 4.5 to 5.5 VCC×0.7 — Test Conditions V 1.65 to 1.95 — VCC×0.35 V 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 4.5 to 5.5 — VCC×0.3 1.65 to 5.5 VCC–0.2 — V IOH = –100 µA 1.65 1.2 — IOH = –4 mA 2.3 1.7 — IOH = –8 mA 2.7 2.2 — IOH = –12 mA 3.0 2.4 — 3.0 2.2 — 4.5 3.8 — IOH = –24 mA 1.65 to 5.5 — 0.2 1.65 — 0.45 V IOL = 4 mA IOL = 100 µA 2.3 — 0.7 IOL = 8 mA 2.7 — 0.4 IOL = 12 mA 3.0 — 0.55 IOL = 24 mA 4.5 — 0.55 Input current IIN 0 to 5.5 — ±5.0 µA VIN = 5.5 V or GND Quiescent supply current ICC 2.7 to 3.6 — ±5.0 µA VIN = 3.6 V to 5.5 V ∆ICC 2.7 to 5.5 — 5.0 2.7 to 3.6 — 500 Rev.2.00 Jan. 14, 2005 page 4 of 7 VIN = VCC or GND µA VIN = one input at(VCC –0.6)V, other inputs at VCC or GND RD74LVC138B Switching Characteristics From To (Input) (Output) Ta = –40 to 85°C Item Propagation delay time Output skew between 1 pins* Input capacitance Note: Symbol VCC (V) Min 1.0 Typ — Max tPLH 1.8±0.15 tPHL 2.5±0.2 1.0 — 9.9 2.7 1.0 — 7.9 3.3±0.3 1.0 — 6.7 22.0 5.0±0.5 1.0 — 6.0 tPLH 1.8±0.15 1.0 — 21.0 tPHL 2.5±0.2 1.0 — 9.4 2.7 1.0 — 7.4 3.3±0.3 1.0 — 6.5 5.0±0.5 1.0 — 6.0 tPLH 1.8±0.15 1.0 — 20.3 tPHL 2.5±0.2 1.0 — 8.4 2.7 1.0 — 6.4 3.3±0.3 1.0 — 5.8 5.0±0.5 1.0 — 5.0 tOSLH 1.8±0.15 — — — tOSHL 2.5±0.2 — — — CIN Unit 2.7 — — — 3.3±0.3 — — 1.0 5.0±0.5 — — 1.0 3.3 — 5.0 — ns A, B, C Y0 to Y7 ns G2A, G2B Y0 to Y7 ns G1 Y0 to Y7 ns pF 1. This parameter is characterized but not tested. tOSLH = |tPLHm – tPLHn|, tOSHL = |tPHLm – tPHLn| Operating Characteristics Ta = 25°C Item Power dissipation capacitance Rev.2.00 Jan. 14, 2005 page 5 of 7 Symbol CPD VCC = (V) Min Typ Max 1.8 — 25 — 2.5 — 26 — 3.3 — 27 — 5.0 — 30 — Unit pF Test Conditions f = 10 MHz RD74LVC138B Test Circuit VCC VCC A Pulse Generator Zout = 50 Ω Output Y0 to Y7 B See Function Table Input CL C RL G1 G2A G2B Note: 1. CL includes probe and jig capacitance. Waveforms tr tf VIH 90 % Vref 90 % Input Vref 10 % 10 % t PLH GND t PHL VOH In phase output Vref Vref VOL t PHL t PLH VOH Out of phase output Vref VOL VCC (V) VCC = 1.8±0.15 V VCC = 2.5±0.2 V VCC = 2.7 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V Note: Vref INPUTS VIH VCC VCC 2.7 V 2.7 V VCC tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns 1. Input waveform: PRR = 10 MHz, duty cycle 50% Rev.2.00 Jan. 14, 2005 page 6 of 7 Vref 1/2 VCC 1/2 VCC 1.5 V 1.5 V 1/2 VCC CL RL 30 pF 30 pF 50 pF 50 pF 50 pF 1.0 kΩ 500 Ω 500 Ω 500 Ω 500 Ω RD74LVC138B Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 2.20 Max *0.20 ± 0.05 5.5 16 1.27 *0.40 ± 0.06 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max 0.20 7.80 +– 0.30 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 *0.20 ± 0.05 1.0 0.13 M Rev.2.00 Jan. 14, 2005 page 7 of 7 *0.15 ± 0.05 1.10 Max *Ni/Pd/Au plating 0.10 0.07 +0.03 –0.04 6.40 ± 0.20 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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