To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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Description
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview
The M16C/10 group (M30100 and M30102 groups) consist of single-chip microcomputers that use highperformance silicon gate CMOS processes and have a on-chip M16C/60 series CPU core. The microcomputers are housed in 32-pin plastic mold QFP or 48-pin plastic mold QFP packages. These single-chip
microcomputers have both high function instructions and high instruction efficiency and feature a onemegabyte address space and the capability to execute instructions at high speed.
The M30100 and M30102 groups consist of several products that have different on-chip memory types,
sizes, and packages.
Features
• Basic machine language instructions .. Compatible with the M16C/60 series
• Memory size ........................................ROM/RAM (See the memory expansion diagram.)
• Shortest instruction execution time ...... 62.5 ns (when f(XIN)=16MHz)
• Power supply voltage ........................... 4.2 V to 5.5V (when f(XIN)=16MHz)
2.7 V to 5.5V (when f(XIN)=5MHz) (This is not applicable to applications for automobile use)
• Interrupts .............................................. 12 internal causes, 7 external causes, 4 software causes
(including key input interrupts)
• 8-bit timers ........................................... 4 with 8-bit prescaler (PWM output of Timer Y, Z: selectable)
• 16-bit timer ........................................... 1 (time measurement timer)
• Serial I/O .............................................. UART or clock synchronization type x 2
• A-D converter ....................................... 10-bit X 12 channels (can be expanded to 14 channels)
• D-A converter ....................................... 1
• Watchdog timer .................................... 1
• Programmable I/O ports ...................... 34
• LED drive ports .................................... 8
• Clock generation circuits ...................... 3 internal circuits
• Main clock generation circuit
An internal feedback resistor and an externally attached ceramic
resonator/quartz crystal oscillator/RC oscillator.
• Sub clock generation circuit
An internal feedback resistor and an externally attached ceramic
resonator/quartz crystal oscillator
• Ring oscillator
Specifications written in this manual are believed to
be accurate, but are not guaranteed to be entirely
free of error.
Specifications in this manual may be changed for
functional or performance improvements. Please
make sure your manual is the latest edition.
Applications
Home appliances, office devices, audio, automobile, other
------Table of Contents------
Central Processing Unit (CPU) ..................... 10
Reset ............................................................. 13
Clock Generation Circuits ............................. 19
Protection ...................................................... 34
Overview of Interrupts ................................... 35
Watchdog Timer ............................................ 57
Timers ........................................................... 59
Serial I/O ....................................................... 97
A-D Converter ............................................. 111
D-A Conberter ............................................. 118
Programmable I/O Ports ............................. 120
Precautionary Note in Using Devices ......... 128
Electric Characteristics ............................... 133
Flash Memory Version ................................ 146
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Description
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Configuration
Figures 1.1.1 and 1.1.2 show pin configurations (top view).
VSS
P31/TZOUT
VCC
P32/TYOUT
P33/TCIN
P07/AN0
IVCC
P30/TXOUT
PIN CONFIGURATION (top view)
24 23 22 21 20 19 18 17
P06/AN1
P05/AN2
P04/AN3
VREF
P03/AN4
P02/AN5
P01/AN6
P00/AN7
25
26
27
28
29
30
31
32
16
M30100 Group
15
14
13
12
11
10
9
P45/INT0
P10/KI0/AN8
P11/KI1/AN9
P12/KI2/AN10
P13/KI3/AN11
P14/TxD0
P15/RxD0
P16/CLK0
VSS
XIN
VCC
P17/CNTR0
P37/TxD1/RxD1
CNVSS
RESET
XOUT
1 2 3 4 5 6 7 8
Package: 32P6U-A
Figure 1.1.1. Pin configuration diagram (top view) of the M30100 group
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Description
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P32/TYOUT
P33/TCIN
VCC
P40/ANEX0
P41/ANEX1
P42/INT3
P43/INT1
P30/TXOUT
VSS
P31/TZOUT
P07/AN0
IVCC
PIN CONFIGURATION (top view)
36 35 34 33 32 31 30 29 28 27 26 25
P06/AN1
P05/AN2
P04/AN3
37
38
39
VREF
N.C
N.C
40
41
42
N.C
P03/AN4
43
44
P02/AN5
P01/AN6
45
46
47
48
P00/AN7
P37/TxD1/RxD1
24
23
22
21
M30102 Group
20
19
18
17
16
15
14
13
P44/INT2
P45/INT0
P10/KI0/AN8
P11/KI1/AN9
P12/KI2/AN10
P20
N.C
P21
P13/KI3/AN11
P14/TxD0
P15/RxD0
P16/CLK0
VSS
XIN
VCC
P17/CNTR0
RESET
XOUT
P36/CLK1
P35/RxD1
P34/CLKS1/DA
CNVSS
P47/XCIN
P46/XCOUT
1 2 3 4 5 6 7 8 9 10 11 12
Package: 48P6Q-A
Figure 1.1.2. Pin configuration diagram (top view) of the M30102 group
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Mitsubishi microcomputers
M30100/M30102 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Diagram
Figure 1.1.3 is a block diagram of the M30100 group.
8
I/O ports
Port P0
5
8
Port P1
1
Port P3
Port P4
Internal peripheral functions
Timer
A-D converter
(10 bits X 12 channels)
Timer 1 (8 bits)
Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
System clock generator
UART/clock synchronous SI/O
(8 bits X 1 channel)
XIN-XOUT
Ring oscillation
UART
(8 bits X 1 channel)
M16C/60 series 16-bit CPU core
Registers
Watchdog timer
(15 bits)
R0L
R0H
R0L
R0H
R1H
R1
R1HR L R1L
RR2
2
AR3
3
AA0
0
F
B
1A1
FB
SB
Program counter
PC
Stack pointers
ISP
USP
Vector table
INTB
Flag register
FLG
Memory
ROM
(Note 1)
RAM
(Note 2)
AAAAA
AAAAA
Multiplier
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 1.1.3. Block diagram for the M30100 group
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Description
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Diagram
Figure 1.1.4 is a block diagram of the M30102 group.
8
I/O ports
Port P0
2
8
Port P4
Port P3
Port P2
Port P1
8
8
Internal peripheral functions
Timer
D-A converter
A-D converter
(8 bits X 1 channel)
(10 bits X 12 channels,
Timer 1 (8 bits)
Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
expandable to 14 channels)
System clock generator
XIN-XOUT
XCIN-XCOUT
Ring oscillation
UART/clock synchronous SI/O
(8 bits X 2 channels)
M16C/60 series 16-bit CPU core
Registers
Watchdog timer
(15 bits)
R0H
R0L
R0H
R0L
R1H
R1
R1HR LR1L
R2
R
2
R3
A
3
A0
A
0
A1
F
1B
FB
SB
Program counter
PC
Stack pointers
ISP
USP
Vector table
INTB
Flag register
FLG
Memory
ROM
(Note 1)
RAM
(Note 2)
AAAAA
AAAAA
Multiplier
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 1.1.4. Block diagram for the M30102 group
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Description
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Overview
Table 1.1.1 gives an overview of the M16C/10 group performance specification.
Table 1.1.1. M16C/10 group performance overview
Item
Performance
M30100
M30102
Number of basic instructions
91 instructions
Shortest instruction execution time
Memory
ROM
62.5 ns (when f(XIN)=16MHz)
See the memory expansion diagram.
size
RAM
See the memory expansion diagram.
I/O port
Multifunction
T1
P0,P1,P3,P4: 22 lines
8 bits x 1
timer
TX, TY, TZ
8 bits x 3
P0 to P4: 34 lines
TC
16 bits x 1
Serial I/O (UART or clock synchronous)
x2
A-D converter
(maximum resolution: 10 bits)
D-A converter
Watchdog timer
Interrupts
Clock generating circuits
Power supply voltage
(one is exclusively for UART)
x 12 channels
x2
x 12 channels
(Expandable up to 14 channels)
8 bits x 1
15 bits x 1 (with prescaler)
12 internal causes, 7 external causes (4 for M30100), 4 software causes
2 internal circuits
3 internal circuits
4.2 V to 5.5V (when f(XIN)=16MHz)
2.7 V to 5.5V (when f(XIN)=5MHz) (Note)
Power consumption
100mW (Vcc=5.0V, f(XIN)=16MHz)
12mW (Vcc=3.0V, f(XIN)=5MHz)
I/O
I/O withstand voltage 5V
characteristics Output current
5mA (10mA:LED drive port)
Device configuration
CMOS silicon gate
Package
32-pin LQFP
48-pin LQFP
Note: This voltage is not applicable to applications for automobile use.
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Description
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M16C/10 group:
(1) Support for mask ROM version and flash memory version
(2) Memory size
(3) Package
32P6U:
Plastic molded LQFP (mask ROM version and flash memory version)
48P6Q:
Plastic molded LQFP (mask ROM version and flash memory version)
As of January, 2003
RAM
(Byte)
AAAAAAA
AAAAAAA
AAAAAAA
M30102M6-XXXFP
M30102M6T-XXXFP
2.5K
2K
1K
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
M30100F3FP
M30100F3TFP
M30100M2-XXXFP
M30102F3FP
M30100M2T-XXXFP M30102F3TFP
M30102M2-XXXFP
M30100M3-XXXFP
M30102M2T-XXXFP M30100M3T-XXXFP
M30102M3-XXXFP
M30102M3T-XXXFP
16K
24K
: Under Development
: Planning Stage
32K
48K
ROM
(
Figure 1.1.5. Memory expansion
Type No.
M30 10 0 M 2 T - XXX FP
Package type:
FP: Package 32P6U, 48P6Q
ROM No.
Omitted for flash memory version
Indicates differences in characteristics and usage etc:
Nothing: Common
T:
Automobiles
ROM size:
2: 16 Kbytes
3: 24 Kbytes
6: 48 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
Indicates pin count, etc
(The value itself has no specific meaning)
M16C/10 Group
M16C Family
Figure 1.1.6. Type No., memory size, and package
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Pin Description
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin name
V
CC, VSS
Vcc,
VSS
Signal name
I/O type
Power supply
input
Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
Connect a capacitor (0.1 µF) between this pin and VSS.
IVCC
8
Function
CNVSS
CNVSS
Input
Connect it to the VSS pin via resistance (about 5 kΩ).
RESET
Reset input
Input
An “L” on this input resets the microcomputer.
XIN
Clock input
Input
XOUT
Clock output
Output
These pins are provided for the main clock oscillation circuit.
Connect a ceramic resonator or crystal between the XIN and
XOUT pins. To use an externally derived clock, input it to the
XIN pin and leave the XOUT pin open.
VREF
Reference
voltage input
Input
This pin is a reference voltage input for the A-D converter.
P00 to P07
I/O port P0
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or
output individually. When set for input, the user can specify in
units of four bits via software whether or not they are tied to a
pull-up resistor. These pins are shared with analog input pins.
P10 to P17
I/O port P1
Input/output
This is an 8-bit I/O port equivalent to P0. P10 to P13 are shared
with analog inputs and key input interrupts. P14 to P16 are
shared with serial I/O pins. P17 is shared with timer input. Can
be used as an LED drive port.
P20 to P21
I/O port P2
Input/output
This is a 2-bit I/O port equivalent to P0.
P30 to P37
I/O port P3
Input/output
This is a 8-bit I/O port equivalent to P0. P30 to P33 are shared
with timer input/output. P34 to P37 are shared with serial I/O.
P34 is shared with analog outputs.
P40 to P47
I/O port P4
Input/output
This is a 8-bit I/O port equivalent to P0. P40 to 41 are shared
with analog inputs. P42 to P45 are shared with interrupt inputs.
P46 to P47 are shared with the I/O pin of the clock oscillation
circuit for the clock.
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Memory
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Operation of Functional Blocks
The M30100/M30102 contain the following devices on a single chip: ROM and RAM, which function as
memory for storing instructions and data; a central processing unit (CPU) that executes operations; and
peripheral devices, such as timers, serial I/O, an A-D converter, an D-A converter, and I/O ports.
The individual devices are described below.
Memory
Figure 1.3.1 is a memory map. The address space extends the 1M bytes from address 0000016 to
FFFFF16. From FFFFF16 down is ROM. For example, in the M30100M2-XXXFP, there is 16K bytes of
internal ROM from FC00016 to FFFFF16. The vector table for fixed interrupts such as the reset are mapped
to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the
vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the
section on interrupts for details.
From 0040016 up is RAM. For example, in the M30100M2-XXXFP, there is 1K byte of internal RAM from
0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 000FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
(For details, see
Figures 1.6.1 and
1.6.2)
FFE0016
0040016
Internal RAM area
Special page
vector table
XXXXX16
FFFDC16
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
YYYYY16
Internal ROM area
FFFFF16
Undefined instruction
Reset
FFFFF16
Internal RAM area
Type No.
Internal ROM area
Memory size
XXXXX16
Memory size
YYYYY16
M30100M2/M2T、M30102M2/M2T
1K byte
007FF16
16K byte
FC00016
M30100M3/M3T/F3/F3T、M30102M3/M3T/F3/F3T
1K byte
007FF16
24K byte
FA00016
2.5K byte
00DFF16
48K byte
F400016
M30102M6
/M6T
: Under Development
: Planning Stage
Figure 1.3.1. Memory map
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CPU
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
b15
R0(Note)
b8 b7
b15
R1(Note)
b8 b7
H
b15
b0
L
H
b19
b0
L
b0
b19
INTB
b15
b15
User stack pointer
b0
Interrupt stack
pointer
ISP
Address
registers
b15
b0
Static base
register
SB
A1(Note)
FB(Note)
b0
b15
b0
b0
Interrupt table
register
USP
A0(Note)
b15
b0
L
H
b0
R3(Note)
b15
Program counter
Data
registers
R2(Note)
b15
b0
PC
b15
b0
Frame base
registers
b0
FLG
Flag register
AA
AAAAAA
AA
AA
AA
AA
AA
AA
AA
AA
AAAAAAAA
AA
AA
AA
AAAA
AA
IPL
U
I O B S Z D C
Note: These registers consist of two register banks.
Figure 1.4.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H),
and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0, R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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CPU
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
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CPU
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
_______
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
AAA
AA
AA
AAAAAAAA
AA
AA
A
AA
AAAAAAAAAAAAAAA
AA
AA
A
AA
b15
b0
IPL
U
I
O B S Z D C
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.4.2. Flag register (FLG)
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Reset
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 200 µsec. When the reset pin level is then returned to the “H”
level, the reset status is cancelled and program execution resumes from the address in the reset vector
table. Since the value of RAM is indeterminate when power is applied, the initial values must be set. Also,
if a reset signal is input during write to RAM, the access to the RAM will be interrupted. Consequently, the
value of the RAM being written may change to an unintended value due to the interruption.
Figures 1.5.1 and 1.5.2 show the example reset circuit. Figure 1.5.3 shows the reset sequence.
5V
4.0V
VCC
0V
5V
VCC
RESET
RESET
0.8V
0V
More than 200 µsec
Example when VCC = 5V.
Figure 1.5.1. Example reset circuit
5V
4.0V
VCC
RESET
VCC
Supply voltage
detection circuit
0V
5V
RESET
0V
More than 200 µsec
Example when VCC = 5V.
Figure 1.5.2. Example reset circuit (example voltage check circuit)
Internal ring
oscillation
More than 20 cycles are needed
RESET
BCLK
28cycles
BCLK
(Internal clock)
FFFFC16
Address
Content of reset vector
FFFFE16
(Internal address
signal)
Figure 1.5.3. Reset sequence
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Reset
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Processor mode register 0
(000416)···
0
0 0
(36) Timer Z primary
(008716)···
(37) Timer Y,Z output control register
(008A16)···
0 0 0
0 0 0 0 0 0
FF16
(2) Processor mode register 1
(000516)··· 0 0
(3) System clock control register 0
(000616)··· 0 1 0 0 1 0 0 0
(38) Timer X mode register
(008B16)···
(4) System clock control register 1
(000716)··· 0 0 1 0 0 0 0 0
(39) Prescaler X
(008C16)···
FF16
(5) Address match interrupt
enable register
(000916)···
0 0
(40) Timer X
(008D16)···
FF16
(6) Protect register
(000A16)···
0 0 0
(41) Timer count source set register
(008E16)···
0016
(7) Oscillation stop detection register
(000C16)··· 0 0 0 0 0 1 0 0
(42) Clock prescaler reset flag
(008F16)··· 0
(8) Watchdog timer control register
(000F16)··· 0 0 0 ? ? ? ? ?
(43) External input enable register
(009616)···
0016
(9) Address match interrupt
register 0
(001016)···
0016
(44) Key input enable register
(009816)···
0016
(001116)···
0016
(45) Timer C control register 0
(009A16)··· 0
0 0 0 0 0
(001216)···
(10) Address match interrupt
register 1
0
0
0 0 0 0
(001416)···
0016
(001516)···
0016
(001616)···
0 0 0 0
(11) INT0 input filter select register
(001E16)···
0 0 0
(12) Key input interrupt control register
(004D16)···
? 0 0 0
(00A016)···
(52) UART1 transmit/receive control
register 1
(53) UART transmit/receive control
register 2
1 1
0016
(00A416)··· 0 0 0 0 1 0 0 0
(00A516)···
0 0 1 0
(00A816)···
0016
(00AC16)··· 0 0 0 0 1 0 0 0
0 0 1 0
(00B016)···
0 0 0 0 0 0 0
(54) A-D control register 2
(00D416)···
0 0 0 0
(55) A-D control register 0
(00D616)··· 0 0 0 0 0 ? ? ?
(56) A-D control register 1
(00D716)···
? 0 0 0
(57) D-A control register
(00DC16)···
? 0 0 0
(58) Port P0 direction register
(00E216)···
0016
? 0 0 0
(59) Port P1 direction register
(00E316)···
0016
(00E616)···
(004E16)···
? 0 0 0
(005116)···
? 0 0 0
(005216)···
? 0 0 0
(16) UART1 transmit interrupt control
register
(005316)···
? 0 0 0
(17) UART1 receive interrupt control
register
(005416)···
? 0 0 0
(18) Timer 1 interrupt control register
(005516)···
(19)Timer X interrupt control register
(005616)···
(005716)···
(009B16)···
(47) UART0 transmit/receive mode
register
(48) UART0 transmit/receive control
register 0
(49) UART0 transmit/receive control
register 1
(50) UART1 transmit/receive mode
register
(51) UART1 transmit/receive control
register 0
(00AD16)···
(13) A-D conversion interrupt
control register
(14) UART0 transmit interrupt control
register
UART0 receive interrupt control
(15)
register
(20)Timer Y interrupt control register
(46) Timer C control register 1
0016
0
(21)Timer Z interrupt control register
(005816)···
? 0 0 0
(60) Port P2 direction register
(22)CNTR0 interrupt control register
(005916)···
? 0 0 0
(61) Port P3 direction register
(00E716)···
0016
(23)TCIN interrupt control register
(005A16)···
? 0 0 0
(62) Port P4 direction register
(00EA16)···
0016
(24)Timer C interrupt control register
(005B16)···
? 0 0 0
(63) Pull-up control register 0
(00FC16)··· 0 0
(25)INT3 interrupt control register
(005C16)···
? 0 0 0
(64) Pull-up control register 1
(00FD16)···
(26)INT0 interrupt control register
(005D16)···
0 0 ? 0 0 0
(65) Port P1 drive capacity control
register
(00FE16)···
(27) INT1 interrupt control register
(005E16)···
0 0 ? 0 0 0
(66) Data registers (R0/R1/R2/R3)
000016
(28) INT2 interrupt control register
(005F16)···
0 0 ? 0 0 0
(67) Address registers (A0/A1)
000016
(29) Timer Y, Z mode register
(008016)··· 0 0 0 0 0 0
(68) Frame base register (FB)
000016
(30) Prescaler Y
(008116)···
FF16
(69) Interrupt table register (INTB)
0000016
(31) Timer Y secondary
(008216)···
FF16
(70) User stack pointer (USP)
000016
(32)Timer Y primary
(008316)···
FF16
(71) Interrupt stack pointer (ISP)
000016
(33) Timer Y, Z waveform output
control register
(34) Prescaler Z
(008416)···
0016
(72) Static base register (SB)
000016
(008516)···
FF16
(73) Flag register (FLG)
000016
(35)Timer Z secondary
(008616)···
FF16
0
0
0 0
0 0 0 0 0
0 0
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer
is reset. The initial values must therefore be set.
Figure 1.5.4. Device's internal status after a reset is cleared
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Software
Software Reset
Wait
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Figure 1.5.5 shows the processor mode register 0 and 1.
Processor mode register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
PM0
Address
000416
Bit symbol
When reset
XXXX0X002
Bit name
Reserved bit
Function
Must always be set to “0”
Nothing is assigned.
AA
R W
In an attempt to write to this bit, write “0”. The value, if read, turns out
to be indeterminate.
PM03
Software reset bit
The device is reset when this bit
is set to “1”. The value of this bit
is “0” when read.
Nothing is assigned.
AA
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0
Symbol
PM1
Address
000516
Bit symbol
Bit name
When reset
00XXX0X02
Function
Must always be set to “0”
Reserved bit
Nothing is assigned.
In an attempt to write to this bits, write “0”. The value, if read, turns
out to be indeterminate.
PM12
WDT interrupt/reset
switching bit
0 : Watchdog timer interrupt
1 : Reset (Note 2)
Nothing is assigned.
AA
R W
AA
AAA
A
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Reserved bit
Must always be set to “0”
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Note 2: After setting this bit to "1", can not change to "0" by software.
Figure 1.5.5. Processor mode register 0 and 1.
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SFR
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
000016
004016
000116
004116
000216
004216
004316
000316
000416
000516
000616
000716
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
000A16
004516
004616
004716
004816
000816
000916
004416
Address match interrupt enable register (AIER)
Protect register (PRCR)
004916
Oscillation stop detection register (CM2)
004A16
000B16
000C16
004B16
000D16
000E16
000F16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
004D16
004E16
001016
001116
004C16
Address match interrupt register 0 (RMAD0)
004F16
001216
005016
001316
005116
001416
005216
001516
Address match interrupt register 1 (RMAD1)
005316
001616
005416
001716
005516
001816
005616
001916
005716
001A16
005816
001B16
005916
001C16
005A16
005B16
001D16
001E16
INT0 input filter select register (INT0F)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
005C16
001F16
005D16
002016
005E16
002116
005F16
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer 1 interrupt control register (T1IC)
Timer X interrupt control register (TXIC)
Timer Y interrupt control register (TYIC)
Timer Z interrupt control register (TZIC)
CNTR0 interrupt control register (CNTR0IC)
TCIN interrupt control register (TCINIC)
Timer C interrupt control register (TCIC)
INT3 interrupt control register (INT3IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Note: The blank area is reserved and must not be read or written.
Figure 1.6.1. Location of peripheral unit control registers (1)
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SFR
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
008016
00C016
008316
Timer Y, Z mode register (TYZMR)
Prescaler Y (PREY)
Timer Y secondary (TYSC)
Timer Y primary (TYPR)
008416
Timer Y, Z waveform output control register (PUM)
00C416
008516
Prescaler Z (PREZ)
Timer Z secondary (TZSC)
Timer Z primary (TZPR)
Prescaler 1 (PRE1)
Timer 1 (T1)
Timer Y, Z output control register (TYZOC)
Timer X mode register (TXMR)
Prescaler X (PREX)
Timer X (TX)
Timer count source set register (TCSS)
Clock prescaler reset flag (CPSRF)
00C516
008116
008216
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
Timer C counter (TC)
00C116
00C316
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
009216
00D216
009316
00D316
009416
00D416
009516
00D516
009616
External input enable register (INTEN)
009716
009816
009A16
009B16
009C16
009D16
00D616
00D716
Key input enable register (KIEN)
009916
00D816
00DA16
Time measurement register (TM)
00DC16
00DB16
UART0 transmit/receive mode register (U0MR)
00DF16
00E016
00A116
UART0 bit rate generator (U0BRG)
00E116
00A516
00A616
00A716
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
00E216
00E316
00E416
00E516
00E616
00E716
00A816
UART1 transmit/receive mode register (U1MR)
00E816
00A916
UART1 bit rate generator (U1BRG)
00E916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
D-A control register (DACON)
00DD16
00A016
00A416
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register (DA)
00DE16
009F16
00A316
A-D control register 2 (ADCON2)
00D916
Timer C control register 0 (TCC0)
Timer C control register 1 (TCC1)
009E16
00A216
A-D register (AD)
00C216
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
00EA16
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
Port P4 direction register (PD4)
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00B116
00F116
00B216
00F216
00B316
00F316
00B416
00F416
00B516
00F516
00B616
00F616
00B716
00F716
00B816
00F816
00B916
00F916
00BA16
00FA16
00BB16
00FB16
00BC16
00FC16
00BD16
00FD16
00BE16
00FE16
00BF16
00FF16
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Port P1 drive capacity control register (DRR)
Note: The blank area is reserved and must not be read or written.
Figure 1.6.2. Location of peripheral unit control registers (2)
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Bus Control
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
During access, the memory areas (ROM, RAM, FLASH, etc.) and the SFR area have different bus cycles.
As shown in Table 1.7.1, memory areas can be accessed in one cycle of the CPU operation clock BCLK.
The SFR area can be accessed in two cycles of BCLK.
0000016
Table 1.7.1. Bus cycles for access areas
Area
Bus cycle
SFR
2 BCLK cycles
Internal ROM/RAM 1 BCLK cycles
SFR area
(For details, see
Figures 1.6.1 and 1.
6.2)
SFR area
0040016
Internal RAM area
XXXXX16
Memory area
YYYYY16
Internal ROM area
FFFFF16
Figure 1.7.1. SFR area and memory areas
The memory areas and the SFR area also have different bus widths. The memory areas have a 16-bit bus
width, while the SFR area has an 8-bit bus width. Consequently, different operations are used when the
areas are accessed in word (16 bits) units. Table 1.7.2 shows the bus cycles that are necessary to access
the SFR area and the memory areas.
Table 1.7.2. Cycles for access areas
Area
Even address
byte access
SFR area
BCLK
BCLK
Address
Data
Data
Add address
word access
Data
18
Data
Data
Odd
Data
Data
BCLK
Even
Data
Even+1
Data
Address
Even/even+1
Word
Data
Data
BCLK
BCLK
Address
Data
Address
Odd
BCLK
Address
Even
BCLK
BCLK
Address
Data
Even address
word access
Address
Even
Data
Add address
byte access
Memory area
Odd
Data
Odd+1
Data
Address
Data
Odd
Data
Odd+1
Data
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Clock Generating Circuit
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The clock generating circuit contains three oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.8.1. Main clock, sub-clock, and ring oscillator generating circuits
Main clock generating circuit
Sub clock generating circuit Ring oscillator generating circuit
Use of clock
• CPU’s operating clock source • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral units’ • Timer 1/X/Y/Z’s count
operating clock source
clock source
• Internal peripheral units’
operating clock source
• Timer Y’s count clock
source
Usable oscillator (Note) Ceramic, crystal or RC
oscillator
Crystal oscillator
–
Pins to connect oscillator XIN, XOUT
XCIN, XCOUT
None (has internal pins)
Oscillation stop/restart function Available
Available
Oscillator status immediately Oscillating
Stopped
after reset
Other
Externally derived clock can be input
Available
Oscillating
–
Note : When not using the main clock generating circuit, pull up the XIN pin and leave the XOUT pin open.
Also, set the main clock stop bit (bit 5 of address 0006) to "1" (stop).
Example of oscillator circuit
Figure 1.8.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.8.2 shows some examples of
sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.8.1 and 1.8.2 vary with each oscillator used. Use the
values recommended by the manufacturer of your oscillator.
Microcomputer
Microcomputer
Microcomputer
(Built-in feedback resistor)
XIN
XOUT
XIN
(Built-in feedback resistor)
XOUT
(Note)
Rd
XIN
XOUT
Open
R
Externally derived clock
CIN
C
COUT
External ceramic oscillator
External RC oscillator
Vcc
Vss
External clock input
Note : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation
drive capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator
manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback
resistor between XIN and XOUT following the instruction.
Figure 1.8.1. Examples of main clock
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Mitsubishi microcomputers
M30100/M30102 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
Note: Insert a damping resistor if
required. The resistance will
vary depending on the oscillator
and the oscillation drive
capacity setting. Use the value
recommended by the maker of
the oscillator.
When the oscillation drive
capacity is set to low, check that
oscillation is stable.
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Figure 1.8.2. Examples of sub-clock
A ring oscillator is built into the microcomputer. The oscillation of the ring oscillator can be used as the
BCLK by setting the main clock select bit (bit 2 of address 000C). Lower power consumption can be
realized because the oscillating frequency of the ring oscillator is much lower compared to that of XIN. The
frequency of the ring oscillator depends on the supply voltage and the operation temperature range. Be
careful that variable frequencies and obtain the sufficient margin when designing application products.
Clock Control
Figure 1.8.3 shows the block diagram of the clock generating circuit.
XCIN
XCOUT
1/32
fC32
f1
CM04
fAD
fC
f8
Sub clock
CM10 “1”
Write signal
f32
S Q
XIN
XOUT
fMAIN
R
RESET
Software reset
Ring
oscillator
oscillation
circuit
Main clock
1/2
b
Main
clock
switching
circuit
a
c
Divider
d CM07=0
fC
fRING
BCLK
CM07=1
CM05
Interrupt request
level judgment output
CM02
Oscillation
stop detection
CM20
CM22
S Q
R
WAIT instruction
R
c
b
a
1/2
1/2
1/2
1/2
1/2
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
CM2i : Bit i at address 000C16
WDCi : Bit i at address 000F16
Figure 1.8.3. Clock generating circuit
20
CM06=0
CM17,CM16=00
Details of divider
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Clock Generating Circuit
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After reset, oscillation starts. The clock
can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock reduces the
power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin
can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive
capacity of the XOUT pin reduces the power dissipation. This bit changes to “1” when shifting from highspeed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that
the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the XCOUT pin
can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the
drive capacity of the XCOUT pin reduces the power dissipation. This bit changes to “1” when shifting to
stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU. The clock source for BCLK is as follows: (1) the clock derived
by dividing the main clock by 1, 2, 4, 8, or 16, (2) fC, or (3) the clock derived by dividing the clock supplied
by the ring oscillator circuit (fRING) by 1, 2, 4, 8 or 16. After reset, the BCLK is derived by dividing the fRING
by 8. When using an external RC oscillator circuit for the main clock, 1 division of the main clock cannot
be selected as BCLK.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed mode to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock
a. f1, f8, f32
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped as follows: (i) by stopping the main clock or (ii) by executing an
WAIT instruction after setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to “1”. When
using an external RC oscillator circuit for the main clock, f1 cannot be selected as the operation clock
of some peripheral devices.
b. fAD
This clock has the same frequency as the main clock and is used in A-D conversion.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer 1, timer X, timer Y and timer
Z counts. Figure 1.8.6 shows the block diagram of fc32 .
(6) fC
This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.
(7) fRING
This clock is supplied by the ring oscillator circuit. In the ring oscillator mode, the clock divided by the
division ratio selected with the main clock division select bit 0 and bit 1(bit 6 at address 000616, and bit 6
and bit 7 at address 000716) is supplied as BCLK. Immediately after reset, 8 divisions of this clock is
supplied as BCLK. The ring oscillator oscillation can be set to BCLK when oscillation stop is detected or
with the main clock switching bit (bit 2 at address 000C16).
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Clock Generating Circuit
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
CM0
Address
000616
Bit symbol
When reset
4816
Bit name
Function
Always set to “0”
Reserved bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
CM02
WAIT peripheral function
clock stop bit
CM03
XCIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
CM04
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM05
Main clock (XIN-XOUT)
stop bit (Note 3,4,5)
0 : On
1 : Off
CM06
Main clock division select
bit 0 (Note 7)
0 : CM16 and CM17 valid
1 : Division by 8 mode
CM07
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
R W
AA
AA
AA
AA
AA
AA
AA
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode.
Note 3: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with XIN
after exiting from the stop mode, set this bit to “0”. When operating with a self-excited oscillator, set the system clock
select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being ON, so XIN turns pulled up to
XOUT (“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” before setting this bit to “1”. Can not write to both bits at the same time.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from
low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fc32 is not included. Do not set to “1” when using low-speed, low power dissipation or ring oscillator mode.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
CM1
Address
000716
Bit symbol
CM10
When reset
2016
Bit name
All clock stop control bit
(Note 4)
Function
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
CM13
XIN oscillation select bit
0 : Ceramic oscillation or crystal oscillation
1 : RC oscillation
CM14
Ring oscillation stop bit
0 : Oscillation enabled
1 : Oscillation stopped (Note 5)
CM15
XIN-XOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
b7 b6
CM16
Main clock division
select bit 1 (Note 3)
CM17
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
AA
AA
A
AA
A
AA
A
AA
A
AA
AA
AA
RW
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/middle-speed mode to stop mode or at reset. When shifting from
low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is ineffective. The mode of power control cannot
be shifted to the stop mode directly from the oscillator mode.
Note 5: This bit can be set to “1” only when both the main clock switch bit (CM22) and clock monitor bit (CM23) are set to “0” .
Moreover, this bit is automatically set to “0” if the main clock switch bit (CM22) is set to “1”.
Figure 1.8.4. System clock control registers 0 and 1
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Clock Generating Circuit
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Oscillation stop detection register (Note 5)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM2
0 0 0 0
Bit symbol
Address
000C16
When reset
0416
Bit name
R W
Function
CM20
Oscillation stop
detection bit
0: The function is invalid.
1: The function is valid. (Note 1)
CM21
Oscillation stop detection
interrupt enable bit
0: Disabled
1: Enabled
(Note 2)
CM22
Main clock switch bit
0: Select XIN clock.
1: Select ring oscillator.
(Note 3)
CM23
0: XIN oscillating normally
Clock monitor bit (Note 4) 1: XIN stopping abnormally
Always set to "0"
Reserved bit
Note 1: Set to “0” before stopping the oscillation of the main clock (XIN-XOUT).
(stop mode, low power dissipation mode, ring oscillation mode)
An oscillation stop is detected if the oscillation of the main clock (XIN-XOUT) is
stopped when the following two conditions are satisfied: (1) the oscillation stop
detection function is valid and (2) CM21=1.
Note 2: Valid when CM20=1.
Note 3: CM22 bit switches to “1“ automatically if an oscillation stop is detected when
both CM20 bit and CM 21 bit are “1”. CM22 bit cannot be cleared when CM23=1.
Note 4: This bit is valid when CM20 bit is “1”. Use this bit for the purpose of confirming
XIN operation for oscillation stop detection interrupt execution.
Note 5: In case of writing to this register, set bit 0 of the protect register(000A16) to "1".
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Bit symbol
Address
008F16
When reset
0XXXXXXX2
Bit name
Function
RW
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAA
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
CPSR
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
Figure 1.8.5. Oscillation stop detection register and clock prescaler reset flag
Clock prescaler
XCIN
Clock prescaler reset flag (bit 7
at address 008F16) set to “1”
1/32
fC32
Reset
Figure 1.8.6. fc32 block diagram
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Stop Mode, Wait Mode
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V.
Because the oscillation of BCLK, f1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions such as
the A-D converter and watchdog timer do not function. However, timer X operate provided that the event
counter mode is set to an external pulse, and UART0 and UART1 function provided an external clock is
selected. Table 1.8.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel
must have been changed to 0 before shifting to stop mode. If returning by an interrupt, that interrupt routine
is executed. If only a hardware reset is used to cancel stop mode, change the priority level of all interrupt to
0, then shift to stop mode.
When shifting from high-speed/medium-speed mode to stop mode or at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
The stop mode must not be used while operating in the ring oscillator mode.
Table 1.8.2. Port status during stop mode
Pin
Port
States
Retains status before stop mode
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. Table 1.8.3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts using as BCLK, the clock that had been selected when the WAIT instruction was
executed.
Table 1.8.3. Port status during wait mode
Pin
States
Port
24
Retains status before wait mode
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Status Transition of BCLK
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.8.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, division by 8 mode is set. The main clock division select bit 0 (bit 6 at address 000616)
changes to “1” when shifting from high-speed/medium-speed mode to stop mode or at a reset. The following shows the operational modes of BCLK. When shifting from low-speed/low power dissipation mode to
stop mode, the value before stop mode is retained.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. Before the user can go from this mode to no division
mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to
low-speed or lower power dissipation mode, sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK. When using an external RC circuit for the main clock,
no-division mode must not be used.
(6) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
(8) Ring oscillator mode
This mode sets the ring oscillator as BCLK. The same as when XIN is the main clock, the modes are no
division, 2-division, 4-division, 8-division, and 16-division.
Note: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
And, be sure to shift from division by 8 mode when you change it to ring oscillator mode. Shift to
other mode after you surely shift to the mode for division by 8 mode when you change it from ring
oscillator mode to other mode.
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.8.4. Operating modes dictated by settings of system clock control registers 0 and 1
26
CM22
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of BCLK
0
0
1
0
0
0
Invalid
Division by 2 mode
0
0
1
Invalid
0
Invalid
0
0
0
1
0
0
Invalid
Invalid
Division by 4 mode
Division by 8 mode
0
0
1
0
1
0
0
0
0
0
0
0
Invalid
Invalid
Division by 16 mode
No-division mode
0
0
Invalid
Invalid
Invalid
Invalid
1
1
Invalid
Invalid
0
1
1
1
1
1
0
1
1
0
0
0
0
0
Invalid
Invalid
Invalid
Invalid
Ring oscillator mode(divided by 2)
Ring oscillator mode(divided by 4)
1
1
Invalid
1
Invalid
1
0
0
1
0
Invalid
Invalid
Invalid
Invalid
Ring oscillator mode(divided by 8)
Ring oscillator mode(divided by 16)
1
0
0
0
0
Invalid
Invalid
Ring oscillator mode(no division)
Low-speed mode
Low power dissipation mode
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Power Control
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
This section gives an overview of power control.
Modes
There are three power save modes.
(1) Normal operating mode
• High-speed mode
In this mode, one main clock cycle forms BCLK. The CPU operates on the BCLK. The peripheral
functions operate on the clocks specified for each respective function.
• Medium-speed mode
In this mode, the main clock is divided into 2, 4, 8, or 16 to form BCLK. The CPU operates on the
BCLK. The peripheral functions operated on the clocks specified for each respective function.
• Low-speed mode
In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the
subclock. The peripheral functions operate on the clocks specified for each respective function.
• Low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on
the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the
subclock was selected as the count source continue to run.
• Ring oscillator mode
This mode sets the ring oscillator as BCLK. The ring oscillator can be set to no division, 2-divisions, 4division, 8-division, or 16-division mode according to the settings for CM06, CM16, and CM17. Increasing the division ratio lowers power consumption. When the microcomputer is operating with the
ring oscillator, the XIN clock driver can be stopped by setting the main clock stop bit to “1.” This can
lower the power dissipation even more.
(2) Wait mode
CPU operation is halted in this mode. The oscillator continues to run.
(3) Stop mode
All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power
saving modes, power savings are greatest in this mode. The mode cannot be shifted to the stop mode
directly from the ring oscillator mode.
Figure 1.9.1 and 1.9.2 show the transition between each of the three modes, (1), (2), and (3).
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Power Control
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transition of stop mode, wait mode
Reset
RIng oscilltor mode
(divided-by-8 mode)
All oscillators stopped
CM10 = “1”
Stop mode
All oscillators stopped
Stop mode
Interrupt
Medium-speed mode
(divided-by-8 mode)
Interrupt
CM10 = “1”
High-speed/mediumspeed mode
All oscillators stopped
CM10 = “1”
Stop mode
Interrupt
Low-speed/low power
dissipation mode
WAIT
instruction
CPU operation stopped
Wait mode
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
Normal mode
(Refer to Fig. 1. 9. 2. for the transition of normal mode.)
Figure 1.9.1. Clock transition (1)
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Power Control
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Ring oscillator mode (divided-by-8 mode)
Main clock is oscillating
Sub clock is stopped
Medium-speed mode (divided-by-8 mode)
CM06=“1”
BCLK: f(RING)/8
CM07=“0”
CM06=“1”
CM22=“1”
CM22=“1”
BCLK: f(XIN)/8
CM22=“0”
CM07=“0” CM06=“1”
(Note 1)
Main clock is stopped
Sub clock is stopped
Ring oscillator mode
CM04=“0”
CM05 = “0”
8-division mode
CM04=“1”
(Notes 1, 3)
CM07=“0“ (Note 1)
CM06=“1”
CM04=“0”
BCLK: f(RING)/8
CM07=“0”
CM05=“1”
CM22=“1”
1-division mode (Note 3)
BCLK: f(RING)
CM07=“0”
CM05=“1”
CM16=“0”
CM06=“0”
CM22=“1”
CM17=“0”
4-division mode (Note 3)
BCLK: f(RING)/4
CM07=“0”
CM05=“1”
CM16=“0”
Main clock is oscillating
Sub clock is oscillating
BCLK : f(XIN )
BCLK : f(XIN )/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN )/4
Medium-speed mode
(divided-by-8 mode)
BCLK: f(RING)/2
CM07=“0”
CM05=“1”
CM16=“1”
CM06=“0”
CM22=“1”
CM17=“0”
16-division mode (Note 3)
BCLK: f(RING)/16
CM07=“0”
CM05=“1”
CM16=“1”
CM06=“0”
CM22=“1”
CM17=“1”
CM07 = “0”
CM06 = “1”
BCLK : f(XCIN )
CM07 = “1”
CM06 = “1”
(Note 2,5)
CM07 = “1”
CM06 = “1”
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
CM04 = “0”
CM05 = “0”
CM04 = “1”
Low power dissipation mode
High-speed mode
Medium-speed mod
(divided-by-2 mode)
BCLK : f(XIN )
BCLK : f(XIN )/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN )/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
CM05 = “1”
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is stopped
CM06 = “0”
(Notes 1,3)
2-division mode (Note 3)
Low-speed mode
CM07 = “0”
(Notes 1, 3)
BCLK : f(XIN )/8
BCLK : f(XIN )/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
CM06=“0”
CM22=“1”
CM17=“1”
CM06=“1”
Main clock is oscillating
Sub clock is oscillating
Medium-speed mode
(divided-by-2 mode)
High-speed mode
CM05 = “1”
BCLK : f(XIN )/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
BCLK : f(XCIN )
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
CM07 = “1”
CM06 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM17 and CM16 before changing CM06.
Note 4: Transit in accordance with arrow.
Note 5: Before switching BCLK to other from the main clock, divide the main
clock by 8 for safty purposes to switch BCLK to the main clock again.
Figure 1.9.2. Clock transition (2)
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Oscillation Stop Detection
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Oscillation Stop Detection Function
The oscillation stop detection function detects abnormal stopping of the main clock by causes such as
opening and shorting of the XIN oscillation circuit. When oscillation stop is detected, an oscillation stop
detection interrupt is issued. When an oscillation stop detection interrupt is issued, the ring oscillator in the
microcomputer operates automatically and is used as the main clock in place of the XIN clock. This allows
interrupt processing.
The oscillation stop detection function can be enabled/disabled with bit 0 and bit 1 of the oscillation stop
detection register. When this bit is set to “112,” the function is enabled. After the reset is released, the
oscillation stop detection function becomes disabled because the bit value is “002.”
Table 1.10.1 gives an specification overview of the oscillation stop detection function, Figure 1.10.2 is a
configuration diagram of the oscillation stop detection circuit and Figure 1.10.3 shows the configuration of
the oscillation stop detection register.
Table 1.10.1. Specification overview of the oscillation stop detection function
Item
Specification
Oscillation stop detectable clock and
XIN ≥ 2 MHz
frequency bandwidth
Enabling condition for oscillation stop When the oscillation stop detection bit (bit 0 of address 000C16)
detection function
and the oscillation stop detection interrupt enable bit (bit 1 of
address 000C16) are set to “1”
Operation at oscillation stop detection • Oscillation stop detection interrupt occurs
Notes on STOP mode, low power
Before stopping the main clock (XIN-XOUT), set the
dissipation mode, and ring oscillator
oscillation stop detection enable bit to “0” to disable the
mode
oscillation stop detection function. Enable main clock
(XIN-XOUT) oscillation and after the oscillation stabilizes,
set the bit to “1” again.
Notes on WAIT mode
If the peripheral function clock is stopped in WAIT mode
with the WAIT mode peripheral function clock stop bit
(bit 2 of the address 000616), oscillation stop will be detected.
Do not stop the peripheral function clock in WAIT mode.
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Mitsubishi microcomputers
M30100/M30102 Group
Oscillation Stop Detection
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Compulsory discharge when CM20=0
Pulse generation
circuit for clock
edge detection
and charge/
discharge control
fMAIN
(Note)
Charge/discharge
circuit
Oscillation stop
detection interrupt
generating circuit
Watchdog
timer
interrupt
CM21
To the CPU
CM22
CM14
Main clock switch control
Ring oscillator
Main clock
To the main clock
division circuit
#:When XIN is supplied, this repeats charge and discharge with pulses by XIN edge detection.
When XIN is not supplied, this continues charging. When the charge exceeds a certain level,
it regards the oscillation as stopped.
Note: As for the fMAIN, refer to Figure 1.8.3 clock generating circuit.
Figure 1.10.1. Oscillation stop detection circuit
Oscillation stop detection register (Note 5)
b7
b6
b5
b4
0 0 0 0
b3
b2
b1
b0
Symbol
CM2
Bit symbol
Address
000C16
When reset
0416
Bit name
R W
Function
CM20
Oscillation stop
detection bit
0: The function is invalid.
1: The function is valid. (Note 1)
CM21
Oscillation stop detection
interrupt enable bit
0: Disabled
1: Enabled
(Note 2)
CM22
Main clock switch bit
0: Select XIN clock.
1: Select ring oscillator.
(Note 3)
CM23
0: XIN oscillating normally
Clock monitor bit (Note 4) 1: XIN stopping abnormally
Reserved bit
Always set to "0"
Note 1: Set to “0” before stopping the oscillation of the main clock (XIN-XOUT).
(stop mode, low power dissipation mode, ring oscillation mode)
An oscillation stop is detected if the oscillation of the main clock (XIN-XOUT) is
stopped when the following two conditions are satisfied: (1) the oscillation stop
detection function is valid and (2) CM21=1.
Note 2: Valid when CM20=1.
Note 3: CM22 bit switches to “1“ automatically if an oscillation stop is detected when
both CM20 bit and CM 21 bit are “1”. CM22 bit cannot be cleared when CM23=1.
Note 4: This bit is valid when CM20 bit is “1”. Use this bit for the purpose of confirming
XIN operation for oscillation stop detection interrupt execution.
Note 5: In case of writing to this register, set bit 0 of the protect register(000A16) to "1".
Figure 1.10.2. Oscillation stop detection register
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Oscillation Stop Detection
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Oscillation stop detection bit (CM20)
You can start the oscillation stop detection by setting this bit to "1" and CM21=1 (oscillation stop detection
interrupt enabled). The detection is not executed when this bit is set to "0" or in reset status. Be sure to set
this bit to "0" before setting for the stop-mode. Set this bit again to "1" after release from stop-mode. Set
this bit to "0" also before setting the main clock stop bit (bit 5 at 000616) to "1".
Do not set this bit to "1" if the frequency of XIN is lower than 2 MHz.
An oscillation stop is detected if CM02=“1” (peripheral function clock has been set for stop in wait mode)
and the mode is shifted to wait.
Oscillation stop detection interrupt enable bit (CM21)
When CM20=1 and CM21=1, an oscillation stop detection interrupt is generated if an abnormal stop of
XIN is detected. The ring oscillator starts operation instead of the XIN clock which stopped abnormally.
The operation goes further with the main clock supplied from the ring oscillator. For the oscillation stop
detection interrupt, judgment on the interrupt condition is necessary, because this interrupt shares the
vector table with watchdog timer interrupt. Figure 1.10.3 shows flow of the judgment with oscillation stop
detection interrupt processing program.
Main clock switch bit (CM22)
When setting this bit to "1", the ring oscillator is selected as main clock. At this time, the ring oscillator
starts simultaneously if it has been stopped (CM14=1). This bit is cleared only when CM23 is "0" (when
XIN is oscillating).
If an oscillation stop is detected while both CM20 and CM21 are “1”, this bit automatically switches to “1”.
When this bit is set to “1”, the ring oscillation stop bit (bit 4 of address 000716) is automatically set to “0”.
Clock monitor bit (CM23)
You can see the operation status of the XIN clock. When this bit is "0", XIN is operating correctly. You can
check the oscillation status of XIN when an oscillation stop detection interrupt is generated or after reset.
When oscillation stop detection is invalid (CM20=“0”), the clock monitor bit is “0”.
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M30100/M30102 Group
Oscillation Stop Detection
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Oscillation stop detection interrupt
or watchdog timer interrupt
is generated
Read oscillation stop
detection register
CM23=1?
NO
YES
CM21=1 and
CM22=1?
NO
YES
Clear CM21 bit (Note)
Jump to the execution
program for oscillation stop
detection interrupt
Jump to the execution
program for watchdog timer
interrupt
Note: Disables multiple interrupts of oscillation stop detection and let watchdog timer
take priority.
Figure 1.10.3. Flow of the judgment
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Protection
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.11.1 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P0 direction register
(address 00E216) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P0.
If, after "1" (write-enabled) has been written to bit "enables writing to port P0 direction register" (bit 2 at
address 000A16), a value is written to any address, the bit automatically reverts to "0" (write-inhibited).
The system clock control registers 0 and 1 and oscillation stop detection register write-enable bit (bit 0 at
000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return
to “0” after a value has been written to an address. The program must therefore be written to return these
bits to “0”.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Bit symbol
PRC0
Address
000A16
When reset
XXXXX0002
Bit name
Function
Enables writing to system clock
0 : Write-inhibited
control registers 0 and 1 (addresses 1 : Write-enabled
000616 and 000716) and oscillation
stop detection register (address 000
C16)
PRC1
Enables writing to processor mode
registers 0 and 1(addresses 000416
and 000516)
0 : Write-inhibited
1 : Write-enabled
PRC2
Enables writing to port P0 direction
register (address 00E216) (Note)
0 : Write-inhibited
1 : Write-enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
AA
AA
AAAA
R W
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 1.11.1. Protect register
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of Interrupt
Type of Interrupts
Figure 1.12.1 lists the types of interrupts.
Hardware
Special
Peripheral I/O*1
Interrupt
Software
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
_______
INT instruction
Reset
DBC
Oscillation stop detection/watchdog timer
Single step
Address matched
UART0 receive interrupt
________
*1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.12.1. Classification of interrupts
• Maskable interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag (I
flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”.
The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
_______
• INT interrupt
_______
An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the
INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so
_______
executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt
does.
_______
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select
the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the
interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So
far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
_______
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Interrupts
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M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
• UART0 receive interrupt
UART0
receive interrupt occurs when UART1 is received. This interrupt can be enabled with bit 2 of
_______
the INT0 input filter select register (address 001E16).
This
interrupt is exclusively for the debugger, do not use it in other circumstances.
_______
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Oscillation stop detection/watchdog timer interrupt
Generated by the oscillation stop detection or watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag
(D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions.
The interrupt vector table is
_______
the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O
interrupts are maskable interrupts.
• Key-input interrupt
___
A key-input interrupt occurs if a falling or rising edge is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer X interrupt
This is an interrupts that timer X generates.
• Timer Y interrupt
This is an interrupt that timer Y generates.
• Timer Z interrupt
This is an interrupt that timer Z generates.
•Timer C interrupt
This is an interrupt that timer C generates.
•CNTR0 interrupt
This interrupt occurs if a falling or rising edge is input to the CNTR0 pin.
•TCIN interrupt
This interrupt occurs if a falling edge, rising edge or both edges are input to the TCIN pin. This interrupt
also occurs
with the RING512.
________
_______
• INT0
to
INT3
interrupt
______
_______
INT0
to
INT2
interrupts occur if any one of a rising edge, a falling edge or a both-edge
is input to the
______
_______
______
INT pin. INT3 inerrupt occurs if either a falling edge or a both-edge is input to the INT pin.
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.12.2 shows format for
specifying interrupt vector addresses.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
MSB
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
Low address
Mid address
0000
High address
0000
0000
Figure 1.12.2. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.12.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.12.1. Interrupt and fixed vector address
Interrupt source
Vector table addresses
Undefined instruction
Overflow
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
BRK instruction
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
FFFE416 to FFFE716
If the vector is filled with FF16, program execution starts from
Address match
FFFE816 to FFFEB16
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Single step (Note)
Oscillation stop detection/
FFFEC16 to FFFEF16
FFFF016 to FFFF316
Do not use
DBC (Note)
FFFF416 to FFFF716
Do not use
UART0 receive (Note)
Reset
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
Do not use
watchdog timer
________
Note: Interrupts used for debugging purposes only.
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Interrupts
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the
first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the
INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes.
Set the first address of the interrupt routine in each vector table. Table 1.12.2 shows the interrupts
assigned to the variable vector tables and addresses of vector tables.
Table 1.12.2. Interrupt causes (variable interrupt vector addresses)
Software interrupt number
Vector table address
Interrupt source
Address (L) to address (H)
Software interrupt number 0
+0 to +3 (Note)
BRK instruction
Software interrupt number 13
+52 to +55 (Note)
Key input interrupt
Software interrupt number 14
+56 to +59 (Note)
A-D
Software interrupt number 17
+68 to +71 (Note)
UART0 transmit
Software interrupt number 18
+72 to +75 (Note)
UART0 receive
Software interrupt number 19
+76 to +79 (Note)
UART1 transmit
Software interrupt number 20
+80 to +83 (Note)
UART1 receive
Software interrupt number 21
+84 to +87 (Note)
Timer 1
Software interrupt number 22
+88 to +91 (Note)
Timer X
Software interrupt number 23
+92 to +95 (Note)
Timer Y
Software interrupt number 24
+96 to +99 (Note)
Timer Z
Software interrupt number 25
+100 to +103 (Note)
CNTR0
Software interrupt number 26
+104 to +107 (Note)
TCIN
Software interrupt number 27
+108 to +111 (Note)
Timer C
Software interrupt number 28
+112 to +115 (Note)
INT3
Software interrupt number 29
+116 to +119 (Note)
INT0
Software interrupt number 30
+120 to +123 (Note)
INT1
Software interrupt number 31
+124 to +127 (Note)
INT2
Software interrupt number 32
+128 to +131 (Note)
to
Software interrupt number 63
to
+252 to +255 (Note)
Software interrupt
Remarks
Cannot be masked by I flag
Cannot be masked by I flag
Note : Address relative to address in interrupt table register (INTB).
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Interrupts
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select
bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are
located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL
are located in the flag register (FLG).
Figure 1.12.3 shows the interrupt control registers.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt control register
AAA
AA
A
AAA
AA
A
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KUPIC
ADIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
T1IC
TXIC
TYIC
TZIC
CNTR0IC
TCINIC
TCIC
INT3IC
Bit symbol
ILVL0
Address
004D16
004E16
005116, 005316
005216, 005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Interrupt request bit
Function
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
AA
AAA
A
AA
AA
R
W
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
AAA
A
AA
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INTiIC(i=0, 1, 2)
Bit symbol
ILVL0
Address
005D16, 005E16
005F16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
When reset
XX00X0002
XX00X0002
Interrupt request bit
Polarity select bit
Reserved bit
Function
b2 b1 b0
AA
AA
AA
AAA
A
AA
AA
AAA
A
R
W
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
(Note 1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
Figure 1.12.3. Interrupt control register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Enable Flag (I Flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.12.3 shows the settings of interrupt priority levels and Table 1.12.4 shows the interrupt levels
enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.12.3. Settings of interrupt priority levels
Table 1.12.4. Interrupt levels enabled according
to the contents of the IPL
Interrupt priority
level select bit
b2 b1 b0
42
Interrupt priority
level
0
0
0
Level 0
(interrupt disabled)
0
0
1
Level 1
0
1
0
0
1
1
Priority
order
IPL
Enabled interrupt priority levels
IPL2 IPL1 IPL0
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Interrupt levels 2 and above are enabled
Level 2
0
1
0
Interrupt levels 3 and above are enabled
1
Level 3
0
1
1 Interrupt levels 4 and above are enabled
0
0
Level 4
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Level 5
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Level 6
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
Level 7
1
1
1
All maskable interrupts are disabled
Low
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Rewrite The Interrupt Control Register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B
#00h, 0055h
NOP
NOP
FSET
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
;
I
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B
#00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B
#00h, 0055h
POPC
FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : MOV
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. After this, the corresponding interrupt request bit becomes "0".
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag)
_______
to “0” (the U flag, however, does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed).
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time
required for executing the interrupt sequence (b). Figure 1.12.4 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
Instruction in
interrupt routine
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.12.4. Interrupt response time
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.12.5.
Table 1.12.5. Time required for executing the interrupt sequence
Interrupt vector address
Stack pointer (SP) value
Without wait
Even
Even
18 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address
000016
Address bus
Interrupt
information
Data bus
R
Indeterminate
Indeterminate
SP-2
SP-2
contents
SP-4
SP-4
contents
vec
vec+2
vec
contents
PC
vec+2
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 1.12.5. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.12.6 is set in the IPL.
Table 1.12.6. Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
Value set in the IPL
Watchdog timer
7
Reset
0
Other
Not changed
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 loworder bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the
program counter. Figure 1.12.6 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m–4
m–4
Program counter (PCL)
m–3
m–3
Program counter (PCM)
m–2
m–2
Flag register (FLGL)
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
Stack pointer
value before
interrupt occurs
Flag register
(FLGH)
Program
counter (PCH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 1.12.6. State of stack before and after acceptance of interrupt request
46
[SP]
New stack
pointer value
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note), at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.12.7 shows the operation of the saving registers.
Note: This is the stack pointer indicated by the U flag.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even)
Program counter (PCL)
[SP] – 3(Odd)
Program counter (PCM)
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
(3)
[SP] – 3 (Even)
Program counter (PCM)
(4)
[SP] – 2(Odd)
Flag register (FLGL)
[SP] – 1 (Even)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
Saved simultaneously,
all 8 bits
(1)
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.12.7. Operation of saving registers
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program
counter (PC), both of which have been saved in the stack area. Then control returns to the program that
was being executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.12.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Interrupt Priority Level Judge Circuit
This circuit selects the interrupt with the highest priority level when two or more interrupts are generated
simultaneously.
Figure 1.12.9 shows the interrupt resolution circuit.
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
________
Reset > UART0 receive > DBC > Oscillation stop detection/watchdog timer >
Peripheral I/O > Single step > Address match
Figure 1.12.8. Hardware interrupts priorities
Priority level of each interrupt
Level 0 (initial value)
High
INT1
INT3
TCIN
Timer Z
Timer X
INT2
INT0
Timer C
CNTR0
Priority of peripheral I/O
interrupts
(if priority levels are same)
Timer Y
UART1 reception
UART0 reception
A-D conversion
Timer 1
UART1 transmission
UART0 transmission
Key input interrupt
Processor interrupt priority level
(IPL)
Low
Interrupt request level
judgment output signal
Interrupt
request
accepted
Interrupt enable flag (I flag)
Address match
Oscillation stop detection/watchdog timer
DBC(Note)
UART0 reception(Note)
Reset
UART0 receive hardware
Interrupt enable bit
Note. Interrupts used for debugging purposes only.
Figure 1.12.9. Interrupt resolution circuit
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
_____
INT Interrupt
______
______
______
______
INT0 to INT3 are triggered by the edges of external inputs. The edge polarity of INT0 to INT2 is selected
using the polarity select bit (bit 4 of addresses 005D16, 005E16 and 005F16). Input to INT0 is available via
filter with three different sampling frequencies.
As to external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by
______
setting the INTi (i=0 to 3) input polarity select bit of the external input enable register (009616) to “1”. To
select both edges, set the polarity switching bit of the corresponding interrupt control register to “0” (falling
edge). To select one edge, set the polarity switching bit of the corresponding interrupt control register to
_________
either “1” (raising edge) or “0” (falling edge). Please note that when one edge is selected using INT3, the
polarity will be a falling edge.
After setting the external input enable register, clear the interrupt request bit, and then enable the corresponding input interrupt. Moreover, you should write to the external input enable bit only under conditions
where the corresponding input interrupt is disabled.
Figure 1.12.10 shows the external input related registers.
A
AA
AA
A
A
AAA
AA
External input enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
INTEN
Bit symbol
INT0EN
Address
009616
When reset
0016
Bit name
INT0 input enable bit
(Note)
Function
0 : Disabled
1 : Enabled
INT0PL
INT0 input polarity select bit
(Note)
0 : One edge
1 : Two edges
INT1EN
INT1 input enable bit
0 : Disabled
1 : Enabled
INT1PL
INT1 input polarity select bit
0 : One edge
1 : Two edges
INT2EN
INT2 input enable bit
0 : Disabled
1 : Enabled
INT2PL
INT2 input polarity select bit
0 : One edge
1 : Two edges
INT3EN
INT3 input enable bit
0 : Disabled
1 : Enabled
INT3PL
INT3 input polarity select bit
0 : One edge
1 : Two edges
R
W
A
A
A
A
A
A
A
A
AA
A
AA
A
AA
A
A
A
AA
Note : This bit must be set in condition of INT0 pin one-shot trigger invalid (INOSTG="0").
A
AA
AA
A
A
AAA
AA
INT0 input filter select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
INT0F
Function
INT0 input filter select bit
b1 b0
UART0 receive hardware
interrupt enable bit (Note)
0 : Disabled
1 : Enabled
INT0F1
INT0F2
When reset
XXXXX0002
Bit name
Bit symbol
INT0F0
Address
001E16
0
0
1
1
0 : No filter
1 : Filter with f1 sampling
0 : Filter with f8 sampling
1 : Filter with f32 sampling
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
Note: Interrupts used for debugging purposes only.
Figure 1.12.10. External input related registers
50
AA
AA
A
AA
A
R
W
–
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
_______
INT0 Input Filter
_______
The INT0 input has a digital filter which can be sampled by one of three sampling clocks. You select the
_______
sampling clock using the INT0 Input Filter Select bits, bits 1 and 0.
_______
INT0 interrupt request occurs when the sampled input level matches three times.
When selecting 'sampling with filter', the value of the port P45, if read, will be the value after filtering.
_____
Figure 1.12.11 shows the INT0 input filter.
INT0 input filter
select bit
INT0
Digital filter
(input level
matches 3x)
Port P45
direction
register
f1
f8
f32
INT0 input enable bit
INT0 interrupt request
______
Figure 1.12.11. INT0 input filter
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CNTR0 interrupt
A CNTR0 interrupt is generated from the selected edge polarity, rising or falling edge, of the CNTR0 input
signal. The edge polarity is selected using the CNTR0 polarity select bit (bit 2 of address 008B16). When
using the CNTR0 interrupt, the port P17 direction register should be set to input.
When the pulse output mode of timer X is selected, the CNTR0 pin functions as a pulse output pin. In this
case, a CNTR0 interrupt occurs by a falling or rising edge output from the CNTR0 pin. The port P17 direction register should also be set to input at this time.
Figure 1.12.12 shows the timer X mode register.
Timer X mode register
b7
b6 b5
b4
b3
b2
b1 b0
Symbol
TXMR
Address
008B16
Bit symbol
TXMOD0
When reset
000000002
Function
Bit name
Operation mode
select bit 0, 1
TXMOD1
b1 b0
0 0 : Timer mode or
pulse period measurement mode
0 1 : Pulse output mode (Note 1)
1 0 : Event counter mode
1 1 : Pulse width measurement mode
R0EDG
CNTR0 polarity
0 : Rising edge
switching bit
1 : Falling edge
(Note 2)
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
TXOCNT
P30/TXOUT
select bit
Function varies with each operation mode
TXMOD2
Operation mode
select bit 2
0 : Except in pulse period measurement mode
1 : Pulse period measurement mode
Effectaul edge
TXEDG
(Note 3) reception flag
Function varies with each operation mode.
Timer X under
flow flag
Function varies with each operation mode.
TXUND
(Note 3)
A
A
AA
AA
AA
AA
AA
A
A
AA
AA
AA
R
W
Note 1: In the pulse output mode, the direction register of port P17 should be set to input.
Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt.
Note 3: TXEDG and TXUND were added after the product Ver.3.0 of the flash memory edition
(M30100F3/M30102F3) after the product Ver.2.0 of the mask ROM edition ( M30100Mx/
M30102Mx). Nothing is assigned to the product before this.
Figure 1.12.12 Timer X mode register
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M30100/M30102 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TCIN interrupt
A TCIN interrupt is generated from edges of a TCIN input signal or after 512 divisions of fRING.
To use TCIN input signal, set the time measurement input source switching bit (bit 7 of address 009A16) of
timer C control register 0 to "0" (TCIN). The level of input to TCIN pin is sampled by one of three sampling
clocks, f1, f8 or f32, selected with the digital filter clock select bit (bits 0 and 1 of address 009B16). The input
level is determined when the sampled input level matches three times. (However, if the port P33 is read, the
value will be the unfiltered value.) The edge polarity of an interrupt can be rising edge, falling edge, or both
edges using the time measurement edge trigger select bits (bits 3 and 4 of address 009A16).
When triggered after 512 divisions of fRING, set the time measurement input source switching bit (bit 7 of
address 009A16) to "1" (RING512).
Figure 1.12.13 shows the timer C control registers 0 and 1.
Timer C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC0
Address
009A16
When reset
0XX000002
Bit symbol
Bit name
Function
TCC00
Time measurement control bit
TCC01
Timer C clock select bit
b2 b1
0 0 : f1 (Note 2)
0 1 : f8
1 0 : f32
1 1 : Inhibit
TCC02
(Note 1)
TCC03
Time measurement input edge
trigger bit
TCC04
(Note 1)
0 : Time measurement disabled
1 : Time measurement enabled
b4 b3
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Inhibit
Nothing is assigned.
When write, set "0". When read, their contents are "0".
AA
AA
AA
AA
AA
AA
AA
AA
R
W
Time measurement input
0 : TCIN
source switching bit
1 : RING512
(Note 1) (Note 3)
Note 1: Change this bit when time measurement is disabled.
Note 2: When using an external RC circuit for the main clock, f1 cannot be selected for the
Timer C clock.
Note 3: Set the ring oscillation stop bit (CM14) to “0” before setting this bit to “1”.
TCC07
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC1
Bit symbol
TCC10
Address
009B16
When reset
XXXXXX112
Function
Bit name
Digital filter clock select bit
TCC11
(Note)
b1 b0
0 0 : Cannot be used
0 1 : f1
1 0 : f8
1 1 : f32
AA
AA
AA
R
W
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Note : Input edge becomes active when the same value from TCIN pin is sampled
three times in succession.
Figure 1.12.13 Timer C control registers 0 and 1
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key Input Interrupt
When the direction register of any of P10 to P13 is set for input and the KIi (i=0 to 3) input enable bit of this
port is set for enabled, if a falling or rising edge is input to that port, a key input interrupt is generated. A key
input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode.
Figure 1.12.14 shows the block diagram of the key input interrupts. When the appropriate signal (“L” for a
pin that has falling edge selected and “H” for a pin that has rising edge selected) is input to a pin for the
input inhibit process has not been executed, inputs to the other pins are not detected as interrupts.
You should overwrite the KIi (i=0 to 3) input polarity select bit or the KIi (i =0 to 3) input enable bit only under
conditions where the key input interrupt is disabled. After overwriting the KIi (i=0 to 3) input polarity select
bit or the KIi (i=0 to 3) input enable bit, clear the interrupt request bit, and then enable the key input interrupt.
Port P10-P13
pull-up select bit
Pull-up
transistor
Key input interrupt control register (address 004D16)
Port P13
direction register
K13 input enable bit
Port P13
direction register
P13/KI3
K13 input polarity
select bit
K12 input enable bit
Pull-up
transistor
Port P12
direction register
Interrupt control
circuit
P12/KI2
K12 input
polarity
select bit
K11 input enable bit
Pull-up
transistor
Key input interrupt
request
Port P11
direction register
P11/KI1
K11 input
polarity
select bit
K10 input enable bit
Port P10
direction register
Pull-up
transistor
P10/KI0
K10 input
polarity
select bit
Figure 1.12.14. Block diagram of key input interrupt
AA
A
AA
A
AAA
AA
A
Key input enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
KIEN
Bit symbol
Bit name
When reset
0016
Function
KI0EN
KI0 input enable bit
0 : Disabled
1 : Enabled
KI0PL
KI0 input polarity select bit
0 : Falling edge
1 : Rising edges
KI1EN
KI1 input enable bit
0 : Disabled
1 : Enabled
KI1PL
KI1 input polarity select bit
0 : Falling edge
1 : Rising edges
KI2EN
KI2 input enable bit
0 : Disabled
1 : Enabled
KI2PL
KI2 input polarity select bit
0 : Falling edge
1 : Rising edges
KI3EN
KI3 input enable bit
0 : Disabled
1 : Enabled
KI3PL
KI3 input polarity select bit
0 : Falling edge
1 : Rising edges
Figure 1.12.15. Key input enable register
54
Address
009816
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
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M30100/M30102 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
An address match interrupt is generated immediately before the instruction at the address indicated by the
address match interrupt register is executed. Two address match interrupts can be set, each of which can
be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not
affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the
program counter (PC) for an address match interrupt varies depending on the instruction being executed.
Figure 1.12.16 shows the address match interrupt-related registers.
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
Bit symbol
Bit name
Function
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
Function
Address setting register for address match interrupt
When reset
X0000016
X0000016
A
Values that can be set R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
Figure 1.12.16. Address match interrupt-related registers
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Interrupts
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Even if the address 0000016 is read out by software, “0” is set to the enabled highest priority interrupt
source request bit. Therefore, interrupt can be canceled and unexpected interrupt can occur.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the
stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset,
generating any interrupts is prohibited.
(3) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 to
_______
INT3 regardless of the CPU operation clock.
________
_______
• When changing a polarity of pins INT0 to INT3, the interrupt request bit may become "1". Clear the
______
interrupt request bit after changing the polarity. Figure 1.12.17 shows the switching condition of INT
interrupt request.
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 1.12.17. Switching condition of INT interrupt request
(4) Changing interrupt control register
See "Rewrite The Interrupt Control Register".
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Watchdog Timer
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt
or reset is generated when an underflow occurs in the watchdog timer. A watchdog timer interrupt or reset
is selected by bit 2 of the processor mode register 1. When XIN is selected for the BCLK, bit 7 of the
watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128).
When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog
timer control register (address 000F16).
When XIN is selected in BCLK
Watchdog timer cycle =
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
BCLK
When XCIN is selected in BCLK
Watchdog timer cycle =
Prescaler division ratio (2) x watchdog timer count (32768)
BCLK
For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is
approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 1.13.1 shows the block diagram of the watchdog timer. Figure 1.13.2 shows the watchdog timerrelated registers.
Prescaler
1/16
BCLK
1/128
“CM07 = 0”
“WDC7 = 0”
“CM07 = 0”
“WDC7 = 1”
"PM12=0"
Watchdog timer
interrupt request
Watchdog timer
"PM12=1"
Reset
“CM07 = 1”
1/2
Write to the watchdog timer
start register
(address 000E16)
Set to
“7FFF16”
RESET
Figure 1.13.1. Block diagram of watchdog timer
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M30100/M30102 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
WDC
Address
000F16
Bit symbol
When reset
000XXXXX2
Function
Bit name
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
AA
AA
A
AA
A
AA
A
R W
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
A
R W
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol
PM1
Address
000516
Bit symbol
Bit name
When reset
00XXX0X02
Function
Must always be set to “0”
Reserved bit
Nothing is assigned.
AA
A
AA
A
AA
A
R W
In an attempt to write to this bits, write “0”. The value, if read, turns
out to be indeterminate.
PM12
WDT interrupt/reset
switching bit
0 : Watchdog timer interrupt
1 : Reset (Note 2)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Reserved bit
Must always be set to “0”
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Note 2: After setting this bit to "1", can not change to "0" by software.
Figure 1.13.2. Watchdog timer control and start registers
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Timer
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
The microcomputer has four 8-bit timers and one 16-bit timer. The four 8-bit timers are Timer 1, Timer X,
Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has time
measurement function. All these timers function independently. The count source for each timer is the
operating clock that regulates the timing of timer operations such as counting and reloading.
Table 1.14.1 shows functional comparison.
Table 1.14.1. Functional comparison
Timer1
Configuration
Count
Count source (Note)
TimerX
TimerY
TimerZ
TimerC
16-bit
free-run
timer
Up
8-bit timer
with 8-bit
prescaler
Down
8-bit timer
with 8-bit
prescaler
Down
8-bit timer
with 8-bit
prescaler
Down
8-bit timer
with 8-bit
prescaler
Down
•f1
•f8
•f32
•fc32
•f1
•f8
•f32
•fc32
•f1
•f8
•fRING
•fc32
•f1
•f1
•f8
•f8
•TmrY underflow •f32
•fc32
Timer mode
Pulse output mode
Event counter mode
√
−
−
√
√
√
√
−
−
√
−
−
−
−
−
Pulse width
measurement mode
Pulse period
measurement mode
Programmable waveform
generation mode
Programmable one-shot
generation mode
Programmable wait
one-shot generation mode
Time measurement
−
√
−
−
−
−
√
−
−
−
−
−
√
√
−
−
−
−
√
−
−
−
−
√
−
Input pin
−
−
−
−
−
INT0
√
TCIN
Output pin
−
−
CNTR0
CNTR0
TXOUT
TmrX int
CNTR0 int
√
TYOUT
TZOUT
−
TmrY int
TmrZ int
√
√
Function
Related interrupt
Timer stop
Tmr1 int
−
_____
TmrC int
TCIN int
√
Note: When using an external RC circuit for the main clock, f1 cannot be selected for the count source.
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Timer 1
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer 1
Timer 1 is an 8-bit timer with an 8-bit prescaler. Figure 1.14.1 shows the block diagram of Timer 1. The
timer constantly counts an internally generated count source (clock source). The count source after reset
is set to f1. The timer cannot stop counting. Table 1.14.2 shows the specifications of Timer 1 and Figure
1.14.2 shows Timer 1 related registers.
Peripheral data bus
Clock source
selection
f1
f8
f32
fC32
Reload register (8)
Reload register (8)
Counter (8)
Counter (8)
fP1
Prescaler 1 (address 008816)
Timer 1 interrupt
request bit
Timer 1 (address 008916)
Figure 1.14.1. Block diagram of Timer 1
Table 1.14.2. Specifications of Timer 1 (Timer mode)
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio
Count start condition
1/(n+1)/(m+1) n : Set value of Prescaler 1, m: Set value of Timer 1
After reset
Count stop condition
Disable to stop counting
Interrupt request generation timing When Timer 1 underflows
Read from timer
Count value can be read out by reading Timer 1 register.
Same applies to Prescaler 1 register.
Write to timer
When a value is written to Timer 1 register, it is written to both reload register and
counter.
Same applies to Prescaler 1 register.
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Timer 1
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Prescaler 1
b7
b0
Symbol
PRE1
Address
008816
When reset
XX16
AA
Function
Values that can be set
When set value = n, Prescaler 1 divides the internal count
source by n+1
0016 to FF16
R W
Timer 1
b7
b0
Symbol
T1
Address
008916
Function
When reset
XX16
A
AA
A
AA
Values that can be set
When set value = m, Timer 1 divides the underflow of
Prescaler 1 by m+1
0016 to FF16
R W
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSS
Address
008E16
Bit symbol
TXCK0
When reset
0016
Bit name
Timer X count source
select bit
TXCK1
(Note 5)
TYCK0
Timer Y count source
select bit
TYCK1
(Note 2)
(Note 5)
TZCK0
Timer Z count source
select bit
TZCK1
(Note 4)
(Note 5)
T1CK0
Timer 1 count source
select bit
T1CK1
Function
b1 b0
0 0 : f1 (Note 1)
0 1 : f8
1 0 : f32
1 1 : fC32
b3 b2
0 0 : f1 (Note 1)
0 1 : f8
1 0 : Ring oscillator output (Note 3)
1 1 : fC32
b5 b4
0 0 : f1 (Note 1)
0 1 : f8
1 0 : Timer Y underflow
1 1 : fC32
b7 b6
0 0 : f1 (Note 1)
0 1 : f8
1 0 : f32
1 1 : fC32
A
A
A
A
A
A
A
A
A
RW
Note 1: When using an external RC circuit for the main clock, f1 cannot be selected for the
count source.
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Note 3: When attempting to select ring oscillator output, set the ring oscillation enable bit (
CM14) of the system clock control register (address 000716) for oscillation enabled.
Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and
f1 for count source.
Note 5: Avoid switching a count source, while a counter is inprogness. Timer counter should
be stopped before switching a count source.
Figure 1.14.2. Timer 1-related register
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Mitsubishi microcomputers
M30100/M30102 Group
Timer X
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Timer X is an 8-bit timer with an 8-bit prescaler. Figure 1.14.3 shows the block diagram of Timer X.
Figures 1.14.4 and 1.14.5 shows the Timer X-related registers.
Timer X has the five operation modes listed as follows:
• Timer mode:
• Pulse output mode:
The timer counts an internal count source (clock source).
The timer counts an internal count source and outputs the pulses
• Event counter mode:
whose polarity is inverted at the timer the timer underflows.
The timer counts pulses from an external source.
• Pulse width measurement mode: The timer measures an external pulse's pulse width.
• Pulse period measurement mode:The timer measures an external pulse's period.
Peripheral data bus
Clock source
selection
• Timer
• Pulse period
measurement
• Pulse output
f1
f8
f32
Reload register (8)
• Pulse width
measurement
fC32
Reload register (8)
fPX
• Event counter
Counter (8)
Counter (8)
Prescaler X (address 008C16)
Timer X (address 008D16)
Timer X interrupt
request bit
Timer X count
start flag
CNTR0 interrupt
request bit
Polarity
switching
CNTR0
"1"
Pulse output
Q
Toggle flip-flop
Q
"0"
P30/TXOUT select bit
T
R
CNTR0 polarity
switching bit
TXOUT
Timer X latch write
Pulse output mode
Figure 1.14.3. Block diagram of Timer X
Timer X mode register
b7
b6 b5
b4
b3
b2
b1 b0
Symbol
TXMR
Bit symbol
TXMOD0
Address
008B16
When reset
000000002
Function
Bit name
Operation mode
select bit 0, 1
TXMOD1
b1 b0
0 0 : Timer mode or
pulse period measurement mode
0 1 : Pulse output mode (Note 1)
1 0 : Event counter mode
1 1 : Pulse width measurement mode
AA
A
AA
A
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
R0EDG
CNTR0 polarity
0 : Rising edge
switching bit
1 : Falling edge
(Note 2)
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
TXOCNT
P30/TXOUT
select bit
Function varies with each operation mode
TXMOD2
Operation mode
select bit 2
0 : Except in pulse period measurement mode
1 : Pulse period measurement mode
Effectaul edge
TXEDG
(Note 3) reception flag
Function varies with each operation mode.
Timer X under
TXUND
(Note 3) flow flag
Function varies with each operation mode.
R
W
Note 1: In the pulse output mode, the direction register of port P17 should be set to input.
Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt.
Note 3: TXEDG and TXUND were added after the product Ver.3.0 of the flash memory edition
(M30100F3/M30102F3) after the product Ver.2.0 of the mask ROM edition ( M30100Mx/
M30102Mx). Nothing is assigned to the product before this.
Figure 1.14.4. Timer X-related registers (1)
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Timer X
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Prescaler X
b7
b0
Symbol
PREX
Address
008C16
Function
When reset
FF16
AA
AA
AA
A
A
AA
AA
Values that can be set
• Timer mode
Internal count source is counted
0016 to FF16
• Pulse output mode
Internal count source is counted
0016 to FF16
• Event counter mode
Externally input pulses are counted
0016 to FF16
• Pulse width measurement mode
Pulse width of externally input pulses is measured
(Internal count source is counted)
0016 to FF16
• Pulse period measurement mode
Pulse period of externally input pulses is measured
(Internal count source is counted)
0016 to FF16
R W
Timer X
b7
b0
Symbol
TX
Address
008D16
Function
When reset
FF16
AA
Values that can be set
0016 to FF16
Underflow of Prescaler X is counted
R W
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSS
Address
008E16
Bit symbol
TXCK0
When reset
0016
Bit name
Timer X count source
select bit
TXCK1
(Note 5)
TYCK0
Timer Y count source
select bit
TYCK1
(Note 2)
(Note 5)
TZCK0
Timer Z count source
select bit
TZCK1
(Note 4)
(Note 5)
T1CK0
Timer 1 count source
select bit
T1CK1
Function
b1 b0
0 0 : f1 (Note 1)
0 1 : f8
1 0 : f32
1 1 : fC32
b3 b2
0 0 : f1 (Note 1)
0 1 : f8
1 0 : Ring oscillator output (Note 3)
1 1 : fC32
b5 b4
0 0 : f1 (Note 1)
0 1 : f8
1 0 : Timer Y underflow
1 1 : fC32
b7 b6
0 0 : f1 (Note 1)
0 1 : f8
1 0 : f32
1 1 : fC32
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
Note 1: When using an external RC circuit for the main clock, f1 cannot be selected for the
count source.
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Note 3: When attempting to select ring oscillator output, set the ring oscillation enable bit (
CM14) of the system clock control register (address 000716) for oscillation enabled.
Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and
f1 for count source.
Note 5: Avoid switching a count source, while a counter is inprogness. Timer counter should
be stopped before switching a count source.
Figure 1.14.5. Timer X-related registers (2)
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Mitsubishi microcomputers
M30100/M30102 Group
Timer X
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.3) Figure 1.14.6
shows the Timer X mode register in timer mode.
Table 1.14.3. Specifications of timer mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
Divide ratio
counting
1/(n+1)/(m+1) n : Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count stop condition
Count start flag is set (=1)
Count start flag is reset (=0)
Interrupt request generation timing When Timer X underflows [Timer X interruption]
CNTR0 pin function
Programmable I/O port, or CNTR0 interrupt input pin
TXOUT pin function
Read from timer
Programmable I/O port
Count value can be read out by reading Timer X register.
Write to timer
Same applies to Prescaler X register.
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
TXMR
Bit symbol
TXMOD0
Address
008B16
When reset
000000002
Function
Bit name
Operation mode
select bit 0, 1
b1 b0
0 0 : Timer mode
TXMOD1
R0EDG
CNTR0 polarity
0 : Rising edge
switching bit
(Note 1) 1 : Falling edge
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
TXOCNT
0 : In timer mode, set to "0"
TXMOD2
0 : In timer mode, set to "0"
TXEDG
Invalid in timer mode.
When write, set "0". When read, this contents is indeteminate.
TXUND
Invalid in timer mode.
When write, set "0". When read, this contents is indeteminate.
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt.
Figure 1.14.6. Timer X mode register in timer mode
64
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AA
AA
AA
AA
AAA
A
AA
AA
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Mitsubishi microcomputers
M30100/M30102 Group
Timer X
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Pulse output mode
In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin
a pulse whose polarity is inverted each time the timer underflows. (See Table 1.14.4) Figure 1.14.7
shows Timer X mode register in pulse output mode.
Table 1.14.4. Specifications of pulse output mode
Item
Specification
Count source
Count operation
f1, f8, f32, fC32
• Down count
Divide ratio
• When the timer underflows, it reloads the reload register contents before continuing counting
1/(n+1)/(m+1) n : Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count stop condition
Count start flag is set (=1)
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 output [CNTR0 interruption] (Note)
CNTR0 pin function
TXOUT pin function
Pulse output
Programmable I/O port or pulse output (Inverted waveform of the pulse output from the
Read from timer
CNTR0 pin)
Count value can be read out by reading Timer X register.
Write to timer
Same applies to Prescaler X register.
When a value is written to Timer X register, it is written to both reload register and counter.
Select function
Same applies to Prescaler X register.
• Pulse output function
Each time the timer underflows, the TXOUT pin’s polarity is reversed
• CNTR0 polarity switching function
The polarity level at starting of pulse output can be selected to be "High" or "Low" with software.
Note: When setting the timer X mode register to pulse output mode, the CNTR0 interrupt request bit becomes "1".
Thus, when using an CNTR0 interrupt, the CNTR0 interrupt request bit must be set to "0" after setting the timer
X mode register.
Timer X mode register
b7
b6 b5
0
b4
b3
b2
b1 b0
0
1
Symbol
TXMR
Bit symbol
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
Address
008B16
When reset
000000002
Operation mode
select bit 0, 1
b1 b0
0 1 : Pulse output mode
(Note 1)
CNTR0 polarity
0: Output starts at "H" (Interrupt at rising edge)
switching bit
1: Output starts at "L" (Interrupt at falling edge)
(Note 3)
Timer X count
start flag
0 : Stops counting
1 : Starts counting
P30/TXOUT
select bit
0 : Port P30
1 : TXOUT output
A
A
AA
AA
AA
AA
AA
AA
A
AA
A
AA
R
Function
Bit name
(Note 2)
0 : Set to "0" in pulse output mode
TXEDG
Invalid in pulse output mode.
When write, set "0". When read, this contents is indeteminate.
TXUND
Invalid in pulse output mode.
When write, set "0". When read, this contents is indeteminate.
W
Note 1: In the pulse output mode, the direction register of port P17 must be set to input.
Note 2: Output is set regardless of the setting of the direction register of port P30.
Note 3: This bit should rewrite with inhibiting the CNTR0 interrupt.
Figure 1.14.7. Timer X mode register in pulse output mode
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Mitsubishi microcomputers
M30100/M30102 Group
Timer X
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Event counter mode
In this mode, the timer counts an external signal fed to CNTR0 pin. (See Table 1.14.5) Figure 1.14.8
shows Timer X mode register in event counter mode.
Table 1.14.5. Specifications of event counter mode
Item
Specification
Count source
External signals fed to CNTR0 pin (Active edge is selected by software)
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
Divide ratio
counting
1/(n+1)/(m+1) n : Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count stop condition
Count start flag is set (=1)
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption]
CNTR0 pin function
TXOUT pin function
Count source input
Programmable I/O port
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Select function
• CNTR0 polarity switching function
The active edge of count source can be selected to be the rising or the falling edge with
software.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
1 0
Symbol
TXMR
Bit symbol
TXMOD0
TXMOD1
R0EDG
TXS
Address
008B16
When reset
000000002
Function
Bit name
Operation mode
select bit 0, 1
b1 b0
1 0 : Event counter mode
CNTR0 polarity
0: Counts at rising edge (Interrupt at rising edge)
switching bit
(Note 1) 1: Counts at falling edge(Interrupt at falling edge)
Timer X count
start flag
0 : Stops counting
1 : Starts counting
TXOCNT
0 : Set to "0" in event counter mode
TXMOD2
0 : Set to "0" in event counter mode
TXEDG
Invalid in event counter mode.
When write, set "0". When read, this contents is indeteminate.
TXUND
Invalid in event counter mode.
When write, set "0". When read, this contents is indeteminate.
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt.
Figure 1.14.8. Timer X mode register in event counter mode
66
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AA
AA
AA
A
AA
AA
AA
AA
AA
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Mitsubishi microcomputers
M30100/M30102 Group
Timer X
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width measurement mode
In this mode, the timer measures the pulse width of an external signal fed to CNTR0 pin. (See Table
1.14.6) Figure 1.14.9 shows the Timer X mode register in pulse width measurement mode. Figure
1.14.10 shows an operation example in pulse width measurement mode.
Table 1.14.6. Specifications of pulse width measurement mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• Down count
• Continuously counts the selected signal only when the measurement pulse is "H" level,
or conversely only "L" level.
• When the timer underflows, it reloads the reload register contents before continuing
counting
Count start flag is set (=1)
Count start condition
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
CNTR0 pin function
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption]
Measurement pulse input
TXOUT pin function
Read from timer
Programmable I/O port
Count value can be read out by reading Timer X register.
Write to timer
Same applies to Prescaler X register.
When a value is written to Timer X register, it is written to both reload register and counter.
Select function
Same applies to Prescaler X register.
• CNTR0 polarity switching function
The measurement pulse input can be selected to be "H" level width or "L" level width by
software.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
1 1
Symbol
TXMR
Bit symbol
TXMOD0
TXMOD1
R0EDG
TXS
Address
008B16
Function
Bit name
Operation mode
select bit 0, 1
When reset
000000002
b1 b0
1 1 : Pulse width measurement mode
CNTR0 polarity
0 : Measures “H” level width (Interrupt at rising edge)
switching bit
(Note 1) 1 : Measures “L” level width (Interrupt at falling edge)
Timer X count
start flag
0 : Stops counting
1 : Starts counting
TXOCNT
0 : Set to "0" in pulse width measurement mode
TXMOD2
0 : Set to "0" in pulse width measurement mode
TXEDG
Invalid in pulse width measurement mode.
When write, set "0". When read, this contents is indeteminate.
TXUND
Invalid in pulse width measurement mode.
When write, set "0". When read, this contents is indeteminate.
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt.
AAA
A
AA
A
AA
AA
AA
AA
AA
AA
R
W
Figure 1.14.9. Timer X mode register in pulse width measurement mode
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Timer X
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Conditions: "H" level width of measurement pulse is measured. (R0EDG=1)
n = high-level: the contents of Timer X reload register, low-level: the contents of Prescaler X reload register
FFFF16
Count start
Underflow
Counter contents
n
Count stop
Count stop
Count restart
000016
Time
Set to "1" by software
Count start flag “1”
“0”
Measurement pulse “H”
(CNTR0 pin input) “L”
Cleared to “0” when interrupt request is accepted, or cleared by software
CNTR0 interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer X interrupt
request bit
“1”
“0”
Figure 1.14.10. Operation example in pulse width measurement mode
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Timer X
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Pulse period measurement mode
In this mode, the timer measures the pulse period of an external signal fed to CNTR0 pin. (See Table
1.14.7) Figure 1.14.11 shows the Timer X mode register in pulse period measurement mode.
Table 1.14.7. Specifications of pulse period measurement mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• Down count
• After valid edge of measurement pulse is input, the timer X reloads contents in the
reload register and continues counting in underflow of the second prescaler X.
Count start flag is set (=1)
Count start condition
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption or Timer
X interrupt]
CNTR0 pin function
TXOUT pin function
Measurement pulse input (Note)
Programmable I/O port
Read from timer
When reading Timer X register, the count value of buffer for read purpose can be read
out. The buffer of read purpose retains the content of Timer X register upon an active
edge of measurement pulse, and starts to read the content of Timer X register by reading Timer X.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Select function
• CNTR0 polarity switching function
The measurement period of pulse input can be selected to be a period from one rising
edge to the next rising edge or from one falling edge to the next falling edge by software.
Note: Avoid a shorter period pulse input than double prescaler X period. Longer pulse for H width and L width than the
prescaler X period should be input to the CNTR0 pin. If shorter pulse than the period is input to the CNTR0 pin, the
input may be disabled.
Timer X mode register
b7
b6 b5
b4
1 0
b3
b2
b1 b0
0
0
Symbol
TXMR
Bit symbol
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
Address
008B16
Function
Bit name
Operation mode
select bit 0, 1
When reset
000000002
b1 b0
0 0 : Pulse period measurement mode
0: Measures a measurement pulse from one
rising edge to the next rising edge
(Interrupt at rising edge)
1: Measures a measurement pulse from one
falling edge to the next falling edge
(Note 1)
(Interrupt at falling edge)
Timer X count
0 : Stops counting
start flag
1 : Starts counting
CNTR0 polarity
switching bit
0 : In pulse period measurement mode, set to "0"
Operation mode
select bit 2
1 : Pulse period measurement mode
Effectaul edge
TXEDG
(Note 2,3) reception flag
Timer X under
TXUND
(Note 2,3) flow flag
A
A
A
A
AA
A
A
A
A
A
A
A
A
AA
R
W
0 : No effectual edge
1 : Effectual edge found
0 : No under flow
1 : Under flow found
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt.
Note 2: TXEDG and TXUND are set to "0" by writing a "0" in a program. (Writing a "1" has no
effect.)
Note 3: TXEDG and TXUND were added after the product Ver.3.0 of the flash memory edition
(M30100F3/M30102F3) after the product Ver.2.0 of the mask ROM edition ( M30100Mx/
M30102Mx). Nothing is assigned to the product before this.
Figure 1.14.11. Timer X mode register in pulse period measurement mode
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Mitsubishi microcomputers
M30100/M30102 Group
Timer X
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Conditions: A period from one rising edge to the next rising edge of measurement pulse is measured. (R0EDG=0)
Timer X=0F16
fPX
Set to "1" by software
Count start flag
“1”
“0”
Count start
Measurement pulse “1”
(CNTR0 pin input)
“0”
Hold
Hold
Timer X
reloads
Timer X
reloads
Timer X
reloads
Timer X
contents (hex)
0F16
0E16 0D16 0F16 0E16 0D16 0C16 0B16 0A16 0916 0F16 0E16 0D16
0116 0016 0F16 0E16
Contents of read
purpose buffer(
Note 1)
0F16
0E16
0116 0016 0F16 0E16
0D16
(Note 2)
Effectaul edge “1”
reception flag “0”
0B16 0A16
0916
Read by software.
(Note 3)
(Note 2)
0D16
Read by software.
(Note 3)
Cleared to "0" by software.
(Note 4)
(Note 6)
Timer X “1”
underflow flag “0”
Cleared to "0" by software.
(Note 5)
Timer X interrupt “1”
request bit “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
CNTR0 interrupt “1”
request bit “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: If timer X is read out in pulse period measurement mode, the contents of the read purpose buffer can be read.
Note 2: After an active edge of measurement pulse is input, effectaul edge reception flag(TXEDG) is set to "1" when
the prescaler X underflows for the second time.
Note 3: The timer X should be read out before the next active edge is input after TXEDG is set to "1". If the timer X is
not read before the next active edge is input, the value in the read purpose buffer remains unchanged and
therefore is not updated on an active edge.
Note 4: When set to "0" by software, use a MOV instruction to write "0" to the bit 6 (TXEDG) in the timer X mode
register (008B16). At the same time, write "1" to the bit 7 (TXUND).
Note 5: When set to "0" by software, use a MOV instruction to write "0" to the bit 7 (TXUND) in the timer X more
register (008B16). At the same time, write "1" to the bit 6 (TXEDG).
Note 6: If the timer X underflow flag (TXUND) and TXEDG are both set to "1". In this case, the validity of TXUND
sholud be judged by the contents of the read purpose buffer.
Figure 1.14.12. Operation example in pulse period measurement mode
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Timer Y
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers - Timer Y Primary and Timer
Y Secondary. Figure 1.14.13 shows the block diagram of Timer Y. Figures 1.14.14 to 1.14.16 show the
Timer Y-related registers.
Timer Y has the two operation modes listed as follows:
• Timer mode: The timer counts an internal count source (clock source).
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
Peripheral data bus
Timer Y primary
(address 008316)
Clock source
selection
Reload register (8)
f1
f8
fRING
fC32
Timer Y secondary
(address 008216)
Reload register (8)
Reload register (8)
Counter (8)
Timer Y interrupt
request bit
Counter (8)
fPY
Prescaler Y (address 008116)
Timer Y (address 008316)
Timer Y count
start flag
Programmable waveform
generation mode
"1"
Q
"0"
Toggle flip-flop
TYOUT
T
Q
Port P32 register
"0"
"1"
Timer Y output
level latch
Timer Y programmable
waveform output
switching bit
Figure 1.14.13. Block diagram of Timer Y
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y operation
mode bit
When reset
000000X02
Function
0 : Timer mode
1 : Programmable waveform generation mode
(Note 1)
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y write
control bit
Function varies depending on
the operation mode
TYS
Timer Y count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
b5 b4
TZMOD0
TZMOD1
Timer Z operation
mode bit
(Note 3)
TZWC
Timer Z write
control bit
TZS
Timer Z count
start flag
AA
A
A
A
A
A
A
A
A
A
AA
A
AA
AA
R W
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation
mode
Function varies depending on
the operation mode
0 : Stops counting (Note 2)
1 : Starts counting
Note 1: In programmable waveform generation mode, port P32 is set for output regardless of the
value of the direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it
stops. Read out the count value before you stop the timer.
Note 3: When timer Z operation mode bit is set for "01", "10" or "11", port P31 is set for output
regardless of the value of the direction register.
Figure 1.14.14. Timer Y-related registers (1)
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Timer Y
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Prescaler Y
b7
Symbol
PREY
b0
Address
008116
When reset
FF16
AA
A
AA
A
AA
A
Function
Values that can be set
• Timer mode
Internal count source is counted
0016 to FF16
• Programmable waveform generation mode
Internal count source is counted
0016 to FF16
(Note)
R W
Note: When using the waveform extend function, set the value "0016" for the
Prescaler Y.
Timer Y Secondary
b7
Symbol
TYSC
b0
Address
008216
When reset
FF16
Function
Values that can be set
• Timer mode
Invalid
• Programmable waveform generation mode
(Note 1)
Underflow of Prescaler Y is counted
0016 to FF16
R W
A
(Note 2)
Note 1: The values of Timer Y Primary and Timer Y Secondary are reloaded to the
Timer Y alternately for counting.
Note 2: The count value can be read out by reading the Timer Y Primary even when
the secondary period is being counted.
Timer Y Primary
b7
Symbol
TYPR
b0
Address
008316
Function
When reset
FF16
AA
A
AA
A
Values that can be set
• Timer mode
Underflow of Prescaler Y is counted
0016 to FF16
• Programmable waveform generation mode
Underflow of Prescaler Y is counted (Note)
0016 to FF16
RW
Note: The values of Timer Y Primary and Timer Y Secondary are reloaded to the
Timer Y alternately for counting.
Timer Y, Z output control register
b7
b6 b5
b4
b3
b2
b1 b0
Symbol
TYZOC
Bit symbol
Address
008A16
When reset
XXXXX0002
Function
Bit name
TZOS
Timer Z one-shot
start bit
TYOCNT
Timer Y programmable
0 : Outputs programmable waveform
waveform generation
output switching bit (Note 2) 1 : Outputs the value of P32 port register
TZOCNT
0 : Stops one-shot
(Note 1) 1 : Starts one-shot
Timer Z programmable
0 : Outputs programmable waveform
waveform generation
output switching bit (Note 2) 1 : Outputs the value of P31 port register
A
A
A
R
W
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Note 1: The timer Z one-shot start bit is automatically cleared to "0" when the output of
one-shot waveform is completed. The timer Z one-shot start bit should be set to "0" by
program when the one-shot waveform output is terminated by setting the count
start flag to "0" during the wave form output.
Note 2: The timer Y/Z programmable waveform generaton output switching bit is valid only
when operating in programmable waveform generation mode.
Figure 1.14.15. Timer Y-related registers (2)
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Timer Y
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z waveform output control register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
PUM
Address
008416
Bit symbol
When reset
0016
Bit name
Function
Timer Y primary
waveform extension
control bit
Timer Y secondary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 1)
TZPUM0
Timer Z primary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 2)
TZPUM1
Timer Z secondary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 2)
TYOPL
Timer Y output level
latch
Function varies depending on the operation mode
TZOPL
Timer Z output level
latch
Function varies depending on the operation mode
TYPUM0
TYPUM1
INOSTG
INOSEG
INT0 pin one-shot
trigger control bit
(Timer Z)
(Note 4)
INT0 pin one-shot
trigger polarity select bit
(Timer Z)
(Note 3)
0 : No waveform extension
1 : Waveform extension (Note 1)
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid
0 : Edge trigger at falling edge
1 : Edge trigger at rising edge
A
A
A
A
A
A
A
A
A
A
RW
Note 1: When setting this bit to "1", the Prescaler Y Register must be set to "0016".
Note 2: When setting this bit to "1", the Prescaler Z Register must be set to "0016".
Note 3: This bit is valid only when INT0 input polarity select bit (bit 1 at address 009616) is
"0" (one-edge).
Note 4: This bit must be set to "1", after setting INT0 input enable bit (bit 0 at address 009616),
INT0 input polarity select bit (bit 1 at address 009616), and INT0 pin one-shot trigger
polarity select bit.
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSS
Bit symbol
TXCK0
Address
008E16
When reset
0016
Bit name
Timer X count source
select bit
TXCK1
(Note 5)
TYCK0
Timer Y count source
select bit
TYCK1
(Note 2)
(Note 5)
TZCK0
Timer Z count source
select bit
TZCK1
(Note 4)
(Note 5)
T1CK0
Timer 1 count source
select bit
T1CK1
Function
b1 b0
0 0 : f1 (Note 1)
0 1 : f8
1 0 : f32
1 1 : fC32
b3 b2
0 0 : f1 (Note 1)
0 1 : f8
1 0 : Ring oscillator output (Note 3)
1 1 : fC32
b5 b4
0 0 : f1 (Note 1)
0 1 : f8
1 0 : Timer Y underflow
1 1 : fC32
b7 b6
0 0 : f1 (Note 1)
0 1 : f8
1 0 : f32
1 1 : fC32
AA
AA
AA
AA
A
A
AA
AA
AA
AA
RW
Note 1: When using an external RC circuit for the main clock, f1 cannot be selected for the
count source.
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Note 3: When attempting to select ring oscillator output, set the ring oscillation enable bit (
CM14) of the system clock control register (address 000716) for oscillation enabled.
Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and
f1 for count source.
Note 5: Avoid switching a count source, while a counter is inprogness. Timer counter should
be stopped before switching a count source.
Figure 1.14.16. Timer Y-related registers (3)
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Timer Y
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.8) The Timer Y
secondary is unused in this mode. Figure 1.14.17 shows the Timer Y, Z mode register and Timer Y, Z
waveform output control register in timer mode.
Table 1.14.8. Specifications of timer mode
Item
Specification
Count source
f1, f8, ring oscillator output, fC32
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting (When the Timer Y underflows, the contents of the Timer Y primary reload
register is reloaded.)
• When a counting stops, the timer reloads the content of the reload register before it
stops.
Divide ratio
Count start condition
1/(n+1)/(m+1) n : Set value of Prescaler Y, m: Set value of Timer Y primary
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0) (Note 1)
Interrupt request generation timing When Timer Y underflows
TYOUT pin function
Read from timer
Programmable I/O port
Count value can be read out by reading Timer Y primary register.
Write to timer
Same applies to Prescaler Y register.
When a value is written to Timer Y Primary register, it is written to both reload register
and counter or written to only reload register. Selected by software.
Same applies to Prescaler Y register.
Select function
• Timer Y write control function
When a value is written to Timer Y Primary register, it can be selected that the value is
written to both reload register and counter or written to only reload register.
Same applies to Prescaler Z register. (Note 2)
Note 1: When the count is stopped, the Timer Y interrupt request flag becomes "1" and an interrupt may occur. Thus,
interrupts must be disabled before the count is stopped. Furthermore, set the Timer Y interrupt request flag to "0"
before starting counting again.
Note 2: If writing to the Timer Y or prescaler Y under the following conditions being filled at the same time the Timer Y
interrupt request flag becomes "1" and an interrupt occurs.
<Conditions>
• Timer Y write control bit (bit 2 of address 0080) is "0" (write to timer and reload register simultaneously)
• Timer Y count start flag (bit 3 of address 0080) is "1" (count start)
To write to the Timer Y or prescaler Y in the above state, disable interrupts before writing.
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Timer Y
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TYZMR
Address
008016
Bit symbol
Bit
TYMOD0
Timer name
Y operation
mode bit
When reset
000000X02
Function
0 : Timer mode
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
TYWC
Timer Y write
control bit
0 : Write to timer and reload register
simultaneously (Note 2)
1 : Write to reload register
TYS
Timer Y count
start flag
0 : Stops counting (Note 1)
1 : Starts counting
TZMOD0
Timer Z-related bit
TZMOD1
TZWC
TZS
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
R
W
Note 1: When this bit is cleared to "0", the timer reloads the content of the reload register
before it stops. Read out the count value before you stop the timer.
Note 2: At the TYWC bit is "0", when you write in the prescaler Y while the timer Y is
counting,the timer Y reload content of the timer Y reload register.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
TYPUM1
TZPUM0
Address
008416
When reset
0016
Bit name
Timer Y primary
waveform extension
control bit
Timer Y secondary
waveform extension
control bit
Function
Invalid in timer mode
Invalid in timer mode
Timer Z-related bits
TZPUM1
TYOPL
Timer Y output level
latch
TZOPL
Timer Z-related bits
Invalid in timer mode
INOSTG
INOSEG
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
Figure 1.14.17. Timer Y, Z mode register in timer mode
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Timer Y
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Programmable waveform generation mode
In this mode, the microcontroller, while counting the set values of Timer Y primary and Timer Y secondary alternately, outputs from the TYOUT pin a waveform whose polarity is inverted each time Timer
Y primary or Timer Y secondary underflows. (See Table 1.14.9) A counting starts by counting the set
value in the Timer Y primary. Figure 1.14.18 shows Timer Y, Z mode register in programmable waveform generation mode. Figure 1.14.19 shows the operation example.
Table 1.14.9. Specifications of programmable waveform generation mode
Item
Specification
Count source
Count operation
f1, f8, ring oscillator output, fC32
• Down count
• When the timer underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing counting.
• When a counting stops, the timer reloads the content of the reload register before it
stops.
Divide ratio
fi/(n+1)/((m+1)+(l+1))
n : Set value of Prescaler Y, m: Set value of Timer Y primary, l: Set value of Timer Y secondary
Count start condition
Count stop condition
Count start flag is set (=1)
Count start flag is reset (=0) (Note 1)
Interrupt request generation timing When Timer Y underflows during secondary period
TYOUT pin function
Pulse output (Note 2)
Read from timer
Count value can be read out by reading Timer Y primary register.
Same applies to Prescaler Y register. (Note 3)
Write to timer
When a value is written to Timer Y primary register, it is written to only reload register.
Same applies to Timer Y secondary register and Prescaler Y register. (Note 4)
Select function
• Output level latch select function
The output level of a waveform being counted during primary and secondary periods is
selectable.
• Programmable waveform generation output switching function
Can select either programmable waveform or the value of Port P32 register for output.
(Note 5)
• Waveform extend function (Note 6)
The waveform output primary period and secondary period can each be extended 0.5
cycles of the count source
Frequency when waveform extended: 2xfi/((2x(m+1))+(2x(l+1))+TYPUM0+TYPUM1)
Duty: (2x(m+1)+TYPUM0)/((2x(m+1)+TYPUM0)+(2x(l+1)+TYPUM1))
m: set value of Timer Y primary, l: set value of Timer Y secondary
TYPUM0: Timer Y primary waveform extension control bit
TYPUM1: Timer Y secondary waveform extension control bit
Note 1: When the count is stopped, the Timer Y interrupt request flag becomes "1" and an interrupt may occur. Thus,
interrupts must be disabled before the count is stopped. Furthermore, set the Timer Y interrupt request flag to "0"
before starting counting again.
Note 2: When the counting stopped, the pin is the secondary period output level.
Note 3: Even when counting the secondary period, read out the Timer Y primary register.
Note 4: The set value of Timer Y secondary register and waveform extension control bits as well as Timer Y primary
register are made effective by writing a value to the Timer Y primary register. The written values are reflected to
the waveform output from the next primary period after writing to the Timer Y primary register.
Note 5: The output is switched in sync with timer Y secondary underflow.
Note 6: When using the waveform extend function, the Prescaler Y register must be set to "0016".
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Timer Y
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
TYZMR
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y operation
mode bit
When reset
000000X02
1 : Programmable waveform generation mode
(Note 1)
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
TYWC
Timer Y write
control bit
Set to "1" in programmable waveform
generation mode
TYS
Timer Y count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
TZMOD0
AA
R W
Function
AA
AAA
A
A
A
AA
AA
AAAA
Timer Z-related bit
TZMOD1
TZWC
TZS
Note 1: Output is set for Port P32 regardless of the value of the direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register
before it stops. Read out the count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
TYPUM1
TZPUM0
Address
008416
Bit name
Timer Y primary
waveform extension
control bit
Timer Y secondary
waveform extension
control bit
Timer Z-related bits
TZPUM1
TYOPL
TZOPL
INOSTG
INOSEG
Timer Y output level
latch
Timer Z-related bits
When reset
0016
Function
0 : No waveform extension
1 : Waveform extension (Note 1)(Note 2)
0 : No waveform extension
1 : Waveform extension (Note 1)(Note 2)
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
0 : Outputs "H" for the period set by Timer Y primary and
"L" for the period set by Timer Y secondary.
"L" is outputted when the timer is stopped.
1 : Outputs "L" for the period set by Timer Y primary and
"H" for the period set by Timer Y secondary.
"H" is outputted when the timer is stopped.
Note 1: When setting this bit to "1", the Prescaler Y Register must be set to "0016".
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Figure 1.14.18. Timer Y, Z mode register and Timer Y, Z waveform output control register in
programmable waveform generation mode
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Timer Y
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Conditions: Timer Y primary=0316, Timer Y primary waveform not extended,
Timer Y secondary=0216, Timer Y secondary waveform extended,
Timer Y output level latch [TYOPL]="0"
Timer Y count source
Set to "1" by
software
Count start flag
“1”
“0”
Timer Y
secondary
reload
Timer Y
primary
reload
Timer Y
secondary
reload
Count start
03 16
The contents of Timer Y
02 16 01 16
00 16 02 16 01 16 00 16
03 16
02 16 01 16 00 16 02 16 01 16
Cleared to “0” when interrupt
request is accepted,
or cleared by software
Timer Y interrupt “1”
request bit
“0”
Timer Y output “1”
level latch
“0”
Cleared to "0"
by software
Waveform
output started
“H”
TYOUT pin output
“L”
Initialized to "L"
Waveform
output inverted
Waveform
output inverted
(Note)
A
A
Waveform
output inverted
Secondary waveform
extended
Note: The waveform output in the secondary period is inverted after 0.5 clock ( 1 clock when secondary waveform
extended) of fPY from occurrence of Timer Y interrupt request.
Figure 1.14.19. Timer Y operation example in programmable waveform generation mode
Programmable waveform generation output switching function
When the Timer Y programmable waveform generation output switching bit (bit 1 at address 008A16)
is set to 0, the output from TYOUT is inverted synchronously when the Timer Y secondary underflows.
And when set to 1, the Port P32 register value is output from TYOUT synchronously when the Timer Y
secondary underflows.
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Z
Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers - Timer Z Primary and Timer
Z Secondary. Figure 1.14.20 shows the block diagram of Timer Z. Figures 1.14.21 to 1.14.24 show the
Timer Z-related registers.
Timer Z has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source (clock source) or Timer Y underflow.
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse.
Peripheral data bus
Timer Z primary
(address 008716)
Reload register (8)
Clock source
selection
f1
f8
Counter (8)
Timer Y underflow
Timer Z count
start flag
INT0
Reload register (8)
Counter (8)
fPZ
Prescaler Z (address 008516)
fC32
Digital
filter
One edge/ both edges
input polarity select
INT0 input polarity select bit
•Programmable waveform generation mode
•Programmable one-shot generation mode
•Programmable wait one-shot generation mode
INT0 input enable bit
Timer Z secondary
(address 008616)
Reload register (8)
Timer Z (address 008716)
•Programmable one-shot generation mode
•Programmable wait one-shot generation mode
Timer Z one-shot start bit
Polarity
select
INT0 one-shot trigger
polarity select bit
"1"
Q
"0"
Toggle flip-flop
TZOUT
Port P31 register
"1"
Timer Z programmable
Timer Z interrupt
request bit
"0"
T
Q
Timer Z output
level latch
Figure 1.14.20. Block diagram of Timer Z
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Mitsubishi microcomputers
M30100/M30102 Group
Timer Z
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y operation
mode bit
When reset
000000X02
Function
0 : Timer mode
1 : Programmable waveform generation mode
(Note 1)
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y write
control bit
Function varies depending on
the operation mode
TYS
Timer Y count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
b5 b4
TZMOD0
TZMOD1
Timer Z operation
mode bit
(Note 3)
TZWC
Timer Z write
control bit
TZS
Timer Z count
start flag
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation
mode
Function varies depending on
the operation mode
0 : Stops counting (Note 2)
1 : Starts counting
A
A
A
A
A
A
A
A
A
R W
Note 1: In programmable waveform generation mode, port P32 is set for output regardless of the
value of the direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it
stops. Read out the count value before you stop the timer.
Note 3: When timer Z operation mode bit is set for "01", "10" or "11", port P31 is set for output
regardless of the value of the direction register.
Figure 1.14.21. Timer Z-related registers (1)
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Prescaler Z
b7
b0
Symbol
PREZ
Address
008516
Function
When reset
FF16
A
AA
A
AA
AA
AA
AA
Values that can be set
• Timer mode
Internal count source or Timer Y underflow is counted
0016 to FF16
• Programmable waveform generation mode
Internal count source or Timer Y underflow is counted
0016 to FF16
(Note)
• Programmable one-shot generation mode
Internal count source or Timer Y underflow is counted
0016 to FF16
(Note)
• Programmable wait one-shot generation mode
Internal count source or Timer Y underflow is counted
0016 to FF16
(Note)
Note: When using the waveform extend function, set the value "0016" for the
Prescaler Z.
Timer Z Secondary
b7
b0
Symbol
TZSC
Address
008616
Function
When reset
FF16
Values that can be set
• Timer mode
Invalid
• Programmable waveform generation mode
(Note 1)
Underflow of Prescaler Z is counted
R W
A
0016 to FF16
(Note 2)
• Programmable one-shot generation mode
Invalid
• Programmable wait one-shot generation mode
Underflow of Prescaler Z is counted
(One-shot width is counted)
R W
A
0016 to FF16
Note 1: Each value of Timer Z Primary and Timer Z Secondary is reloaded to the
Timer Z alternately for counting.
Note 2: The count value can be read out by reading the Timer Z Primary even when
the secondary period is being counted.
Timer Z Primary
b7
b0
Symbol
TZPR
Address
008716
Function
When reset
FF16
AA
A
AA
A
AA
AA
A
AA
A
AA
Values that can be set
• Timer mode
Underflow of Prescaler Z is counted
0016 to FF16
• Programmable waveform generation mode
Underflow of Prescaler Z is counted (Note)
0016 to FF16
• Programmable one-shot generation mode
Underflow of Prescaler Z is counted
(One-shot width is counted)
0016 to FF16
• Programmable wait one-shot generation mode
Underflow of Prescaler Z is counted
(Wait period is counted)
0016 to FF16
RW
Note: Each value of Timer Z Primary and Timer Z Secondary is reloaded to the
Timer Z alternately for counting.
Figure 1.14.22. Timer Z-related registers (2)
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z waveform output control register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
PUM
Address
008416
Bit symbol
When reset
0016
Bit name
Function
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
RW
Timer Y primary
waveform extension
control bit
Timer Y secondary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 1)
TZPUM0
Timer Z primary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 2)
TZPUM1
Timer Z secondary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 2)
TYOPL
Timer Y output level
latch
Function varies depending on the operation mode
TZOPL
Timer Z output level
latch
Function varies depending on the operation mode
INT0 pin one-shot
trigger control bit
(Timer Z)
(Note 4)
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid
INT0 pin one-shot
trigger polarity select bit
(Timer Z)
(Note 3)
0 : Edge trigger at falling edge
1 : Edge trigger at rising edge
TYPUM0
TYPUM1
INOSTG
INOSEG
0 : No waveform extension
1 : Waveform extension (Note 1)
Note 1: When setting this bit to "1", the Prescaler Y Register must be set to "0016".
Note 2: When setting this bit to "1", the Prescaler Z Register must be set to "0016".
Note 3: This bit is valid only when INT0 input polarity select bit (bit 1 at address 009616) is
"0" (one-edge).
Note 4: This bit must be set to "1", after setting INT0 input enable bit (bit 0 at address 009616),
INT0 input polarity select bit (bit 1 at address 009616), and INT0 pin one-shot trigger
polarity select bit.
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSS
Bit symbol
TXCK0
Address
008E16
When reset
0016
Bit name
Timer X count source
select bit
TXCK1
(Note 5)
TYCK0
Timer Y count source
select bit
TYCK1
(Note 2)
(Note 5)
TZCK0
Timer Z count source
select bit
TZCK1
(Note 4)
(Note 5)
T1CK0
Timer 1 count source
select bit
T1CK1
Function
b1 b0
0 0 : f1 (Note 1)
0 1 : f8
1 0 : f32
1 1 : fC32
b3 b2
0 0 : f1 (Note 1)
0 1 : f8
1 0 : Ring oscillator output (Note 3)
1 1 : fC32
b5 b4
0 0 : f1 (Note 1)
0 1 : f8
1 0 : Timer Y underflow
1 1 : fC32
b7 b6
0 0 : f1 (Note 1)
0 1 : f8
1 0 : f32
1 1 : fC32
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
Note 1: When using an external RC circuit for the main clock, f1 cannot be selected for the
count source.
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Note 3: When attempting to select ring oscillator output, set the ring oscillation enable bit (
CM14) of the system clock control register (address 000716) for oscillation enabled.
Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and
f1 for count source.
Note 5: Avoid switching a count source, while a counter is inprogness. Timer counter should
be stopped before switching a count source.
Figure 1.14.23. Timer Z-related registers (3)
82
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZOC
Address
008A16
Bit symbol
When reset
XXXXX0002
AA
AAAA
A
A
AA
R
Function
Bit name
TZOS
Timer Z one-shot
start bit
TYOCNT
Timer Y programmable
0 : Outputs programmable waveform
waveform generation
output switching bit (Note 2) 1 : Outputs the value of P32 port register
0 : Stops one-shot
(Note 1) 1 : Starts one-shot
W
Timer Z programmable
0 : Outputs programmable waveform
waveform generation
output switching bit (Note 2) 1 : Outputs the value of P31 port register
TZOCNT
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Note 1: The timer Z one-shot start bit is automatically cleared to "0" when the output of
one-shot waveform is completed. The timer Z one-shot start bit should be set to "0" by
program when the one-shot waveform output is terminated by setting the count
start flag to "0" during the wave form output.
Note 2: The timer Y/Z programmable waveform generaton output switching bit is valid only
when operating in programmable waveform generation mode.
External input enable register
AA
AA
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
INTEN
Bit symbol
INT0EN
Address
009616
When reset
0016
Bit name
Function
INT0 input enable bit
(Note)
0 : Disabled
1 : Enabled
INT0PL
INT0 input polarity select bit
(Note)
0 : One edge
1 : Two edges
INT1EN
INT1 input enable bit
0 : Disabled
1 : Enabled
INT1PL
INT1 input polarity select bit
0 : One edge
1 : Two edges
INT2EN
INT2 input enable bit
0 : Disabled
1 : Enabled
INT2PL
INT2 input polarity select bit
0 : One edge
1 : Two edges
INT3EN
INT3 input enable bit
0 : Disabled
1 : Enabled
INT3PL
INT3 input polarity select bit
0 : One edge
1 : Two edges
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
R
W
Note : This bit must be set in condition of INT0 pin one-shot trigger invalid (INOSTG="0").
INT0 input filter select register
AA
AA
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
INT0F
Function
INT0 input filter select bit
b1 b0
UART0 receive hardware
interrupt enable bit (Note)
0 : Disabled
1 : Enabled
INT0F1
INT0F2
When reset
XXXXX0002
Bit name
Bit symbol
INT0F0
Address
001E16
0
0
1
1
AA
A
AA
A
AA
A
R
W
–
–
0 : No filter
1 : Filter with f1 sampling
0 : Filter with f8 sampling
1 : Filter with f32 sampling
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
Note: Interrupts used for debugging purposes only.
Figure 1.14.24. Timer Z-related registers (4)
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source or Timer Y underflow. (See Table
1.14.10) The Timer Z secondary is unused in this mode. Figure 1.14.25 shows the Timer Y, Z mode
register and Timer Y, Z waveform output control register in timer mode.
Table 1.14.10. Specifications of timer mode
Item
Specification
Count source
f1, f8, Timer Y underflow, fC32
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting (When the Timer Z underflows, the contents of the Timer Z primary reload
register is reloaded.)
• When a counting stops, the timer reloads the content of the reload register before
stopping counting.
Divide ratio
Count start condition
1/(n+1)/(m+1) n : Set value of Prescaler Z, m: Set value of Timer Z primary
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0) (Note 1)
Interrupt request generation timing When Timer Z underflows
TYOUT pin function
INT0 pin function
Programmable I/O port
Programmable I/O port, or external interrupt input pin
Read from timer
Count value can be read out by reading Timer Z primary register.
Same applies to Prescaler Z register.
Write to timer
When a value is written to Timer Z Primary register, it is written to both reload register
and counter or written to only reload register. Selected by software.
_______
Select function
Same applies to Prescaler Z register.
• Timer Z write control function
When a value is written to Timer Z Primary register, it can be selected that the value is
written to both reload register and counter or written to only reload register.
Same applies to Prescaler Z register. (Note 2)
Note 1: When the count is stopped, the Timer Z interrupt request flag becomes "1" and an interrupt may occur. Thus,
interrupts must be disabled before the count is stopped. Furthermore, set the Timer Z interrupt request bit to "0"
before starting counting again.
Note 2: If writing to the Timer Z or prescaler Z under the following conditions being filled at the same time the Timer Z
interrupt request flag becomes "1" and an interrupt occurs.
<Conditions>
• Timer Z write control bit (bit 6 of address 0080) is "0" (write to timer and reload register simultaneously)
• Timer Z count start flag (bit 7 of address 0080) is "1" (count start)
To write to the Timer Z or prescaler Z in the above state, disable interrupts before writing.
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z mode register
b7
b6 b5
b4
b3
b2
b1 b0
0 0
Symbol
TYZMR
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y-related bit
When reset
000000X02
Function
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y-related bits
TYS
b5 b4
Timer Z operation
mode bit
0 0 : Timer mode
TZWC
Timer Z write
control bit
0 : Write to timer and reload register
simultaneously (Note 2)
1 : Write to reload register
TZS
Timer Z count
start flag
0 : Stops counting (Note 1)
1 : Starts counting
TZMOD0
TZMOD1
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
R
W
Note 1: When this bit is cleared to "0", the timer reloads the content of the reload register
before it stops. Read out the count value before you stop the timer.
Note 2: At the TZWC bit is "0", when you write in the prescaler Z while the timer Z is
counting,the timer Z reload content of the timer Z reload register.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
Address
008416
Bit name
When reset
0016
Function
Timer Y-related bits
TYPUM1
TZPUM0
Timer Z primary
waveform extension
control bit
Invalid in timer mode
TZPUM1
Timer Z secondary
waveform extension
control bit
Invalid in timer mode
TYOPL
Timer Y-related bit
TZOPL
Timer Z output level
latch
Invalid in timer mode
INOSTG
INT0 pin one-shot
trigger control bit
Invalid in timer mode
INOSEG
INT0 pin one-shot
trigger polarity select bit
Invalid in timer mode
RW
A
A
AA
A
A
AA
A
A
AA
A
A
AA
Figure 1.14.25. Timer Y, Z mode register and Timer Y, Z waveform output control register in timer mode
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Programmable waveform generation mode
In this mode, the microcontroller, while counting the set values of Timer Z primary and Timer Z secondary alternately, outputs from the TZOUT pin a waveform whose polarity is inverted each time Timer
Z primary or Timer Z secondary underflows. (See Table 1.14.11) A counting starts by counting the
value set in the Timer Z primary. Figure 1.14.26 shows Timer Y, Z mode register and Timer Y, Z
waveform output control register in this mode. The Timer Z operates in the same way as the Timer Y
in this mode. See Figure 1.14.19 shown the Timer Y operating example in programmable waveform
generation mode.
Table 1.14.11. Specifications of programmable waveform generating mode
Item
Specification
Count source
Count operation
f1, f8, Timer Y underflow, fC32
• Down count
• When the timer underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing counting.
• When a counting stops, the timer reloads the content of the reload register before it stops.
Divide ratio
fi/(n+1)/((m+1)+(l+1))
n : Set value of Prescaler Z, m: Set value of Timer Z primary, l: Set value of Timer Z secondary
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0) (Note 1)
Interrupt request generation timing When Timer Z underflows during secondary period
TZOUT pin function
Pulse output (Note 2)
INT0 pin function
Programmable I/O port, or external interrupt input pin
Read from timer
Count value can be read out by reading Timer Z primary register.
Same applies to Prescaler Z register. (Note 3)
Write to timer
When a value is written to Timer Z primary register, it is written to only reload register.
Same applies to Timer Z secondary register and Prescaler Z register. (Note 4)
Select function
• Output level latch select function
The output level of an waveform being counted during primary and secondary periods
is selectable.
• Programmable waveform generation output switching function
Can select either programmable waveform or the value of Port P3 1 register for output. (Note 5)
• Waveform extend function(Note 6)
The waveform output primary and secondary periods can each be extended 0.5 cycles
of the count source
Frequency when waveform extended: 2xfi/((2x(m+1))+(2x(l+1))+TZPUM0+TZPUM1)
Duty: (2x(m+1)+TZPUM0)/((2x(m+1)+TZPUM0)+(2x(l+1)+TZPUM1))
m: set value of Timer Z primary, l: set value of Timer Z secondary
TZPUM0: Timer Z primary waveform extension control bit
TZPUM1: Timer Z secondary waveform extension control bit
Note 1: When the count is stopped, the Timer Z interrupt request flag becomes "1" and an interrupt may occur. Thus,
interrupts must be disabled before the count is stopped. Furthermore, set the Timer Z interrupt request bit to "0"
before starting counting again.
Note 2: When the counting stopped, the pin is the secondary period output level.
Note 3: Even when counting the secondary period, read out the Timer Z primary register.
Note 4: The set value of Timer Z secondary register and waveform extension control bits as well as Timer Z primary
register are made effective by writing a value to the Timer Z primary register. The written values are reflected to
the waveform output from the next primary period after writing to the Timer Z primary register.
Note 5: The switching of output is synchronized with a timer Z secondary underflow.
Note 6: When using the waveform extend function, the Prescaler Z register must be set to "0016".
When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used.
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1
Symbol
TYZMR
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y-related bit
When reset
000000X02
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y-related bits
TYS
b5 b4
Timer Z operation
mode bit
0 1 : Programmable waveform generation mode
(Note 1)
TZWC
Timer Z write
control bit
Set to "1" in programmable waveform
generation mode
TZS
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
TZMOD0
A
AA
A
AA
AA
AAA
A
A
A
AA
AA
AAAA
R W
Function
TZMOD1
Note 1: When selecting programmable waveform generation mode, output is set for Port
P31 regardless of the value of the direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register
before it stops. Read out the count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM
0
Address
008416
Bit name
When reset
0016
Function
Timer Y-related bits
TYPUM
1
TZPUM0
Timer Z primary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note)
TZPUM1
Timer Z secondary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note)
TYOPL
Timer Y-related bit
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
Timer Z output level
latch
0 : Outputs "H" for the period set by Timer Z primary and
"L" for the period set by Timer Z secondary.
"L" is outputted when the timer is stopped.
1 : Outputs "L" for the period set by Timer Z primary and
"H" for the period set by Timer Z secondary.
"H" is outputted when the timer is stopped.
INOSTG
INT0 pin one-shot
trigger control bit
Invalid in programmable waveform generation
mode
INOSEG
INT0 pin one-shot
trigger polarity select bit
Invalid in programmable waveform generation
mode
TZOP
L
Note : When setting this bit to "1", the Prescaler Z Register must be set to "0016".
RW
Figure 1.14.26. Timer Y, Z mode register and Timer Y, Z waveform output control register in
programmable waveform generation mode
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Programmable one-shot generation mode
_______
In this mode, upon software command or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZOUT pin. (See Table 1.14.12) When a trigger occurs, the
timer starts operating from the point only once for a given period equal to the set value of the Timer Z
primary. Timer Z secondary is unused in this mode. Figure 1.14.27 shows the Timer Y, Z mode
register and Timer Y, Z waveform output control register in this mode. Figure 1.14.28 shows the Timer
Z operation example in this mode.
Table 1.14.12. Specifications of programmable one-shot generating mode
Item
Specification
Count source
f1, f8, Timer Y underflow, fC32
Count operation
• Downcounts the set value of Timer Z primary
• When the timer underflows, it reloads the contents of reload register before stopping
counting.
• When a counting stops, the timer reloads the contents of the reload register before it
Divide ratio
stops.
1/(n+1)/(m+1)
Count start condition
n : Set value of Prescaler Z, m: Set value of Timer Z primary
• Timer Z one-shot start bit is set (=1) (Note 1)
Count stop condition
• Valid trigger is input to INT0 pin (Note 2)
• When reloading is completed after count value was set to "0016"
_______
• When Count start flag is reset (=0) (Note 3)
• Timer Z one-shot start bit is reset (=0) (Note 3)
Interrupt request generation timing When count value becomes "0016"
TZOUT pin function
Pulse output
_______
INT0 pin function
Read from timer
Programmable I/O port, external interrupt input pin, or external trigger input pin
Count value can be read out by reading Timer Z primary register.
Write to timer
Same applies to Prescaler Z register.
When a value is written to Timer Z primary register, it is written to only reload register.
Select function
Same applies to Prescaler Z register. (Note 4)
• Output level latch select function
The output level of one-shot pulse waveform is selectable.
_______
• INT0 pin one-shot trigger control function and polarity select function
_______
The trigger input from the INT0 pin can be set to valid or invalid. Also, the valid trigger's
polarity can be chosen to be the rising edge, falling edge, or rising and falling both
edges.
• Waveform extend function
The one-shot pulse waveform can be extended 0.5 cycles of the count source (Note 5)
Frequency when waveform extended: 2/(n+1)/(2x(m+1)+TZPUM0)
n: set value of Prescaler Z, m: set value of Timer Z primary
TZPUM0: Timer Z primary waveform extension control bit
Note 1: Count start flag must have been set to "1".
_______
_______
Note 2: Count start flag must have been set to "1", INT0 input enable bit [INT0EN] to "1", and INT0 one-shot trigger
control bit to "1".
Note 3: When the count is stopped by writing 0 to the count start flag or Timer Z one-shot start bit, the Timer Z interrupt
request flag becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is
stopped. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again.
Note 4: Each set value becomes effective by writing to the Timer Z primary register. And the set values are reflected
collectively beginning with the next one-shot pulse after writing to the Timer Z primary.
Note 5: When using the waveform extend function, the Prescaler Z register must be set to "0016".
When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used.
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Mitsubishi microcomputers
M30100/M30102 Group
Timer Z
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 0
Symbol
TYZMR
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y-related bit
When reset
000000X02
Function
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y-related bits
TYS
b5 b4
TZMOD0
Timer Z operation
mode bit
R W
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
1 0 : Programmable one-shot generation mode
(Note 1)
TZMOD1
TZWC
1: Set to "1" in programmable one-shot generation mode
TZS
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
Note 1: When selecting programmable one-shot generation mode, output is set for Port P31
regardless of the value of the direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register
before it stops. Read out the count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
Address
008416
Bit name
When reset
0016
AA
A
A
A
A
AA
AA
A
A
A
A
AA
A
A
A
A
AA
RW
Function
Timer Y-related bits
TYPUM1
TZPUM0
Timer Z primary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 1)
TZPUM1
Timer Z secondary
waveform extension
control bit
Invalid in programmable one-shot generation
mode
TYOPL
Timer Y-related bit
TZOPL
Timer Z output level
latch
0 : Outputs "H" level one-shot pulse.
"L" is outputted when the timer is stopped.
1 : Outputs "L" level one-shot pulse
"H" is outputted when the timer is stopped.
INOSTG
INT0 pin one-shot
trigger control bit
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid
INOSEG
INT0 pin one-shot
trigger polarity select bit
(Note 2)
0 : Edge trigger at falling edge
1 : Edge trigger at rising edge
(Note 3)
Note 1: When setting this bit to "1", the Prescaler Z Register must be set to "0016".
Note 2: This bit is valid only when INT0 input polarity select bit (bit 1 at address 009616) is
"0" (one-edge).
Note 3: When changing this bit to "1", set the INT0 input filter select bit (bits 0, 1 of
address 1E16).
Figure 1.14.27. Timer Y, Z mode register and Timer Y, Z waveform output control register in
programmable one-shot generation mode
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Conditions: Timer Z primary=0316, Timer Z primary waveform extended,
Timer Z output level latch [TZOPL]="0",
INT0 one-shot trigger is valid at rising edge
fPZ
Set to "1" by
software
Count start flag “1”
“0”
Cleared to "0"
when counting
completed
Set to "1" by
software
Set to "1" by
INT0 pin input
trigger
One-shot “1”
start bit
“0”
INT0 pin “1”
input
“0”
Timer Z Count
primary start
reload
Count
start
The contents of
Timer Z
0316
0216 0116 0016
0316
Timer Z
primary
reload
0216 0116 0016
0316
Cleared to “0” when interrupt
request is accepted,
or cleared by software
Timer Z interrupt “1”
request bit
“0”
Timer Z output “1”
level latch
“0”
Cleared to "0"
by software
Waveform
output starts
“H”
TZOUT pin output
“L”
Initialized to "L"
Waveform Waveform
output ends output starts
A
A
Primary waveform
extended
Figure 1.14.28. Operation example in programmable one-shot generation mode
90
Waveform
output ends
AA
AA
Primary waveform
extended
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Programmable wait one-shot generation mode
_______
In this mode, upon software command or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZOUT pin after waiting for a given length of time. (See Table
1.14.13) When a trigger occurs, from this point, the timer starts outputting pulses only once for a given
length of time equal to the Timer Z primary set value after waiting for a given length of time equal to the
Timer Z primary set value. Figure 1.14.29 shows the Timer Y, Z mode register and Timer Y, Z waveform
output control register in this mode. Figure 1.14.30 shows the Timer Z operation example in this mode.
Table 1.14.13. Specifications of programmable wait one-shot generating mode
Item
Count source
Count operation
Specification
f1, f8, Timer Y underflow, fC32
• Downcounts the set value of Timer Z primary
• When Timer Z primary underflows, the contents of Timer Z secondary is reloaded before continuing counting.
• When Timer Z secondary underflows, the contents of Timer Z primary is reloaded before stopping counting.
Wait time
• When a counting stops, the timer reloads the contents of the reload register before it stops.
fi x (n+1) x (m+1), n : Set value of Prescaler Z, m: Set value of Timer Z primary
One-shot pulse output time fi x (n+1) x (l+1), n : Set value of Prescaler Z, l: Set value of Timer Z secondary
Count start condition
• Timer Z one-shot start bit is set (=1) (Note 1)
_______
Count stop condition
• Valid trigger is input to INT0 pin (Note 2)
• When reloading is completed after count value at counting Timer Z secondary was set to "0016"
• When Count start flag is reset (=0) (Note 3)
• Timer Z one-shot start bit is reset (=0) (Note 3)
Interrupt request generation timing When count value at counting Timer Z secondary becomes "0016"
TZOUT pin function
Pulse output
_______
INT0 pin function
Read from timer
Programmable I/O port, external interrupt input pin, or external trigger input pin
Count value can be read out by reading Timer Z primary register.
Write to timer
Same applies to Prescaler Z register.
When a value is written to Timer Z primary register, it is written to only reload register.
Select function
Same applies to Prescaler Z register. (Note 4)
• Output level latch select function
The output level of one-shot pulse waveform is selectable.
_______
• INT0 pin one-shot trigger control function and polarity select function
_____
The trigger input from the INT0 pin can be set to valid or invalid. Also, the valid trigger's
polarity is selectable: rising edge, falling edge, or rising and falling both edges.
• Waveform extend function
Waiting time and one-shot pulse waveform can each be extended 0.5 cycles of the
count source (Note 5)
Waiting time when waveform extended: fi x (n+1) x (2x(m+1)+TZPUM0)/2
One-shot pulse output time when waveform extended: fi x (n+1) x (2x(l+1)+TZPUM1)/2
n: set value of Prescaler Z, m: set value of Timer Z primary, l: set value of Timer Z secondary
TZPUM0: Timer Z primary waveform extension control bit, TZPUM1: Timer Z secondary waveform extension control bit
Note 1: Count start flag must have been set to "1". _______
_______
Note 2: Count start flag must have been set to "1", INT0 input enable bit [INT0EN] to "1", and INT0 one-shot trigger
control bit to "1".
Note 3: When the count is stopped by writing 0 to the count start flag or Timer Z one-shot start bit, the Timer Z interrupt
request flag becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is
stopped. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again.
Note 4: Each set value becomes effective by writing to the Timer Z primary register. And the set values are reflected
collectively beginning with the next one-shot pulse after writing to the Timer Z primary.
Note 5: When using the waveform extend function, the Prescaler Z register must be set to "0016".
When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used.
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Mitsubishi microcomputers
M30100/M30102 Group
Timer Z
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1
Symbol
TYZMR
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y-related bit
When reset
000000X02
Function
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y-related bits
TYS
b5 b4
TZMOD0
Timer Z operation
mode bit
R W
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
1 1 : Programmable wait one-shot generation
mode
(Note 1)
TZMOD1
TZWC
1: Set to "1" in programmable wait one-shot generation mode
TZS
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
Note 1: When selecting programmable wait one-shot generation mode, output is set for
Port P31 regardless of the value of the direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register
before it stops. Read out the count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
Address
008416
Bit name
When reset
0016
Function
Timer Y-related bits
TYPUM1
TZPUM0
Timer Z primary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 1)
TZPUM1
Timer Z secondary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 1)
TYOPL
Timer Y-related bit
TZOPL
Timer Z output level
latch
0 : Outputs "H" level one-shot pulse.
"L" is outputted when the timer is stopped.
1 : Outputs "L" level one-shot pulse
"H" is outputted when the timer is stopped.
INOSTG
INT0 pin one-shot
trigger control bit
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid
(Note 3)
INOSEG
INT0 pin one-shot
trigger polarity select bit
(Note 2)
0 : Edge trigger at falling edge
1 : Edge trigger at rising edge
Note 1: When setting this bit to "1", the Prescaler Z Register must be set to "0016".
Note 2: This bit is valid only when INT0 input polarity select bit (bit 1 at address 009616) is
"0" (one-edge).
Note 3: When changing this bit to "1", set the INT0 input filter select bit (bits 0, 1 of
address 1E16).
AA
AA
AA
AA
AA
AA
AA
AA
RW
Figure 1.14.29. Timer Y, Z mode register and Timer Y, Z waveform output control register in
programmable wait one-shot generation mode
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Timer Z
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Conditions: Timer Z primary=0316, Timer Z primary waveform extended,
Timer Z primary=0416, Timer Z secondary waveform not extended,
Timer Z output level latch [TZOPL]="0",
INT0 one-shot trigger is valid at rising edge
fPZ
Set to "1" by
software
Count start flag
“1”
“0”
Cleared to "0"
when counting
completed
Set to "1" by software, or set
to "1" by INT0 pin input
trigger
One-shot “1”
start bit
“0”
INT0 pin “1”
input
“0”
The contents of
Timer Z
Timer Z
secondary
reload
Count
start
Timer Z
primary
reload
0216 0116 0016 0416 0316 0216 0116 0016
0316
0316
Cleared to “0” when interrupt
request is accepted, or
cleared by software
Timer Z interrupt “1”
request bit “0”
Timer Z output “1”
level latch
“0”
Cleared to "0"
by software
Wait starts
“H”
Waveform
output starts
Waveform
output ends
(Note)
TZOUT pin output
“L”
Initialized to "L"
Note: The waveform output of one-shot pulse is completed after 0.5 clock (1 clock when primary waveform
extended) of fPZ from occurrence of Timer Z interrupt request.
Figure 1.14.30. Operation example in programmable wait one-shot generation mode
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Timer C
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer C
Timer C is a 16-bit free-running timer. Figure 1.14.31 shows the block diagram of Timer C. The Timer C
uses an edge input to TCIN pin or the output of 512 fRING divisions as trigger to latch the timer count value
and generates an interrupt request. The TCIN input has a digital filter and this prevents an error caused by
noise or so on from occurring. Table 1.14.14 shows Timer C specifications. Figure 1.14.32 shows Timer
C-related registers. Figure 1.14.33 shows an operation example of Timer C and timer measurement
register.
Data bus
Address 009D16
Address 009C16
Lower 8 bits
Upper 8 bits
Time measurement register (16)
Timer C clock
select bit
f1
f8
Upper 8 bits
Lower 8 bits
Timer C counter (16)
Address 009116
Address 009016
f32
"0"
Digital
filter
TCIN
Digital filter clock
select bit
1/2
Reload signal
Edge detection
"1"
Time measurement
input source
switching bit
f1
f8
f32
Ring oscillation
Timer C overflow interrupt
TCIN interrupt
1/256
Figure 1.14.31. Block diagram of Timer C
Table 1.14.14. Specifications of Timer C
Item
Count source
Count operation
Specification
f1, f8, f32
• Up count
• Transfer counter value to time measurement register at active edge of
measurement pulse
Count start condition
• Do not reset counter value even if active edge is detected
• Time measurement control bit is set (=1)
Counter stop condition
• Time measurement control bit is reset (=0)
Interrupt request generation timing • When active edge of measurement pulse is input [TCIN interrupt]
TCIN pin function
• When the time underflows [Timer C interrupt]
Measurement pulse input
Count value reset timing
Read from timer (Note)
When time measurement control bit is reset (=0)
• Count value can be read out by reading Timer C. (Note)
• Count value at measurement pulse active edge input can be read out by reading time
measurement register.
Write to timer
Select function
Cannot write to Timer C and time measurement register
• Measurement pulse active edge: selectable (rising edge/falling edge/both edges)
• Measurement pulse: selectable (input from TCIN pin/512 divisions of fRING)
• Digital filter sampling frequency: selectable (f1/f8/f32)
Note: The Timer C and the timer measurement register must be read in word-size.
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Timer C
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer C
(b15)
b7
(b8)
b0 b7
b0
Symbol
TC
Address
009116, 009016
When reset
Indeterminate
A
Function
R W
Internal count source is counted
Time measurement register
(b15)
b7
(b8)
b0 b7
b0
Symbol
TM
Address
009C16, 009D16
When reset
Indeterminate
A
A
Function
RW
When active edge of measurement pulse is input, the count value of
(Note)
Timer C is stored
Note: When time measurement is disabled, the value is indeterminate.
After enabling time measurement, the value is indeterminate until the first
trigger is generated.
Timer C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC0
Address
009A16
When reset
0XX000002
Bit symbol
Bit name
Function
TCC00
Time measurement control bit
TCC01
Timer C clock select bit
0 : Time measurement disabled
1 : Time measurement enabled
b2 b1
0 0 : f1 (Note 2)
0 1 : f8
1 0 : f32
1 1 : Inhibit
TCC02
(Note 1)
TCC03
Time measurement input edge
trigger bit
TCC04
(Note 1)
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
R W
b4 b3
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Inhibit
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Time measurement input
0 : TCIN
source switching bit
1 : RING512
(Note 1) (Note 3)
Note 1: Change this bit when time measurement is disabled.
Note 2: When using an external RC circuit for the main clock, f1 cannot be selected for the
Timer C clock.
Note 3: Set the ring oscillation stop bit (CM14) to “0” before setting this bit to “1”.
TCC07
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC1
Address
009B16
Bit symbol
TCC10
When reset
XXXXXX112
Function
Bit name
Digital filter clock select bit
TCC11
(Note)
b1 b0
0 0 : Cannot be used
0 1 : f1
1 0 : f8
1 1 : f32
AA
A
R W
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Note : Input edge becomes active when the same value from TCIN pin is sampled
three times in succession.
Figure 1.14.32. Timer C-related register
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Timer C
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Conditions: Time measurement input edge trigger is set for falling egde (TCC03="1", TCC04="0")
Overflow
Counter contents (hex)
FFFF16
Count start
Measurement value 2
Measurement value 1
Measurement
value 3
000016
Time
Cleared to "0"
by software
Set to "1" by software
Time measurement “1”
control bit “0”
Measurement pulse “H”
(TCIN pin input) “L”
The delay caused
by digital filter
Transmit
Transmit
(Measurement (Measurement
value 1)
value 2)
Transmit
(Measurement
value 3)
Transmit timing from
Timer C counter to
time measurement register
Indeterminate
Indeterminate
Time measurement register
Measurement value 2
Measurement
value 1
Measurement
value 3
Cleared to “0” when interrupt request is accepted, or cleared by software
TCIN interrupt “1”
request bit “0”
Cleared to “0” when interrupt
request is accepted, or
cleared by software
Timer C interrupt “1”
request bit “0”
Figure 1.14.33. Operation example of Timer C and time measurement register
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as two channels: UART0 and UART1. UART0 and UART1 each have an exclusive
timer to generate a transfer clock, so they operate independently of each other.
Figure 1.15.1 shows the block diagram of UARTi (i=0,1). Figure 1.15.2 shows the block diagram of the
transmit/receive unit.
UART0 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/
O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 00A016 and
00A816) determine whether UART0 is used as a clock synchronous serial I/O or as a UART. Although a few
functions are different, UART0 and UART1 have almost the same functions.
Figures 1.15.3 through 1.15.5 show the registers related to UARTi.
(UART0)
RxD0
TxD0
UART reception
1/16
Clock source selection
Bit rate generator
f1
f8
Clock synchronous type
Reception
control circuit
Receive
clock
Internal (Address 00A116)
f32
fc
1 / (n0+1)
UART transmission
1/16
Clock synchronous type
External
Transmission
control circuit
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
CLK
polarity
reversing
circuit
CLK0
(UART1)
RxD1
TxD1
UART reception
1/16
Clock source selection
Bit rate generator
f1
f8
Clock synchronous type
Reception
control circuit
Receive
clock
Internal (Address 00A916)
1 / (n1+1)
f32
fc
External
UART transmission
1/16
Clock synchronous type
Transmission
control circuit
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
CLK1
CLKS1
CLK
polarity
reversing
circuit
Clock synchronous type
(when external clock is selected)
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
Clock output pin
select switch
Figure 1.15.1. Block diagram of UARTi (i = 0, 1)
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock
synchronous
type
Clock
synchronous
PAR
type
disabled
1SP
RxDi
SP
SP
UART (7 bits)
UART (8 bits)
UARTi receive register
UART (7 bits)
PAR
UART
PAR
enabled
2SP
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive
buffer register
D1
D0
UARTi transmit
buffer register
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
UART (8 bits)
UART (9 bits)
UART (9 bits)
PAR
enabled
2SP
SP
SP
UART
Clock
synchronous
type
TxDi
PAR
1SP
Clock
PAR
disabled synchronous
type
“0”
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
Figure 1.15.2. Block diagram of transmit/receive unit
98
UART (7 bits)
UARTi transmit register
SP: Stop bit
PAR: Parity bit
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
Address
00A316, 00A216
00AB16, 00AA16
When reset
Indeterminate
Indeterminate
Function
A
R W
Transmit data (Note)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: When transfer data length is 9-bit long, write high-byte first then low-byte with bytesize.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
b0
Bit
symbol
Address
00A716, 00A616
00AF16, 00AE16
When reset
Indeterminate
Indeterminate
Function (During clock
synchronous serial I/O
mode)
Bit name
Receive data
Function
(During UART mode)
Receive data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
OER
Overrun error flag
(Note)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
FER
Framing error flag
(Note)
Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag
(Note)
Invalid
0 : No parity error
1 : Parity error found
SUM
Error sum flag
(Note)
Invalid
0 : No error
1 : Error found
R W
A
A
AA
A
A
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bits (bit 2 to 0 at
addresses 00A016 and 00A816) are set to “0002” or receive enable bit to “0”. (Bit 15 is
set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 00A616, and 00AE16)
is read out or when this register is read out in word-size. When reading data from the
UARTi receive buffer, data should be read high-byte first then low-byte using bytesize.
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U1BRG
Address
00A116
00A916
Function
Assuming that set value = n, BRGi divides the
count source by n + 1
When reset
Indeterminate
Indeterminate
Values that can be set
0016 to FF16
AA
RW
Figure 1.15.3. Serial I/O-related registers (1)
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Bit
symbol
Address
00A016, 00A816
Bit name
SMD0 Serial I/O mode select bit
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
b2 b1 b0
0 : Internal clock
1 : External clock (Note)
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
PRYE
Parity enable bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
Must always be set to “0”
Reserved bit
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
Invalid
R W
Note: Set the corresponding port direction register to “0”.
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
UiC0(i=0,1)
Bit
symbol
CLK0
Address
When reset
00A416, 00AC16
0816
Bit name
BRG count source
select bit
CLK1
Reserved bit
TXEPT
Transmit register empty
flag
Function (Note)
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
b1 b0
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : fc is selected
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : fc is selected
Must set to "0".
0 : Data present in transmit
0 : Data present in transmit register
register (during transmission)
(during transmission)
1 : No data present in transmit
1 : No data present in transmit
register (transmission
register (transmission completed)
completed)
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be "0".
NCH
Data output select bit
CKPOL
CLK polarity select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
Must always be “0”
O
Figure 1.15.4. Serial I/O-related registers (2)
100
AA
A
AA
A
AA
A
AA
A
AA
AA
AA
A
AA
A
AA
A
R W
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1
Symbol
UiC1(i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Bit
symbol
Address
00A516,00AD16
When reset
0216
Function (Note 1)
(During clock synchronous
serial I/O mode)
Bit name
Function
(During UART mode)
AAA
AA
AA
AAA
AA
AA
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
(Note)
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
RW
Note : As for the UART1, set the RXD1 input port select bit before setting this bit to reception enabled.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Bit
symbol
U0IRS
Address
00B016
Bit
name
UART0 transmit
interrupt cause select bit
When reset
0016
Function
(During clock synchronous
serial I/O mode)
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Function
(During UART mode)
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1 CLK/CLKS select
bit 1 (Note 1)
0 : Normal mode
Fixed to “0”
(CLK output is CLK0 only)
1 : Transfer clock output
from multiple pins
function selected
0 : P37
1 : P35
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AAA
AAA
AAA
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous
receive mode enable bit
RXD1EN RxD1 input port
select bit (Note 2)
R W
0 : P37
1 : P35
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 00A016) = “0”.
Note 2: For P37, select "0" for data receive, and "1" for data transfer. And set the direction register
of port P37 to input ("0") when receiving.
Figure 1.15.5. Serial I/O-related registers (3)
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Clock
serial I/O mode
Serial synchronous
I/O
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table
1.15.1.) Figure 1.15.6 shows the UARTi transmit/receive mode register.
Table 1.15.1. Specifications of clock synchronous serial I/O mode
Specification
Item
Transfer data format • Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 00A016,00A816 = “0”) : fi/ 2(n+1) (Note 1)
Transfer clock
fi = f1, f8, f32, fc
• When external clock is selected (bit 3 at address 00A016,00A816 = “1”) : Input from CLKi pin
• To start transmission, the following requirements must be met:
Transmission start
_ Transmit enable bit (bit 0 at address 00A516,00AD16) = “1”
condition
_ Transmit buffer empty flag (bit 1 at addresses 00A516,00AD16) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = “1”: CLKi input level = “L”
• To start reception, the following requirements must be met:
Reception start
_ Receive enable bit (bit 2 at address 00A516,00AD16) = “1”
conditio
_ Transmit enable bit (bit 0 at address 00A516,00AD16) = “1”
_ Transmit buffer empty flag (bit 1 at address 00A516,00AD16) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = “1”: CLKi input level = “L”
• When transmitting
Interrupt request
_ Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B016) = “0”: Intergeneration timing
rupts requested when data transfer from UARTi transfer buffer register to UARTi
transmit register is completed
_ Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B016) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed
• Overrun error (Note 2)
Error detection
This error occurs when the next data is ready before contents of UARTi receive
buffer register are read out
•
CLK
polarity selection
Select function
Whether transmit data is output/input at the rising edge or falling edge of the transfer
clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART1 transfer clock can be chosen by software to be output from one of the two pins set
• RxD1 input pin selection
UART1 RxD1 can be chosen by software to be input to one of the two pins set
Note 1: “n” denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
UiMR (i=0,1)
0 0 1
Bit symbol
SMD0
Address
00A016, 00A816
Bit name
Function
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Internal/external clock
select bit
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock (Note)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be “0” in clock synchronous serial I/O mode)
Note : Set the corresponding port direction register to “0”.
AA
AA
AAAA
AA
AA
AA
AA
A
AA
RW
Figure 1.15.6. UARTi transmit/receive mode register in clock synchronous serial I/O mode
Table 1.15.2 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
table shows the pin functions when the transfer clock output from multiple pins is not selected. Note that
for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs
an “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 1.15.2. Input/output pin functions in clock synchronous serial I/O mode
Function
Serial data output
Serial data input
Pin name
Remarks
Method of selection
Port P14 cannot be used as an I/O port even when
performing only serial data input but not serial data output)
TxD0 (P14)
TxD1 (P37)
RxD1 input pin select bit
(bit 6 at address 00B016)= “1”
Port P37 cannot be used as an I/O port even when
performing only serial data input but not serial data output)
RxD0 (P15)
Port P15 direction register
(bit 5 at address 00E116)= “0”
Port P15 can be used as an I/O port when performing only
serial data output but not serial data input)
RxD1 (P35)
Port P35 direction register
(bit 5 at address 00E716)= “0”
RxD1 input pin select bit
(bit 6 at address 00B016)= “1”
Port P37 direction register
(bit 7 at address 00E716)= “0”
RxD1 input pin select bit
(bit 6 at address 00B016)= “0”
Port P35 can be used as an I/O port when performing only
serial data output but not serial data input)
RxD1 (P37)
When setting Port P37 as RxD1, serial data output cannot
be performed.
Port P35 can be used as an I/O port.
Transfer clock output CLKi (P16, P36) Internal/external clock select bit
(bit 3 at addresses 00A016 and
00A816) = “0”
Transfer clock input
CLKi (P16, P36) Internal/external clock select bit
(bit 3 at address 00A016 and
00A816) = “1”
Ports P16 and P36 direction
register (bit 6 at address 00E316
and 00E716) = “0”
(When transfer clock output from multiple pins is not selected)
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
bit (TE)
“0”
Data is set in UARTi transmit buffer
register
“1”
Transmit buffer
empty flag (Tl)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit
register
TCLK
Stopped pulsing because transfer enable bit = “0”
CLKi
D 0 D1 D 2 D 3 D 4 D 5 D 6 D 7 D0 D1 D 2 D3 D4 D5 D6
TxDi
Transmit
register empty
flag (TXEPT)
D7
D 0 D1 D2 D3 D 4 D 5 D 6 D7
“1”
“0”
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f1, f8, f32, fc)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
Transmit enable
bit (TE)
“0”
Transmit buffer
empty flag (Tl)
“0”
“1”
Dummy data is set in UARTi transmit buffer register
“1”
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
CLKi
Receive data is taken in
D 0 D1 D 2 D3 D 4 D5 D6 D 7
RxDi
Receive complete “1”
flag (Rl)
“0”
Receive interrupt
request bit (IR)
Transferred from UARTi receive register
to UARTi receive buffer register
D0 D 1 D 2
D3 D4 D5
Read out from UARTi receive buffer register
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• CLK polarity select bit = “0”.
Meet the following conditions when the CLKi input level
before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
fEXT: frequency of external clock
Figure 1.15.7. Typical transmit/receive timings in clock synchronous serial I/O mode
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
(a) Polarity select function
As shown in Figure 1.15.8, the CLK polarity select bit (bit 6 at addresses 00A416 and 00AC16) allows
selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: The CLKi pin level when not
transferring data is “H”.
• When CLK polarity select bit = “1”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 2: The CLKi pin level when not
transferring data is “L”.
Figure 1.15.8. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.15.9, when the transfer format select bit (bit 7 at addresses 00A416 and 00AC16)
= “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
LSB first
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
• When transfer format select bit = “1”
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
MSB first
Note: This applies when the CLK polarity select bit = “0”.
Figure 1.15.9. Transfer format
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 00B016). (See Figure 1.15.10.)
The multiple pins function is valid only when the internal clock is selected for UART1.
Microcomputer
TXD1 (P37)
CLKS (P34)
CLK1 (P36)
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 1.15.10. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 00B016) is set to “1”, the unit is
placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit
simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer
register back again.
(e) RxD1 input pin selection function (UART1)
This function allows the setting two RxD1 input pins and choosing one of the two to input serial data by
using the RxD1 input pin select bit (bits 6 at address 00B016).
When selecting "1" (P35) for RxD1 input pin select bit, P37 functions as TxD1 output pin. When selecting "0" (P37), serial data output cannot be performed. However, P35 can be used as an input/output
port.
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Clock
serial I/O (UART) mode
Serial asynchronous
I/O
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. (See Table 1.15.3.) Figure 1.15.11 shows the UARTi transmit/receive mode register.
Table 1.15.3. Specifications of UART Mode
Item
Transfer data format
Transfer clock
Transmission start
condition
Reception start condition
Interrupt request generation timing
Error detection
Select function
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 00A016, 00A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
• When external clock is selected (bit 3 at addresses 00A016=“1”) :
fEXT/16(n+1) (Note 1) (Note 2)
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 00A516, 00AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 00A516, 00AD16) = “0”
• To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 00A516, 00AD16) = “1”
- Start bit detection
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 00B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 00B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is
completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
• RxD1 input pin selection
UART1 RxD1 can be chosen by software to be input to one of the two pins set
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
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serial I/O (UART) mode
Serial asynchronous
I/O
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Bit symbol
SMD0
Address
00A016, 00A816
Bit name
Function
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Internal / external clock
select bit
Stop bit length select bit
0 : Internal clock
1 : External clock (Note 1)
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
STPS
Reserved bit
Must always be set to “0”
Note : Set the corresponding port direction register to “0”.
A
AA
A
A
A
AA
RW
Figure 1.15.11. UARTi transmit/receive mode register in UART mode
Table 1.15.4 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the Nchannel open-drain is selected, this pin is in floating state.)
Table 1.15.4. Input/output pin functions in UART mode
Function
Serial data output
Serial data input
Pin name
108
Remarks
Port P14 cannot be used as an I/O port even when
performing only serial data input but not serial data output)
TxD0 (P14)
TxD1 (P37)
RxD1 input pin select bit
(bit 6 at address 00B016)= “1”
RxD0 (P15)
Port P15 direction register
(bit 5 at address 00E116)= “0”
RxD1 (P35)
Port P35 direction register
(bit 5 at address 00E716)= “0”
RxD1 input pin select bit
(bit 6 at address 00B016)= “1”
Port P37 direction register
(bit 7 at address 00E716)= “0”
RxD1 input pin select bit
(bit 6 at address 00B016)= “0”
RxD1 (P37)
Transfer clock input
Method of selection
Port P37 cannot be used as an I/O port even when
performing only serial data input but not serial data output)
Port P15 can be used as an I/O port when performing only
serial data output but not serial data input)
Port P35 can be used as an I/O port when performing only
serial data output but not serial data input)
When setting Port P37 as RxD1, serial data output cannot
be performed.
Port P35 can be used as an I/O port.
CLKi (P16, P36) Internal/external clock select bit Ports P16 and P36 can be used as an I/O port when not
performing transfer clock input. In this case, set the
(bit 3 at address 00A016 and
internal/external clock select bit to "0".
00A816) = “1”
Ports P16 and P36 direction
register (bit 6 at address 00E316
and 00E716) = “0”
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serial I/O (UART) mode
Serial asynchronous
I/O
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register.
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P
Stopped pulsing because transmit enable bit = “0”
Stop
bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1
SP
Transmit register “1”
empty flag
“0”
(TXEPT)
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit register
empty flag
(TXEPT)
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“1”
“0”
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• Transmit interrupt cause select bit = “0”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Figure 1.15.12. Typical transmit timings in UART mode
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serial I/O (UART) mode
Serial asynchronous
I/O
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
Receive enable bit
“1”
“0”
Stop bit
Start bit
RxDi
D1
D0
Sampled “L”
D7
Receive data taken in
Transfer clock
Receive
complete flag
“1”
Receive interrupt
request bit
“1”
“0”
Reception triggered when transfer clock
is generated by falling edge of start bit
Transferred from UARTi receive register to
UARTi receive buffer register
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
Figure 1.15.13. Typical receive timing in UART mode
(a) RxD1 input pin selection function (UART1)
This function allows the setting two RxD1 input pins and choosing one of the two to input serial data by
using the RxD1 input pin select bit (bits 6 at address 00B016).
When selecting "1" (P35) for RxD1 input pin select bit, P37 functions as TxD1 output pin. When selecting "0" (P37), serial data output cannot be performed. However, P35 can be used as an input/output
port.
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A-D Converter
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P00 to P07, P10 to P13, P40 and P41 also function as the analog signal input pins.
The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit
(bit 5 at address 00D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into
the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after connecting to VREF.
The result of A-D conversion is stored in the A-D registers. When set to 10-bit precision, the low 8 bits are
stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 1.16.1 shows the performance of the A-D converter. Figure 1.16.1 shows the block diagram of the AD converter, and Figures 1.16.2 and 1.16.3 show the A-D converter-related registers.
Table 1.16.1. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to VCC
Operating clock φAD (Note 2) VCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V • Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN11 input : ±3LSB
ANEX0 and ANEX1 input (including mode in which external
VCC = 3V
operation amp is connected) : ±7LSB
• Without sample and hold function (8-bit resolution)
±2LSB
Operating modes
One-shot mode and repeat mode (Note 3)
Analog input pins
12 pins (AN0 to AN11) + 2 pins (ANEX0 to ANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Divide fAD if (XIN) exceeds 10MHz, and make φAD equal to or lower than 10MHz. Also if Vcc is less
than 4.2V or an external RC circuit is used for the main clock, divide fAD and make φAD equal to or
lower than fAD/2.
Without sample and hold function, set the φAD frequency to 250kHz min.
With the sample and hold function, set the φAD frequency to 1MHz min.
Note 3: In repeat mode, only 8-bit mode can be used.
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A-D Converter
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CKS1=1
CKS0=1
fAD
1/2
fAD
1/2
CKS1=0
CKS0=0
A-D conversion rate
selection
VCUT=0
V SS
V REF
Resistor ladder
VCUT=1
Successive conversion register
A-D control register 1 (address 00D716)
A-D control register 0 (address 00D616)
Addresses
(00C116, 00C016)
A-D register 0(16)
Vref
Decoder
Data bus low-order
VIN
Port P0 group
P07/AN0
P06/AN1
P05/AN2
P04/AN3
P03/AN4
P02/AN5
P01/AN6
P00/AN7
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
ADGSEL0=0
OPA1, OPA0=0, 0
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
Port P1 group
P10/AN8
P11/AN9
CH2,CH1,CH0=100
P12/AN10
P13/AN11
CH2,CH1,CH0=110
CH2,CH1,CH0=101
ADGSEL0=1
CH2,CH1,CH0=111
OPA1,OPA0=1,1
OPA0=1
P40/ANEX0
P41/ANEX1
OPA1=1
Figure 1.16.1. Block diagram of A-D converter
112
OPA1,OPA0=0,1
Comparator
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A-D Converter
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON0
Bit symbol
Address
00D616
When reset
00000XXX2
Bit name
Function
RW
b2 b1 b0
CH0
Analog input pin select bit
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4, AN8 is selected
1 0 1 : AN5, AN9 is selected
1 1 0 : AN6, AN10 is selected
1 1 1 : AN7, AN11 is selected
A-D operation mode
select bit 0
0 : One-shot mode
1 : Repeat mode
A-D input group select bit
0 : Port P0 group is selected
1 : Port P1 group is selected
CH1
CH2
MD0
ADGSEL0
(Note 2, 3)
(Note 2)
Set this bit to “0”.
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
A
AA
AA
A
AA
A
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: AN4 to AN7 and AN8 to AN11 are selected by the A-D input group select bit.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
ADCON1
Bit symbol
Address
00D716
When reset
0016
Bit name
Function
Set this bit to “0”. When read, their values are “0”.
BITS
CKS1
VCUT
OPA0
8/10-bit mode select bit 0 : 8-bit mode
(Note 2) 1 : 10-bit mode
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
(Note 3) 1 : fAD is selected
Vref connect bit
External op-amp
connection mode bit
OPA1
0 : Vref not connected
1 : Vref connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
AAA
AAAA
AA
AAA
AAA
AAA
AA
RW
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: In repeat mode, only 8-bit mode can be used.
Note 3: When f(XIN) is over 10 MHz, the φAD frequency must be under 10 MHz by dividing.
Figure 1.16.2. A-D converter-related registers (1)
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A-D Converter
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
Address
When reset
ADCON2
00D416
XXXX00002
Bit symbol
SMP
Bit name
A-D conversion method
select bit
Reserved bit
Function
0 : Without sample and hold
1 : With sample and hold
Always set to “0”
AAAA
AA
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
A-D register
(b15)
b7
AD
(b8)
b0 b7
Address
00C016
00C116
When reset
Indeterminate
Indeterminate
b0
Function
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be indeterminate.
Figure 1.16.3. A-D converter-related registers (2)
114
AA
A
R W
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A-D Converter
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. (See Table 1.16.2.) Figure 1.16.4 shows the A-D control register in one-shot mode.
Table 1.16.2. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN11, as selected
Reading of result of A-D converter Read A-D register
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
ADCON0
Bit symbol
CH0
Address
00D616
When reset
00000XXX2
b2 b1 b0
Analog input pin select bit
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4, AN8 is selected
1 0 1 : AN5, AN9 is selected
1 1 0 : AN6, AN10 is selected
1 1 1 : AN7, AN11 is selected
CH1
CH2
MD0
ADGSEL0
A
A
A
A
A
A
AA
A
A
A
A
A
A
A
A
A
A
A
A
AA
RW
Function
Bit name
A-D operation mode
select bit 0
0 : One-shot mode
A-D input group select bit
0 : Port P0 group is selected
1 : Port P1 group is selected
(Note 2, 3)
(Note 2)
Set this bit to “0”.
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: AN4 to AN7 and AN8 to AN11 are selected by the A-D input group select bit.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0 0
Symbol
ADCON1
Bit symbol
Address
00D716
When reset
0016
Bit name
Function
Set this bit to “0”. When read, their values are “0”.
BITS
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
(Note 2)
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
1 : Vref connected
VCUT
OPA0
OPA1
External op-amp
connection mode bit
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
A
A
A
A
A
A
A
A
AA
A
A
AA
RW
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When f(XIN) is over 10 MHz, the φAD frequency must be under 10 MHz by dividing.
Figure 1.16.4. A-D conversion register in one-shot mode
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Mitsubishi microcomputers
M30100/M30102 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
(See Table 1.16.3.) Figure 1.16.5 shows the A-D control register in repeat mode.
Table 1.16.3. Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN11, as selected (Note)
Reading of result of A-D converter Read A-D register (at any time)
Note : AN4 to AN7 can be used in the same way as for AN8 to AN11.
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Symbol
ADCON0
Bit symbol
CH0
Address
00D616
When reset
00000XXX2
b2 b1 b0
Analog input pin select bit
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4, AN8 is selected
1 0 1 : AN5, AN9 is selected
1 1 0 : AN6, AN10 is selected
1 1 1 : AN7, AN11 is selected
CH1
CH2
MD0
ADGSEL0
A
A
A
A
A
A
A
A
A
A
AA
A
A
A
A
AA
AA
RW
Function
Bit name
A-D operation mode
select bit 0
1 : Repeat mode
A-D input group select bit
0 : Port P0 group is selected
1 : Port P1 group is selected
(Note 2, 3)
(Note 2)
Set this bit to “0”.
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: AN4 to AN7 and AN8 to AN11 are selected by the A-D input group select bit.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0 0 0
Symbol
ADCON1
Bit symbol
Address
00D716
When reset
0016
Function
Bit name
Set this bit to “0”. When read, their values are “0”.
BITS
8/10-bit mode select bit 0 : 8-bit mode
(Note 2)
CKS1
Frequency select bit 1
(Note 3)
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
1 : Vref connected
VCUT
OPA0
OPA1
External op-amp
connection mode bit
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
A
A
A
A
A
A
A
A
A
A
A
A
AA
RW
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: In repeat mode, only 8-bit mode can be used.
Note 3: When f(XIN) is over 10 MHz, the φAD frequency must be under 10 MHz by dividing.
Figure 1.16.5. A-D conversion register in repeat mode
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A-D Converter
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 00D416) to “1”.
When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 øAD
cycle is achieved with 8-bit resolution and 33 øAD with 10-bit resolution. Sample and hold can be
selected in all modes. However, in all modes, be sure to specify before starting A-D conversion
whether sample and hold is to be used.
• Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1
can also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 00D716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital.
When bit 6 of the A-D control register 1 (address 00D716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital.
• External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1,
can be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 00D716) is “1” and bit 7 is “1”, input via AN0 to AN11
is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored
in the A-D register. The speed of A-D conversion depends on the response of the external operation
amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.16.6 is an example of how to
connect the pins in external operation amp mode.
Resistance ladder
Successive conversion register
Analog
input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
ADGSEL0=0
ADGSEL0=1
ANEX0
ANEX1
Comparator
External op-amp
Figure 1.16.6. Example of external op-amp connection mode
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D-A Converter
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains one independent D-A converter of this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bit 0 (D-A output
enable bit) of the D-A control register decide if the result of conversion is to be output. Do not set the target
port to output mode if D-A conversion is to be performed. When D-A output is set for enabled, the corresponding port is inhibited to be pulled up.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF: reference voltage
Table 1.17.1 lists the performance of the D-A converter. Figure 1.17.1 shows the block diagram of the D-A
converter, Figure 1.17.2 shows the D-A control register and Figure 1.17.3 shows D-A converter equivalent
circuit.
Table 1.17.1. Performance of D-A converter
Item
Conversion method
R-2R method
Resolution
8 bits
Analog output pin
1 channel
Performance
A
D-A register (8)
(Address 00D816)
AAAAA
AAAAA
D-A output enable bit
R-2R resistance ladder
Figure 1.17.1. Block diagram of D-A converter
118
P34 / CLKS1 / DA
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D-A Converter
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A control register
b7
b6
b5
b4
b3
b2
b1
Symbol
DACON
b0
0
Address
00DC16
Bit symbol
DAE
When reset
0016
Bit name
AA
Function
RW
0 : Output disabled
1 : Output enabled
D-A output enable bit
Nothing is assigned.
When write, set "0". When read, the value of this bit is "0".
Must always set to “0”
Reserved bit
Nothing is assigned.
When write, set "0". When read, the value of these bits is "0".
D-A register
b7
Symbol
DA
b0
Address
00D816
When reset
Indeterminate
AA
Function
RW
R
W
Output value of D-A conversion
Figure 1.17.2. D-A control register
D-A output enable bit
"0"
R
R
R
R
R
R
R
2R
DA
"1"
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
D-A register 0
2R
"0"
"1"
VSS
VREF
Note 1: In the above figure, the D-A register value is "2A16".
Note 2: To save power when not using the D-A converter, set the D-A output enable bit to "0"
and the D-A register to "0016", and prevent current flowing to the R-2R resistance.
Figure 1.17.3. D-A converter equivalent circuit
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Programmable I/O Port
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
There are 34 programmable I/O ports: P0 to P4 (when M30102). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. The port
P1 allows the drive capacity of its N-channel output transistor to be set as necessary. The port P1 can be
used as LED drive port if the drive capacity is set to “HIGH”.
Figures 1.18.1 to 1.18.4 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.18.5 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.
(2) Port registers
Figure 1.18.6 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.18.7 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
(4) Port P1 drive capacity control register
Figure 1.18.7 shows a structure of the port P1 drive capacity control register.
This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit in
this register corresponds one for one to the port pins.
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Programmable I/O Port
P00 to P07, P40, P41
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
Direction register
Data bus
Port latch
A-D input
Pull-up selection
P10 to P13
Direction register
Data bus
Port latch
Input to respective peripheral functions
P1X driving capacity
A-D input
P14
Pull-up selection
Direction
register
"1"
output
Data bus
Port latch
P14 driving capacity
Figure 1.18.1. Programmable I/O ports (1)
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Programmable I/O Port
P15
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
Direction
register
Data bus
Port latch
P15 driving capacity
Input to respective peripheral functions
P16, P17
Pull-up selection
Direction register
"1"
output
Data bus
Port latch
Input to respective peripheral functions
P20, P21
Pull-up selection
Direction register
Data bus
Port latch
Figure 1.18.2. Programmable I/O ports (2)
122
P1X driving capacity
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Programmable I/O Port
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P37, P36
Pull-up selection
Direction
register
"1"
Data bus
Port latch
output
Input to respective peripheral functions
P34
D-A output enable
Pull-up selection
Direction
register
"1"
Data bus
output
Port latch
Analog input
D-A output enable
Pull-up selection
P30, P31, P32
Direction
register
"1"
Data bus
output
Port latch
Figure 1.18.3. Programmable I/O ports (3)
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Programmable I/O Port
P33, P35, P42 to P44
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
Direction
register
Data bus
Port latch
Input to respective peripheral functions
P45
Pull-up selection
Direction
register
Data bus
Port latch
Input to respective peripheral functions
P47
Digital
filter
Pull-up selection
Direction
register
Data bus
Port latch
(Note)
fc
P46
Rf
Pull-up selection
Direction
register
Rd
"1"
output
Data bus
Port latch
(Note)
Note :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 1.18.4. Programmable I/O ports (4)
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Programmable I/O Port
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi direction register (Notes 1, 2)
Symbol
PDi (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Address
00E216, 00E316, 00E616,
00E716, 00EA16
Bit name
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
PDi_4
Port Pi3 direction register
Port Pi4 direction register
PDi_5
Port Pi5 direction register
PDi_6
Port Pi6 direction register
PDi_7
Port Pi7 direction register
When reset
0016
0016
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
A
A
A
A
A
A
RW
Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the
port P0 direction register.
Note 2: Nothing is assigned in bit 2 to bit 7 of port P2 direction register.
When write, set “0”.
When read, their contents are “0”.
Figure 1.18.5. Direction register
Port Pi register (Note)
Symbol
Pi (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Address
00E016, 00E116, 00E416,
00E516, 00E816
Bit name
Pi_0
Port Pi0 register
Pi_1
Pi_2
Port Pi1 register
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Port Pi4 register
Pi_5
Port Pi5 register
Pi_6
Port Pi6 register
Pi_7
Port Pi7 register
When reset
Indeterminate
Indeterminate
Function
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
Note : Nothing is assigned in bit 2 to bit 7 of port P2 register.
When write, set “0”.
When read, their contents are “0”.
A
AA
AAA
A
AA
AA
AA
AAA
A
AA
RW
Figure 1.18.6. Port register
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Programmable I/O Port
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
00FC16
Bit symbol
Bit name
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
When reset
00X000002
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
PU04
P20, P21 pull-up
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
PU06
P30 to P33 pull-up
PU07
P34 to P37 pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Pull-up control register 1
AA
AA
AA
AA
AAA
A
A
AA
A
AA
A
AA
RW
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
00FD16
Bit symbol
Bit name
PU10
P40 to P43 pull-up
PU11
P44 to P47 pull-up
When reset
XXXXXX002
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
AA
AA
R W
Port P1 drive capacity control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DRR
Bit symbol
Bit name
DRR0
Port P10 drive capacuty
DRR1
Port P11 drive capacuty
DRR2
DRR3
Port P12 drive capacuty
Port P13 drive capacuty
DRR4
Port P14 drive capacuty
DRR5
Port P15 drive capacuty
DRR6
Port P16 drive capacuty
DRR7
Port P17 drive capacuty
Figure 1.18.7. Pull-up control register
126
Address
00FE16
When reset
0016
Function
Set P1 N-channel output
transistor drive capacity
0 : LOW
1 : HIGH
AA
AA
AA
AA
AAA
A
AA
AA
AAA
A
R W
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Programmable I/O Port
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example connection of unused pins
Table 1.18.1. Example connection of unused pins
Pin name
Connection
Ports P0 to P4
After setting for input mode, connect every pin to VSS (pull-down) via a
1)
resistor; or after setting for output mode, leave these (Note
pins open.
XOUT (Note 2)
Open
VREF
Connect to VSS
XIN (Note 3)
Connect to VCC (pull-up) via a resistor
Note 1: Connect unused pins as described above. If connected otherwise, power supply current may
increase due to flow-through current on Schmitt circuit in the port.
Note 2: With external clock input to XIN pin, or the main clock oscillation circuit isn't used.
Note 3: When the main clock oscillation circuit isn't used, connect XIN pin to VCC (pull-up), leave XOUT pin
open.or set main clock stop bit (bit 5 at address 000616) to "1"(STOP).
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Precautionary Notes in Using the Device
Serial I/O
(1) When reading data from the UARTi receive buffer in the clock asynchronous serial I/O mode, data should be
read high-byte first then low-byte using byte-size. If data is read as low-byte then high-byte or in word-size,
the framing error and parity error flags are cleared.
A code example is shown below.
MOV.B
MOV.B
00A7H. R0H
00A6H. R0L
; Read the high-byte of UART0 receive buffer register
; Read the low-byte of UART0 receive buffer register
(2) When writing data to the UARTi transmit buffer register in the clock asynchronous serial I/O mode with 9-bit
transfer data length, data should be written high-byte first then low-byte using byte-size.
A code example is shown below.
MOV.B
MOV.B
#XXH, 00A3H
#XXH, 00A2H
; Write the high-byte of UART0 transmit buffer register
; Write the low-byte of UART0 transmit buffer register
A-D Converter
(1) Only write to each bit (except bit 6) of the AD Control Register 0, or each bit of the AD Control Register 1, or
bit 0 of the AD Control Register 2 when AD conversion is stopped (before a trigger occurs).
When the Vref Connection Bit is changed from “0” to “1”, wait 1 µs or longer before starting AD conversion.
(2) When changing AD operation mode, select an analog pin again.
(3) One Shot Mode
Read the AD register only after confirming AD conversion is completed, which can be determined by using
the AD conversion interrupt.
(4) Repeat Mode
Use the undivided main clock as the internal CPU clock when using this mode. The main clock can be
divided by an internal divider circuit but make sure that you use main clock when using this mode.
(5) If A-D conversion is forcibly terminated while in progress by setting the ADST bit of ADCON0 register to 0 (AD conversion halted), the conversion result of the A-D converter is indeterminate. If the ADST bit is cleared
to 0 in a program, ignore the value of AD register.
Stop and Wait Mode
(1) You must put at least four NOPs after a stop (All-Clock Stop Bit to "1") or a wait instruction. When switching
to a stop or wait mode, 4 instructions are prefetched after the stop or wait instruction. And so, ensure that at
least four NOPs follow the stop or wait instruction.
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Stop Mode
(1) After returning from stop mode, an unexpected operation may occur (for example, undefined instruction
interrupt, BRK instruction interrupt, etc.).
Execute a JMP.B instruction after an instruction to write data to the all clock stop control bit. A program
example is described as follows:
MOV.B:S
#21H, CM1 ; writing to the all clock stop control bit to “1”(stop mode)
JMP.B
L1
L1 :
NOP
NOP
NOP
NOP
Interrupts
(1) Reading Address 0 by Firmware
• Please do not read address 0 by firmware. In the CPU's interrupt processing sequence, when a
maskable interrupt occurs, the interrupt information (interrupt no. and interrupt request level) are read
from address 0. This read in turn, clears the interrupt request bit to "0" even pending with higher request
level. Reading address 0 by firmware may cause interrupt cancellation or unexpected interrupts so
please do not read address 0 by firmware.
(2) Stack Pointer
• Set the value of the stack pointer before accepting interrupts. Immediately after a reset, the value of the
stack pointer is 000016. Accepting an interrupt before setting a value of the stack pointer may produce
unpredictable results (runaway program, etc.) Make sure that you set the value of the stack pointer
before accepting interrupts.
(3) External interrupts
• Clear the interrupt request bit to "0" when the INT0 - INT3 polarity is changed. The reason being is that
an interrupt request may be generated when the polarity is changed.
(4) Rewriting the Interrupt Control Register
• When rewriting the Interrupt Control Register, do it at a point where it does not generate an interrupt
request for that register. If there is a possibility that an interrupt may occur, disable the interrupt before
rewriting. Examples are shown below.
Example 1:
INT_SWITCH1:
FCLR
I
AND.B
#00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
;
; Enable interrupts.
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Usage precaution
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example 2:
INT_SWITCH2:
FCLR
I
AND.B
#00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B
#00h, 0055h
POPC
FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
; Enable interrupts.
Note: The reason why two NOP instructions or dummy read were inserted before the FSET I for ex. 1 &
2 is to prevent interrupt enable flag from being set, due to the effects of instruction queue, before
the rewritten value of the interrupt control register takes effect.
• When an instruction to rewrite the interrupt control register is executed while the interrupt is disabled,
depending on the instruction used for rewriting, there are times the interrupt request bit is not set even if
an interrupt request for that register has been generated. If this creates a problem, please use any of the
instructions below to rewrite the register.
Instructions : AND, OR, BCLR, BSET
• Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : MOV
Noise
(1) Bypass Capacitor between VCC and VSS Pins
• Insert a bypass capacitor (at least 0.1 µF) between VCC and VSS pins as noise and latch-up countermeasures. In addition, make sure that connecting lines are the shortest and widest possible.
(2) Port Control Registers Data Read Error
• During severe noise testing, mainly power supply system noise, and introduction of external noise, the
data of port related registers may changed. As a firmware countermeasure, it is recommended to periodically re-set the port registers, port direction registers and pull-up control registers. However, you
should fully examine before introducing the re-set routine as conflicts may be created between this reset routine and interrupt routines (i. e. ports are switched during interrupts).
(3) CNVss pin wiring
• In order to improve the pin tolerance to noise, insert a pull down resistance (about 5 kΩ) between CNVss
and Vss, and placed as close as possible to the CNVss pin.
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer 1
(1) Even if the prescaler 1 and Timer 1 are read out simultaneously in word-size, these registers are read byteby-byte in the microcomputer. Consequently, the timer value may be updated during the period these two
registers are being read.
Timers X, Y and Z
(1) These timers stop counting after reset. Therefore, set values to Timer (X, Y, Z) and prescaler (X, Y, Z) before
starting counting.
(2) Even if prescaler (X, Y, Z) and Timer (X, Y, Z) are read out simultaneously in word-size, these registers are
read byte-by-byte in the microcomputer. Consequently, the timer value may be updated during the period
these two registers are being read.
Timer X
(1) Using in the timer X pulse period measurement mode, the effectaul edge rception flag and the timer X under
flow flag are setted to "0" by writing a "0" in a program. Writing a "1" has no effect. Write "1" in the other flag
by using the MOV instruction when you make the flag of either one side "0" by program. (The clearance of
the flag which isn't intend can be prevnted.)
Example:
MOV.B
#10XXXXXXB,008Bh
(2) When changing to the timer X pulse period measurement mode from other mode, the contents of the
effectaul edge rception flag and the timer X under flow flag are indetermind. Write "0" in the effectaul edge
rception flag and the timer X under flow flag before starting the timer.
Timer Y
(1) When count is stopped by writing "0" to the timer Y count start flag, the timer reloads the value of reload
register and stops. Therefore, the timer count value should be read out before the timer stops.
(2) When count is stopped by writing "0" to the timer Y count start flag, the timer Y interrupt request flag becomes "1" and an interrupt may occur. Thus, disable interrupts before the timer stops. Furthermore, set the
Timer Y interrupt request flag to "0" before starting the timer again.
Timer Z
(1) When count is stopped by writing "0" to the timer Z count start flag, the timer reloads the value of reload
register and stops. Therefore, the timer count value should be read out before the timer stops.
(2) When count is stopped by writing "0" to the timer Z count start flag (all modes) or by writing "0" to the oneshot start bit (programmable one-shot generation mode/programmable wait one-shot generation mode), the
timer Z interrupt request flag becomes "1" and an interrupt may occur. Thus, disable interrupts before the
timer stops. Furthermore, set the Timer Z interrupt request flag to "0" before starting the timer again.
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Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer C
(1) When reading out the timer C or timer measurement register, use a word-size instruction. Even if the Timer
C is read out in word-size, the timer value is not updated during the period the high-byte and low-byte are
being read.
Example:
MOV.W
132
0091H,R0
; Read out timer C
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Electrical characteristics (Vcc = 5V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table 1.19.1. Absolute maximum ratings
Symbol
Parameter
Vcc
Supply voltage
VI
Input voltage
VO
Output voltage
Condition
Rated value
- 0.3 to 6.5
RESET, VREF, XIN
P00 to P07, P10 to P17, P20, P21,
P30 to P37, P40 to P47, CNVss
P00 to P07, P10 to P17, P20, P21,P30 to P37,
P40 to P47,XOUT
IVCC
Unit
V
- 0.3 to Vcc + 0.3
V
- 0.3 to Vcc + 0.3
V
- 0.3 to 3.6V
V
300
mW
Pd
Power dissipation
Topr
Operating ambient temperature
- 20 to 85 (Note 1)
°C
Tstg
Storage temperature
- 40 to 150 (Note 2)
°C
Ta = 25 °C
Note 1: Extended operating temperature version: -40 to 85 °C. When flash memory version is program/erase
mode: 25±5 °C.
Specify a product of -40 to 85°C to use it.
Note 2: Extended operating temperature version: -65 to 150 °C.
Note 3: For M30100 (32-pin version), P20, P21, P34 to P36, P40 to P44, P46 and P47 are not accessed to
external pins.
133
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Electrical characteristics (Vcc = 5V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.19.2. Recommended operating conditions (Note 1)
Symbol
Parameter
Min
(Note 1)
Vcc
Supply voltage
Vss
Supply voltage
VIH
HIGH input
voltage
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
XIN, RESET, CNVSS,
VIL
LOW input
voltage
XIN, RESET, CNVSS,
IOH (peak)
HIGH peak
output current
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
IOH (avg)
HIGH average
output current
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
LOW peak
IOL (peak) output current
IOL (avg)
f (XIN)
LOW average
output current
5.0
5.5
V
V
0
0.2Vcc
V
- 10.0
mA
- 5.0
mA
10.0
mA
HIGH POWER
20.0
LOW POWER
10.0
mA
5.0
mA
P00 to P07, P20, P21, P30 to P37, P40 to P47,
Main clock input
oscillation frequency
V
Vcc
P00 to P07, P20, P21, P30 to P37, P40 to P47,
P10 to P17
Unit
0.8Vcc
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
(Note 5)
f (XcIN)
Max.
0
P10 to P17
IOL (peak)
IOL (avg)
2.7
Standard
Typ.
HIGH POWER
10.0
LOW POWER
5.0
16
Vcc=4.2V to 5.5V
0
Vcc=2.7V to 4.2V
0
Subclock oscillation frequency
mA
MHz
7.33 x VCC
MHz
- 14.791
32.768
50
kHz
Highest operation frequency [MHz]
Note 1: For applications for automobile use, this value is 4.2V.
Note 2: Unless otherwise noted: VCC = 2.7V to 5.5V, Ta = – 20 to 85oC
Note 3: The average output current is an average value measured over 100ms.
Note 4: Keep output current as follows:
The sum of port P00 to P03, P13 to P17, P20, P34 to P37, P46 to P47 IOL (peak) is under 60 mA. The
sum of port P00 to P03, P13 to P17, P20, P34 to P37, P46 to P47 IOH (peak) is under 60 mA. The sum
of port P04 to P07, P10 to P12, P21, P30 to P33, P40 to P45 IOL (peak) is under 60 mA. The sum of port
P04 to P07, P10 to P12, P21, P30 to P33, P40 to P45 IOH (peak) is under 60 mA.
Note 5: Relationship between main clock oscillation frequency and supply voltage is shown as below.
Note 6: For M30100 (32-pin version), P20, P21, P34 to P36, P40 to P44, P46 and P47 are not accessed to
external pins.
AAA
AAA
AAA
Main clock input oscillation frequency
16.0
7.33 x Vcc - 14.791MHz
5.0
0.0
2.7
4.2
Power supply voltage [V]
(Main clock : no division)
134
5.5
Tentative Specifications REV.E1
t
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en Specifications in this manual are tentative and subject to change.
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Electrical characteristics (Vcc = 5V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Table 1.19.3. (1) Electrical characteristics
(Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) = 16MHz)
Symbol
VOH
VOH
VOH
Parameter
HIGH output P00 to P07,P10 to P17,P20,P21,
voltage
P30 to P37,P40 to P47
HIGH output
voltage
XOUT
HIGH output
voltage
XCOUT
(Note)
VOL
VOL
VOL
VOL
VT+ -VT-
Measuring condition
LOW output
voltage
LOW output
voltage
Hysteresis
P10 to P17
XOUT
XcOUT
Unit
3.0
V
IOH = - 200 µA
4.7
V
3.0
LOW POWER IOH = - 0.5 mA
3.0
V
HIGH POWER No load
Flash memory
3.3
No load
Mask ROM
Flash memory
3.0
Mask ROM
1.6
LOW POWER No load
No load
V
3.3
IOL = 5 mA
2.0
V
IOL = 200 µA
0.45
V
HIGH POWER IOH = 10 mA
2.0
LOW POWER IOH = 5 mA
2.0
HIGH POWER IOH = 1 mA
2.0
LOW POWER IOH = 0.5 mA
2.0
V
HIGH POWER No load
0
LOW POWER No load
0
V
V
CNTR0,TCIN,
INT0 to INT3,CLK0,CLK1
RxD0, RxD1,KI0 to KI3,P45
0.2
0.8
V
0.2
1.8
V
5.0
µA
-5.0
µA
50.0 167.0
kΩ
VT+ -VT-
Hysteresis
RESET
IIH
HIGH input
current
P00 to P07,P10 to P17,P20,P21,
P30 to P37,P40 to P47, XIN
RESET, CNVss
LOW input
current
P00 to P07,P10 to P17,P20,P21,
P30 to P37,P40 to P47, XIN
RESET, CNVss
RPULLUP
Pull-up
resistor
P00 to P07,P10 to P17,P20,P21,
P30 to P37,P40 to P47
IIL
Standard
Typ. Max.
IOH = - 5 mA
HIGH POWER IOH = - 1 mA
LOW output P00 to P07,P20,P21,
voltage
P30 to P37,P40 to P47
LOW output
voltage
Min.
VI = 5V
VI = 0V
VI = 0V
30.0
RfXIN
Feedback resistor
XIN
RfXCIN
Feedback resistor
XCIN
V RAM
RAM retention voltage
When clock is stopped
2.0
ROSC
Oscillation frequency of
Ring oscillator
Mask ROM
300
600
1200
Flash memory
300
600
1200
1.0
MΩ
6.0
MΩ
V
kHz
Note: The VOH standard values of XCOUT differ between flash memory version and mask ROM version.
Therefore, please note that the oscillation constants of sub clock may differ between these versions.
135
Tentative Specifications REV.E1
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Electrical characteristics (Vcc = 5V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Table 1.19.3. (2) Electrical characteristics
(Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) = 16MHz))
Symbol
Icc
Parameter
Power supply current
Measuring condition
I/O pin Mask ROM
has no
load
Flash memory
Mask ROM
Flash memory
Mask ROM
Flash memory
Mask ROM
Flash memory
Mask ROM
Flash memory
Mask ROM
Flash memory
136
Min.
Standard
Typ. Max.
Unit
f(XIN)=16MHz
Square wave, no division
20.0
36.0
mA
f(XIN)=16MHz
Square wave, no division
18.0
36.0
mA
Ring oscillator mode
No division
800
µA
1300
µA
100
µA
Ring oscillator mode
No division
Ring oscillator mode
When a WAIT instruction
is executed
Ring oscillator mode
When a WAIT instruction
is executed
f(XCIN)=32kHz
Square wave
f(XCIN)=32kHz
Square wave
f(XCIN)=32kHz
When a WAIT instruction
is executed
f(XCIN)=32kHz
When a WAIT instruction
is executed
400
µA
50
µA
700
µA
6
µA
350
µA
Ta=25 C when clock is
stopped
2
µA
Ta=85 C when clock is
stopped
Ta=25 C when clock is
stopped
300
600
Ta=85 C when clock is
stopped
300
600
20
µA
Tentative Specifications REV.E1
t
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en Specifications in this manual are tentative and subject to change.
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Mitsubishi microcomputers
M30100/M30102 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Table 1.19.4. A-D conversion characteristics (Note 1)
Symbol
Parameter
Measuring condition
Min.
Standard
Typ. Max.
Resolution
VREF =VCC
Absolute Sample & hold function not available
VREF =VCC = 5V
accuracy Sample & hold function available(10bit) VREF =VCC= 5V AN0 to AN11 input
–
–
ANEX0, ANEX1 input,
external op-amp
connected mode
Sample & hold function available(8bit)
RLADDER
tCONV
tCONV
tSAMP
VREF
VIA
VREF = VCC = 5V
Unit
Bits
10
±3
±3
LSB
LSB
±7
LSB
±2
LSB
40
Ladder resistance
Conversion time(10bit)
VREF =VCC
10
f(XIN)=10MHz, øAD=fAD=10MHz
Conversion time(8bit)
Sampling time
f(XIN)=10MHz, øAD=fAD=10MHz
Reference voltage
f(XIN)=10MHz, øAD=fAD=10MHz
3.3
2.8
0.3
2
VCC
kΩ
µs
µs
µs
V
Analog input voltage
f(XIN)=10MHz, øAD=fAD=10MHz
0
VREF
V
f(XIN)=10MHz, øAD=fAD=10MHz
Note 1: Unless otherwise noted: VCC = VREF =5V, VSS = 0V at Ta = 25oC, f(XIN) = 16MHz
Note 2: Divide the fAD if f(XIN) exceeds 10MHz, and make AD operation clock frequency (øAD) equal to or
lower than 10MHz.
Table 1.19.5. D-A conversion characteristics (Note 1)
Symbol
tsu
RO
IVREF
Parameter
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Measuring condition
Min.
4
(Note 2)
Standard
Typ. Max.
10
8
1.0
3
20
1.5
Unit
Bits
%
µs
kΩ
mA
Note 1: Unless otherwise noted: VCC = VREF =5V, VSS = 0V at Ta = 25oC, f(XIN) = 16MHz
Note 2: The A-D converter's ladder resistance is not included.
When D-A register contents are not "0016", the current IVREF always flows even though VREF may
have been set to be unconnected by the A-D control register.
137
Tentative Specifications REV.E1
t
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Electrical characteristics (Vcc = 5V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Ta =
25oC)
Table 1.19.6. XIN input
Symbol
Parameter
tc(XIN)
XIN input cycle time
twH(XIN)
XIN input HIGH pulse width
twL(XIN)
XIN input LOW pulse width
Standard
Min.
Max.
Unit
ns
62.5
30
30
ns
ns
Table 1.19.7. CNTR0 input
Symbol
Parameter
tc(CNTR0)
CNTR0 input cycle time
twH(CNTR0)
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
twL(CNTR0)
Standard
Min.
Max.
Unit
100
40
ns
40
ns
ns
Table 1.19.8. TCIN input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TCIN)
TCIN input cycle time
400 (Note1)
ns
twH(TCIN)
TCIN input HIGH pulse width
TCIN input LOW pulse width
200 (Note2)
200 (Note2)
ns
twL(TCIN)
ns
Note1 : Use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value.
Note2 : Use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
Table 1.19.9. Serial I/O
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
tw(CKH)
CLKi input cycle time
CLKi input HIGH pulse width
200
100
ns
ns
tw(CKL)
CLKi input LOW pulse width
100
ns
td(C-Q)
th(C-Q)
TxDi output delay time
tsu(D-C)
th(C-D)
80
TxDi hold time
RxDi input setup time
RxDi input hold time
0
30
90
ns
ns
ns
ns
_______
Table 1.19.10. External interrupt INTi input
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
Standard
Min.
Max.
250 (Note1)
250 (Note2)
Unit
ns
ns
Note1 : When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width to the greater
value,either ( 1/ digital filter clock frequency x 3) or min. value.
Note2 : When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pusle width to the greater
value,either ( 1/ digital filter clock frequency x 3) or min. value.
138
Tentative Specifications REV.E1
t
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Electrical characteristics (Vcc = 5V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P0
30pF
P1
P2
P3
P4
Figure 1.19.1. Port P0 to P4 measurement circuit
Figure 1.19.2. Vcc=5V timing diagram
139
Tentative Specifications REV.E1
t
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en Specifications in this manual are tentative and subject to change.
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Electrical characteristics (Vcc = 5V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TxDi
tsu(D-C)
td(C-Q)
RxDi
tw(INL)
INTi input
tw(INH)
140
th(C-D)
Tentative Specifications REV.E1
t
r
en Specifications in this manual are tentative and subject to change.
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Electrical characteristics (Vcc = 3V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.19.11. (1) Electrical characteristics
(Note: Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 5MHz)
Parameter
Symbol
VOH
VOH
VOH
Measuring condition
HIGH output P00 to P07,P10 to P17,P20,P21,
voltage
P30 to P37,P40 to P47
HIGH output
voltage
XOUT
HIGH output
voltage
XCOUT
(Note)
IOH = - 1 mA
VOL
2.5
LOW POWER IOH = - 50 µA
2.5
VOL
VOL
VT+ -VT-
LOW output
voltage
LOW output
voltage
Hysteresis
P10 to P17
XOUT
XcOUT
V
Flash memory
Mask ROM
3.0
LOW POWER No load
Flash memory
Vcc
Mask ROM
1.6
Vcc
V
IOL = 1 mA
0.5
HIGH POWER IOH = 2 mA
0.5
LOW POWER IOH = 1mA
0.5
HIGH POWER IOH = 0.1 mA
0.5
LOW POWER IOH = 50 µA
0.5
HIGH POWER No load
0
LOW POWER No load
0
V
V
V
V
CNTR0,TCIN,
INT0 to INT3,CLK0,CLK1
RxD0, RxD1,KI0 to KI3,P45
0.2
0.8
V
0.2
1.8
V
4.0
µA
-4.0
µA
120.0 500.0
kΩ
VT+ -VT-
Hysteresis
RESET
IIH
HIGH input
current
P00 to P07,P10 to P17,P20,P21,
P30 to P37,P40 to P47, XIN
RESET, CNVss
LOW input
current
P00 to P07,P10 to P17,P20,P21,
P30 to P37,P40 to P47, XIN
RESET, CNVss
RPULLUP
Pull-up
resistor
P00 to P07,P10 to P17,P20,P21,
P30 to P37,P40 to P47
IIL
Unit
V
HIGH POWER No load
No load
LOW output P00 to P07,P20,P21,
voltage
P30 to P37,P40 to P47
LOW output
voltage
Standard
Typ. Max.
2.5
HIGH POWER IOH = - 0.1 mA
No load
VOL
Min.
VI = 3V
VI = 0V
VI = 0V
66.0
RfXIN
Feedback resistor
XIN
RfXCIN
Feedback resistor
XCIN
V RAM
RAM retention voltage
When clock is stopped
2.0
ROSC
Oscillation frequency of
Ring oscillator
Mask ROM
150
300
600
Flash memory
250
500
1000
3.0
MΩ
10.0
MΩ
V
kHz
Note: The VOH standard values of XCOUT differ between flash memory version and mask ROM version.
Therefore, please note that the oscillation constants of sub clock may differ between these versions.
141
Tentative Specifications REV.E1
t
r
en Specifications in this manual are tentative and subject to change.
de
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Electrical characteristics (Vcc = 3V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.19.11. (2) Electrical characteristics
(Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 5MHz)
Symbol
Icc
Parameter
Power supply current
Measuring condition
I/O pin Mask ROM
has no
load
Flash memory
Standard
Typ. Max.
Unit
f(XIN)=5MHz
Square wave, no division
4.0
8.0
mA
f(XIN)=5MHz
Square wave, no division
8.0
14.0
mA
Mask ROM
Ring oscillator mode
No division
200
µA
Flash memory
Ring oscillator mode
No division
1000
µA
Mask ROM
Ring oscillator mode
When a WAIT instruction
is executed
Ring oscillator mode
When a WAIT instruction
is executed
40
µA
350
µA
30
µA
550
µA
4
µA
300
µA
Flash memory
Mask ROM
Flash memory
Mask ROM
Flash memory
Mask ROM
Flash memory
142
Min.
f(XCIN)=32kHz
Square wave
f(XCIN)=32kHz
Square wave
f(XCIN)=32kHz
When a WAIT instruction
is executed
f(XCIN)=32kHz
When a WAIT instruction
is executed
Ta=25 C when clock is
stopped
2
Ta=85 C when clock is
stopped
20
µA
Ta=25 C when clock is
stopped
250
500
Ta=85 C when clock is
stopped
250
500
µA
Tentative Specifications REV.E1
t
r
en Specifications in this manual are tentative and subject to change.
de
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v
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Electrical characteristics (Vcc = 3V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.19.12. A-D conversion characteristics (Note)
Symbol
–
–
RLADDER
tCONV
VREF
VIA
Parameter
Resolution
Absolute Sample & hold function not available
accuracy (8-bit)
Ladder resistance
Conversion time(8-bit)
Reference voltage
Measuring condition
Min.
Standard
Typ. Max.
10
±2
VREF =VCC
VREF =VCC = 3V, øAD=fAD/2
10
VREF =VCC
Analog input voltage
Note: Unless otherwise noted: VCC = VREF =3V, VSS = 0V at Ta =
25oC,
40
Unit
Bits
LSB
14.0
2.7
VCC
kΩ
µs
V
0
VREF
V
f(XIN) = 7MHz
Table 1.19.13. D-A conversion characteristics (Note 1)
Symbol
tsu
RO
IVREF
Parameter
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Measuring condition
Min.
4
(Note 2)
Standard
Typ. Max.
10
8
1.0
3
20
1.5
Unit
Bits
%
µs
kΩ
mA
Note 1: Unless otherwise noted: VCC = AVCC =VREF = 3V, VSS = AVSS =0V at Ta = 25oC, f(XIN) = 7MHz
Note 2: The A-D converter's ladder resistance is not included.
When D-A register contents are not "0016", the current IVREF always flows even though VREF may
have been set to be unconnected by the A-D control register.
143
Tentative Specifications REV.E1
t
r
en Specifications in this manual are tentative and subject to change.
de
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Electrical characteristics (Vcc = 3V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = 25oC)
Table 1.19.14. XIN input
Symbol
Parameter
tc(XIN)
XIN input cycle time
twH(XIN)
XIN input HIGH pulse width
twL(XIN)
XIN input LOW pulse width
Standard
Min.
Max.
Unit
143
ns
70
70
ns
ns
Table 1.19.15. CNTR0 input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CNTR0)
twH(CNTR0)
CNTR0 input cycle time
CNTR0 input HIGH pulse width
300
120
ns
ns
twL(CNTR0)
CNTR0 input LOW pulse width
120
ns
Table 1.19.16. TCIN input
Symbol
Parameter
tc(TCIN)
TCIN input cycle time
twH(TCIN)
TCIN input HIGH pulse width
TCIN input LOW pulse width
twL(TCIN)
Standard
Min.
Max.
Unit
1200(Note1)
ns
600(Note2)
600(Note2)
ns
ns
Note1 : Use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value.
Note2 : Use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
Table 1.19.17. Serial I/O
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
tw(CKH)
CLKi input cycle time
CLKi input HIGH pulse width
300
150
ns
ns
tw(CKL)
CLKi input LOW pulse width
150
ns
td(C-Q)
th(C-Q)
TxDi output delay time
tsu(D-C)
th(C-D)
160
TxDi hold time
0
50
RxDi input setup time
RxDi input hold time
90
ns
ns
ns
ns
_______
Table 1.19.18. External interrupt INTi input
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
Standard
Min.
Max.
380(Note1)
380(Note2)
Unit
ns
ns
Note1 : When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width to the greater
value,either ( 1/ digital filter clock frequency x 3) or min. value.
Note2 : When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pusle width to the greater
value,either ( 1/ digital filter clock frequency x 3) or min. value.
144
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Electrical characteristics (Vcc = 3V)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TxDi
tsu(D-C)
td(C-Q)
th(C-D)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 1.19.3. Vcc=3V timing diagram
145
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M30100/M30102 Group
Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
Outline Performance
Table 1.20.1 shows the outline performance of the M16C/10 (flash memory version).
Table 1.20.1. Outline performance of the M16C/10 (flash memory version)
Item
Performance
Power supply voltage
4.2V to 5.5V when f(XIN)=16MHz
Program/erase voltage
Vcc=5.0V±10%
Flash memory operation mode
Standard serial I/O
Erase block
division
User ROM area
One division (24 Kbytes)
Boot ROM area
One division (384 bytes) (Note)
Program method
Collective program
Erase method
Collective erase
Program/erase count
100 times
Data retention
10 years
Note: The boot ROM area contains a control program which is used to communicate with a dedicated
external device (writer). This area cannot be erased nor programmed.
146
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Appendix Standard Serial I/O Mode (Flash Memory Version)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
The M16C/10 (flash memory version) contains the flash memory that can be rewritten with a single voltage. For this flash memory, one mode is available in which to read, program, and erase: standard serial I/
O mode in which the flash memory can be manipulated using a decicated external device (writer).
Figure 1.20.1 shows the on-chip flash memory. In addition to the ordinary user ROM area to store a
microcomputer operation control program, the flash memory has a boot ROM area that is used to store a
program to control communications with the dedicated external device (writer) in the standard serial I/O
mode. This boot ROM area cannot be erased nor rewritten.
0FA00016
User ROM area
(24Kbytes)
Type
Flash memory
size
Flash memory
start address
M30100F3
M30102F3
24Kbytes
0FA00016
Note : The boot ROM area cannot be erased /
written.
Boot ROM area
(384bytes)
0FFFFF16
0FFE8016
0FFFFF16
Figure 1.20.1. Block diagram of flash memory version
147
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M30100/M30102 Group
Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
Pin functions (Flash memory standard serial I/O mode)
Name
Pin
VCC,VSS
Description
I/O
Power input
Apply program/erase protection voltage (5V±10%) to Vcc pin and
0 V to Vss pin.
Connect a capacitor (0.1µF) to Vss pin.
IVCC
IVCC
CNVSS
CNVSS
I
Connect to Vcc.
RESET
Reset input
I
Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
VREF
Reference voltage input
I
Enter the reference voltage for AD from this pin.
P00 to P07
Input port P0
I
P10 to P17
Input port P1
I
P20 to P27
Input port P2
I
P30 to P37
Input port P3
I
P40 to P47
Input port P4
I
148
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Tentative Specifications REV.E1
ent Specifications in this manual are tentative and subject to change.
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Mitsubishi microcomputers
M30100/M30102 Group
Appendix Standard Serial I/O Mode (Flash Memory Version)
Mode setup method
Signal
Value
CNVss
Vcc
RESET
Vss to Vcc
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Vcc = 5V±10%
VCC
P32/TYOUT
P33/TCIN
P30/TXOUT
VSS
P31/TZOUT
P07/AN0
IVCC
0.1µF
24 23 22 21 20 19 18 17
P06/AN1
P05/AN2
P04/AN3
VREF
P03/AN4
P02/AN5
P01/AN6
P00/AN7
25
26
27
28
29
16
M30100F3FP
M30100F3TFP
30
31
32
15
14
13
12
11
10
9
1 2 3 4 5 6
P45/INT0
P10/KI0/AN8
P11/KI1/AN9
P12/KI2/AN10
P13/KI3/AN11
P14/TxD0
P15/RxD0
P16/CLK0
TxD0
RxD0
CLK0
7 8
VSS
XIN
VCC
P17/CNTR0
Connect
oscillator
circuit.
BUSY
RESET
P37/TxD1/RxD1
CNVSS
RESET
XOUT
VSS
VCC
Package: 32P6U-A
Figure 1.20.2. Pin connections for serial I/O mode (1)
149
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M30100/M30102 Group
Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M o d e se tu p m e th o d
S ig n a l
V a lu e
C N V ss
V cc
RESET
V ss to V cc
Mitsubishi microcomputers
P42/INT3
P43/INT1
P32/TYOUT
P33/TCIN
VCC
P40/ANEX0
P41/ANEX1
P07/AN0
IVCC
0.1µF
P30/TXOUT
VSS
P31/TZOUT
* V cc = 5 V ±10%
36 35 34 33 32 31 30 29 28 27 26 25
P06/AN1
P05/AN2
P04/AN3
VREF
N.C
N.C
N.C
P03/AN4
P02/AN5
P01/AN6
P00/AN7
P37/TxD1/RxD1
24
23
22
21
37
38
39
40
41
42
43
44
45
46
47
48
20
19
M30102F3FP
M30102F3TFP
1
2
3 4
5
6 7
8
18
17
16
15
14
13
9 10 11 12
P44/INT2
P45/INT0
P10/KI0/AN8
P11/KI1/AN9
P12/KI2/AN10
P20
N.C
P21
P13/KI3/AN11
P14/TxD0
P15/RxD0
TxD0
RxD0
P16/CLK0
CLK0
Connect
oscillator
circuit.
VCC
BUSY
RESET
XOUT
VSS
XIN
VCC
P17/CNTR0
RESET
P36/CLK1
P35/RxD1
P34/CLKS1/DA
CNVSS
P47/XCIN
P46/XCOUT
VSS
Package: 48P6Q-A
Figure 1.20.3. Pin connections for serial I/O mode (2)
150
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Appendix Standard Serial I/O Mode (Flash Memory Version)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the control functions, addresses and data needed to
operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two
standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both
modes require a dedicated external device (writer).
In the standard serial I/O mode, the CPU controls rewrite to the flash memory and communication with the
dedicated external device (writer). This mode starts when the reset is released, which is done when the
CNVss pin is "H" level. (In the ordinary microprocessor mode, set CNVss pin to "L" level.)
This control program for communications with the dedicated external device (writer) is written in the boot
ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the boot
ROM area cannot be erased nor rewritten. Figures 1.20.2 and 1.20.3 show the pin connections for the
standard serial I/O mode. The communications with the dedicated external device (writer) uses UART0.
Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized)
according to the level of CLK0 pin when the reset is released.
To use standard serial I/O mode 1 (clock synchronized), set the CLK0 pin to "H" level and release the reset.
The operation uses the four UART0 pins CLK0, RxD0, TxD0 and BUSY.
To use standard serial I/O mode 2 (clock asynchronized), set the CLK0 pin to "L" level and release the
reset. The operation uses the two UART0 pins RxD0 and TxD0. The BUSY pin should be open.
151
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M30100/M30102 Group
Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
Example Circuit Application for The Standard Serial I/O Mode 1
The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary
according to dedicated external device (writer), therefore see the dedicated external device (writer)
manual for more information.
Clock input
BUSY output
CLK0
BUSY
Data input
RXD0
Data output
TXD0
M16C/10 Group
(Flash memory version)
CNVss
(1) Control pins and external circuitry will vary according to the dedicated
external device (writer). For more information, see the dedicated external
device (writer) manual.
(2) In this example, the microprocessor mode and standard serial I/O mode
are switched via a switch.
Figure 1.20.4. Example circuit application for the standard serial I/O mode 1
152
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Appendix Standard Serial I/O Mode (Flash Memory Version)
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example Circuit Application for The Standard Serial I/O Mode 2
The below figure shows a circuit application for the standard serial I/O mode 2.
CLK0
Monitor output
BUSY
Data input
RXD0
Data output
TXD0
M16C/10 Group
(Flash memory version)
CNVss
(1) In this example, the microprocessor mode and standard serial I/O mode
are switched via a switch.
Figure 1.20.5. Example circuit application for the standard serial I/O mode 2
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Mitsubishi microcomputers
M30100/M30102 Group
Package
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Package
32P6U-A
MMP
EIAJ Package Code
LQFP32-P-0707-0.80
Plastic 32pin 7✕7mm body LQFP
Weight(g)
Lead Material
Cu Alloy
MD
b2
HD
D
ME
e
JEDEC Code
–
32
25
I2
24
Recommended Mount Pad
Symbol
E
HE
1
8
17
9
16
A
b
x
L
Lp
M
y
EIAJ Package Code
LQFP48-P-77-0.50
A3
x
y
b2
I2
MD
ME
Detail F
MMP
48P6Q-A
c
A1
A2
F
A3
L1
e
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.32
0.37
0.45
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
0.8
–
–
8.8
9.0
9.2
8.8
9.0
9.2
0.3
0.5
0.7
1.0
–
–
0.6
0.45
0.75
–
0.25
–
–
–
0.2
0.1
–
–
0°
10°
–
0.5
–
–
1.0
–
–
7.4
–
–
–
–
7.4
Plastic 48pin 7✕7mm body LQFP
Weight(g)
–
Lead Material
Cu Alloy
MD
ME
e
JEDEC Code
–
b2
HD
D
48
37
1
I2
Recommended Mount Pad
36
E
HE
Symbol
25
12
13
24
A
F
L1
A3
A2
e
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
b
154
x
M
L
Detail F
Lp
c
y
A1
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.17
0.22
0.27
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
0.5
–
–
8.8
9.0
9.2
8.8
9.0
9.2
0.35
0.5
0.65
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.08
–
–
0.1
–
0°
8°
–
–
0.225
1.0
–
–
7.4
–
–
–
–
7.4
REVISION HISTORY
Rev.
Date
Page
B
04/20/01
All pages
1
1
2-4
5-7
8
9
9
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11
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15
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17
18 - 19
21
21
24
25
26
27
29
31
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32
33
33
35
38
38
40
42
46
50
51
51
53
53
53
56
58
59
59
60
60
M30100/M30102 GROUP DATA SHEET
Description
Summary
Figure and Table numbers are revised.
Features are partly revised.
Page numbers of Table of Contents are partly revised.
Figure 1.1.1 to Figure 1.1.3 are partly revised.
Figure 1.1.4 to Figure 1.1.6 are partly revised.
Table 1.1.1 is partly revised.
Figure 1.1.7 is partly revised.
Figure 1.1.8 is partly revised.
Pin description is partly revised.
Explanation of “Memory” is partly revised.
Explanation of “Reset” is partly revised.
Figure 1.5.2 (example reset circuit for voltage check circuit )is added.
Figure 1.5.3 is partly revised.
Figure 1.5.4 is partly revised.
Explanation of “Software Reset” is partly revised.
Processor mode register 0 in Figure 1.5.5 is partly revised. Note 2 is deleted.
Processor mode register 1 is added to Figure 1.5.5.
Figure 1.6.1 and Figure 1.6.2 are partly revised.
Table 1.8.1 is partly revised.
Figure 1.8.1 is partly revised. External RC oscillator is added.
Figure 1.8.4 is partly revised.
Figure 1.8.5 is added.
Explanation of “Stop Mode” is partly revised.
Table 1.8.4 is partly revised.
Figure 1.9.1 is partly revised.
Explanation of “Oscillation Stop Detection Function” is partly revised.
Table 1.10.1 is partly revised.
Figure 1.10.1 is partly revised.
Figure 1.10.2 is partly revised. Note 2 and Note 3 is partly revised. Note 5 is deleted.
Explanation of “Oscillation stop detection interrupt enable bit (CM21) partly revised.
Operation select bit (CM27) is deleted.
Figure 1.11.1 is partly revised.
“UART1 receive interrupt” in (1) Special interrupts is partly revised.
“Timer C interrupt” in (2) Peripheral I/O interrupt is partly revised.
Table 1.12.2 is partly revised.
Figure 1.12.3 is partly revised.
Table 1.12.5 is partly revised.
Figure 1.12.9 is_______
partly revised.
Explanation of “INT interrupt” is partly revised.
External interrupt enable register in Figure 1.12.10 is partly revised.
Explanation of “Key interrupt” is partly revised.
Figure 1.12.13 is partly revised.
Figure 1.12.14 is partly revised.
Explanation of “Watchdog Timer” is partly revised.
Explanation of “Timer 1” is partly revised.
Figure 1.14.2 is partly revised.
Figure 1.14.3 is partly revised. Note 1 and Note 2 are added.
Explanation of “(2) Pulse output mode” is partly revised.
Explanation of “(4) Pulse width measure mode” is partly revised.
155
REVISION HISTORY
Rev.
M30100/M30102 GROUP DATA SHEET
Date
Description
Summary
Page
B1
156
05/15/01
61
61
61
62
63
64
65
65
66
66
67
68
72
72
72
73
73
74
75
78
78
78
79
79
81
84
85
86
89
89
90
91
92
94
94
95
95
96
96
97
98
100
101
102
103
104
105
Explanation of “(5) Pulse period measure mode” is partly revised.
Explanation of precaution is partly revised.
Figure 1.14.4 is partly revised.
Explanation of Timer Y is partly revised.
Explanation of “(2) Programmable waveform generation mode” is partly revised.
Figure 1.14.5 is partly revised.
Figure 1.14.6 is partly revised.
Note 1 and Note 2 are added to Timer Y, Z mode register in Figure 1.14.6.
Explanation of Timer Z is partly revised.
Figure 1.14.7 is partly revised.
Figure 1.14.9 is partly revised.
Explanation of “(2) Programmable waveform generation mode” is partly revised.
Explanation of “Timer C” is partly revised.
Figure 1.14.10 is partly revised.
Note 1 is added to Timer C control register 0 in Figure 1.14.10.
Figure 1.14.11 is partly revised.
Figure 1.14.12 is partly revised.
Table 1.14.1 and its Note are partly revised.
Figure 1.15.1 is partly revised.
Note is added to UARTi transmit/receive mode register in Figure 1.15.4 is partly revised.
UARTi transmit/receive control register 0 in Figure 1.15.4 is partly revised.
Note 1 and Note 2 of UARTi transmit/receive control register 0 in Figure 1.15.4 are deleted .
Note 1 is added to UARTi transmit/receive control register 1 in Figure 1.15.5.
UARTi transmit/receive control register 2 is added to Figure 1.15.5.
Table 1.15.2 is partly revised.
Figure 1.15.10 is partly revised.
Table 1.15.3 is partly revised.
Table 1.15.4 is partly revised.
Explanation of “A-D Converter” is partly revised.
Table 1.16.1 is partly revised.
Figure 1.16.1 is partly revised.
A-D control register 0 in Figure 1.16.2 is partly revised.
Figure 1.16.3 is partly revised.
“Input pin” and Note in Table 1.16.3 are revised.
Figure 1.16.5 is partly revised.
Explanation of “Extended analog input pins” is partly revised.
Explanation of “External operation amp connection mode” is partly revised.
Explanation of “D-A Converter” is partly revised.
Figure 1.17.1 is partly revised.
Figure 1.17.3 is partly revised.
Explanation of “Programmable I/O Ports” is partly revised.
Figure 1.18.2 is revised.
Figure 1.18.3 is revised.
Figure 1.18.4 is revised.
Figure 1.18.5 is revised.
Figure 1.18.6 is revised.
Table 1.18.1 is revised.
15
19
31
Figure 1.5.3 is partly revised.
Figure 1.6.2 is partly revised.
Table 1.10.1 is partly revised.
REVISION HISTORY
Rev.
Date
Page
32
51
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91
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C1
11/20/01
01
01
02 - 05
08
09
09
10
11
15
15
16
19
21
22
22
23
24
25
26
27
27
29
31
32
32
33
34
36
39
39
41
45
52
52
53
54
54
56
59 - 72
59 - 72
M30100/M30102 GROUP DATA SHEET
Description
Summary
Figure 1.10.1 is_______
partly revised.
Explanation of “INT interrupt” is partly revised.
Note 3 is added to Table 1.16.1.
Figure 1.16.2 is partly revised.
Figure 1.16. 3 is partly revised.
Table 1.16.2 is partly revised.
Table 1.16.3 is partly revised.
Figure 1.16.5 is partly revised.
Features are partly revised.
Page numbers of Table of Contents are partly revised.
Figure 1.1.1 to 1.1.4 are partly revised.
Table 1.1.1 is partly revised
Explanation of (3) package if partly revised.
Figure 1.1.7 is partly revised.
Pin description is partly revised.
Figure 1.3.1 is partly revised.
Explanation of reset is partly revised.
Figure 1.5.3 is partly revised.
Figure 1.5.4 is partly revised.
Figure 1.6.2 is partly revised.
Figure 1.8.1 is partly revised.
Explanation is partly revised.
Figure 1.8.3 is partly revised.
Explanation of (1)main clock, (3)BCLK and (7)fRING are partly revised.
Note (2) and (5) of register CM1 in Figure 1.8.4 are partly revised.
Register CM2 in Figure 1.8.5 is partly revised.
Explanation of stop mode is partly revised.
Explanation of “status transition of BCLK”, (3)division by 8 mode, (5)no-division
mode and (8)ring oscillation mode are partly revised.
Note is added.
Explanation of power control is partly revised.
Figure 1.9.2 is partly revised.
Explanation of oscillation stop detection function is partly revised.
Table 1.10.1 is partly revised.
Figure 1.10.1 and 1.10.2 are partly revised.
Explanation of CM20 to CM22 are partly revised.
Explanation of protection is partly revised.
Explanation of “UART1
receive interrupt” of (1)special interrupts is partly revised.
_______
_______
Explanation of “INT0 to INT3 interrupt” of (2)peripheral I/O interrupts is partly revised.
Table 1.12.2 is partly revised.
Program examples
are partly revised.
_______
Explanation of INT interrupt is partly revised.
Figure 1.12.10 is partly revised.
Figure 1.12.11 is partly revised.
Explanation of key input interrupt is partly revised.
Figure 1.12.13 and 1.12.14 is partly revised.
Explanation of (1)reading address 0000016 is partly revised.
“Latch” used for reload register related are changed to “reload register.”
Expression of counter content is changed from “00h” to “0016.”
157
REVISION HISTORY
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106
107 - 108
109 - 119
D
158
July/08/02
1
3(ver.C)
6(ver.C)
6
7
7
8
9
M30100/M30102 GROUP DATA SHEET
Description
Summary
Figure 1.14.3 is partly revised.
Explanation of (3) event counter mode is partly revised.
Explanation of (4) pulse width measure mode is partly revised.
Explanation of (5) pulse period measure mode is partly revised.
Figure 1.14.4 is partly revised.
Explanation of (2) programmable waveform generation mode is partly revised.
Explanation of “use of the waveform extend function” is added.
Last paragraph in precaution is partly revised.
Figure 1.14.6 is partly revised.
Figure 1.14.7 is partly revised.
Figure 1.14.8 and 1.14.9 are partly revised.
Explanation of (2) programmable waveform generation mode is partly revised.
Explanation of (3) programmable one-shot generation mode is partly revised.
Explanation of (4) programmable wait one-shot generation mode is partly revised.
Explanation of “use of the waveform extend function” is added.
Explanation of “change of set count values” is partly revised.
Last paragraph in precaution is partly revised.
Figure 1.14.10 is partly revised.
Figure 1.15.1 is partly revised.
Figure 1.15.2 is partly revised.
Figure 1.15.3 is partly revised.
Figure 1.15.4 is partly revised.
Figure 1.15.5 is partly revised.
Table 1.15.1 is partly revised.
Figure 1.15.7 is partly revised.
(e) RxD1 input pin selection function (UART) is added.
Table 1.15.3 is partly revised.
Figure 1.15.13 is partly revised.
(b) RxD1 input pin selection function (UART) is added.
Table 1.16.1, Note 2 is partly revised.
Figure 1.16.1 is partly revised.
Figure 1.16.2 is partly revised.
Figure 1.16.4 is partly revised
Table 1.16.3 is partly revised.
Figure 1.16.5 is partly revised
Explanation of extended analog input pins is partly revised.
Figure 1.16.6 is partly revised.
Explanation of programmable I/O ports is partly revised.
Figure 1.18.1 to 1.18.6 are partly revised.
Table 1.18.1 is partly revised.
Explanation of usage of precaution is added.
Section of electric characteristics is added.
Explanation of overview is partly revised.
Figure 1.1.2 is deleted.
Figure 1.1.5 is deleted.
Table 1.1.1 is partly revised.
(3)Package is partly revised.
Figures 1.1.7 and 1.1.8 are partly revised.
Explanation on CNVss of pin description is partly revised.
Explanation of operation of functional blocks is partly revised.
REVISION HISTORY
Rev.
Date
Page
M30100/M30102 GROUP DATA SHEET
Description
Summary
9
9
14
18
19
20
21
21
23
23
30
31
35
37
37
Explanation of memory is partly revised.
Figure 1.3.1 is partly revised.
Figure 1.5.4 is partly revised.
Figure 1.7.1 is partly revised.
Table 1.8.1 is partly revised.
Figure 1.8.3 is partly revised.
Explanation of (1) main clock is partly revised.
Explanation of (5) fc32 is partly revised.
Figure 1.8.5 is partly revised.
Figure 1.8.6 is added.
Explanation of oscillation stop detection function is partly revised.
Figure 1.10.2 is partly revised.
Figure 1.12.1 is partly revised.
Explanation of UART0 receive interrupt of (1)special interrupts is partly revised.
Explanation of CNTR0 interrupt and TCIN interrupt are added to (2)peripheral I/O
interrupts instead of CNTR0 and TCIN interrupt.
Table 1.12.1 is partly revised.
38
49
Figure 1.12.8 is partly revised.
Figure 1.12.9 is partly revised.
49
Explanation of INT0 input filter is partly revised.
51
Figure 1.12.11 is partly revised.
51
53(rev.C) Explanation of UART0 Receive Hardware Input and Figure 1.12.12 are deleted.
Explanation of CNTR0 interrupt and Figure 1.12.13 are added.
52
Explanation of TCIN interrupt and Figure 1.12.14 are added.
53
Figure 1.13.1 is partly revised.
57
PM1 register is added to Figure 1.13.2.
58
59-94 Timer: Full-fledged revision
Note is added to UARTi transmit buffer register in Figure 1.15.3.
97
UARTi transmit/receive control register 0 of Fig 1.15.4 is partly revised.
98
99
Note of UARTi transmit/receive control register 1 of Fig 1.5.5 is partly revised.
99
Note 2 is added to UART transmit/receive control register 2 in Fig 1.15.5.
100
Table 1.15.1 Note 1 is partly revised.
Table 1.15.2 is partly revised.
101
102
Figure 1.15.7 is partly revised.
104
Explanation of (e) is partly revised.
105
Note 1 of Table 1.15.1 is partly revised.
Table 1.15.4 is partly revised.
106
108
Explanation of (b) is partly revised.
113
Figure 1.16.4 is partly revised.
114
Figure 1.16.5 is partly revised.
118
Figure numbers are revised.
119-122 Figures 1.18.1 to 1.18.4 are partly revised.
123
Figure 1.18.5 is partly revised.
124
Figure 1.18.6 is partly revised.
126
Note 1 is added to Table 1.18.1.
127
(2) is added to explanation of precautionary note of serial I/O.
129
(3) is added to explanation of precautionary note of noise.
129
Explanation of precautionary notes of Timers Y, Z and C are added.
130
Notes 2 and 3 of Table 1.19.2 are partly revised.
131
Note 5 of Table 1.19.2 is partly revised.
159
REVISION HISTORY
Rev.
Date
Page
M30100/M30102 GROUP DATA SHEET
Description
Summary
132-133 Table 1.19.3 (1) and (2) are partly revised.
138-139 Table 1.19.11 (1) and (2) are partly revised.
143-150 Section “Flash memory version” is added.
D1
160
Aug/09/02
1
1
1
2
3
6
13
16
19
19
20
20
21
21
22
24
25
27
43
56
57
59
59
60
61
62
63
69
69
69
70
71
72
73
75
75
77
78
81
82
83
85
85
87
88
89
Explanation of overview is partly revised.
Power supply voltage in Features is partly revised.
Flash memory version is added to the table of contents.
Fig 1.1.1 is partly revised
Fig 1.1.2 is partly revised.
Table 1.1.6 is partly revised.
Figs 1.5.1 and 1.5.2 are partly revised.
Note is added to Figs 1.6.1 and 1.6.2.
Note is added to Table 1.8.1.
Note 2 is added to Fig 1.8.1.
Explanation of ring oscillator is partly revised.
Fig 1.8.3 is partly revised.
Explanation of (3)BCLK is partly revised.
Explanation of (4) peripheral function clock is partly revised.
Note 8 for CM0 and Note 1 for CM1 in Fig 1.8.4 are partly revised.
Explanation of stop mode is partly revised.
Explanation of (5) no-division mode is partly revised.
Explanation of (3) stop mode is partly revised.
Explanation of changing the interrupt request bit is added.
Explanation of changing the interrupt request bit is added.
Explanation of WDT is partly revised.
Explanation of timer is partly revised.
Note is added to Table 1.14.1.
Fig 1.14.1 is partly revised.
TCSS register in Fig 1.14.2 is partly revised.
Fig 1.14.3 is partly revised.
TCSS register in Fig 1.14.5 is partly revised.
Table 1.14.7 partly revised.
Note is added to Table 1.14.7.
Note is deleted from Fig 1.14.11.
Fig 1.14.13 is partly revised.
TYZOC register in Fig 1.14.15 is partly revised.
TCSS register in Fig 1.14.16 is partly revised.
Note 1 and Note 2 are added to Table 1.14.8.
Explanation of (2) programmable waveform generation mode is partly revised.
Notes of Table 1.14.9 are partly revised.
Note is added to Fig 1.14.19.
Fig 1.14.20 is partly revised.
TCSS register in Fig 1.14.23 is partly revised.
TYZOC register in Fig 1.14.24 is partly revised.
Note 1 and Note 2 are added to Table 1.14.10.
Explanation of (2) programmable waveform generation mode is partly revised.
Notes of Table 1.14.11 are partly revised.
Notes of Table 1.14.12 are partly revised.
Note 3 of PUM in Fig 1.14.27 is partly revised.
Fig 1.14.28 is partly revised.
REVISION HISTORY
Rev.
Date
Page
E
Dec/20/02
90
90
92
93
94
95
98
99
106
107
109
110
127
127
128
129
130
130
130
130
132
133-134
139-140
147
148
1
2
3
13
19
20
22
25
26
49
50
52
53
54
54
55
57
61
62
63
64
65
66
67
69
M30100/M30102 GROUP DATA SHEET
Description
Summary
Explanation of (4) programmable wait one-shot generation mode is partly revised.
Notes of Table 1.14.13 are partly revised.
Fig 1.14.30 is added.
Table 1.14.14 are partly revised.
TCC0 register in Fig 1.14.32 is partly revised.
Fig 1.14.33 is partly revised.
Notes of UiTB register and UiRB register in Fig 1.15.3 are partly revised.
UiMR register in Fig 1.15.4 is partly revised.
Sleep mode is deleted from select function on Table 1.15.3.
Fig 1.15.11 is partly revised.
Explanation of (a) sleep mode is deleted.
Note 2 in Table 1.16.1 is partly revised.
Explanation of serial I/O is partly revised.
Explanation #5 is added to A-D converter.
Explanation of stop mode is added.
Explanation of changing the interrupt request bit is added.
Explanation of Timer 1 and Timer X, Y, Z are added.
Explanation of #2 of Timer Y is partly revised.
Explanation of #2 of Timer Z is partly revised.
Explanation of #1 of Timer C is partly revised.
Note 1 is added to Table 1.19.2.
Table 1.19.3 (1) and (2) are partly revised.
Table 1.19.11 (1) and (2) are partly revised.
Fig 1.20.1 is partly revised.
Fig 1.20.2 is partly revised.
Table of Contents is partly revised.
Fig 1.1.1 is partly revised.
Fig 1.1.2 is partly revised.
Explanation of Reset and Fig.1.5.1 are partly revised.
Table1.18.1 is partly revised.
Fig 1.8.2 and Fig 1.8.3. are partly revised.
Fig 1.8.4 is partly revised.
Note is partly revised.
Table 1.8.4 is partly revised.
Fig 1.12.9 is partly revised.
Explanation of INT interrupt is partly revised.
Note 2 and Note 3 are added to Table 1.12.12.
Fig 1.12.13. is partly revised.
Header is partly revised.
Explanation of key input interrupt is partly revised.
Header is partly revised.
Explanation of WDT and Fig 1.13.1 are partly revised.
Note 5 is added to Table 1.14.2.
Fig 1.14.4 is partly revised. Note 2 and Note 3 are added to Fig 1.14.4.
Note 5 is added to Table 1.14.5.
Fig 1.14.6 is partly revised. Note 1 is added to Fig 1.14.6.
Fig 1.14.7 is partly revised. Note 3 is added to Fig 1.14.7.
Fig 1.14.8 is partly revised. Note 1 is added to Fig 1.14.8.
Fig 1.14.9 is partly revised. Note 1 is added to Fig 1.14.9.
Table 1.14.7 is partly revised. Note is partly revised.
161
REVISION HISTORY
Rev.
Date
E
Dec/20/02
Page
69
70
73
75
79
82
82
83
83
85
89
95
104
110
117
127
131
135
136
138
138
138
141
142
144
E1
162
Feb/13/03
144
144
149
150
154
6
7
9
29
134
136
142
M30100/M30102 GROUP DATA SHEET
Description
Summary
Fig 1.14.11.is partly revised. Note 1 and Note 2 are added to Fig 1.14.11.
Fig 1.14.12 is added.
Fig 1.14.16 is partly revised. Note 5 is added to Fig 1.14.16.
Note 2 is added to Fig 1.14.17.
Fig 1.14.20 is partly revised.
Note 4 is added to Timer Y,Z waveform output control register in Fig 1.14.23.
Note 5 is added to Timer count source setting register in Fig 1.14.23.
Note 2 is partly revised to Timer Y,Z output control register in Fig 1.14.24.
Note is added to External input enable register in Fig 1.14.24.
Note 2 is added to Fig 1.14.25.
Fig 1.14.27 is partly revised.
Fig 1.14.32 is partly revised.
Fig 1.15.7 is partly revised.
Fig 1.15.13 is partly revised.
Fig 1.16.6 is partly revised.
Table 1.18.1 is partly revised and Note 3 is added.
Explanation of Timer X is added.
Table 1.19. 3 (1) is partly revised.
Table 1.19. 3 (2) is partly revised.
Table 1.19.6, Table 1.19.7 and Table 1.19.8 is changed to Table.1.19.7, Table
1.19.8 and Table 1.19.6.
Note 1 and Note 2 are added to Table 1.19.8.
Note 1 and Note 2 are added to Table 1.19.10.
Table 1.19. 11 (1) is partly revised.
Table 1.19. 11 (2) is partly revised.
Table 1.19.14, Table 1.19.15 and Table 1.19.16 is changed to Table.1.19.15, Table
1.19.16 and Table 1.19.14.
Note 1 and Note 2 are added to Table 1.19.16.
Note 1 and Note 2 are added to Table 1.19.18.
Fig 1.20.2 is partly revised.
Fig 1.20.3 is partly revised.
Package is added.
Table 1.1.1 value of power consumption
Fig 1.1.5 is partly revised.
Fig 1.3.1 is partly revised.
Fig 1.9.2 is partly revised.
Table 1.19.2 IOL(peak)/IOL(avg)
Table 1.19.3(2) Icc
Table 1.19.11(2) Icc
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Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
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© 2003 MITSUBISHI ELECTRIC CORP.
Printed in Japan (ROD) II
New publication, effective February. 2003.
Specifications subject to change without notice.