APW7075

APW7075
Step-Up Converter and LDO Combo
Features
•
General Description
The APW7075 is a PWM/PFM, high-efficiency, and stepup DC-DC converter with an integrated LDO input switch
Built-In a 500mA LDO and Synchronous Step-Up
DC-DC Converter
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for dual mode application. During battery mode operation,
the APW7075 acts as synchronous rectifier and step-up
Built-In PWM/PFM Operating Mode
DC-DC converter with a fixed or adjustable output voltage.
When the VIN pin sense 5V input voltage, the APW7075 is
Provided Dual Input Power Sources
Connect FB to OUT for 3.3V Output Voltage or
switched to LDO operation mode, maintaining the con-
GND for 2.5V Output Voltage or an External
stant output voltage.
Resistor Divider for Adjustable Output Voltage.
The input voltage ranges from 0.6 V to 4.5V for step-up
Fixed 300kHz Operating Frequency
DC-DC converter. The start-up is guaranteed at 1V and
the device operates down to 0.6V. When the device is at
High Efficiency Up to 94% at 200mA Output
Current
LDO operating mode, the suitable output voltage 3.3V
and loading current 500mA for maximum power con-
0.6V to 4.5V Operating Voltage
sumption are guaranteed.
1V Start-Up Input Voltage
The APW7075 is suited for dual mode and portable bat-
Low Battery Voltage Detection
tery powered appliance with low-battery detector. In dualmode applications, the APW7075 draws power from any
Reverse Voltage Protection
available 5V USB connection and reverts to battery power
when the USB power is removed.
Internal Synchronous Rectifier
Automatic Detection Input Voltage
Pin Configuration
Compact SOP-8P and TSSOP-8 Packages
Lead Free and Green Devices Available
TSSOP-8 Top View
(RoHS Compliant)
Applications
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Dual Mode Power System
SOP-8P Top View
VIN
1
8
OUT
VIN
1
8
FB
2
7
LX
FB
2
7
LX
SHDN
3
6
GND
SHDN
3
6
GND
LBI
4
5
LBO
LBI
4
5
LBO
OUT
USB Peripheral
Camcorders and Digital Camera
= Thermal Pad
(connected to GND plane for better heat
dissipation)
Hand-Held Instrument
PDAs
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
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APW7075
Ordering and Marking Information
Package Code
KA : SOP-8P
O : TSSOP-8
Temperature Range
C : 0 to 70 °C
I : -40 °C to 85°C
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APW7075
Assembly Material
Handling Code
Temperature Range
Package Code
APW7075 KA :
APW7075
XXXXX
XXXXX - Date Code
APW7075 O :
APW7075
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
Value
Unit
Supply Voltage (OUT to GND)
-0.3 to 6.0
V
VIO
Input / Output Pins
-0.3 to 6.0
V
TA
Operating Ambient Temperature Range
0 to 85
°C
TJ
Junction Temperature Range
0 to 150
°C
TSTG
Storage Temperature Range
-65 to +150
°C
260
°C
Typical Value
Unit
124
80
160
°C/W
VOUT
TS
Parameter
Soldering Temperature, 10 Seconds
Thermal Characteristics
Symbol
R θJA
Parameter
Thermal Resistance − Junction to Ambient
SOP-8
SOP-8-P
TSSOP-8
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Rev. A.7 - Oct., 2008
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APW7075
Electrical Characteristics
VBAT = 2V, FB = OUT (VOUT = 3.3V), RL = ∞, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
APW7075
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
Minimum Operating Input Voltage
(Note1)
0.6
-
-
V
Operating Voltage
0.6
-
4.5
V
STEP-UP SECTION
VBAT
Start-up Voltage
RL = 3kΩ
-
0.9
1
V
FSW
Operating Frequency
VOUT = 3.3VX96%
-
300
-
kHz
DMAX
Maximum PWM Duty Cycle
VOUT = 3.3VX96%
-
90
-
%
ILX = 100mA
-
0.3
0.6
Ω
ILX = 100mA
-
0.6
0.9
Ω
FB = OUT, ILOAD = 0mA
3.234
3.3
3.366
V
FB = GND, ILOAD = 0mA
2.45
2.5
2.55
V
Output Voltage Range
External divider
2.5
-
5.5
V
VOUT Dropping Voltage (Note 2)
VOUT = 3.3V, C OUT = 100µF
-
-
150
mV
TSS
Soft-Start Time
VOUT = 3.3V
-
30
100
ms
VREF
FB Input Threshold
ILOAD = 0mA
1.176
1.2
1.224
V
FB Input Current
VFB = 1.4V
-
0.03
50
nA
VOUT = 3.3VX96%, ILOAD = 0mA
-
70
140
µA
Shutdown Current
VSHDN = 0
-
0.1
5
µA
SHDN Input Current
VSHDN = 0 or VOUT
-
0.07
50
nA
Logic LOW (VIL)
-
0.8
0.3
V
Logic HIGH(VIH)
1.4
0.8
-
V
-
10
-
mV
0.588
0.6
0.612
V
POWER MOSFET
RDS(on)-N
Active Switch ON Resistance
RDS(ON)-P Synchronous Switch on Resistance
CONTROL
Output Voltage
VOUT
VOUT(drop)
IFB
IDD
ISHDN
Operating Current
(Note3)
SHDN
LBI Input Hysteresis
VLBI
LBI Threshold
ILBI
LBI Input Current
VLBI = 0.8V
-
1
50
nA
VLBO
LBO Logic Low
VLBI = 0, ISINk = 1mA
-
0.2
0.4
V
ILBO
LBO Off Leakage Current
VLBO = 5.5V, VLBI = 5.5V
-
0.07
1
µA
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APW7075
Electrical Characteristics (Cont.)
Unless otherwise noted these specifications apply over full temperature, 3.9V≤VIN<5.5V, COUT≥10µF, SHDN=VIN ,
Typical values are at TA=+25°C.)
APW7075
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
LDO SECTION (Note 4)
VIN(upper)
Upper VIN Threshold Voltage
VIN increasing
3.75
3.9
4.05
V
VIN(lower)
Lower VIN Threshold Voltage
VIN decreasing
3.65
3.8
3.95
V
-
100
-
mV
VOUT-2
VOUT
VOUT+2
V
VTH
VIN Threshold Hysteresis
VOUT
Output Voltage
ILIM
Current Limit
VIN = 5V
-
1
-
A
ISHORT
Short Current
VOUT = 0V
-
110
-
mA
IOUT
Load Current
500
-
-
mA
0.9
V
VDROP
Iq
Dropout Voltage
ILOAD = 500mA
-
0.6
No load
-
800
1000
uA
ILOAD = 500mA
-
1.1
1.5
mA
Quiescent Current
REGLINE
Line Regulation
4V<VIN<5.5V, ILOAD = 0mA
-
4
10
mV
REGLOAD
Load Regulation
VIN = 5V, 0mA<ILOAD<500mA
-
20
30
mV
Note1: The min. operating voltage is dependent on the duty cycle.
Note2: The dropped output voltage is that the input power (VIN pin) is switched to battery power (LX pin),
when the VIN power is removed.
Note3: Device is boostrapped ( power to the IC comes from OUT). This correlates directly with the actual
battery supply.
Note4: If the LDO mode is used, the output voltage should be under 3.8V.
Copyright  ANPEC Electronics Corp.
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APW7075
Function Pin Description
VIN (Pin 1)
Input supply voltage for dual-mode application. Connect
a schokkty diode (current rating >500mA) to USB port or
5V adapter. If the LDO mode is not used, ties the VIN pin
to the ground.
FB (pin 2)
Internal 1.2V reference voltage. Connect to OUT for 3.3V
output. Connect to the GND for 2.5V output. Use a resistor
divider to set the output voltage from 2.5V to 5.5V.
SHDN (pin 3)
Shutdown input. High = operating mode; Low = shutdown mode.
LBI (Pin 4)
Low-battery comparator input. Internally set to trip at 0.6V.
LBO (pin 5)
Open-drain low battery comparator output. Connect LBO
to OUT through a 100kΩ resistor. Output is low as VLBI <
0.6V. Open-drain device is turned on during shutdown.
OUT (pin 8)
Power output. OUT provides bootstrap power to the IC.
GND (Pin 6)
Ground pins of the circuitry and all ground pins must be
soldered to PCB with proper power dissipation.
LX (pin 7)
N-channel and P-channel power MOSFET drain
connection.
Copyright  ANPEC Electronics Corp.
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APW7075
Application Schematic
VBAT
L1
22UH
C1
10µF
1N5817
Adapter C3
5V 10µF
VOUT 3.3V
R6
1
2
ON
3
8
VIN
OUT
7
FB
SHDN
GND
LBI
LBO
4
OFF
R3
C4
1µF
LX
C2
100µF
6
5
R5
100kΩ
APW7075
R4
Low Battery Output
Connect the R6=500Ω to 1kΩ to GND
Figure 1. Dual Model : 3.3V Output Voltage
VBAT
L1
22UH
C1
10µF
1N5817
Adapter C3
5V 10µF
VOUT 2.5V
R6
1
2
ON
3
8
VIN
OUT
FB
LX
SHDN
GND
LBI
LBO
4
OFF
R3
7
C4
1µF
C2
100µF
6
5
R5
100kΩ
APW7075
R4
Low Battery Output
Connect the R6=500Ω to 1kΩ to GND
Figure 2. Dual Model : 2.5V Output Voltage
Copyright  ANPEC Electronics Corp.
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APW7075
Application Schematic (Cont.)
VBAT
L1
22UH
C1
10µF
1N5817
2.5V ≦ VOUT ≦ 3.8V
Adapter C3
5V 10µF
VOUT 3.6V
R1
R6
300kΩ
1
2
ON
3
8
VIN
OUT
FB
LX
SHDN
GND
LBI
LBO
4
OFF
7
C4
1µF
C2
100µF
6
5
R5
100kΩ
R2
APW7075
150kΩ
R4
Low Battery Output
Connect the R6=500Ω to 1kΩ to GND
Figure 3. Dual Model: Adjustable Output Voltage
0.6V ≦
VBAT ≦ 4.5V
VBAT
L1
22UH
C1
10µF
2.5V ≦ VOUT ≦ 5V
3.6V
VOUT
R1
300kΩ
1
2
ON
3
8
VIN
OUT
FB
LX
SHDN
GND
LBI
LBO
4
OFF
R3
7
C4
1µF
C2
100µF
6
5
100kΩ
R2
150kΩ
APW7075
R4
Low Battery Output
Figure 4. Single Boost Converter
Copyright  ANPEC Electronics Corp.
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APW7075
Block Diagram
VIN
SHDN
Vref
VDD
VDD
FB
VDD
P-MOS
Current
Limit
Y
Q1
VDD
VOUT A
GND B
R1,R2 C
OUT
Vref
Q2
P-MOS
A
B
VDD
Y
PWM/
PFM
controller
C
phase
compensation
FB
LX
Drive
Q3
Oscillator
N-MOS
voltage
reference
GND
soft-start
Q4
LBI
Vref
2
LBO
N-MOS
SHDN
Typical Operating Characteristics
Power Up (VBATTERY=2.4V)
Power Up (VBATTERY=1.2V)
IOUT=100mA
IOUT=100mA
VBAT(1V/div)
VBAT(1V/div)
VOUT(1V/div)
VOUT(1V/div)
LX(2V/div)
LX(2V/div)
Time(10ms/div)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
Time(10ms/div)
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APW7075
Typical Operating Characteristics (Cont.)
Power Down
Enable
IOUT=100mA
IOUT=100mA
SHDN(1V/div)
VBAT(2V/div)
VOUT(1V/div)
VOUT(1V/div)
LX(2V/div)
LX(2V/div)
Time(5ms/div)
Time(10ms/div)
Shutdown
Heavy Load Operating Waveforms
IOUT=100mA
SHDN(1V/div)
IL(200mA/div)
IOUT=100mA, VOUT=3.3V
VBAT=2.4V, CBAT=10µF
COUT=100µF, L=22µH
VOUT(1V/div)
LX(2V/div)
LX(2V/div)
LOUT(100mV/div)
Time(1ms/div)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
Time(1µs/div)
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APW7075
Typical Operating Characteristics (Cont.)
Output Current vs. Start-up Voltage
Light Load Operating Waveforms
1.4
Start-up Voltage(V)
1.2
IL(200mA/div)
IOUT=30mA, VOUT=3.3V
VBAT=2.4V, CBAT=10µF
COUT=100µF, L=22µH
LX(2V/div)
1
0.8
0.6
0.4
0.2
0
LOUT(100mV/div)
0.1
1
Effciency vs. Output Current
Effciency vs. Output Current
100
100
VIN=2.4V
90
80
80
70
70
VIN=1.2V
Effciency(%)
Effciency(%)
100
Output Current(mA)
Time(5µs/div)
90
10
60
50
40
50
40
30
30
20
VOUT=3.3V, L=22µH
20
10
10
0
0.01
VOUT=2.5V, L=22µH
VIN=1.2V
60
0.1
1
10
100
0
0.01
1000
1
10
100
1000
Output Current(mA)
Output Current(mA)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
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10
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APW7075
Typical Operating Characteristics (Cont.)
Efficiency vs. Output Current
Efficiency vs. Output Current
100
100
VIN=2.4V
90
80
80
70
70
60
Efficiency(%)
Efficiency(%)
90
VIN=1.2V
50
40
30
VOUT=3.3V, L=10µH
20
VOUT=2.5V, L=10µH
VIN=1.2V
60
50
40
30
20
10
10
0
0.01
0.1
1
10
100
0
0.01
1000
0.1
Output Current(mA)
1
10
1000
Output Current(mA)
Maximum Output Current vs.Input Voltage
Operating Curretnt into OUT vs. Output Voltage
0.5
1000
Operating Current into OUT(mA)
L=22µH
Maximum Output Current (mA)
100
VOUT=3.3V VOUT=3.6V
750
VOUT=2.5V
500
250
VOUT=5V
FB=1.4V
0.4
0.3
0.2
0.1
0
0
1
1.5
2
2.5
3
3.5
0
4
Input Voltage(V)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
0.5
1
1.5
2
2.5
3
3.5
4
Output Voltage(V)
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APW7075
Typical Operating Characteristics (Cont.)
Transition from PFM to PWM vs. Input Voltage
Transition from PFM to PWM vs. Input Voltage
500
L=10µH
The transition from PFM to PWM(mA)
The transition from PFM to PWM(mA)
500
VOUT=3.3V
400
VOUT=3.6V
300
VOUT=2.5V
VOUT=5V
200
100
L=22µH
400
300
200
VOUT=3.6V
VOUT=3.3V
VOUT=5V
VOUT=2.5V
100
0
0
1
1.5
2
2.5
3
3.5
1
4
Input Voltage(V)
1.5
2
2.5
3
3.5
4
Input Voltage(V)
Line Transient Response
Input Battery Current vs. Input Battery Voltage
300
VBAT(2V/div)
Input Battery Current(µA)
250
IOUT=100mA, VOUT=3.3V
VBAT=2V~3V
200
VOUT=3.3V
150
VOUT=2.4V
100
VOUT(200mV/div)
50
0
0
0.5
1
1.5
2
2.5
3
Input Battery Voltage(V)
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
Time(2ms/div)
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APW7075
Typical Operating Characteristics (Cont.)
Load Transient Response
PWM to LDO
V IN(2V/div)
VOUT(200mV/div)
IOUT=100mA, VOUT=3.3V
CIN=10µF, VBAT=2.4V
VBAT=2.4V, VOUT=3.3V
L=22µH
VOUT(100mV/div)
IOUT=10~300mA
LX(2V/div)
Time(0.5ms/div)
Time(50µs/div)
LDO to PWM
LDO Power Up
V IN(2V/div)
IOUT=100mA
IOUT=100mA, VOUT=3.3V
CIN=10µF, VBAT=2.4V
V IN(2V/div)
VOUT(100mV/div)
VOUT(2V/div)
LX(2V/div)
IIN(1A/div)
Time(0.2ms/div)
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Time(10ms/div)
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APW7075
Typical Operating Characteristics (Cont.)
LDO Power Down
LDO Load Transient Response
IOUT=100mA
VIN(20V/div)
VOUT(50mV/div)
VIN=5V, VOUT=3.
VOUT(2V/div)
IOUT=10mA~500mA
IN(1A/div)
Time(10ms/div)
Time(5µs/div)
LDO Load Transient Response
LBO Rising Delay Time
VOUT(50mV/div)
VBAT=2.4V, VOUT=3.3V
LBI(0.5V/div)
VIN=5V, VOUT=3.
IOUT=10mA~500mA
LBO(2V/div)
Time(5µs/div)
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Time(5µs/div)
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APW7075
Typical Operating Characteristics (Cont.)
LBO Falling Delay Time
LBO Output Sink Current vs. LBO Low Voltage
30
VOUT=3.3V
25
LBO Sink Current(mA)
LBI(0.5V/div)
VBAT=2.4V, VOUT=3.3V
LBO(2V/div)
20
15
10
5
0
0
0.25
0.5
0.75
1
1.25
1.5
LBO Output Low Voltage(V)
Time(5µs/div)
LDO Current Limit vs. LDO Input Voltage
LDO Quiescent Current vs. LDO Input Voltage
2
1.2
1.8
LDO Quiescent Current (A)
LDO Current Limit(A)
1
0.8
0.6
0.4
0.2
1.6
1.4
IOUT=10mA
1.2
1
0.8
0.6
IOUT=0mA
0.4
0.2
0
0
4
4.5
5
5.5
6
4
LDO Input Voltage(V)
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Rev. A.7 - Oct., 2008
4.5
5
5.5
6
LDO Input Voltage(V)
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APW7075
Typical Operating Characteristics (Cont.)
Dropout Voltage vs. LDO Output Current
Quiescent Current vs. LDO Output Current
700
1.2
VOUT=4.2V
Dropout Voltage (mV)
1
Quiescent Current (mA)
600
V IN=5V
0.8
0.6
0.4
0.2
500
400
300
200
100
0
0
0
100
200
300
400
0
500
100
LDO Output Current(mA)
300
400
500
LDO Output Current(mA)
Output Voltage vs. Temperature
Output Voltage vs. LDO Input Voltage
3.3
3.303
IOUT=0mA
Iout=0mA
3.302
3.295
3.301
3.29
Output Voltage (V)
Output Voltage (V)
200
3.3
3.299
3.285
3.28
3.275
3.298
3.297
4
4.5
5
5.5
3.27
-40
6
0
20
40
60
80
100
120
140
Temperature (oC )
LDO Input Voltage(V)
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APW7075
Function Description
PFM Control Scheme
Soft-Start
The APW7075 features the PFM control scheme to im-
The APW7075 provides the soft-start function to get the
prove the efficiency during light load. In PFM mode, the
inductor stores the energy during internal N-channel
controlled output voltage rise. When the battery voltage
(<1.8V) is supplied to the device and exceeds the start-up
MOSFET turns on, and the energy is transferred to output
capacitors and load during internal P-channel MOSFET
voltage, the internal N-channel and P-channel MOSFETs
start to switch and pump up the output voltage to 1.8V( if
turns on. If the energy which is charged to output capacitors exceeds the requirement of load, the current will re-
the battery voltage is over 1.8V, the output voltage will
equal battery voltage during this time ), which control cir-
verse from output capacitors to inductor and input
capacitors. The PFM comparator compares the source
cuitry can operate normally. The soft-start controls the
rise of internal reference voltage. When the internal refer-
(OUT) and drain (LX) of the internal P-channel MOSFET.
When the current that flows through the internal P-chan-
ence voltage exceeds the feedback voltage which is divided by the resistor from the output voltage, the soft-start
nel MOSFET is backward (from OUT to LX), the internal Pchannel MOSFET will be turned off, and the output capaci-
circuit will control the output voltage until the output voltage is in regulation. The soft-start interval is approximately
tor supplies the load and maintains the output voltage.
During PFM mode, the IC switches only as need to serve
30ms.
LDO
the load, reduce the switching frequency and associate
losses in the internal switches and the external inductor.
The output voltage has two operation modes. When VIN
Some jitter are normal during transition from PFM to PWM
mode; the transition of the PFM to PWM is dependent on
exceeds 3.9V, the output will become the LDO regulator
and the step-up converter will be disabled. The LDO out-
the inductance values, VIN and VOUT. The output ripple is
higher during PFM operation, a larger output capacitor
put is a P-channel low dropout regulator with 1A current
limit. When the VIN is below 3.8V, the output will return to
can be used to minimize the output ripple.
the step-up converter, and the LDO mode will be disabled.
Note that when LDO mode is used, the output voltage
Synchronous Rectification
should be under 3.8V.
The APW7075 has an internal N-channel and a P-channel
Low Battery Detection
MOSFET, it is no need for external components, the internal low RDS(ON) P-channel MOSFET replaces the dis-
The low battery detection is used to monitor the battery
crete Schottky diode, and it reduces cost and board space.
During the cycle off time, the P-channel MOSFET turns
voltage and to generate a signal. This function includes
two pins, LBI is the inverting input of the comparator and
on, and the power dissipation on the P-channel MOSFET
is lower than discrete Schottky diode, thus, the conver-
LBO is an open drain output (See Block Diagram). When
the LBI voltage drops below the threshold voltage 0.6V,
sion efficiency can be improved.
the open drain device will turn on and LBO becomes low.
The Low battery threshold voltage can be programmed
Shutdown
with a resistive divider from battery to LBI pin to the ground.
Since the LBO is an open drain output, it usually requires
The APW7075 has an active high enable function. Force
SHDN high (>1.4V) to enable the step-up converter, SHDN
an external pull-up resistor.
low (<0.3V) to disable the step-up converter and the device enters shutdown mode. In shutdown mode, the converter stops switching and all internal control circuits are
turned off, but the output is still applied by input voltage
through the body diode of P-channel MOSFET, it is about
Vin-0.6V. Note that when the output is applied from the
VIN (LDO mode), the shutdown function is disabled.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
17
www.anpec.com.tw
APW7075
Application Information
Output Voltage Selection
The inductor’s DC resistance affects the efficiency; larger
The output voltage of APW7075 can be adjusted by an
resistance dissipates more power, it should be as small
as possible. It is important to choose the inductor’s satu-
external resistor divider, or connect FB pin to OUT for
3.3V and to the ground for 2.5V (see Application
ration current rating greater than the peak current which
the inductor will flow in the application.
Schematic). The internal reference voltage is 1.2V and
the allowed output voltage is from 2.5V to 5.5V. The fol-
Boost Converter Input Capacitor Selection
lowing equation can be used to calculate the output
voltage:
V OUT
At least a 10µF input capacitor is recommended to stabilize the battery voltage and minimizes the peak current
ripple from the battery.
 R1 
= 1+
 × 1.2V
 R2 
LDO Input Capacitor Selection
Programming Low Battery Threshold Voltage
The LDO input capacitor with larger values and lower
The low battery threshold voltage can be programmed
with a resistive divider from battery to LBI pin to the ground
ESRs provides better PSRR and line transient response.
At least a 10µF capacitor is recommended.
(see Application Schematic). The internal reference voltage is 0.6V, and the low battery threshold voltage must
Output Capacitor Selection
The output capacitor is used for supplying the output dur-
be below the battery voltage. The following equation can
be used to calculate the low battery threshold voltage:
ing internal N-channel MOSFET turns on time. Larger capacitance and lower ESR reduce the output voltage ripple.
The output voltage supplies the power to the IC and so
 R3 
VBAT - TH =  1 +
 × 0.6V
 R4 
the output voltage ripple must be as small as possible to
provide better PSRR. In general, a 100µF to 220µF low
Inductor Selection
ESR Tantalum capacitor is recommended, a 1µF ceramic
capacitor in parallel for bypassing the noise is also
recommended. The following equation calculates the
The APW7075 works well with a 22µH inductor in most
applications. The inductance values determine the inductor ripple current and affect the output current. Higher in-
output ripple.
ductance values reduce ripple and improve efficiency.
Lower inductance values have fast response but increase
Voripple= IOUT× (
the ripple and reduce the efficiency. The maximum allowed LX current is 1A (the maximun output current shows
Layout Consideration
in Typical Characteristics), therefore, the peak inductor
current cannot exceed it. The following equations calcu-
The correct PCB layout is important for all switching
converters. If the layout is not carefully done, the regulator
could show stability problems as well as EMI problems.
late the inductor current, and output current.
Figure 5 illustrates the layout guidelines, the bold lines
indicate the high current paths; these traces must be short
IOUT = IL x (1-D)
∆IL = (VOUT− VIN) ×
Where:
D=
VOUT− VBAT
+ ESR)
COUT×FSW × VOUT
(1− D)
and wide. The input capacitors, output capacitors, and the
inductor should be as close to the IC as possible. Use a
L× f
common ground plane for power ground and a different
one for control ground to minimize the effects of the ground
VOUT −VIN
VOUT
noise. Connect these ground planes at a node close to
the GND pin of IC. The feedback and LBI resistor dividers
should be placed as close to the IC as possible.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
18
www.anpec.com.tw
APW7075
Application Information (Cont.)
Layout Consideration (Cont.)
USB 5V
1
2
3
4
C2
100uF
C4
1uF
C3
10uF
VIN
FB
SHDN
LBI
OUT
LX
GND
LBO
8
7
6
VOUT
C1
10uF
22UH
5
VBAT
APW7075
Figure 5. Recommended Layout Diagram
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
19
www.anpec.com.tw
APW7075
Package Information
SOP-8P
D
SEE VIEW
A
E
E2
THERMAL
PAD
E1
D1
h X 45
°
c
A
0.25
b
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e
VIEW A
S
Y
M
B
O
L
SOP-8P
MILLIMETERS
MIN.
MAX.
MAX.
MIN.
0.063
1.60
A
A1
INCHES
0.006
0.000
0.15
0.00
0.049
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
D1
2.25
3.50
0.098
0.138
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
E2
2.00
3.00
0.079
0.118
e
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
0o
8o
0o
8o
Note : 1. Follow JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
20
www.anpec.com.tw
APW7075
Package Information
TSSOP-8
D
E
E1
SEE VIEW A
C
A
0.25
b
A2
e
GAUGE PLANE
A1
SEATING PLANE
S
Y
M
B
O
L
VIEW A
L
TSSOP-8
INCHES
MILLIMETERS
MIN.
MIN.
MAX.
A
MAX.
0.047
1.20
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.031
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.008
D
2.90
3.10
0.114
0.122
E
6.20
6.60
0.244
0.260
E1
4.30
4.50
0.169
0.177
0.65 BSC
e
L
0.45
0
0
°
0.026 BSC
0.75
8°
0.018
0.030
0°
8°
Note : 1. Follow JEDEC MO-153 AA
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
21
www.anpec.com.tw
APW7075
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
330.0±2.00 50 MIN.
P0
P1
P2
4.0±0.10
8.0±0.10
2.0±0.05
A
H
SOP-8P
Application
330.0±2.00 50 MIN.
TSSOP-8
T1
C
d
D
W
E1
12.4+2.00 13.0+0.50
-0.00
-0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10
P0
P1
D0
1.5+0.10
-0.00
D1
1.5 MIN.
D0
1.5+0.10
4.00±0.10 8.00±0.10 2.00±0.05
-0.00
D1
1.5 MIN.
5.5±0.05
T
A0
B0
K0
0.6+0.00 6.40±0.20 5.20±0.20 2.10±0.20
-0.40
T1
C
d
D
W
E1
12.4+2.00 13.0+0.50
-0.00
-0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10
P2
F
F
5.5±0.10
T
A0
B0
K0
0.6+0.00
-0.40 6.90±0.20 3.40±0.20 1.60±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP-8P
Tape & Reel
2500
TSSOP-8
Tape & Reel
2500
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
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www.anpec.com.tw
APW7075
Taping Direction Information
SOP-8P
t
USER DIRECTION OF FEED
TSSOP-8
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
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APW7075
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Time 25°C to Peak Temperature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
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APW7075
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
3
3
Package Thickness
Volume mm
<350
Volume mm
≥350
<2.5 mm
≥2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
Package Thickness
3
Volume mm
<350
Volume mm
350-2000
3
Volume mm
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.7 - Oct., 2008
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