AS5SP128K32

SSRAM
81
84
82
83
85
87
86
89
88
91
90
92
93
95
96
94
97
100
1
80
DQc
DQc
VDDQ
VSSQ
2
79
3
78
4
77
5
76
DQc
DQc
6
75
7
74
DQc
DQc
8
73
9
72
VSSQ
VDDQ
10
71
11
70
DQc
12
69
DQc
NC
13
68
VDD
15
NC
VSS
DQd
16
65
17
64
18
63
DQd
19
62
VDDQ
VSSQ
20
61
21
60
VSSQ
DQd
22
59
DQd
DQd
23
58
24
57
DQa
DQa
DQa
DQd
VSSQ
VDDQ
25
56
DQa
26
55
27
54
DQd
DQd
NC
28
53
29
52
VSSQ
VDDQ
DQa
DQa
30
51
NC
14
67
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
50
49
48
47
46
45
44
43
42
41
66
NC
DQb
DQb
VDD
NC*
NC*
A
A
A
A
A
A
A
40
39
38
37
36
35
34
MODE
A
A
A
A
A1
A0
NC*
NC*
VSS
33
SSRAM [SPB]
31
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
• RoHs compliant options available
NC
32
Pipeline Burst, Single Cycle Deselect
FEATURES
98
Plastic Encapsulated Microcircuit
4.0Mb, 128K x 32, Synchronous SRAM
99
A
A
CE1\
CE2
BWd\
BWc\
BWb\
BWa\
CE3\
VDD
VSS
CLK
GW\
BWE\
OE\
ADSC\
ADSP\
ADV\
A
A
AS5SP128K32
FAST ACCESS TIMES
Parameter
CycleTime
ClockAccessTime
OutputEnableAccessTime
Symbol 200Mhz 166Mhz 133Mhz 100Mhz Units
tCYC
5.0
6.0
7.5
10.0
ns
tCD
3.0
3.5
4.0
5.0
ns
tOE
3.0
3.5
4.0
5.0
ns
The AS5SP128K32 is a 4.0Mb High Performance Synchronous
Pipeline Burst SRAM, available in multiple temperature
screening levels, fabricated using High Performance CMOS
technology and is organized as a 128K x 32. It integrates
address and control registers, a two (2) bit burst address counter
supporting four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
I/O Gating and Control
CE3\
BWE\
BWx\
CONTROL
BLOCK
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
AS5SP128K32
Rev. 1.5 10/13
BURST CNTL.
Address
Registers
Row
Decode
GENERAL DESCRIPTION
Memory Array
x36
SBP
T Synchronous Pipeline
Burst
N Two (2) cycle load
N One (1) cycle
de-select
N One (1) cycle latency
on Mode change
Output
Register
Input
Register
Output
Driver
The AS5SP128K32 includes advanced control options including
Global Write, Byte Write as well as an Asynchronous Output
enable. Burst Cycle controls are handled by three (3) input pins,
ADV, ADSP\ and ADSC\. Burst operation can be initiated with
either the Address Status Processor (ADSP\) or Address Status
Cache controller (ADSC\) inputs. Subsequent
DQx, DQPxburst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
Column
Decode
Micross Components reserves the right to change products or specifications without notice.
1
SSRAM
AS5SP128K32
PIN DESCRIPTION / ASSIGNMENT TABLE
Signal Name
Clock
Symbol
CLK
Type
Input
Pin
Address
A0, A1
Input
Address
A
Input(s)
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Input
Input
Input
Input
Byte Write Enable
Output Enable
Address Strobe Controller
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
35, 34, 33, 32, 100,
99, 82, 81, 44, 45, 46,
47, 48, 49, 50
98, 92
97
88
93, 94, 95, 96
Input
Input
Input
87
86
85
Address Strobe from Processor
ADSP\
Input
84
Address Advance
ADV\
Input
83
Power-Down
ZZ
Input
64
Data Input/Outputs
DQa, DQb, DQc
DQd
Input/
Output
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
MODE
VDD
VSS
VDDQ
Input
Supply
Supply
Supply
I/O Ground
VSSQ
Supply
No Connection(s)
NC
NA
89
37, 36
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
31
91, 15, 41, 65
90, 17, 40, 67
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
1, 14, 16, 30, 38, 39,
51, 42,43, 66, 80
Description
This input registers the address, data, enables, Global and Byte
writes as well as the burst control functions
Low order, Synchronous Address Inputs and Burst counter
address inputs
Synchronous Address Inputs
Active Low True Chip Enables
Active High True Chip Enable
Active Low True Global Write enable. Write to all bits
Active Low True Byte Write enables. Write to byte segments
Active Low True Byte Write Function enable
Active Low True Asynchronous Output enable
Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Burst
When ADSP\ and ADSC are both asserted, only ADSP is recognized
Synchronous Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
Advance input Address. When asserted HIGH, address in burst
counter is incremented.
Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Data lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
Isolated Input/Output Buffer Supply
Isolated Input/Output Buffer Ground
No connections to internal silicon
LOGIC BLOCK DIAGRAM
A 0, A 1, A
A DDRESS
REGISTER
2
A [1:0]
M ODE
A DV
CLK
Q1
BURST
COUNTER
A ND Q0
LOGIC
CLR
A DSC
A DSP
BW D
DQ D
BYTE
W RITE REGISTER
DQ D
BYTE
W RITE DRIVER
BW C
DQ C
BYTE
W RITE REGISTER
DQ C
BYTE
W RITE DRIVER
DQ B
BYTE
W RITE REGISTER
DQ B
BYTE
W RITE DRIVER
BW B
BW A
BW E
GW
CE 1
CE 2
CE 3
OE
ZZ
AS5SP128K32
Rev. 1.5 10/13
SENSE
A M PS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQ A
BYTE
W RITE DRIVER
DQ A
BYTE
W RITE REGISTER
ENA BLE
REGISTER
M EM ORY
A RRA Y
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Micross Components reserves the right to change products or specifications without notice.
2
SSRAM
AS5SP128K32
Functional Description
Micross Components AS5SP128K32 Synchronous SRAM is
manufactured to support today’s High Performance platforms
utilizing the Industries leading Processor elements including
those of Intel and Motorola. The AS5SP128K32 supports Synchronous SRAM READ and WRITE operations as well as Synchronous Burst READ/WRITE operations. All inputs with the
exception of OE\, MODE and ZZ are synchronous in nature
and sampled and registered on the rising edge of the devices
input clock (CLK). The type, start and the duration of Burst
Mode operations is controlled by MODE, ADSC\, ADSP\ and
ADV as well as the Chip Enable pins CE1\, CE2, and CE3\.
All synchronous accesses including the Burst accesses are
enabled via the use of the multiple enable pins and wait state
insertion is supported and controlled via the use of the Advance control (ADV).
The AS5SP128K32 supports both Interleaved as well as Linear Burst modes therefore making it an architectural fit for either the Intel or Motorola CISC processor elements available
on the Market today.
The AS5SP128K32 supports Byte WRITE operations and enters this functional mode with the Byte Write Enable (BWE\)
and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\).
Global Writes are supported via the Global Write Enable (GW\)
and Global Write Enable will override the Byte Write inputs and
will perform a Write to all Data I/Os.
The AS5SP128K32 provides ease of producing very densearrays via the multiple Chip Enable input pins and Tri-state
outputs.
Single Cycle Access Operations
A Single READ operation is initiated when all of the following
conditions are satisfied at the time of Clock (CLK) HIGH: [1]
ADSP\ or ADSC\ is asserted LOW, [2] Chip Enables are all
asserted active, and [3] the WRITE signals (GW\, BWE\) are in
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH.
The address presented to the Address inputs is stored within
the Address Registers and Address Counter/Advancement
Logic and then passed or presented to the array core. The
corresponding data of the addressed location is propagated to
the Output Registers and passed to the data bus on the next
rising clock via the Output Buffers. The time at which the data
is presented to the Data bus is as specified by either the Clock
to Data valid specification or the Output Enable to Data Valid
spec for the device speed grade chosen. The only exception
occurs when the device is recovering from a deselected to select state where its outputs are tristated in the first machine
cycle and controlled by its Output Enable (OE\) on following
cycle. Consecutive single cycle READS are supported. Once
the READ operation has been completed and deselected by
use of the Chip Enable(s) and either ADSP\ or ADSC\, its outputs will tri-state immediately.
AS5SP128K32
Rev. 1.5 10/13
A Single ADSP\ controlled WRITE operation is initiated when
both of the following conditions are satisfied at the time of
Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip
Enable(s) are asserted ACTIVE. The address presented to the
address bus is registered and loaded on CLK HIGH, then presented to the core array. The WRITE controls Global Write,
and Byte Write Enable (GW\, BWE\) as well as the individual
Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are ignored on the first machine cycle. ADSP\ triggered WRITE accesses require two (2) machine cycles to complete. If Global
Write is asserted LOW on the second Clock (CLK) rise, the
data presented to the array via the Data bus will be written
into the array at the corresponding address location specified
by the Address bus. If GW\ is HIGH (inactive) then BWE\ and
one or more of the Byte Write controls (BWa\, BWb\, BWc\ and
BWd\) controls the write operation. All WRITES that are initiated in this device are internally self timed.
A Single ADSC\ controlled WRITE operation is initiated when
the following conditions are satisfied: [1] ADSC\ is asserted
LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are
asserted (TRUE or Active), and [4] the appropriate combination of the WRITE inputs (GW\, BWE\, BWx\) are asserted
(ACTIVE). Thus completing the WRITE to the desired Byte(s)
or the complete data-path. ADSC\ triggered WRITE accesses
require a single clock (CLK) machine cycle to complete. The
address presented to the input Address bus pins at time of
clock HIGH will be the location that the WRITE occurs. The
ADV pin is ignored during this cycle, and the data WRITTEN to
the array will either be a BYTE WRITE or a GLOBAL WRITE
depending on the use of the WRITE control functions GW\ and
BWE\ as well as the individual BYTE CONTOLS (BWx\).
Deep Power-Down Mode (SLEEP)
The AS5SP128K32 has a Deep Power-Down mode and is
controlled by the ZZ pin. The ZZ pin is an Asynchronous input
and asserting this pin places the SSRAM in a deep powerdown mode (SLEEP). While in this mode, Data integrity is
guaranteed. For the device to be placed successfully into this
operational mode the device must be deselected and the Chip
Enables, ADSP\ and ADSC\ remain inactive for the duration
of tZZREC after the ZZ input returns LOW. Use of this deep
power-down mode conserves power and is very useful in multiple memory page designs where the mode recovery time can
be hidden.
Micross Components reserves the right to change products or specifications without notice.
3
SSRAM
AS5SP128K32
SYNCHRONOUS TRUTH TABLES
CE1\
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
CE2
X
L
X
L
X
H
H
H
X
X
X
X
X
X
X
X
CE3\
X
X
H
X
H
L
L
L
X
X
X
X
X
X
X
X
ADSP\
X
L
L
X
X
L
H
H
H
X
H
X
H
X
H
X
ADSC\
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
WT / RD
X
X
X
X
X
X
WT
RD
RD
RD
WT
WT
RD
RD
WT
WT
CLK
Address Accessed
NA
NA
NA
NA
NA
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Operation
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst, READ
Begin Burst, WRITE
Begin Burst, READ
Continue Burst, READ
Continue Burst, READ
Continue Burst, WRITE
Continue Burst, WRITE
Suspend Burst, READ
Suspend Burst, READ
Suspend Burst, WRITE
Suspend Burst, WRITE
Notes:
1. X = Don’t Care
2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE
BURST SEQUENCE TABLES
Burst Control
Pin [MODE]
First Address
State
HIGH
Case 1
A1
A0
0
0
1
1
Fourth Address
Burst Control
Pin [MODE]
First Address
State
LOW
Interleaved Burst
Case 2
A1
A0
0
0
1
0
0
1
1
1
Case 1
A1
A0
0
0
1
1
Fourth Address
0
1
0
1
Linear Burst
Case 2
A1
A0
0
1
1
0
CAPACITANCE
Case 3
A1
1
0
1
0
Case 4
A0
1
1
0
0
A1
0
1
0
1
1
1
0
0
Case 3
A1
1
0
1
0
1
0
1
0
Case 4
A0
1
1
0
0
A0
A1
0
1
0
1
1
0
1
0
WRITE TABLE
GW\
H
H
H
H
H
H
L
BW\
H
L
L
L
L
L
X
BWa\
X
H
L
H
H
L
X
BWb\
X
H
H
L
H
L
X
BWc\
X
H
H
H
L
L
X
BWd\
X
H
H
H
L
L
X
Symbol
VDD
VDDQ
VIN
VIO
PD
tSTG
/IT
/ET
/XT
ZZ
H
L
L
L
L
Max.
Units
-0.3
4.6
V
-0.3
VDD+0.3
V
-0.3
VDDQ+0.3
V
-65
150
VDD
Max.
6
8
6
Units
pF
pF
pF
OE\
X
L
H
X
X
I/O Status
High-Z
DQ
High-Z
Din, High-Z
High-Z
AC TEST LOADS
Output
Rt = 50 ohm
Zo=50 ohm
Diagram [A]
Min.
Vt= Termination Voltage
Rt= Termination Resistor
30 pF
Vt= 1.50v for 3.3v VDDQ
Vt= 1.25v for 2.5v VDDQ
V
1.6
-40
85
-40
105
-55
Operation
Power-Down (SLEEP)
READ
WRITE
De-Selected
Operation
READ
READ
WRITE Byte [A]
WRITE Byte [B]
WRITE Byte [C], [D]
WRITE ALL Bytes
WRITE ALL Bytes
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on VDD Pin
Voltage on VDDQ Pins
Voltage on Input Pins
Voltage on I/O Pins
Power Dissipation
Storage Temperature
Operating Temperatures
[Screening Levels]
Symbol
CI
CIO
CCLK
ASYNCHRONOUS TRUTH TABLE
A0
1
0
0
1
Parameter
Input Capacitance
Input/Output Capacitance
Clock Input Capacitance
R= 317 ohm@3.3v
R= 1667 ohm@2.5v
Output
3.3/2.5v
W
C
R
5 pF
R
C
R= 351 ohm@3.3v
R= 1538 ohm@2.5v
R
C
R
Diagram [B]
C
125
*Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for any
duration or segment of time may affect device reliability.
AS5SP128K32
Rev. 1.5 10/13
Micross Components reserves the right to change products or specifications without notice.
4
SSRAM
AS5SP128K32
DC ELECTRICAL CHARACTERISTICS (VDD=3.3v -5%/+10%,
TA= Min. and Max temperatures of Screening level chosen)
Symbol
VDD
VDDQ
VoH
Parameter
Power Supply Voltage
I/O Supply Voltage
Output High Voltage
Test Conditions
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
VDD=Min., IOH=-4mA
VDD=Min., IOH=-1mA
VoL
Output Low Voltage
VDD=Min., IOL=8mA
VDD=Min., IOL=1mA
VIH
Input High Voltage
VIL
Input Low Voltage
IIL
IZZL
IOL
IDD
Input Leakage (except ZZ)
Input Leakage, ZZ pin
Output Leakage
Operating Current
Automatic CE. Power-down
Current -TTL inputs
Output Disabled, VOUT=VSSQ to VDDQ
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
10 ns Cycle, 100 Mhz
VDD=Max., f=Max.,
ISB4
ISB3
Automatic CE. Power-down
Current - CMOS Inputs
Automatic CE. Power-down
Current -TTL inputs
Automatic CE. Power-down
Current - CMOS Inputs
Max
3.630
VDD
0.4
0.4
VDD+0.3
VDD+0.3
0.8
0.7
5
30
5
265
240
225
205
Units
V
V
V
V
V
V
V
V
V
V
uA
uA
uA
mA
mA
mA
mA
110
100
90
80
65
mA
mA
mA
mA
mA
70
mA
95
85
75
65
mA
mA
mA
mA
Notes
1
1,5
1,4
1,4
1,4
1,4
1,2
1,2
1,2
1,2
3
3
Max. VDD, Device De-Selected,
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
10 ns Cycle, 100 Mhz
VIN>/=VIH or VIN</=VIL
f=fMAX=1/tCYC
ISB2
2
1.7
-0.3
-0.3
-5
-30
-5
VDD=Max., VIN=VSS to VDD
IOH=0mA
ISB1
Min
3.135
2.375
2.4
2
Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v
f=fMAX=1/tCYC
Max. VDD, Device De-Selected, VIN>/=VIH or VIN </= VIL, f=0
Max. VDD, Device De-Selected, or
VIN</=0.3v or VIN >/=VDDQ-0.3v,
f-Max=1/tCYC
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
10 ns Cycle, 100 Mhz
THERMAL RESISTANCE
Parameter
ȺJA
ȺJC
Description
ThermalResistance
(JunctiontoAmbient)
ThermalResistance
(JunctiontoCase)
TestConditions
Testconditionsfollowstandardtest
methodsandproceduresfor
measuringthermalimpedance,per
EIA/JESD51
DQ
DQC
Package Package Unit
42
35.25
o
9
7.96
o
C/W
C/W
Notes:
[1] All Voltages referenced to VSS (Logic Ground)
[2] Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA
Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA
Power-up: VIH <+3.6V and VDD<3.135V for t<200ms
[3] MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA
[4] The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies.
AC load current is higher than stated values, AC I/O curves can be made available upon request
[5] VDDQ should never exceed VDD, VDD and VDDQ can be connected together
[6] This parameter is sampled
AS5SP128K32
Rev. 1.5 10/13
Micross Components reserves the right to change products or specifications without notice.
5
SSRAM
AS5SP128K32
AC SWITCHING CHARACTERISTICS (VDD=3.3V -5%/+10%,
TA= MIN. AND MAX TEMPERATURES OF SCREENING LEVEL CHOSEN)
Parameter
Clock (CLK) Cycle Time
Clock (CLK) High Time
Clock (CLK) Low Time
Clock Access Time
Clock (CLK) High to Output Low-Z
Clock High to Output High-Z
Output Enable to Data Valid
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Address Set-up to CLK High
Address Hold from CLK High
Address Status Set-up to CLK High
Address Status Hold from CLK High
Address Advance Set-up to CLK High
Address Advance Hold from CLK High
Chip Enable Set-up to CLK High (CEx\, CE2)
Chip Enable Hold from CLK High (CEx\, CE2)
Data Set-up to CLK High
Data Hold from CLK High
Write Set-up to CLK High (GW\, BWE\, BWx\)
Write Hold from CLK High (GW\, BWE\, BWX\)
ZZ High to Power Down
ZZ Low to Power Up
Symbol
tCYC
tCH
tCL
tCD
tCLZ
tCHZ
tOE
tOH
tOELZ
tOEHZ
tAS
tAH
tASS
tASH
tADVS
tADVH
tCES
tCEH
tDS
tDH
tWES
tWEH
tPD
tPU
-5 [200Mhz]
Min.
Max.
5.00
2.00
2.00
3.00
1.25
1.25
3.00
3.00
1.25
0.00
3.00
1.30
0.50
1.30
0.50
1.30
0.50
1.30
0.50
1.30
0.50
1.30
0.50
2
2
-6 [166Mhz]
Min.
Max.
6.00
2.50
2.50
3.50
1.25
1.25
3.50
3.50
1.25
0.00
3.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
2
2
-7.5 [133Mhz]
Min.
Max.
7.50
3.00
3.00
4.00
1.25
1.25
3.50
4.00
1.25
0.00
3.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
1.50
0.50
2
2
-10 [100Mhz]
Min.
Max.
10.00
3.50
3.50
5.00
1.50
1.50
3.50
4.00
1.50
0.00
3.50
2.00
0.50
2.00
0.50
2.00
0.50
2.00
0.50
2.00
0.50
2.00
0.50
2
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
cycles
Notes
1
1
2
2,3,4,5
2,3,4,5
6
2,3,4,5
2,3,4,5
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
Notes to Switching Specifications:
1. Measured as HIGH when above VIH and Low when below VIL
2. This parameter is measured with the output loading shown in AC Test Loads
3. This parameter is sampled
4. Transition is measured +500mV from steady state voltage
5. Critical specification(s) when Design Considerations are being reviewed/analyized for Bus Contentention
6. OE\ is a Don't Care when a Byte or Global Write is sampled LOW
7. A READ cycle is defined by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required
SET-UP and HOLD times
8. This is a Synchronous device. All addresses must meet the specified SET-UP and HOLD times for all rising
edges of CLK when either ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous
inputs must meet the SET-UP and HOLD times with stable logic levels for all rising edges of clock (CLK) during
device operation (enabled). Chip Enable (Cex\, CE2) must be valid at each rising edge of clock (CLK) when
either ADSP\ or ADSC\ is LOW to remain enabled.
AS5SP128K32
Rev. 1.5 10/13
Micross Components reserves the right to change products or specifications without notice.
6
SSRAM
AS5SP128K32
AC SWITCHING WAVEFORMS
WRITE CYCLE TIMING
Single Write
Burst Write
tCYC
Pipelined Write
tCH
CLK
tASS
tASH
tCL
ADSP\
ADSP\ Ignored with CE1\ inactive
ADSC\
tASS
tASH
ADV\
tADVS
Ax
tADVH
A1
ADV\ Must be Inactive for ADSP\ Write
A3
A2
tAS
tAH
GW\
tWES
tWEH
tWEH
tWES
BWE\, BWx\
tCES
tCEH
CE1\ Masks ADSP\
CE1\
CE2
CE3\
OE\
tDS
tDH
DQx,DQPx
W1
W2a
W2b
W2c
W2d
W3
DON'T CARE
UNDEFINED
AS5SP128K32
Rev. 1.5 10/13
Micross Components reserves the right to change products or specifications without notice.
7
SSRAM
AS5SP128K32
AC SWITCHING WAVEFORMS
READ CYCLE TIMING
Single Read
Burst Read
tCYC
tCH
Pipelined Read
tCL
CLK
tASS
tASH
ADSP\ Ignored with CE1\ Inactive
ADSP\
ADSC\ Initiated Read
ADSC\
Suspend Burst
ADV\
tADVS
tADVH
Ax
A2
A1
tAS
A3
tAH
GW\
tWES
tWEH
BWE\, BWx\
tCES
CE1\ Masks ADSP\
tCEH
CE1\
Unselected with CE2
CE2
CE3\
OE\
tOEHZ
tOE
tCD
DQx,DQPx
R1
tOH
R2a
R2b
R2c
R2d
R3a
DON'T CARE
UNDEFINED
AS5SP128K32
Rev. 1.5 10/13
Micross Components reserves the right to change products or specifications without notice.
8
SSRAM
AS5SP128K32
AC SWITCHING WAVEFORMS
READ / WRITE CYCLE TIMING
Pipelined Read
Burst Read
tCYC
tCH
tCL
CLK
tASS
tASH
ADSP\
ADSC\
ADV\
tADVS
tADVH
tAS
Ax
A1R
A2W
A3W
A4R
A5R
tAH
GW\
tWES
tWEH
BWE\, BWx\
tCES
tCEH
tCES
tCEH
CE1\
CE2
CE3\
OE\
tOEHZ
tOE
DQx,DQPx
DON'T CARE
A1O
tOH
A2I
A4O
[a]
A3I
A4O
[b]
A4O
[c]
A4O
[d]
tOELZ
tCD
UNDEFINED
AS5SP128K32
Rev. 1.5 10/13
Micross Components reserves the right to change products or specifications without notice.
9
SSRAM
AS5SP128K32
POWER DOWN (SNOOZE MODE)
Power Down or Snooze is a Power conservation mode which when building large/very dense arrays, using multiple devices in a multi-banked or paged array, can greatly reduce the Operating current requirements of your total
memory array solution.
The device is placed in this mode via the use of the ZZ pin, an asynchronous control pin which when asserted, places the array into the lower power or Power Down mode. Awakening the array or leaving the Power Down (SNOOZE)
mode is done so by deasserting the ZZ pin .
While in the Power Down or Snooze mode, Data integrity is guaranteed. Accesses pending when the device entered the mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the Power Down mode, all Chip Enables, ADSP\ and ADSC\ must remain inactive for the
duration of ZZ recovery time (tZZREC).
ZZ MODE TIMING DIAGRAM
CLK
ADSP\
ADSC\
CEx\
CE2
ZZ
tZZS
IDD
tZZREC
IDDzz
ZZ MODE ELECTRICAL CHARACTERISTICS
Parameter
Power Down (SNOOZE) Mode
ZZ Active (Signal HIGH) to Power Down
ZZ Inactive (Signal Low) to Power Up
AS5SP128K32
Rev. 1.5 10/13
Symbol
Test Conditon
IDDzz
ZZ >/- VDD - 0.2V
tZZS
ZZ >/- VDD - 0.2V
tZZR
ZZ </- 0.2V
Min.
2 tCYC
Max.
60
2 tCYC
Units
mA
ns
ns
Micross Components reserves the right to change products or specifications without notice.
10
SSRAM
AS5SP128K32
MECHANICAL DEFINITION
100-Pin TQFP (Package Designator DQ)
51-85050-*C
AS5SP128K32
Rev. 1.5 10/13
Micross Components reserves the right to change products or specifications without notice.
11
SSRAM
AS5SP128K32
ORDERING INFORMATION
TQFP
Part Number
AS5SP128K32DQ-7.5/IT
AS5SP128K32DQ-10/IT
AS5SP128K32DQ-7.5/ET
AS5SP128K32DQ-10/ET
AS5SP128K32DQ-7.5/XT
AS5SP128K32DQ-10/XT
Configuration
128Kx32, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
128Kx32, 3.3vCore/3.3,2.5vIO
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
ET = Enhanced Temperature Range
XT = Military Temperature Range
AS5SP128K32
Rev. 1.5 10/13
tCD
(ns)
4.0
5.0
4.0
5.0
4.0
5.0
Clock
(Mhz)
133
100
133
100
133
100
-40oC to +85oC
-40oC to +105oC
-55oC to +125oC
Micross Components reserves the right to change products or specifications without notice.
12
SSRAM
AS5SP128K32
DOCUMENT TITLE
4.0Mb, 128K x 32, Synchronous SRAM Pipeline Burst, Single Cycle Deselect
REVISION HISTORY
Rev #
1.2
History
Updated Micross information
Release Date
October 2010
Status
Release
1.3
Added copper lead frame and RoHS
compliant options, changed IDDzz
from 10mA to 60mA max.
May 2011
Release
1.4
Added Thermal Resistance for DQC
package, page 5. Updated DC
electrical characteristics, page 5:
From
To
ISB2
40
65
ISB4
45
70
September 2011
Release
1.5
Removed Cu-lead frame option
October 2013
Release
AS5SP128K32
Rev. 1.5 10/13
Micross Components reserves the right to change products or specifications without notice.
13