90847

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R031-93.
92-11-24
M.A. Frye
B
Changes in accordance with NOR 5962-R205-95.
95-12-15
M.A. Frye
C
Update and make changes to case outline N. Update boilerplate.
Editorial changes throughout.
96-06-06
M.A. Frye
D
Changes in accordance with NOR 5962-R050-98.
98-03-06
Raymond Monnin
E
Changes in accordance with NOR 5962-R138-98.
98-07-20
Raymond Monnin
F
Update figure 1 for case Z to indicate pin 1. Update boilerplate
paragraphs. ksr
04-12-17
Raymond Monnin
G
Update boilerplate paragraphs. glg
10-02-26
Charles Saffle
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REV STATUS
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OF SHEETS
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PMIC N/A
PREPARED BY
Rajesh Pithadia
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
STANDARD
MICROCIRCUIT
DRAWING
http://www.dscc.dla.mil
CHECKED BY
Kenneth Rice
APPROVED BY
Michael A. Frye
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF
THE
DRAWING APPROVAL DATE
MICROCIRCUIT, MEMORY,
DIGITAL, CMOS 1MEG X 4 DRAM,
MONOLITHIC SILICON
92-03-04
DEPARTMENT OF
DEFENSE
AMSC N/A
REVISION LEVEL
G
SIZE
CAGE CODE
A
67268
5962-90847
SHEET
1 OF
DSCC FORM 2233
APR 97
41
5962-E206-10
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
90847
01
M
R
X
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number 1/
01
02
03
Circuit function
Access time
1 M x 4, DYNAMIC RAM
1 M x 4, DYNAMIC RAM
1 M x 4, DYNAMIC RAM
120 ns
100 ns
80 ns
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
M
Q or V
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN
class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
R
X
Y
Z
U
T
M
N
Descriptive designator
Terminals
GDIP1-T20 or CDIP2-T20
See figure 1
See figure 1
See figure 1
See figure 1
See figure 1
See figure 1
See figure 1
20
20
26/20
26/20
20
26/20
20
20
Package style
dual-in-line
flat pack
leadless ceramic chip carrier
J-leaded chip carrier
dual-in-line
leadless ceramic chip carrier
flat pack
zig-zag in-line
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1/
Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and
will also be listed in MIL-HDBK-103.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
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REVISION LEVEL
G
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2
1.3 Absolute maximum ratings. 2/
Voltage range on any pin-----------------------------------Voltage range on VCC----------------------------------------Short circuit output current ---------------------------------Maximum power dissipation (PD) ------------------------Storage temperature range --------------------------------Lead temperature (soldering, 10 seconds) -----------Thermal resistance, junction-to-case (θJC)
Case outline R -----------------------------------------------Case outlines X, Y, Z, U, T, M, and N ----------------Junction temperature (TJ) 4/ -------------------------------
-1 V dc to 7 V dc
-1 V dc to 7 V dc
50 mA
1W
-65°C to +150°C
+300°C
See MIL-STD-1835
20°C/W 3/
+175°C
1.4 Recommended operating conditions.
Supply voltage range (VCC) 5/ ----------------------------High-level input voltage (VIH) ------------------------------Low-level input voltage (VIL) 6/ --------------------------Case operating temperature range (TC) ----------------
+4.5 V dc to +5.5 V dc
2.4 V dc minimum to 6.5 V dc maximum
-1.0 V dc minimum to 0.8 V dc maximum
-55°C to +125°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
2/
3/
4/
5/
6/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated
herein.
Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
All voltage values in this drawing are with respect to VSS.
The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used in this drawing
for logic voltage levels only.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
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SHEET
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ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD78
-
IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201; http://www.jedec.org.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1 .
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2 .
3.2.3 Truth tables. The truth table shall be as specified on figure 3 .
3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix A. If the test patterns
cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be
allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the
manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V,
alternate test patterns shall be under the control of the device manufacturer's Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request.
3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only.
Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the
internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor
testing may not be decreased unless approved by the preparing activity. Samples may be pulled any time after seal.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
4
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 41 (see MIL-PRF-38535, appendix A).
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical
parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b.
The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).
c.
Interim and final electrical parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MILPRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
5
TABLE I. Electrical performance characteristics.
Test
High-level output
voltage
Low-level output
voltage
Input leakage
current
Output leakage
current
Average operating power
supply current (random
read or write cycle) 3/
Standby power supply
current (TTL)
Average operating power
supply current ( RAS -only
refresh, or CBR refresh)
4/
Average operating power
supply current (Page mode)
3/
Input capacitance,
address inputs
Input capacitance,
RAS, , W, OE
I/O capacitance, DQ's
│
│Symbol
│
│
│
│
│
│ VOH
│
│
│
│ VOL
│
│
│
│ II
│
│
│
│
│
Conditions 1/ 2/
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│
│ IOH = -5 mA, VIL = 0.8 V
│ VIH = 2.4 V
│
│
│ IOL = 4.2 mA, VIL = 0.8 V
│ VIH = 2.4 V
│
│
│ VI = 0 V to 6.5 V,
│ VCC = 5.5 V,
│ All other pins = 0 V to VCC
│
│
│
│
│
│ ICC2
│ Addresses, RAS , CAS cycling │
│
│
│
│
│
│
│ VCC = 5.5 V, VIH = 2.4 V
│ 1,2,3
│ IO
│
│
│
│ ICC1
│
│
│
│Group A │Device
│subgroups │ type
│
│
│
│
│
│
│
│
│ 1,2,3
│ All
│
│
│
│
│
│
│ 1,2,3
│ All
│
│
│
│
│
│
│ 1,2,3
│ All
│
│
│
│
│
│
│ VCC = 5.5 V, CAS high
│ VO = VCC to 0 V,
│
│
│ Minimum cycle time,
│ VCC = 5.5 V
│ 1,2,3
│
│
│
│ 1,2,3
│
│ All
│
│
│
│ 01
│
│ 02
│
│ 03
│
│ All
│
│
│ Limits
│ Unit
│
│
│
│
│
│
│
│
│
│ Min │ Max │
│
│
│
│ 2.4 │
│V
│
│
│
│
│
│
│
│
│
│
│ 0.4 │ V
│
│
│
│
│
│
│
│
│
│
│ ±10 │ μA
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ ±10
│
│
│
│ 70
│
│ μA
│
│
│
│ mA
│
│
│
│
│
│
│ 80
│
│ 90
│
│ 4
│
│
│
│
│ mA
│
│
│
│ ICC3
│ RAS and CAS high
│
│
│ VCC = 5.5 V, Minimum cycle,
│
│
│
│ 1,2,3
│
│
│
│ 01
│
│
│
│
│
│
│
│ 70
│
│
│
│ mA
│
│
│
│
│
│
│
│ 80
│
│
│
│ RAS , CAS , addresses cycling │
│ (CBR refresh)
│
│ RAS = 0.8 V,
│ 1,2,3
│
│ 03
│
│
│
│ 90
│
│
│
│
│
│
│
│CI(A)
│
│
│CI(S)
│
│
│ CDQ
│
│ CAS , addresses cycling,
│ tPC = minimum,
│ VCC = 5.5 V
│
│
│ f = 1 MHz See 4.4.1e
│ Bias on pins under test = 0 V
│ VCC = 5.0 V nominal
│ TA = 25°C
│For CI(A) the max capacitance
│for packages N, R, and T is
│11 pF
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ pF
│
│
│ pF
│
│
│ pF
│
│
│ ICC4
RAS cycling, CAS = 2.4 V
│
│ ( RAS only refresh)
│ 02
4
4
4
│ 01
02
03
All
All
All
│
│ 40
50
60
7
10
10
│
│ mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
G
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6
TABLE IA. Electrical performance characteristics - continued.
Test
Access time from
column address
Access time from
CAS low
9/
Access time from
column pre-charge
Access time from
RAS low
10/
Access time from
OE low
11/
Output disable time after
CAS high
12/
Output disable time
after OE high
12/
Cycle time, random
read or write
13/
Cycle time,
read-write
│
│Symbol
│
│
│
│ tAA
│
│
│
│
│ tCAC
│
│
│
│
│ tCPA
│
│
│
│
│ tRAC
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│ (See figures 4 and 5)
│ 1/ 2/ 5/ 6/ 7/ 8/
│
│
│
│
│
│
│Group A │Device
│subgroups │ type
│
│
│
│
│ 9,10,11 │ 01
│
│
│
│ 02
│
│
│
│ 03
│ 9,10,11 │ 01
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│
│ Limits
│
│
│
│
│ Min │ Max
│
│ 55
│
│
│
│ 45
│
│
│
│ 40
│
│ 30
│
│ Unit
│
│
│
│ ns
│
│
│
│
│ ns
03
01
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
45
120
│
│
│
│
│ ns
│
│
│
│
│ ns
02
03
01
02
25
20
55
50
│
│
│
│
│ tOEA
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│ 02
│
│ 03
│ 01
│
│
│
│
│
│
│ 100
│
│ 80
│ 30
│
│
│
│
│ ns
│ or
│ tOE
│
│
│
│ tOFF
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│ 02
│
│ 03
│
│ 01
│
│
│
│
│
│
│
│ 25
│
│ 20
│
│ 30
│
│
│
│
│
│ ns
│
│
│
│
│
│ tOEZ
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│ 02
│
│ 03
│
│ 01
│
│
│
│
│
│
│
│ 25
│
│ 20
│
│ 30
│
│
│
│
│
│ ns
│ or
│ tOD
│
│
│
│ tRC
│
│
│
│
│
│ tRWC
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 25
│
│ 20
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│ ns
│
│
│
│
02
03
01
02
03
01
02
03
210
180
150
285
245
205
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
7
TABLE I. Electrical performance characteristics - continued.
Test
Cycle time, pagemode read or write
14/
Cycle time, pagemode read-write
Pulse duration, page-mode,
RAS low 15/
Pulse duration, non-page-mode, RAS low
15/
Pulse duration, CAS low 16/
Pulse duration, CAS high
(Page-mode and non-pagemode) 17/
Pulse duration, RAS high
(pre-charge)
Pulse duration, write
│
│Symbol
│
│
│
│
│ tPC
│
│
│
│
│tPRWC
│
│
│
│
│tRASP
│
│
│
│
│
│ tRAS
│
│
│
│
│
│
│
│ tCAS
│
│
│
│
│
│
│
│ tCP
│ or
│ tCPN
│
│
│
│ tRP
│
│
│
│
│
│ tWP
│
│
│
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│(See figures 4 and 5)
│1/ 2/ 5/ 6/ 7/ 8/
│
│
│
│
│
│
│
│
│
│
│
│Group A │Device
│subgroups │ type
│
│
│
│
│
│
│ 9,10,11 │ 01
│
│
│
│ 02
│
│
│
│ 03
│ 9,10,11 │ 01
│
│
│
│ 02
│
│
│
│ 03
│ 9,10,11 │ 01
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
02
03
All
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
01
│
│
│
│
│
│
│
│
│
│
│
01
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│
01
│
│ 02
│
│ 03
│ All
│
│
02
03
All
│ 01
│
│ 02
│
│ 03
│
02
03
01
02
03
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Limits
│ Unit
│
│
│
│
Min │ Max │
│
│
65 │
│ ns
│
│
60 │
│
│
│
50 │
│
135 │
│ ns
│
│
120 │
│
│
│
105 │
│
120 │
│
│ 100
│ 80
│
│
│
│ 120
│
│
│ 100
│
│
│
│ ns
│
│ μs
│
│
│ ns
│ 30
│
│ 25
│
│ 20
│
│
│
│
│
│
│
│
│ 10
│
│
│ ns
│
│
│
│
│ μs
│
│
│
│ 100
│
│ 80
│
│
│
│ 15
│
│ 12
│
│ 12
│
│
│
│
│
│
│
│
│
│
│
│
80
70
60
25
20
15
│
│
│
│
│ 10
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ μs
│
│
│ ns
│
│
│
│
│
│ ns
│
│
│
│
│
│ ns
│
│
│
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
8
TABLE I. Electrical performance characteristics - continued.
Test
Setup time, column-address
before CAS low
Setup time, row-address
before RAS low
Setup time, data 18/
Setup time, read
│
│Symbol
│
│
│
│
│ tASC
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│(See figures 4 and 5)
│
│
│Group A │Device
│subgroups │ type
│
│
│
│
│
│
│ 9,10,11 │ All
│
│
│ Limits
│ Unit
│
│
│
│
│
│
│ Min │ Max │
│
│
│
│ 0
│
│ ns
│
│
│ tASR
│ 1/ 2/ 5/ 6/ 7/ 8/
│
│
│
│
│ 9,10,11
│
│
│ All
│
│
│
│
│
│
│ tDS
│
│ tRCS
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│ 9,10,11
│
│
│
│ All
│
│ All
│
│
│
│
│
│
│ tCWL
│
│ 9,10,11
│ 01
│ 30
│ 9,10,11
│ 01
│ 30
│ 9,10,11
│ All
│
│
│
before CAS low
Setup time, W low before
│
│
│
│
CAS high
Setup time, W low before
│ tRWL
│
│
│
│
RAS high
Setup time, W low before
CAS low (Early write
operation only)
19/
Setup time, W high ( CAS
before RAS refresh only)
Hold time, column-address
│
│
│
│ tWSR
│ or
│ tWRP
│
│ tCAH
│
│
│
│
│
│ tDHR
after CAS low
Hold time, data
after RAS low
Hold time, data
│ tWCS
18/
│
│
│
│
│ tDH
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 02
│
│ 03
0
│
│
│
│
│
│
│
│
│
│
│
│ ns
│
│ ns
│
│ ns
│
│
│
│
│
│ 25
│
│ 20
│
│
│
│
│
│
│
│
│
│ 25
│
│ 20
│
│
│
│
│
│
│
│
│
│
│
│
│
│
0
│
│ ns
│
│ ns
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│ 01
│
│
│
│ 20
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│ 02
│
│ 03
0
│
│
│ ns
│
│
│
│ 9,10,11
│
│
│
│
│
│
0
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│ All
│ 10
│
│ 02
│
│ 03
│
│ 01
│
│ 20
│
│ 15
│
│ 90
02
75
│
│
│
│
│
│
│
│
│
03
01
02
03
60
25
20
15
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│ ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
9
TABLE I. Electrical performance characteristics - continued.
Test
Hold time, column address
after RAS low
16/
Hold time, rowaddress after
RAS low
Hold time, read after CAS
high
20/
Hold time, read after RAS
high
20/
Hold time, write after CAS
low (Early write
operation only)
│
│Symbol
│
│
│
│
│ tAR
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│(See figures 4 and 5)
│
│
│Group A │Device
│subgroups │ type
│
│
│
│
│
│
│ 9,10,11 │ 01
│
│
│ Limits
│ Unit
│
│
│
│
│
│
│ Min │ Max │
│
│
│
│ 90 │
│ ns
│
│
│
│
│
│
│
│
│
│ 15
│
│ 10
│
│
│
│
│
│ tRAH
│
│ tRCH
│
│
│ tRRH
│
│
│ tWCH
│
│
│
│
│ 1/ 2/ 5/ 6/ 7/ 8/
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│ 02
│
│ 03
│
│ 01
│
│ 9,10,11
│
│
│ All
│
│
│ 9,10,11
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
Hold time, write after RAS
low
16/
│ tWCR
│
│
│
│
Hold time, W high CAS
before RAS refresh only
│ tWHR
│ or
│ tWRH
│
│
│ tAWD
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│ 9,10,11
│ tCHR
│
│ 9,10,11
Delay time, column address
to W low (Read write
operation only)
19/
Delay time, RAS low to CAS
high ( CAS -before RAS
refresh only)
21/
│
│
│
│
│
│
│
│
Delay time, CAS high to RAS │ tCRP
low
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│
│ 02
│
│ 03
│ All
│
│
│ 01
│
│ 02
│
│ 03
│ 01
│
│ 02
│
│ 03
│ All
│
│
│
│
│ 01
│
│ 75
│
│ 60
│
│ 15
│
│
│
│
│
│
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
0
0
│ 25
│
│ 20
│
│ 15
│ 90
│
│ 75
│
│ 60
│
│
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│ ns
│
│
│
│
│ 10
│
│
│
│
│ 90
│
│
│
│
│
│
│ ns
│
│
│
│
│ ns
│ 25
│
│ ns
│
│
│
│
│
│ 02
│
│ 03
│
│ 80
│
│ 70
│
│
│
│
│
│
│
│
│
│ 02
│
│ 03
│
│ 20
│
│ 20
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│ 01
│ 02
│ 03
│ 10
│ 5
│ 5
│
│
│
│ ns
│
│
│ 01
│
│
│
│
│
│
│
│
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
10
TABLE I. Electrical performance characteristics - continued.
│
│Symbol
│
│
│
│
│
│
│Group A │Device
│subgroups │ type
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│ 01
│
│ 02
│
│ 03
│
│
│ Limits
│ Unit
│
│
│
│
│
│
│ Min │ Max │
│
│
│
Delay time, RAS low to CAS
high
│ tCSH
│
│
│
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│ 120
│
│ 100
│
│ 80
│
│
│
│
│
│
│ ns
│
│
│
Delay time, CAS low to RAS
│ tCSR
│
│ 9,10,11
│ All
│ 10
│
│ ns
Delay time, CAS low to W low │ tCWD
(Read-write operation only)
│
19/
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│ 01
│
│ 02
│
│ 03
│ 70
│
│ 60
│
│ 50
│
│
│
│
│
│ ns
│
│
│
│
Hold time, OE command 22/ │ tOEH
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│ 01
│
│ 02
│
│ 03
│ 30
│
│ 25
│
│ 20
│
│
│
│
│
│ ns
│
│
│
│
│ tOED
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│ 01
│
│ 02
│
│ 03
│ 30
│
│ 25
│
│ 20
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ 02
│
│ 03
│
│ 25
│
│ 20
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ ns
Test
low ( CAS before RAS
refresh only)
21/
Delay time, OE to data 23/
│
│
│
Hold time, RAS referenced to │ tROH
to OE
24/
Delay time, RAS low to
column-address
25/
Delay time, column-address
to RAS high
Delay time, column-address
to CAS high
23/
│ tRAD
│
│
│
│
│
│ tRAL
│
│
│
│
│
│ tCAL
│
│
│
│
│ (See figures 4 and 5)
│ 1/ 2/ 5/ 6/ 7/ 8/
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│
│ 01
│
│
│
│
│
│
│
01
02
03
01
│
│ 02
│
│ 03
│
│ 01
│
│ 02
│
│ 03
│
│
│
│ 30
│
│
│
│
│
│
│
20
20
15
55
│
│ 50
│
│ 40
│
│ 55
│
│ 50
│
│ 40
│
│
│
│
│
│
│
│ ns
│ 65
│
│ 50
│
│ 40
│
│
│
│
│
│
│ ns
│
│
│
│
│
│ ns
│
│
│
│
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - continued.
│
│Symbol
│
│
│
│
│
│
Conditions
│
-55°C ≤ TC ≤ +125°C
│
4.5 V ≤ VCC ≤ 5.5 V
│ unless otherwise specified
│
│
│
│Group A │Device
│subgroups │ type
│
│
│
│
│
│
│
│
│ Limits
│ Unit
│
│
│
│
│
│
│ Min │ Max │
│
│
│
Delay time, RAS high to CAS │ tRPC
low
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│
│
│
│
│
Delay time RAS low to W low │ tRWD
(Read-write operation
│
only)
19/
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│
│
Test
Delay time, RAS low to CAS
low
26/
│ tRCD
│
│
│
│
│
Delay time, CAS low to RAS │ tRSH
high
│
│
│
│
CAS to output in low Z 23/
Refresh time interval
Setup time, OE prior to RAS
during hidden refresh
cycle
23/
│ tCLZ
│
│
│ tREF
│
│ tORD
│
│
│
│ (See figures 4 and 5)
│ 1/ 2/ 5/ 6/ 7/ 8/
│
│
│
│
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│
│
│
│ 9,10,11
│
│
│
│ 01
│
│ 02
│
│ 03
│
│ All
│
│
│ 01
│
│ 02
│
│ 03
│ 01
│
│ 02
│
│ 03
│ All
│
│
│ All
│
│ All
│
│
│
│ 25
│
│ 25
│
│ 20
│
0
│ 30
│
│ 25
│
│ 20
│ 160
│
│ 135
│
│ 110
│
│
│
│
│
│
│
│
│
0
0
│ 90
│
│ 75
│
│ 60
│
│ ns
│
│
│
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│ ns
│
│
│
│
│
│
│
│
│ ns
│
│
│
│ 27/
│
│
│ 16
│
│ ns
│
│
│ ms
│
1/
VSS is common for all voltages.
2/
An initial pause of 200 μs is required after power-up followed by a minimum of 8 initialization cycles after full VCC level is
achieved. The 8 initialization cycles need to be RAS only refresh or CBR with W high to assure proper device
operation. The 8 initialization cycles should be repeated any time the 16 ms refresh requirement is exceeded.
3/
ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the
outputs open.
4/
ICC is dependent on cycle rates.
5/
AC characteristics assume transition time tT = 5 ns.
6/
VIL (max) and VIH (min) are reference levels for measuring timing of input signals. Transition times are measured
between VIL and VIH.
7/
In addition to meeting the transition rate specification, all input signals must make the transition between VIL and VIH (or
VIH and VIL) in a monotonic manner.
8/
When operating the device, transition times (rise and fall) for all input signals are to be a minimum of 3 ns and a
maximum of 50 ns.
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TABLE I. Electrical performance characteristics - continued.
9/
Assumes that tRCD > tRCD (max).
10/
Assumes that tRCD < tRCD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will
increase by the amount that tRCD exceeds the value shown.
11/
During a read cycle, if OE is low and then taken high, DQs go high impedance. If OE is permanently held low, a
late-write or read-modify-write operation is not possible.
12/
tOFF and t OEZ or t OD are specified when the output is no longer driven. The output is disabled (high impedance) by
bringing either OE or CAS high and it is not referenced to VOH or V OL.
13/
The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range (-55°C ≤ TC ≤ +125°C) is assured.
14/
To guarantee tPC min, tASC should be greater than or equal to tCP.
15/
In a read-write cycle, tRWD and tRWL must be observed.
16/
In a read-write cycle, tCWD and tCWL must be observed.
17/
If CAS is low at the falling edge of RAS , DQs will be maintained from the previous cycle. To initiate a new cycle and
clear the data out buffer, CAS must be pulsed high for tCPN.
18/
These parameters are referenced to CAS leading edge in early-write cycles and W leading edge in late-write or
read-modify-write cycles.
19/
tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in late-write and read-modify-write cycles only. If tWCS >
tWCS (min), the cycle is an early-write cycle and the data outputs will remain open circuit throughout the entire cycle. If
tRWD > tRWD (min), tAWD > tAWD (min) and tCWD > tCWD (min), the cycle is a read-write and the data outputs will contain data
read from the selected cells. If neither of the above conditions are met, the state of the data outputs (at access time and
until CAS goes back to VIH) is indeterminate.
20/
Either tRRH or t RCH must be satisfied for a read cycle.
21/
Enables on-chip refresh and address counters.
22/
Late-write and read-modify-write cycles must have both tOD and tOEH met ( OE high during write cycle) in order to
ensure that the output buffers will be open during the write cycle. The DQs will provide the previously read data if CAS
remains low and OE is taken back low after tOEH is met. If CAS goes high prior to OE going back low, then the DQs
will remain open.
23/
This parameter may not be tested, but shall be guaranteed to the limits specified in table I and is included to help with
device application.
24/
This parameter does not apply where OE is not related to RAS in device design.
25/
Maximum value specified only to guarantee access time. Operation within the tRAD (max) limit ensures that tRCD (max)
can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then
access time is controlled exclusively by tAA.
26/
Maximum value specified only to guarantee access time. Operation within the tRCD (max) limit ensures that tRAC (max)
can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then
access time is controlled exclusively by tCAC.
27/
Valid data is presented at the output after all access times are satisfied but may go from three-state to an invalid data
state prior to the specified access times as the outputs are driven when CAS goes low.
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Case X
Inches
.003
.005
.007
.010
.015
.016
.018
mm
0.08
0.13
0.18
0.25
0.38
0.41
0.46
Inches
.030
.050
.090
.117
.355
.490
.700
mm
0.76
1.27
2.29
2.97
9.02
12.45
17.78
FIGURE 1. Case outline.
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Case Y
Inches
.006
.010
.022
.028
.040
.050
.060
.068
.070
mm
0.15
0.25
0.56
0.71
1.02
1.27
1.52
1.72
1.78
Inches
.080
.100
.105
.125
.393
.407
.590
.610
.690
.710
mm
2.03
2.54
2.68
3.18
9.98
10.34
14.98
15.49
17.52
18.03
FIGURE 1. Case outlines – Continued.
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Case Z
Inches
.006
.013
.016
.023
.025
.035
.045
.055
.063
.078
mm
0.15
0.33
0.41
0.58
0.64
0.89
1.14
1.40
1.60
1.98
Inches
.130
.160
.318
.340
.370
.592
.608
.665
.685
mm
3.30
4.06
8.08
8.64
9.40
15.04
15.44
16.89
17.40
FIGURE 1. Case outlines – Continued.
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Case U
Inches
.003
.010
.011
.015
.018
.045
.060
.065
.070
.100
mm
0.08
0.25
0.28
0.38
0.46
1.14
1.52
1.65
1.78
2.54
Inches
.125
.175
.200
.380
.385
.410
.420
.900
.980
1.030
mm
3.18
4.44
5.08
9.65
9.78
10.41
10.67
22.86
24.89
26.16
FIGURE 1. Case outlines – Continued.
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Case T
Inches
.006
.010
.022
.025
.028
.035
.045
.050
.055
mm
0.15
0.25
0.56
0.64
0.71
0.89
1.14
1.27
1.40
Inches
.060
.080
.100
.343
.357
.590
.610
.665
.685
mm
1.52
2.03
2.54
8.71
9.07
14.99
15.49
16.89
17.40
FIGURE 1. Case outlines – Continued.
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Case M
Inches
.004
.006
.010
.015
.019
.027
.033
.045
.055
.097
mm
0.10
0.15
0.25
0.38
0.48
0.69
0.84
1.14
1.40
2.46
Inches
.117
.127
.290
.324
.336
.370
.405
.415
.692
.708
mm
2.97
3.23
7.37
8.23
8.53
9.40
10.29
10.54
17.58
17.98
FIGURE 1. Case outlines – Continued.
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Case N
Millimeters
Inches
Symbol
A2
b
b2
c
e
eA
D
E
L
L1
Min
Max
Min
Max
9.02
0.41
0.89
0.20
1.14
2.16
26.29
2.54
3.18
0.38
10.29
0.58
1.14
0.38
1.40
2.92
27.05
3.30
5.08
1.27
.355
.016
.035
.008
.045
.085
1.035
.100
.125
.015
.405
.023
.045
.015
.055
.115
1.065
.130
.200
.050
FIGURE 1. Case outlines – Continued.
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Device types
Case outlines
01, 02, 03
R, X, U, M
Terminal
number
Y, Z, T
N
Terminal symbol
1
2
DQ1
DQ2
DQ1
DQ2
3
4
W
W
RAS
RAS
5
6
7
8
9
10
11
12
13
14
15
16
A9
A0
A1
A2
A3
VCC
A4
A5
A6
A7
A8
A9
NP
NP
NP
A0
A1
A2
A3
VCC
A4
A5
VSS
DQ1
DQ2
OE
A6
A4
17
CAS
A7
A5
18
19
20
21
22
23
24
25
26
DQ3
DQ4
VSS
A8
NP
NP
NP
A6
A7
A8
OE
CAS
DQ3
DQ4
W
RAS
A9
A0
A1
A2
A3
VCC
OE
CAS
DQ3
DQ4
VSS
NP=NO PIN
FIGURE 2. Terminal connections.
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Inputs
Operation
Input / Output
RAS
CAS
W
OE
Row
address
Column
address
D
Q
Read
ACT
ACT
NAC
ACT
APD
APD
DNC
VLD
Write (early write)
ACT
ACT
ACT
DNC
APD
APD
VLD
DNC
Write (late write)
ACT
ACT
ACT
NAC
APD
APD
VLD
OPN
Read-modify-write
ACT
ACT
ACT
ACT
APD
APD
VLD
VLD
RAS - only refresh
ACT
NAC
DNC
DNC
APD
DNC
DNC
OPN
Hidden refresh (read)
ACT
ACT
NAC
ACT
APD
APD
DNC
VLD
Hidden refresh (write)
ACT
ACT
ACT
DNC
APD
APD
VLD
DNC
CAS before RAS
ACT
ACT
NAC
DNC
DNC
DNC
DNC
OPN
NAC
NAC
DNC
DNC
DNC
DNC
DNC
OPN
refresh
Standby
ACT = active
NAC = non-active
DNC = don't care
VLD = valid
APD = applied
OPN = open
FIGURE 3. Truth table.
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Note: Output may go from three-state to an invalid state prior to the specified access time.
FIGURE 4. Timing waveforms.
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FIGURE 4. Timing waveforms .- Continued.
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FIGURE 4. Timing waveforms .- Continued.
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Note: Output may go from three-state to an invalid data state prior to the specified time.
FIGURE 4. Timing waveforms .- Continued.
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Notes: 1. Output may go from three-state to an invalid state prior to the specified access time.
2. Access time is tCPA or tAA dependent.
FIGURE 4. Timing waveforms .- Continued.
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Notes: 1. tDS and tDH are referenced to CAS or W , whichever occurs last.
2. A read cycle or a read-write cycle can be intermixed with a write cycle as long as read and read-write
timing specifications are not violated.
FIGURE 4. Timing waveforms .- Continued.
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Notes: 1. Output may go from three-state to an invalid data state prior to the specified time.
2. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing
specifications are not violated.
FIGURE 4. Timing waveforms .- Continued.
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FIGURE 4. Timing waveforms .- Continued.
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FIGURE 4. Timing waveforms .- Continued.
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FIGURE 4. Timing waveforms .- Continued.
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FIGURE 4. Timing waveforms .- Continued.
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FIGURE 5. Load circuits.
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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Line
no.
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
TM 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M
Device
class Q
Device
class V
1
Interim electrical
parameters (see 4.2)
1, 7, 9
2
Static burn-in
(method 1015)
3
Same as line 1
4
Dynamic burn-in
(method 1015)
5
Same as line 1
6
Final electrical
parameters (see 4.2)
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
7
Group A test
requirements (see 4.4)
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
8
Group C end-point
electrical
parameters (see 4.4)
2, 3, 7,
8A, 8B
2, 3, 7,
8A, 8B
1, 2, 3, 7, 8A,
8B, 9, 10, 11 ∆
9
Group D end-point
electrical
parameters (see 4.4)
2, 3, 8A, 8B
2, 3, 8A, 8B
2, 3, 8A, 8B
10
Group E end-point
electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
Not
required
Not
required
Required
1*, 7* ∆
Required
Required
Required
1*, 7* ∆
1/
2/
3/
4/
5/
6/
Blank spaces indicate tests are not applicable.
Any or all subgroups may be combined when using high-speed testers.
Subgroups 7 and 8 functional tests shall verify the truth table.
* indicates PDA applies to subgroup 1 and 7.
** see 4.4.1e.
∆ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed
with reference to the previous interim electrical parameters (see line 1).
7/ See 4.4.1d.
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TABLE IIB. Delta limits at +25°C.
Device types
Test
1/
All
ICC2 standby
±10% of specified value in table I
IIH, IIL
±10% of specified value in table I
IOHZ, IOLZ
±10% of specified value in table I
1/ The above parameter shall be recorded before and after the required
burn-in and life tests to determine the delta ∆.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted.
c.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
d.
O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be used for reference.
e.
Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the designated
terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output
terminals tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
36
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MILPRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All
device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25ºC
±5ºC, after exposure, to the subgroups specified in table IIA herein.
4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7,
and 9.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
CIN C OUT --------------------------------GND --------------------------------------ICC -----------------------------------------IIL -------------------------------------------
Input and bidirectional output, terminal-to-GND capacitance.
Ground zero voltage potential.
Supply current.
Input current low
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
37
IIH ------------------------------------------TC ----------------------------------------TA ----------------------------------------VCC ----------------------------------------VIC-----------------------------------------O/V----------------------------------------O/I ------------------------------------------
Input current high
Case temperature.
Ambient temperature
Positive supply voltage.
Positive input clamp voltage
Latch-up over-voltage
Latch-up over-current
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the
system must supply at least that much time (even though most devices do not require it). On the other hand, responses from
the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never
provides data later than that time.
6.5.2 Waveforms.
Waveform
symbol
Input
Output
MUST BE
VALID
WILL BE
VALID
CHANGE FROM
H TO L
WILL CHANGE
FROM
H TO L
CHANGE FROM
L TO H
WILL CHANGE
FROM
L TO H
DON'T CARE
ANY CHANGE
PERMITTED
CHANGING
STATE
UNKNOWN
HIGH
IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
38
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-90847
FUNCTIONAL ALGORITHMS
A.1. SCOPE
A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper
operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is
understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each
manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be
used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be
applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information
contained herein is intended for compliance.
A.2. APPLICABLE DOCUMENTS. This section is not applicable to this appendix.
A.3. ALGORITHMS
A.3.1 Algorithm A (pattern 1).
A.3.1.1 Output High Impedance (toff). This pattern verifies the output buffer switches to high impedence (tri-state) within the
specified tOFF after the rise of CAS . It is performed in the following manner.
Step 1 Perform 8 pump cycles.
Step 2 Load address location with data.
Step 3 Raise CAS and read address location and guarantee VOL < VOUT < VOH after TOFF delay.
A.3.2 Algorithm B (pattern 2).
A.3.2.1 Vcc Slew. This pattern indicates sense amplifier margin by slewing the supply voltage between memory writing and
reading. It is performed in the following manner:
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Perform 8 pump cycles.
Load memory with background data with VCC at 4.5 V.
Change VCC to 5.5 V.
Read data from memory.
Write memory with data complement.
Change VCC to 4.5 V.
Read data complement from memory.
A.3.3 Algorithm C (pattern 3).
A.3.3.1 March data. This pattern tests for address uniqueness and multiple selection. It is performed in the following
manner:
Step 1 Perform 8 pump cycles.
Step 2 Write memory with data.
Step 3 Read location 0.
Step 4 Write location 0 with data complement.
Step 5 Repeat step 3 and 4 for all other locations in the memory (sequentially).
Step 6 Read data complement in maximum address location.
Step 7 Write data in maximum address location.
Step 8 Repeat step 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 9 Read data in maximum address location.
Step 10 Write data complement in maximum address location.
Step 11 Repeat steps 9 and 10 for all other locations in the memory from maximum to minimum address.
Step 12 Read data complement from memory.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
39
APPENDIX A – Continued.
APPENDIX A FORMS A PART OF SMD 5962-90847
A.3.4 Algorithm D (pattern 4).
A.3.4.1 Refresh test (cell retention) +125°C only. This test is used to check the retention time of the memory cells. It is
performed in the following manner:
Step 1
Step 2
Step 3
Step 4
Step 5
Perform 8 pump cycles.
Load memory with background data.
Pause TREF (stop all clocks).
Read memory with background data.
Repeat steps 2, 3, and 4 with data complement.
A.3.5 Algorithm E (pattern 5).
A.3.5.1 Read-modify-write (RMW). This pattern verifies the Read-modify-write mode for the memory. It is performed in the
following manner:
Step 1
Step 2
Step 3
Step 4
Step 5
Perform 8 pump cycles.
Write memory with data.
Read location 0 and write location 0 with data complement using RMW cycle.
Repeat step 3 for all other locations in the memory.
Repeat steps 3 and 4 using invert data.
A.3.6 Algorithm F (pattern 6).
A.3.6.1 Page mode. This pattern verifies the Page mode for the memory. It is performed in the following manner:
Step 1
Step 2
Step 3
Step 4
Step 5
Perform 8 pump cycles.
Load first page of memory with background data using page mode cycle.
Read first page of memory with data and load with data complement using page mode cycle.
Read first page of memory with data complement and load with data using page mode cycle.
Repeat steps 2, 3, and 4 for remaining memory locations.
A.3.6.2 Page mode (alternate). This pattern verifies the page mode for the memory. It is performed in the following manner:
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Perform 8 pump cycles.
Write memory with data using row fast addressing.
Read data from first page of memory and write it with data complement using page mode cycle.
Repeat for rest of memory pages.
Read data complement from memory using row fast addressing.
Repeat steps 3, 4, and 5 using data.
A.3.7 Algorithm G (pattern 7).
A.3.7.1 CAS -Before- RAS refresh test. This test is used to verify the functionality of the CAS -Before- RAS mode of cell
refreshing. It is done at +125°C only and is performed in the following manner:
Step 1 Perform 8 pump cycles.
Step 2 Load memory with background data for 16ms.
Step 3 Perform 1024 CAS -Before- RAS cycles, while attempting to modify data.
Step 4 Repeat steps 2 and 3 until all address locations have been loaded.
Step 5 Read memory with data for 16 ms.
Step 6 Perform 1024 CAS -Before- RAS cycles.
Step 7 Repeat steps 5 and 6 until all address locations have been loaded.
Step 8 Repeat steps 2 through 7 with data complement.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
40
APPENDIX A – Continued.
APPENDIX A FORMS A PART OF SMD 5962-90847
A.3.7.2 CAS -Before- RAS refresh test (alternate). This test is used to verify the functionality of the CAS -Before- RAS mode
of cell refreshing. It is done at +125°C only and is performed in the following manner:
Step 1 Perform 8 pump cycles.
Step 2 Write memory data.
Step 3 Pause for tREF (stop all clocks high).
Step 4
Step 5
Step 6
Step 7
Perform 1024 CAS -Before- RAS cycles.
Repeat steps 3 and 4 for 250 ms.
Read data from memory.
Repeat steps 2 through 6 with data complement.
A.3.8 Algorithm H (pattern 8).
A.3.8.1 RAS -Only refresh test. This test is used to verify the functionality of the RAS -only mode of cell refreshing. It is
done at +125°C only and is performed in the following manner:
Step 1 Perform 8 pump cycles.
Step 2 Load memory with background data for 16 ms.
Step 3 Perform 1024 RAS -only cycles.
Step 4 Repeat steps 2 and 3 until all address locations have been loaded.
Step 5 Read memory with data for 16ms.
Step 6 Perform 1024 RAS -only cycles.
Step 7 Repeat steps 5 and 6 until all address locations have been loaded.
Step 8 Repeat steps 2 through 7 with data complement.
A.3.8.2 RAS -Only refresh test (cell retention) +125°C only (alternate). This test is used to verify the functionality of the RAS
-only mode of cell refreshing. It is done at +125°C only and is performed in the following manner:
Step 1 Perform 8 pump cycles.
Step 2 Write memory with data.
Step 3 Pause for tREF (stop all clocks high).
Step 4
Step 5
Step 6
Step 7
Perform 1024 RAS -only cycles.
Repeat steps 3 and 4 for 250 ms.
Read data from memory.
Repeat steps 2 through 6 with data complement.
A.3.9 Algorithm I (pattern 9).
A.3.9.1 Refresh test (periphery retention) +125°C only. This test is used to check the minimum periphery retention time and
is optional at the discretion of the manufacturer. It is performed in the following manner:
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Step 8
Step 9
Perform 8 pump cycles.
Write memory with data.
Read data from memory.
Pause for TREF (stop all clocks high).
Load memory with data complement.
Read data complement from memory.
Pause for TREF (stop all clocks high).
Write memory with data.
Read data from memory.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90847
A
REVISION LEVEL
G
SHEET
41
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 10-02-26
Approved sources of supply for SMD 5962-90847 are listed below for immediate acquisition information only and shall be
added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include
the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has
been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MILHDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at
http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
5962-9084701MRA
0EU86
MT4C4001JCN-12
3/
SMJ44400-12JDBM
5962-9084701MXA
0EU86
SMJ44400-12HRM
5962-9084701MYA
3/
MT4C4001JEC-12
3/
SMJ44400-12HMM
5962-9084701MZA
3/
SMJ44400-12HJ
5962-9084701MUA
0EU86
MT4C4001JC-12
0EU86
SMJ44400-12JDM
0EU86
MT4C4001JECN-12
3/
SMJ44400-12HLM
5962-9084701MMA
3/
MT4C4001JF-12
5962-9084701MNA
3/
MT4C4001JCZ-12
3/
SMJ44400-12SVM
0EU86
MT4C4001JCN-10
3/
SMJ44400-10JDBM
5962-9084702MXA
0EU86
SMJ44400-10HRM
5962-9084702MYA
3/
MT4C4001JEC-10
3/
SMJ44400-10HMM
5962-9084702MZA
3/
SMJ44400-10HJ
5962-9084702MUA
0EU86
MT4C4001JC-10
0EU86
SMJ44400-10JDM
0EU86
MT4C4001JECN-10
3/
SMJ44400-10HLM
5962-9084702MMA
3/
MT4C4001JF-10
5962-9084702MNA
3/
MT4C4001JCZ-10
3/
SMJ44400-10SVM
0EU86
MT4C4001JCN-8
3/
SMJ44400-80JDBM
5962-9084701MTA
5962-9084702MRA
5962-9084702MTA
5962-9084703MRA
See notes at end of table.
Page 1 of 2
Vendor
similar
PIN 2/
STANDARD MICROCIRCUIT DRAWING BULLETIN – Continued.
DATE: 10-02-26
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9084703MXA
0EU86
SMJ44400-80HRM
5962-9084703MYA
3/
3/
MT4C4001JEC-8
SMJ44400-80HMM
5962-9084703MZA
3/
SMJ44400-80HJ
5962-9084703MUA
0EU86
MT4C4001JC-8
0EU86
SMJ44400-80JDM
0EU86
MT4C4001JECN-8
3/
SMJ44400-80HLM
5962-9084703MMA
3/
MT4C4001JF-8
5962-9084703MNA
3/
MT4C4001JCZ-8
3/
SMJ44400-80SVM
5962-9084703MTA
1/ The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer listed
for that part. If the desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items
acquired to this number may not satisfy the performance requirements
of this drawing.
3/ Not available from an approved source.
Vendor CAGE
number
0EU86
Vendor name
and address
Micross Components
8701 Cross Park Dr
Austin, Texas 78754-4566
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
Page 2 of 2