90622

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R204-95. jb
95-10-30
Michael A. Frye
B
Changes in accordance with NOR 5962-R051-98. ksr
98-03-06
Raymond Monnin
C
Changes in accordance with NOR 5962-R137-98. glg
98-07-20
Raymond Monnin
D
Boilerplate update and part of five year review. tcr
07-05-03
Robert M. Heber
E
Update drawing to meet current MIL-PRF-38535 requirements. - glg
15-11-16
Charles Saffle
REV
E
E
E
E
E
E
SHEET
35
36
37
38
39
40
REV
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
SHEET
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
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REV STATUS
REV
E
E
E
E
E
E
E
E
E
E
E
E
E
E
OF SHEETS
SHEET
1
2
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4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Kenneth Rice
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
Kenneth Rice
APPROVED BY
Michael A. Frye
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS 4M X 1 DYNAMIC RANDOM ACCESS
MEMORY (DRAM) MONOLITHIC SILICON
DRAWING APPROVAL DATE
92-03-05
REVISION LEVEL
E
SIZE
A
SHEET
DSCC FORM 2233
APR 97
CAGE CODE
67268
1 OF
5962-90622
40
5962-E050-16
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
90622
01
M
X
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number 1/
01
02
03
Circuit function
Access time
4M x 1 Dynamic random access memory
4M x 1 Dynamic random access memory
4M x 1 Dynamic random access memory
120 ns
100 ns
80 ns
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Z
U
T
N
V
M
Case outline
See figure 1, (20-lead, 0.710" x 0.497" x 0.100"), flat package (top brazed)
See figure 1, (26/20-terminal, .710" x .407" x .092"), rectangular chip carrier package
See figure 1, (26/20-terminal, .685" x .370" x .160"), J-leaded, rectangular chip carrier package
See figure 1, (26/20-terminal, .685" x .357" x .080"), rectangular chip carrier package
See figure 1, (18-lead, .910" x .410" x .140"), dual in-line package
See figure 1, (20-lead, 1.050" x .395" x .105"), zig-zag in-line package
D-6 (18-lead, .960" x .310" x .200"), dual-in-line package
See figure 1, (20-lead, .708" x .415" x .117"), flat package (bottom brazed)
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
_______
1/ Generic numbers are listed on the Standardized Military Drawing Source Approval Bulletin at the end of this document and
will also be listed in MIL-HDBK-103 and QML-38535 (see 6.6.2 herein).
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
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DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
E
SHEET
2
1.3 Absolute maximum ratings. 2/
Voltage range on any pin ....................................................................................
Voltage range on VCC ..........................................................................................
Short circuit output current ..................................................................................
Maximum power dissipation (PD) ........................................................................
Storage temperature range ...............................................................................
Thermal resistance, junction-to-case (θJC):
Case outline V................................................................................................
Case outlines X, Y, Z, U, T, N, and M ..........................................................
Junction temperature (TJ) 4/...............................................................................
-1.0 V dc to 7.0 V dc
-1.0 V dc to 7.0 V dc
50 mA
1W
-65°C to +150°C
See MIL-STD-1835
20°C/W 3/
+175°C
1.4 Recommended operating conditions.
Supply voltage range (VCC) 5/ ..........................................................................
High level input voltage range (VIH).....................................................................
Low level input voltage range (VIL) 6/ ..................................................................
Case operating temperature range (TC) ..............................................................
+4.5 V dc to +5.5 V dc
2.4 V dc minimum to 6.5 V dc maximum
-1.0 V dc minimum to 0.8 V dc maximum
-55°C to +125°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
_______
2/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
3/
When a thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated
herein.
4/
Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
5/
All voltage values in this drawing are with respect to VSS.
6/
The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used in this drawing
for logic voltage levels only.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
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SHEET
3
2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
ASTM INTERNATIONAL (ASTM)
ASTM Standard F1192
-
Standard Guide for the Measurement of Single Event Phenomena (SEP) induced by
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor
Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)
JEDEC - SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JESD 78
-
IC Latch-Up Test.
(Copies of this document are available on line at http://www.jedec.org or from JEDEC - Solid State Technology Association,
3103 North 10th Street, Suite 247, Arlington, VA 22201)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in
the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M
shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table. The truth table shall be as specified on figure 3.
3.2.4 Test load circuits. The test load circuits shall be as specified on figure 4.
3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5.
3.2.6 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns
cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be
allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the
manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V
alternate test patterns shall be under the control of the device manufacturer’s Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request.
3.2.7 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only.
Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the
internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor
testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements
as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
E
SHEET
4
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of
supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MILPRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of
product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime's agent,
and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore
documentation shall be made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 41 (see MIL-PRF-38535, appendix A).
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)
electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b.
The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1)
c.
Dynamic burn-in (method 1015 of MIL-STD-883, test condition D) using the circuit submitted (see 4.2b herein).
Interim and final electrical parameters shall be as specified in table IIA herein.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
E
SHEET
5
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
d.
O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JESD 78 may be used for reference.
e.
Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the
designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and
output terminals tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
Delta limits shall apply to group C inspection and shall consist of tests specified in table IIB herein.
4.4.2.1 Additional criteria for device class M.
a. Steady-state life test conditions, method 1005 of MIL-STD-883:
(1)
Test condition D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent
specified in method 1005 of MIL-STD-883.
(2)
TA = +125°C, minimum.
(3)
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
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SHEET
6
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
High level output
voltage
VOH
VCC = 4.5 V, IOH = -5 mA,
VIL = .8 V, VIH = 2.4 V
1,2,3
All
Low level output
voltage
VOL
VCC = 4.5 V, IOL = 4.2 mA,
VIL = .8 V, VIH = 2.4 V
1,2,3
All
0.4
V
Input leakage
current
II
VI = 0 V to 6.5 V,
VCC = 5.5 V,
All other pins = 0 V to VCC
1,2,3
All
±10
µA
Output leakage
current
IO
VCC = 5.5 V, CAS high,
VO = VCC to 0 V
1,2,3
All
±10
µA
Power supply current
read or write
cycle
ICC1
Minimum cycle,
VCC = 5.5 V
Measured for a maximum of
One address transition while
1,2,3
01
70
mA
02
80
03
85
1,2,3
All
4
mA
1,2,3
01
65
mA
02
75
03
85
01
40
02
50
03
60
RAS = VIL
Power supply current
standby
ICC2
After 1 memory cycle,
2.4
V
RAS and CAS high,
VIH = 2.4 V
Power supply current
average refresh
( RAS –only or CBR)
ICC3
VCC = 5.5 V, minimum cycle,
RAS cycling, CAS high
( RAS – only)
RAS low after CAS low (CBR)
Measured for a maximum of
one address transition while
RAS = VIL
Power supply current
average page
ICC4
1,2,3
RAS low, CAS cycling,
tPC = minimum,
VCC = 5.5 V
Measured for a maximum of
one address transition while
CAS = VIH
mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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REVISION LEVEL
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TABLE I. Electrical performance characteristics - continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Input capacitance,
address inputs
CI(A)
f = 1 MHz See 4.4.1e
Bias on pins under test = 0 V
4
All
8
pF
Input capacitance,
data inputs
CI(D)
VCC = 5.0 V nominal
4
All
7
pF
Input capacitance,
strobe inputs
CI(S)
4
All
10
pF
Input capacitance,
Write-enable
inputs
CI(W)
4
All
10
pF
Output capacitance
CO
4
All
10
pF
Access time from
column address
tAA
9,10,11
01
55
ns
02
50
03
40
01
30
02
25
03
20
01
55
02
50
03
45
01
120
02
100
03
80
01
30
02
25
03
20
Access time from
CAS low
Access time from
column precharge
Access time from
RAS low
Output disable time
after CAS high 2/
Cycle time, random
read or write 3/
For CI(A) the Max capacitance for
packages U, T, and N which use
HYPER die with On-Chip-Routing
(OCR) will be 11 pF Max.
See figures 4 and 5
1/
tCAC
9,10,11
tCPA
9,10,11
tRAC
9,10,11
tOFF
9,10,11
tRC
9,10,11
01
210
02
180
03
150
ns
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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REVISION LEVEL
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TABLE I. Electrical performance characteristics - continued.
Test
Symbol
Cycle time,
read-write
tRWC
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
Group A
subgroups
Pulse duration,
page-mode, RAS
low 5/
Limits
Min
1/
9,10,11
Cycle time, pagetPC
mode read or write 4/
Cycle time, pagemode read or write
Device
type
9,10,11
tPRWC
9,10,11
tRASP
9,10,11
01
255
02
220
03
205
01
65
02
60
03
50
01
135
02
115
03
100
01
120
02
100
03
80
All
Pulse duration,
non-page-mode,
RAS low 5/
tRAS
9,10,11
tCAS
9,10,11
01
120
02
100
03
80
tCP
9,10,11
ns
ns
ns
ns
µs
ns
10
01
30
02
25
03
20
All
Pulse duration,
CAS high
Max
100
All
Pulse duration,
CAS low 6/
Unit
µs
ns
10
01
15
02
12
03
12
µs
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
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TABLE I. Electrical performance characteristics - continued.
Test
Symbol
Pulse duration,
RAS high
(precharge)
Pulse duration,
write
tRP
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
Group A
subgroups
Device
type
Limits
Min
1/
9,10,11
tWP
9,10,11
01
80
02
70
03
60
01
25
02
20
03
15
Unit
Max
ns
ns
Setup time, columnaddress before
CAS low
tASC
9,10,11
All
0
ns
Setup time, rowaddress before
RAS low
tASR
9,10,11
All
0
ns
Setup time,
data 7/
tDS
9,10,11
All
0
ns
Setup time, read
before CAS low
tRCS
9,10,11
All
0
ns
Setup time,
W low before
CAS high
tCWL
9,10,11
01
30
ns
02
25
03
20
01
30
02
25
03
20
Setup time,
W low before
RAS high
tRWL
9,10,11
ns
Setup time, W low
before CAS low
(Early write operation
only)
tWCS
9,10,11
All
0
ns
Setup time, W high
tWSR
9,10,11
All
10
ns
tCAH
9,10,11
01
20
ns
02
20
03
15
( CAS before RAS
Refresh only)
Hold time, columnaddress after CAS
low
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - continued.
Test
Symbol
Hold time, data 7/
Hold time, data
tDH
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
See figures 4 and 5
Group A
subgroups
1/
9,10,11
tDHR
9,10,11
tAR
9,10,11
address after RAS
low 8/
Hold time, rowaddress after
tRAH
9,10,11
RAS low
Hold time, read
Limits
Min
after RAS low
Hold time, column
Device
type
01
25
02
20
03
15
01
90
02
75
03
60
01
90
02
75
03
60
01
15
02
15
03
10
Unit
Max
ns
ns
ns
ns
tRCH
9,10,11
All
0
ns
tRRH
9,10,11
All
0
ns
tWCH
9,10,11
01
25
ns
02
20
03
15
01
90
02
75
03
60
All
10
after CAS high 9/
Hold time, read
after RAS high 9/
Hold time, write
after CAS low
(Early write
operation only)
Hold time, write
tWCR
9,10,11
after RAS low 6/
Hold time, W high
tWHR
9,10,11
ns
ns
( CAS -before- RAS
refresh only)
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
tAWD
Group A
subgroups
Device
type
Limits
Min
9,10,11
01
60
02
50
03
40
01
10
02,03
5
01
25
CAS high ( CAS - before-
02
20
RAS refresh only)
03
20
01
120
02
100
03
80
Delay time, column
address to W low
(Read – write
operation only)
Delay time,
tCRP
See figures 4 and 5
1/
9,10,11
CAS high to RAS low
Delay time, RAS low to
Delay time,
tCHR
9,10,11
tCSH
9,10,11
RAS low to CAS high
Delay time,
Unit
Max
ns
ns
ns
ns
tCSR
9,10,11
All
10
ns
tCWD
9,10,11
01
30
ns
02
25
03
20
01
20
65
02
20
50
03
15
40
01
55
02
50
03
40
01
55
02
50
03
40
CAS low to RAS low ( CAS -
before- RAS refresh only)
Delay time,
CAS low to W low
(Read-write operation only)
tRAD
Delay time,
9,10,11
RAS low to columnaddress 10/
Delay time, column-
tRAL
9,10,11
address to RAS high
Delay time, column-
tCAL
9,10,11
address to CAS high
ns
ns
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
subgroups
tRCD
Delay time,
01
25
90
02
25
75
03
20
60
01
30
02
25
03
20
9,10,11
All
0
ns
9,10,11
01
120
ns
02
100
03
80
9,10,11
CAS low to RAS
high
Delay time,
tRPC
See figures 4 and 5
1/
Unit
Max
9,10,11
tRSH
Limits
Min
RAS low to CAS low
10/
Delay time,
Device
type
ns
ns
RAS high to CAS
low
Delay time,
tRWD
RAS low to W low
(Read-write operation
only)
tCLZ
9,10,11
All
See 11/
ns
tREF
9,10,11
All
16
ms
CAS to output in low Z
Refresh time interval
1/
Transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 50 ns.
2/
3/
tOFF is specified when the output is no longer driven. The output is disabled when CAS is brought high.
All cycle times assume tT = 5 ns.
4/
To assure tPC minimum, tASC should be greater than or equal to tCP.
5/
In a read-write cycle, tRWD and tRWL must be observed.
6/
In a read-write cycle, tCWD and tCWL must be observed.
7/
Referenced to the later of CAS or W in write operations.
8/
The minimum value is measured when tRCD is set to tRCD minimum as a reference.
9/
Either tRRH or tRCH must be satisfied for a read cycle.
10/
Maximum value specified only to guarantee access time.
11/
Valid data is presented at the output after all access times are satisfied but may go from three-state to an invalid data state
prior to the specified access times as the outputs are driven when CAS goes low.
STANDARD
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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/
Line
No.
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Test
requirements
Subgroups
(in accordance with
MIL-PRF-38535,
method 5005, table III)
Device
class M
1/
2/
3/
4/
5/
6/
Device
class Q
Device
class V
1,7,9
or 2,8A,10
1,7,9
or 2,8A,10
Not
required
Required
1
Interim electrical
parameters (see 4.2)
2
Static burn-in I and II
(method 1015)
3
Same as line 1
4
Dynamic burn-in
(method 1015)
5
Same as line 1
6
Final electrical
parameters
1*,2,3,7*,
8A,8B,9,10,11
1*,2,3,7*,
8A,8B,9,10,11
1*,2,3,7*,
8A,8B,9,10,11
7
Group A test
requirements
1,2,3,4**,5,6,7,
8A,8B,9,10,11
1,2,3,4**,5,6,7,
8A,8B,9,10,11
1,2,3,4**,5,6,7,
8A,8B,9,10,11
8
Group C end-point
electrical parameters
2,3,7,
8A,8B
1,2,3,7,
8A,8B Δ
1,2,3,7,
8A,8B,9,10,11 Δ
9
Group D end-point
electrical parameters
2,3,8A,8B
2,3,8A,8B
2,3,8A,8B
10
Group E end-point
electrical parameters
1,7,9
1,7,9
1,7,9
Not
required
1*,7* Δ
Required
Required
Required
1*,7*
Δ
Blank spaces indicate tests are not applicable.
Any or all subgroups may be combined when using high-speed testers.
Subgroups 7 and 8 functional tests shall verify the truth table.
* indicates PDA applies to subgroup 1 and 7.
** see 4.4.1e.
Δ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be
computed with reference to the previous electrical parameters (see table IIB).
TABLE IIB. Delta limits at +25°C.
Parameter 1/
Device types
All
ICC2 standby
±10% of specified value in table I
II , IO
±10% of specified value in table I
1/ The above parameter shall be recorded before and after
the required burn-in and life tests to determine the delta.
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Case X
Inches
.003
.005
.007
.010
.015
.016
.018
mm
.08
.13
.18
.25
.38
.41
.46
Inches
.030
.050
.090
.117
.355
.490
.700
mm
0.76
1.27
2.29
2.97
9.02
12.45
17.78
20 Pin flat pack
FIGURE 1. Case outlines.
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Case Y
Inches
.006
.010
.022
.028
.040
.050
.060`
.068
.070
mm
0.15
0.25
0.56
0.71
1.02
1.27
1.52
1.72
1.78
Inches
.080
.100
.105
.125
.393
.407
.590
.610
.690
.710
mm
2.03
2.54
2.68
3.18
9.98
10.34
14.98
15.49
17.52
18.03
20 Pin, small-outline leadless ceramic chip carrier
FIGURE 1. Case outlines – continued.
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Case Z
Inches
.006
.013
.016
.023
.025
.035
.045
.055
.063
.078
mm
0.15
0.33
0.41
0.58
0.63
0.89
1.14
1.40
1.60
1.98
Inches
.130
.160
.318
.340
.370
.592
.608
.665
.685
mm
3.30
4.06
8.08
8.64
9.40
15.04
15.44
16.89
17.40
20/26 Pin, ceramic small-outline, j-leaded chip carrier, 350 mil
FIGURE 1. Case outlines - continued.
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Case U
Inches
.006
.010
.022
.025
.028
.035
.045
.050
.055
.060
mm
0.15
0.25
0.56
0.64
0.71
0.89
1.14
1.27
1.40
1.52
Inches
.080
.100
.343
.357
.590
.610
.665
.585
mm
2.03
2.54
8.71
9.06
14.98
15.49
16.89
17.40
20-Pin, (350 mil) small-outline, leadless ceramic chip carrier
FIGURE 1. Case outlines - continued.
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Case T
Inches
.003
.010
.011
.015
.018
.045
.060
.065
.070
.100
mm
0.08
0.25
0.28
0.38
0.46
1.14
1.52
1.65
1.78
2.54
Inches
.125
.175
.200
.380
.385
.410
.420
.800
.880
.930
mm
3.18
4.44
5.08
9.65
9.78
10.41
10.68
20.32
22.35
23.62
18-Pin, ceramic side brazed, dual-in-line package
FIGURE 1. Case outlines - continued.
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Case N
Inches
.008
.012
.016
.025
.020
.035
.045
.055
.090
mm
0.20
0.30
0.41
0.64
0.51
0.89
1.14
1.40
2.29
Inches
.102
.110
.122
.125
.175
.385
.405
1.040
1.060
mm
2.59
2.79
3.10
3.18
4.45
9.78
10.29
26.42
26.92
FIGURE 1. Case outlines - continued.
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Case M
Inches
.004
.006
.010
.015
.019
.027
.033
.045
.055
.097
.117
mm
0.10
0.15
0.25
0.38
0.48
0.69
0.84
1.14
1.40
2.46
2.97
Inches
.127
.290
.310
.324
.336
.405
.415
.435
.455
.692
.708
mm
3.23
7.37
7.87
8.23
8.53
10.29
10.54
11.05
11.56
17.58
17.98
20 Pin flat pack.
FIGURE 1. Case outlines - continued.
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Device
types
Case
outlines
Terminal
number
1
01, 02, 03
T, V
X, M
Y, U, Z
N
Terminal Symbol
D
D
D
A9
2
W
W
W
CAS
3
RAS
RAS
RAS
Q
4
5
6
A10
A0
A1
NC
A10
A0
NC
A10
---
VSS
D
7
A2
A1
---
RAS
8
9
10
11
12
13
14
15
A3
VCC
A4
A5
A6
A7
A8
A9
A2
A3
VCC
A4
A5
A6
A7
A8
--A0
A1
A2
A3
VCC
A4
A5
A10
NC
NC
A0
A1
A2
A3
VCC
16
CAS
A9
A6
A4
17
Q
NC
A7
A5
18
VSS
CAS
A8
A6
19
20
21
22
23
-----------
Q
VSS
-------
------A9
NC
A7
A8
-------
24
---
---
CAS
---
25
26
-----
-----
Q
VSS
-----
W
FIGURE 2. Terminal connections.
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Inputs
Operation
Input
Output
RAS
CAS
W
Row
address
Column
address
D
Q
Read
ACT
ACT
NAC
APD
APD
DNC
VLD
Write (early write)
ACT
ACT
ACT
APD
APD
VLD
OPN
Write (late write)
ACT
ACT
ACT
APD
APD
VLD
ILD 1/
Read-modify-write
ACT
ACT
ACT
APD
APD
VLD
VLC
RAS – only refresh
ACT
NAC
DNC
APD 2/
DNC
DNC
OPN
Hidden refresh
ACT
ACT
NAC
APD
DNC
DNC
VLD
CAS before RAS refresh
ACT
ACT
NAC
DNC
DNC
DNC
OPN
Standby
NAC
NAC
DNC
DNC
DNC
DNC
OPN
1/
Output may go from high impedance to an invalid data state prior to the specified
2/
access time as the output is driven when CAS goes low.
A10 is a don't care.
ACT = active
NAC = nonactive
DNC = don't care
VLD = valid
ILD = invalid
APD = applied
OPN = open
FIGURE 3. Truth table.
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FIGURE 4. Load circuits.
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Read cycle timing
NOTE: Output may go from three-state to an invalid state prior to the specified access time.
FIGURE 5. Timing waveform diagrams.
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Early write cycle timing
FIGURE 5. Timing wave diagrams - continued.
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Write cycle timing
FIGURE 5. Timing wave diagrams - continued.
STANDARD
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Read-write cycle timing
NOTE: Output may go from three-state to an invalid state prior to the specified access time.
FIGURE 5. Timing wave diagrams - continued.
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Enhanced page-mode read cycle timing
NOTES:
1. Output may go from three-state to an invalid state prior to the specified access time.
2. Access time is tCPA or tAA dependent.
FIGURE 5. Timing wave diagrams - continued.
STANDARD
MICROCIRCUIT DRAWING
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Enhanced page-mode write cycle timing
NOTES:
1. tDS and tDH are referenced to CAS or W , whichever occurs last.
2. A read cycle or a read-write cycle can be intermixed with write write cycle as long as the read and read-write
timing specification are not violated.
FIGURE 5. Timing wave diagrams - continued.
STANDARD
MICROCIRCUIT DRAWING
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Enhanced page-mode read-write cycle timing
NOTES:
1. Output may go from three-state to an invalid state prior to the specified access time.
2. A read or read-write cycle can be intermixed with read-write cycles as long as the read and write
timing specification are not violated.
FIGURE 5. Timing wave diagrams - continued.
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RAS - only refresh timing
NOTE: A10 is a don't care.
FIGURE 5. Timing wave diagrams - continued.
STANDARD
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Automatic ( CAS -before- RAS ) refresh cycle timing
FIGURE 5. Timing wave diagrams - continued.
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Hidden refresh cycle (read)
FIGURE 5. Timing wave diagrams - continued.
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Hidden refresh cycle (write)
FIGURE 5. Timing wave diagrams - continued.
STANDARD
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35
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table IIA herein.
4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after life test perform final electrical parameter tests, subgroups 1, 7, and
9.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
E
SHEET
36
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331 and herein:
CIN and COUT .......................... Input and bidirectional output, terminal-to-GND capacitance.
GND ....................................... Ground zero voltage potential.
ICC .......................................... Supply current.
IIL ............................................ Input current low.
IIH ........................................... Input current high.
TC ........................................... Case temperature.
TA ........................................... Ambient temperature.
VCC ......................................... Positive supply voltage.
VIC .......................................... Positive input clamp voltage
O/V ......................................... Latch-up over-voltage
O/I .......................................... Latch-up over-current
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the
system must supply at least that much time (even though most devices do not require it). On the other hand, responses from
the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never
provides data later than that time.
6.5.2 Waveforms.
WAVEFORM
SYMBOL
INPUT
OUTPUT
MUST BE VALID
WILL BE VALID
CHANGE FROM
H TO L
WILL CHANGE FROM
H TO L
CHANGE FROM
L TO H
WILL CHANGE FROM
L TO H
DON'T CARE ANY
CHANGE
PERMITTED
CHANGING STATE
UNKNOWN
HIGH IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535
and MIL-HDBK-103. The vendors listed in QML-38535 and MIL-HDBK-103 have submitted a certificate of compliance (see 3.6
herein) to DLA Land and Maritime-VA and have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MILHDBK-103 . The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6
herein) has been submitted to and accepted by DLA Land and Maritime-VA.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
E
SHEET
37
APPENDIX A
FUNCTIONAL ALGORITHMS
A.1 SCOPE
A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper
operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is
understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each
manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be
used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be
applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information
contained herein is intended for compliance.
A.2 APPLICABLE DOCUMENTS
This section is not applicable to this appendix.
A.3 ALGORITHMS
A.3.1 Algorithm A (pattern 1).
A.3.1.1 Output high impedance (tOFF). This pattern verifies the output buffer switches to high impedence (three-state) within
the specified tOFF after the rise of CAS . It is performed in the following manner:
Step 1: Perform 8 pump cycles.
Step 2: Load address location with data.
Step 3: Raise CAS and read address location and guarantee VOL < VOUT < VOH after tOFF delay.
A.3.2 Algorithm B (pattern 2).
A.3.2.1 Vcc Slew. This pattern indicates sense amplifier margin by slewing the supply voltage between memory writing and
reading. It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Step 6:
Step 7:
Perform 8 pump cycles.
Load memory with background data with Vcc at 5.0 V.
Change Vcc to 5.5 V.
Read memory with background data.
Load memory with background data complement.
Change Vcc to 4.5 V.
Read memory with background data complement.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
E
SHEET
38
APPENDIX A – continued.
FUNCTIONAL ALGORITHMS
A.3.3 Algorithm C (pattern 3).
A.3.3.1 March data. This pattern tests for address uniqueness and multiple selections. It is performed in the following
manner:
Step 1: Perform 8 pump cycles.
Step 2: Load memory with background data.
Step 3: Read location 0.
Step 4: Write data complement in location 0.
Step 5: Repeat step 3 and 4 for all other locations in the memory (sequentially).
Step 6: Read data complement in maximum address location.
Step 7: Write data in maximum address location.
Step 8: Repeat step 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 9: Read data in maximum address location.
Step 10: Write data complement in maximum address location.
Step 11: Repeat step 6 and 7 for all other locations in the memory from maximum to minimum address.
Step 12: Read memory with data complement.
A.3.4 Algorithm D (pattern 4).
A.3.4.1 Refresh test (cell retention) +125°C only. This test is used to check the retention time of the memory cells. It is
performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load memory with background data.
Pause TREF (stop all clocks).
Read memory with background data.
Repeat steps 2-4 with data complement.
A.3.5 Algorithm E (pattern 5).
A.3.5.1 Read-modify-write (RMW). This pattern verifies the Read-modify-write mode for the memory. It is performed in the
following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load memory with background data.
Read memory with data and load with data complement using RMW cycle.
Repeat step 3 for all address locations.
Repeat steps 2 and 3 using data complement.
A.3.6 Algorithm F (pattern 6).
A.3.6.1 Page mode. This pattern verifies the Page mode for the memory. It is performed in the following manner:
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Perform 8 pump cycles.
Load first page of memory with background data using Page mode cycle.
Read first page of memory with data and load with data complement using Page mode cycle.
Read first page of memory with data complement and load with data using Page mode cycle.
Repeat steps 2-4 for remaining memory locations.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
E
SHEET
39
APPENDIX A – continued.
FUNCTIONAL ALGORITHMS
A.3.7 Algorithm G (pattern 7).
A.3.7.1 CAS -Before- RAS refresh test. This test is used to verify the functionality of the CAS before RAS mode of cell
refreshing. It is done at +125°C only and is performed in the following manner:
Step 1: Perform 8 pump cycles.
Step 2: Load memory with background data.
Step 3: Perform 1024 CAS -before- RAS cycles while attempting to modify data.
Step 4: Read memory with background data.
A.3.8 Algorithm H (pattern 8).
A.3.8.1 RAS -Only refresh test. This test is used to verify the functionality of the RAS -only mode of cell refreshing. It is done
at +125°C only and is performed in the following manner:
Step 1: Perform 8 pump cycles.
Step 2: Load memory with background data.
Step 3: Perform 1024 RAS -only cycles while attempting to modify data.
Step 4: Repeat step 3 for 1 second.
Step 5: Read memory with background data.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90622
A
REVISION LEVEL
E
SHEET
40
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 15-11-16
Approved sources of supply for SMD 5962-90622 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit
drawing PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9062201MXA
3/
SMJ44100-12HR
3/
MT4C1004JEC-12
SMJ44100-12HM
3/
SMJ44100-12HJ
3/
MT4C1004JECN-12
SMJ44100-12HL
3/
MT4C1004JC-12
SMJ44100-12JD
5962-9062201MYA
5962-9062201MZA
5962-9062201MUA
5962-9062201MTA
5962-9062201MVA
57300
5962-9062201MMA
3/
MT4C1004JF-12
5962-9062201MNA
3/
MT4C1004JCZ-12
5962-9062202MXA
3/
SMJ44100-12HR
3/
MT4C1004JEC-10
SMJ44100-12HM
3/
SMJ44100-12HJ
3/
MT4C1004JECN-10
SMJ44100-10HL
5962-9062202MTA
3/
MT4C1004JC-10
SMJ44100-10JD
5962-9062202MVA
57300
5962-9062202MMA
3/
MT4C1004JF-10
5962-9062202MNA
3/
MT4C1004JCZ-10
5962-9062203MXA
3/
SMJ44100-80HR
5962-9062203MYA
3/
3/
MT4C1004JEC-8
SMJ44100-80HM
5962-9062203MZA
3/
SMJ44100-80HJ
5962-9062203MUA
3/
3/
MT4C1004JECN-8
SMJ44100-80HL
5962-9062203MTA
3/
3/
MT4C1004JC-8
SMJ44100-80JD
5962-9062203MVA
57300
MT4C1004JCN-8
5962-9062203MMA
3/
MT4C1004JCZ-8
5962-9062203MNA
3/
MT4C1004JF-8
5962-9062202MYA
5962-9062202MZA
5962-9062202MUA
See footnotes at end of table.
1 of 2
MT4C1004JCN-12
MT4C1004JCN-10
STANDARD MICROCIRCUIT DRAWING BULLETIN – continued.
DATE: 15-11-16
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that part.
If the desired lead finish is not listed contact the vendor to determine
its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired to
this number may not satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
Vendor name
and address
57300
Micross Components.
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
2 of 2