20160329113254143

APA2622
15W Stereo Class-D Audio Power Amplifier
Features
General Description
•
•
The APA2622 is a stereo, high efficiency, Class-D audio
•
•
Supply Voltage is 4.5V ~ 26V
Class D operation eliminates heat sink & reduce
power supply requirement
20,26, 32, 36, 4 steps gain setting
15W/ch into an 8Ω Stereo Loads at 10% THD+N
•
from a 16-V supply
10W/ch into an 8Ω Stereo Loads at 10% THD+N
•
from a 12-V supply
30W into a 4Ω Mono Load at 10% THD+N from a 16-
•
V supply
90% Efficient Class-D Operation Eliminates Need
•
•
•
•
amplifier and is available in TSSOP-28P and QFN4x428B pins packages.
The Class-D power amplifier has higher efficiency compared to the traditional Class-AB power amplifier. The
filter free Class-D architecture eliminates the external low
pass filters. The internal gain setting can minimize the
external component counts, and for the flexible application the gain can be set to 4-step 20, 26, 32, 36dB by gain
control pins (GAIN0 and GAIN1). The AGC function pro-
for Heat Sinks
External AGC function
tects speaker from being out of its power rating but keeps
acceptable performance.
Thermal and Over-Current Protections with AutoRecovery option
The integration of Class-D power amplifier is a best so-
TSSOP-28P with thermal pad packages
QFN4x4-28B with thermal pad packages
lution for high efficiency and low BOM costs. The operating voltage is from 4.5V to 26V. The APA2622 power amplifiers are capable of driving 15 W at VDD=16V into 8Ω
speaker, and provides thermal and over-current
Applications
•
•
•
protections. It also can detect the DC and then prevent
the speaker voice coil from being detroyed.
LCD Monitor
LCD TV
Consumer Audio Equipment
Simplified Application Circuit
APA2622
LOUTP
Left
Channel
Input
Right
Channel
Input
LINP
LINN
RINN
FERRITE
BEAD
FILTER
Left
Channel
Speaker
FERRITE
BEAD
FILTER
Right
Channel
Speaker
LOUTN
ROUTN
RINP
ROUTP
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
1
www.anpec.com.tw
APA2622
26 LBSP
LINN 4
25 LOUTP
LOUTP 1
GAIN0 5
24 PGND
LBSP 2
GAIN1 6
23 LOUTN
AVDD 7
AGND 8
APA2622
TSSOP-28P
22 PGND
23 ROUTN
24 RBSN
25 NC
27 LPVDD
LINP 3
26 LBSN
28 LPVDD
28 PGND
SD 1
FLAG 2
27 LOUTN
Pin Configuration
21 ROUTP
20 RBSP
LPVDD 3
22 LBSN
SD 4
19 RPVDD
APA2622
QFN4*4-28B
18 MONO
15 RINN
RINN 11
18 ROUTP
17 RBSP
16 RPVDD
MONO 14
15 RPVDD
17 FREQ
AGC 14
RINP 12
FREQ 13
VCLAMP 13
LINN 7
AGND 12
19 PGND
AVDD 11
16 RINP
AGC 10
GAIN1 10
LINP 6
NC 8
FLAG 5
GAIN0 9
21 RBSP
20 ROUTN
VCLAMP 9
Ordering and Marking Information
Package Code
R: TSSOP-28P QA: QFN4x4-28B
Operating Ambient Temperature Range
I : -40 to 85 o C
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APA2622
Assembly Material
Handling Code
Temperature Range
Package Code
APA2622 R:
APA2622 QA:
APA2622
XXXXX
XXXXX - Date Code
APA2622
XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
2
www.anpec.com.tw
APA2622
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol
VD D
Para mete r
Rat ing
Supp ly Voltage
-0 .3 to 30
Inp ut Voltage (/SD, GA IN0 and GAIN1, MONO and /FLA G,
FREQ)
VI
TJ
-0.3 to V DD+0 .3
AGC
-0.3 to 6 .3
LINP, LINN, RINP, RINN
-0.3 to 6 .3
Ma ximum Junction Temp erature
Stor age Tem perature Range
T SDR
Ma ximum So lderin g Temper atu re Ra nge, 10 se co nds
2 60
PVDD > 15V
4.8
PVDD < 1 5V
3.2
MONO mo de
3.2
PD
V
1 50
T STG
RL
Unit
-65 to +1 50
Power Dissipa tio n
ο
C
Ω
Intern ally Limite d
W
Notes 1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Thermal Resistance -Junction to Ambient
Typical Value
Unit
(Not e 2)
TSSOP-28P
QFN4x4-28
45
40
TSSOP-28P
QFN4x4-28
8
7
Thermal Resistance -Junction to Case(Note 3)
ο
C /W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TSSOP-28P is soldered directly on the PCB
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TSSOP-28P package
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
3
www.anpec.com.tw
APA2622
Recommended Operating Conditions
Symbol
V DD
VIH
VIL
Parameter
Min.
Max.
4.5
26
2.0
-
-
0 .8
Supply Volta ge
High Le ve l Thre sh old
Voltage
Lo w Level Thresho ld
Voltage
/SD ,GAIN0, GA IN1, MONO,
FREQ
/SD, GAIN0, GA IN1, MONO ,
FREQ
Unit
V
ο
TA
Am bient Tempe rature Range
-40
85
C
TJ
Junction Temperature Rang e
-40
12 5
RL
Spe aker Re sistance,P VDD<9V
3.5
-
ο
C
Ω
Electrical Characteristics
VDD=12V, GND=0V, AV=20dB, TA= 25oC(unless otherwise noted)
Sym bol
Param eter
Tes t Condition
Min.
Typ.
Max.
Unit
4.5
5
5.5
V
Regula te d vol tag e
I O=2mA,VD D=6 ~24 V,TJ=-40 οC
~125ο C
Maxi mum Output Voltage
Under AGC Control
VAGC=1V, A V=20d B
-
5.6
-
Vp
t DCD ET
DCP de te ct time
VR IN P=5V,V RINN=0V
-
500
-
ms
T SD(ON)
Shu tdo wn Turn-O n Time
/SD=2 .2V
-
16
-
ms
T SD(OFF)
Shu tdo wn Turn-O ff Time
/SD=0 .8V
-
2
-
μs
I DD
Quie scen t Su pply Cu rrent
No Loa d
-
17
35
mA
I SD
Quie scen t Su pply Cu rrent
in shutd own mode
/SD = 0V
-
180
300
μA
In put Cu rrent
/SD, G AIN0, GAIN1, FREQ
MONO=12V
-
34
50
μA
FREQ=High, fixed frequ ency
-
300
-
kHz
I L=0.5 A
-
200
-
mΩ
Ga in0=0, G ain1 =0
-
20
-
Ga in0=1, G ain1 =0
-
26
-
Ga in0=0, G ain1 =1
-
32
-
Ga in0=1, G ain1 =1
-
36
-
V CLAMP
VO
II
FOSC
R DSON
AV
In te rnal Oscillator
Freque ncy
Static Dra in-S ource
On-State Re sistance
Ga in
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
4
dB
www.anpec.com.tw
APA2622
STEREO MODE
VDD=12V, GND=0V, AV=20dB, TA= 25oC(unless otherwise noted).
ο
VD D=1 6V, TA=25 C, AV=20dB
Sym bol
Po
Parameter
Output Power
Test Condition
VDD =16 V
THD+N = 1%, F IN = 1KHz,
VDD =16 V
THD+N = 1 0%, F IN = 1kHz
THD+N
Crossta lk
PSRR
SNR
A tt shu tdo wn
|V OS|
Vn
Min.
Typ.
Max .
R L = 8Ω
-
14
-
R L = 8Ω
-
17
-
Unit
W
Total Harmon ic
Distortion Pul se Noise
VDD =16 V
FIN = 1kHz, PO = 7.5W , R L = 8Ω
-
0 .0 6
-
Cha nnel sepa ration
VO =1V rms, FIN = 1kHz, AV=20dB
-
-90
-
Power Supp ly
Reje ctio n Ratio
RL =4Ω ,input AC-Gro und, FIN=1kHz
-
-70
-
Signal -to -noise ratio
Ma xim um o utp ut at THD+N<1%,
FREQ= High
FIN=1 kHz, A V=20d B, A-weighted
-
95
-
Shutdown Attenuatio n
FIN = 1kHz, R L = 8Ω, V in= 1 VPP
-
-1 10
-
Offset Volta ge
AV=20dB
-
5
-
mV
Noise Outp ut Vo lta ge
In put A C gr ound with A-weigh te d Filter
(AV=20dB), FREQ=High
-
120
-
µV (rms)
Test Condition
Min.
Typ.
Max .
Unit
R L = 8Ω
-
8
-
R L = 8Ω
-
10
-
%
dB
ο
VD D=1 2V, TA=25 C, AV=20dB
Sym bol
Po
THD+N
Crossta lk
PSRR
Parameter
Output Power
VDD =12 V
THD+N = 1%, F IN = 1KHz
VDD =12 V
THD+N = 1 0%, F IN =
1kHz,
W
Total Harmon ic
Distortion Pul se Noise
VDD =12 V
FIN = 1kHz, PO = 5W, RL = 4Ω
-
0 .0 5
Cha nnel sepa ration
VO =1V rms, FIN = 1kHz, AV=20dB
-
-90
-
Power Supp ly
Reje ctio n Ratio
RL =4Ω ,input AC-Gro und, FIN=1kHz
-
-70
-
Signal -to -noise ratio
Ma xim um o utp ut at THD+N<1%,
FREQ= High
FIN=1 kHz, A V=20d B, A-weighted
-
95
-
Shutdown Attenuatio n
FIN = 1kHz, R L = 8Ω, V in= 1 VPP
-
-1 10
-
Offset Volta ge
AV=20dB
-
5
-
mV
Noise Outp ut Vo lta ge
In put A C gr ound , FRE Q= High
With A -we ighted Filter (AV=20dB)
-
120
-
µV (rms)
-
%
dB
SNR
A tt shu tdo wn
|V OS|
Vn
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
5
www.anpec.com.tw
APA2622
MONO MODE
ο
VDD=12 V,TA=25 C
S ymbol
Po
THD+N
P SRR
SNR
Att shutdown
|VOS|
Vn
Pa ra met er
Total Harmonic
Disto rtio n Pulse Noise
Te st Condition
V DD=16V
R L = 4Ω
THD+N = 1% , F IN = 1 KHz
V DD=16V
R L = 4Ω
THD+N = 10%, F IN = 1KHz
V DD=16V
F IN = 1kHz, PO = 6W, R L = 4Ω
Po we r Suppl y
Rejection Ratio
R L=4Ω ,in put AC-G round , F IN =1kHz
Ou tp ut Po we r
Min.
Typ.
Ma x.
-
28
-
-
35
-
-
0.05
-
-5 0
-
Unit
W
-
%
-
95
-
Sh utdown Atte nuation
Ma ximum ou tpu t at THD+N<1%,
FREQ =High
FIN=1kHz, AV=20dB, A- we ighted
F IN = 1kHz, R L = 8Ω, Vi n= 1V rms
-
-100
-
Offse t Vo ltag e
A V=2 0dB
-
10
-
mV
Noise Outpu t Voltag e
Inp ut AC gro und, FREQ=High
W ith A-weig hted Filter (AV=20dB )
-
1 20
-
µV (rms)
Si gnal-to- noise ratio
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
6
dB
www.anpec.com.tw
APA2622
Typical Operating Characteristics
THD+N vs. Output Power
THD+N vs. Output Power
10
10
1
1
THD+N (%)
THD+N (%)
VDD=12V
0.1
0.01
0
5
10
15
VDD=24V
0.1
FIN=1kHz
RL=4Ω
Av=20dB
AES-17(20kHz)
VDD=12V
VDD=8V
VDD=19V
25
20
30
FIN=1kHz
RL=8Ω
Av=20dB
AES-17(20kHz)
VDD=8V
0.01
35
0
10
Output Power (W)
20
30
40
Output Power (W)
THD+N vs. Output Power
10
10
THD+N vs. Frequency
VDD=12V
RL=8Ω
Av=20dB
AES-17(20kHz)
0.1
MONO Mode
FIN=1kHz
RL=4Ω
Av=20dB
AES-17(20kHz)
VDD=12V
VDD=8V
0.01
0
1
VDD=16V
THD+N (%)
THD+N (%)
1
10
20
30
Po=5W
0.1
0.01
20
40
Po=2.5W
100
Output Power (W)
10
THD+N vs. Frequency
10
VDD=24V
RL=8Ω
Av=20dB
AES-17(20kHz)
1
THD+N (%)
THD+N (%)
1
Po=18W
0.1
1k
10k 20k
Frequency (Hz)
Po=9W
THD+N vs. Frequency
MONO Mode
VDD=12V
RL=4Ω
Av=20dB
AES-17(20kHz)
Po=10W
0.1
Po=5W
PO=2W
0.01
20
100
1k
0.01
20
10k 20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
100
1k
10k 20k
Frequency (Hz)
7
www.anpec.com.tw
APA2622
Typical Operating Characteristics (Cont.)
10
-40
MONO Mode
VDD=16V
RL=4Ω
Av=20dB
AES-17(20kHz)
VDD=12V
RL=8Ω
VO=1Vrms
AV=20dB
AES-17(20kHz)
-60
Crosstalk(dB)
1
THD+N (%)
Crosstalk vs. Frequency
THD+N vs. Frequency
Po=15W
Po=8W
0.1
-80
L-Channel to R-Channel
-100
R-Channel to L-Channel
0.01
20
100
1k
10k 20k
20
100
Frequency (Hz)
1k
10k 20k
Frequency (Hz)
Crosstalk vs. Frequency
Output Noise Voltage vs. Time
-40
VDD=24V
RL=8Ω
VO=1Vrms
AV=20dB
AES-17(20kHz)
Output Noise Voltage(Vrms)
Crosstalk(dB)
-60
VDD=24V
RL=8Ω
Cin=1µF
AES-17(20kHz)
A-Weighting
400µ
300µ
-80
AV=36dB
200µ
L-Channel to R-Channel
-100
AV=20dB
100µ
R-Channel to L-Channel
20
100
1k
0
10k 20k
10
Output Noise Voltage(Vrms)
Power Supply Rejection Ratio(dB)
MONO Mode
VDD=16V
RL=8Ω
Cin=1µF
AES-17(20kHz)
A-Weighting
300µ
AV=36dB
200µ
AV=20dB
100µ
0
10
30
PSRR vs. Frequency
Output Noise Voltage vs. Time
400µ
20
Time (Sec)
Frequency (Hz)
20
-30
VDD=12V
RL=8Ω
Av=20dB
Vrr=0.2Vpp
AES-17(20kHz)
-50
Left channel
-70
Right channel
-90
20
30
Time (Sec)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
-10
100
1k
10k 20k
Frequency (Hz)
8
www.anpec.com.tw
APA2622
Typical Operating Characteristics (Cont.)
Frequency Response
+28
MONO Mode
VDD=12V
RL=8Ω
Av=20dB
Vrr=0.2Vpp
AES-17(20kHz)
-10
+150
Av=26dB
+24
+100
Av=20dB
+22
Gain(dB)
-30
+200
+26
-50
+50
+20
+0
+18
Phase
+14
-70
+10
100
1k
20
10k 20k
100
Frequency (Hz)
+200
+36
+150
Gain(dB)
Phase
-50
+26
+22
+20
-100
VDD=12V
RL=8Ω
AES-17(20kHz)
20
100
Phase(Deg)
+50
Av=32dB
+0
+24
Shutdown Attenuation(dB)
+100
+32
+28
Right channel
Left channel
-150
1k
Frequency (Hz)
20k
-120
-200
200k
20
10
8
8
Output Power(W)
10
6
4
VDD=12V
RL=8Ω
Av=20dB
AES-17(20kHz)
2
2.0
3.0
4.0
1k
10k 20k
Frequency (Hz)
6
4
VDD=24V
RL=8Ω
Av=20dB
AES-17(20kHz)
2
0
5.0
VAGC (V)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
100
Output Power vs. AGC Voltage
12
1.0
200k
-100
Output Power vs. AGC Voltage
0
-200
20k
-80
12
0
1k
Frequency (Hz)
VDD=12V
RL=8Ω
Av=20dB
AES-17(20kHz)
-60
Av=36dB
+30
-150
Shutdown Attenuation vs. Frequency
Frequency Response
+38
+34
-100
VDD=12V
RL=8Ω
AES-17(20kHz)
+12
-90
20
Output Power(W)
-50
+16
Phase(Deg)
Power Supply Rejection Ratio(dB)
PSRR vs. Frequency
0
1.0
2.0
3.0
4.0
5.0
VAGC (V)
9
www.anpec.com.tw
APA2622
Typical Operating Characteristics (Cont.)
Shutdown Current vs. Supply Voltage
Supply Current vs. Supply Voltage
250
30
NO Load
200
Shutdown Current(µA)
Supply Current(mA)
25
20
15
10
150
100
50
5
NO Load
0
0
0
0
5
10
15
25
20
30
10
5
AGC Function Output Power vs.
Input AC
2
15
25
20
30
Supply Voltage(V)
Supply Voltage(V)
AGC Function Output Power vs.
Input AC
8
1.6
Output Power (W)
Output Power (W)
6
1.2
0.8
VDD=12V
RL=8Ω
Av=20dB
VAGC=1V
AES-17(20kHz)
0.4
0
0
0.4
0.8
1.2
1.6
4
VDD=24V
RL=8Ω
Av=20dB
VAGC=2V
AES-17(20kHz)
2
0
2
0.4
0
Input Voltage (Vrms)
Efficiency vs. Output Power
2
1.6
100
90
90
80
VDD =12 V
VDD =24V
80
VDD =16 V
70
VDD =12V
70
Efficiency(%)
Efficiency(%)
1.2
Efficiency vs. Output Power
100
60
50
40
R L=4 Ω+33µH
fin=1kHz
Av=20 dB
AES- 17(20kHz)
Stereo mode
30
20
10
0
0.8
Input Voltage (Vrms)
0
10
20
Output Power(W)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
60
50
40
R L=4 Ω+33µH
fin=1kHz
Av=20 dB
AES- 17(20kHz)
Stereo mode
30
20
10
0
30
10
0
10
20
Output Power(W)
30
www.anpec.com.tw
APA2622
Typical Operating Characteristics (Cont.)
EN55013 Radiated Emissions Results
Radiated Emission - Horizontal
VDD =12 V(Battery supply)
R L=8 Ω+33µΗ
PO =1.25W
30cm Speaker cable
EN55013 Radiated Emissions Results
Radiated Emission - Vertical
VDD =12 V(Battery supply)
R L=8 Ω+33µΗ
PO =1.25W
30cm Speaker cable
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
11
www.anpec.com.tw
APA2622
Typical Operating Characteristics (Cont.)
EN55013 Radiated Emissions Results
Radiated Emission - Horizontal
VDD =12 V(Battery supply)
R L=8 Ω+33µΗ
PO =8W
30cm Speaker cable
EN55013 Radiated Emissions Results
Radiated Emission - Vertical
VDD =12 V(Battery supply)
R L=8 Ω+33µΗ
PO =8W
30cm Speaker cable
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
12
www.anpec.com.tw
APA2622
Pin Function Description
Pin
NO.
TSSOPQFN4x4
28P
-28B
Name
I/O/P
FUNCTION
1
4
/SD
I
2
5
/FLAG
O
3
6
LINP
I
Shutdown logic input for audio amp (Low=outputs disabled, High=output enabled).
TTL logic levels with compliance to AVDD.
Open drain output used to display short circuit or dc detect fault status. Voltage
compliant to AVDD. Short circuit faults can be set to auto-recovery by connecting
/FLAG pin to /SD pin. Otherwise, both short circuit faults and dc detect faults must
be reset by cycling PVDD.
Positive audio input for left channel.
4
7
LINN
I
Negative audio input for left channel.
5
9
GAIN0
I
Gain select least significant bit. TTL logic levels with compliance to AVDD.
6
10
GAIN1
I
Gain select least significant bit. TTL logic levels with compliance to AVDD.
7
11
AVDD
P
Analog supply.
8
12
P
Analog signal ground. Connect to the thermal pad.
9
13
AGND
VCLAM
P
I
Regulated voltage, Nominal voltage is 5V.
10
14
AGC
I
AGC level adjust. Connect a resistor divider from VCLAMP to GND to set AGC.
Connect directly to VCLAMP for no AGC.
11
15
RINN
I
Negative audio input for right channel.
12
16
RINP
I
Positive audio input for right channel.
-
8,25
NC
13
17
FREQ
I
FOSC selection control, pulling and holding this pin to logic high selects fixed
frequency mode while logic low selects spread spectrum mode.
14
18
MONO
I
Parallel BTL mode switch
15,16
19
RPVDD
P
Power supply for right channel H-bridge. Right channel and left channel power
supply inputs are connected internally.
17
20
RBSP
I
Bootstrap I/O for right channel, positive high-side FET.
18
21
ROUTP
O
19, 24
22,28
PGND
20
23
ROUTN
O
21
24
RBSN
I
Bootstrap I/O for right channel, negative high-side FET.
22
26
LBSN
I
Bootstrap I/O for left channel, negative high-side FET.
23
27
LOUTN
O
Class-D H-bridge negative output for left channel.
25
1
LOUTP
O
Class-D H-bridge positive output for left channel.
26
2
LBSP
I
Bootstrap I/O for left channel, positive high-side FET.
27,28
3
LPVDD
P
Power supply for left channel H-bridge. Right channel and left channel power
supply inputs are connected internally.
Not connected.
Class-D H-bridge positive output for right channel.
Power ground for the H-bridges.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
Class-D H-bridge negative output for right channel.
13
www.anpec.com.tw
APA2622
Block Diagram
LBSP
VCLAMP
LPVDD
LPVDD
LOUTP FB
AGC Control
MONO Select
LOUTP FB
Gate
Drive
LOUTP
LINP
PWM
Logic
Gain
Control
PGND
VCLAMP
LPVDD
LBSN
LPVDD
LINN
LOUTN FB
AGC Control
Gate
Drive
LOUTN FB
LOUTN
FLAG
Biases and
References
SD
TTL
Buffer
GAIN0
GAIN
Control
GAIN1
AGC
Reference
AGC
FREQ
RAMP
GEN.
PGND
SD Detect
DC Detect
LPVDD
Thermal
Detect
RPVDD
Startup
Protection
Logic
UVLO/OCL
O
RBSP
VCLAMP
AVDD
LDO
Regulator
RPVDD
VCLAMP
RPVDD
VCLAMP
AGC Control
ROUTP FB
Gate
Drive
ROUTN
ROUTN FB
RINN
PWM
Logic
Gain
Control
PGND
VCLAMP
RPVDD
RBSN
RPVDD
RINP
AGC Control
ROUTN FB
MONO Select
Gate
Drive
ROUTP
ROUTP FB
TTL
Buffer
MONO
MONO
Select
PGND
AGND
200k
FREQ
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
14
www.anpec.com.tw
APA2622
Typical Application Circuit
VDD
100µF
Shutdown Control
1µF
SD 1
28 LPVDD
FLAG 2
LINP 3
27 LPVDD
26 LBSP
25 LOUTP
LINN 4
GAIN0 5
1µF
Gain Setting
1µF
23 LOUTN
AVDD 7
22 LBSN
VCLAMP 9
1µF
70kΩ
30kΩ
1µF
Right Channel
Input Signal
1µF
FOSC
H=Fix Freq
L or Floating =Spread Spectrum
0.22µF
BEAD
1000pF
24 PGND
GAIN1 6
AGND 8
1µF
1000 pF
(Recommmanded)
1kΩ
(Recommmanded)
Left Channel
Input Signal
0.1µF
100kΩ
10Ω
APA2622
BEAD
0.22µF
0.22µF
21 RBSN
BEAD
20 ROUTN
AGC 10
1000pF
1000pF
19 PGND
RINN 11
18 ROUTP
RINP 12
17 RBSP
FREQ 13
16 RPVDD
MONO 14
15 RPVDD
BEAD
1000 pF
0.22µF
100 µF
0.1µF
1000 pF
29
GND
Stereo
VDD
VDD
100µF
(Recommmanded)
1kΩ
(Recommmanded)
Shutdown Control
SD 1
28 LPVDD
FLAG 2
LINP 3
27 LPVDD
26 LBSP
25 LOUTP
LINN 4
Gain Setting
1µF
GAIN0 5
24 PGND
GAIN1 6
23 LOUTN
AVDD 7
22 LBSN
AGND 8
VCLAMP 9
1µF
APA2622
1µF
1µF
21 RBSN
BEAD
1000pF
19 PGND
18 ROUTP
RINP 12
17 RBSP
FOSC
MONO 14
H=Fix Freq
L or Floating=Spread Spectrum
BEAD
1000pF
RINN 11
FREQ 13
0.47µF
16 RPVDD
15 RPVDD
100µF
0.1µF
1000pF
29
GND
MONO
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
0.47µF
20 ROUTN
AGC 10
Right Channel
Input Signal
1000pF
0.1µF
100kΩ
10Ω
15
VDD
www.anpec.com.tw
APA2622
AGC Gain Table
VDD=12V, VGND=0V, TA=25OC, No Load
Gain=20dB
Gain=26dB
Gain=32dB
Gain=36dB
dB
dB
dB
dB
1
20.15
26.15
32.15
36.15
2
19.65
25.65
31.65
35.65
3
19.15
25.15
31.15
35.15
4
18.65
24.65
30.65
34.65
5
18.15
24.15
30.15
34.15
6
17.65
23.65
29.65
33.65
7
17.15
23.15
29.15
33.15
8
16.65
22.65
28.65
32.65
9
16.15
22.15
28.15
32.15
10
15.65
21.65
27.65
31.65
11
15.15
21.15
27.15
31.15
12
14.65
20.65
26.65
30.65
13
14.15
20.15
26.15
30.15
14
13.65
19.65
25.65
29.65
15
13.15
19.15
25.15
29.15
16
12.65
18.65
24.65
28.65
17
12.15
18.15
24.15
28.15
18
11.65
17.65
23.65
27.65
19
11.15
17.15
23.15
27.15
20
10.65
16.65
22.65
26.65
Step
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
16
www.anpec.com.tw
APA2622
AGC Gain Table
VDD=12V, VGND=0V, TA=25OC, No Load
Gain=20dB
Gain=26dB
Gain=32dB
Gain=36dB
dB
dB
dB
dB
21
10.15
16.15
22.15
26.15
22
9.65
15.65
21.65
25.65
23
9.15
15.15
21.15
25.15
24
8.65
14.65
20.65
24.65
25
8.15
14.15
20.15
24.15
26
7.65
13.65
19.65
23.65
27
7.15
13.15
19.15
23.15
28
6.65
12.65
18.65
22.65
29
6.15
12.15
18.15
22.15
30
5.65
11.65
17.65
21.65
31
5.15
11.15
17.15
21.15
32
4.65*
10.65
16.65*
20.65*
Step
*Powerlimit
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
17
www.anpec.com.tw
APA2622
Function Description
Class-D Operation
Gain Setting Operation
Output = 0
Gain1
0
0
1
1
VOUTP
Gain0
0
1
0
1
Gain
20
26
32
36
Input Impedance
60kΩ
30kΩ
15kΩ
9kΩ
Table 1 : The gain setting
VOUTN
The APA2622’s gain can be set by GAIN0, GAIN1. The
detail gain setting value is listed at table 1.
VOUT
(VOUTP-VOUTN)
Shutdown Operation
In order to reduce power consumption while not in use,
the APA2622 contains a shutdown function to externally
IOUT
Output > 0
turn off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when logic low is placed on the SD
VOUTP
pin for APA2622. The trigger point between a logic high
and logic low level is typically 1.5V. It is best to switch
VOUTN
between ground and the supply voltage VDD to provide
maximum device performance. By switching the SD pin
VOUT
(VOUTP-VOUTN)
to low level, the amplifier enters a low-consumption- current state, IDD for APA2622 is in shutdown mode. On normal operating, APA2622’s SD pin should pull to high level
to keep the IC out of the shutdown mode. The SD pin
IOUT
Output < 0
VOUTP
should be tied to a definite voltage to avoid unwanted
state changes.
VOUTN
AGC Function Operation
The APA2622 provides the non-clipping control. When
the output reaches the maximum power setting value,
the internal Programmable Gain Amplifier (PGA) will de-
VOUT
(VOUTP-VOUTN)
crease the gain to prevent the output waveform from
clipping. Using the AGC pin to set the non-clipping funcIOUT
tion and limit the output power.
Figure1. The APA2622 Output Waveform
Attack Time=2.8ms
Release Time=1.2S
The APA2622 uses a modulation scheme that allows
operation without the classic LC reconstruction filter when
the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The VOUTP and VOUTN
VP=5.6 x AGC voltage if AGC<2.5V
are in phase with each other with no input so that there is
little or no current in the speaker. The duty cycle of VOUTP
VCLAMP Supply
The VCLAMP is used to power the gates of the output full
is greater than 50% and VOUTN is less than 50% for positive
output voltages. The duty cycle of VOUTP is less than 50%
bridge transistors. It can also be used to supply the AGC
voltage divider circuit. Add a 1µF capacitor to ground at
and VOUTN is greater than 50% for negative output voltages.
The voltage across the load sits at 0V throughout most of
this pin.
the switching period, reducing the switching current, which
reduces any I2R losses in the load.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
18
www.anpec.com.tw
APA2622
Stereo/Mono switching Operation
APA2622 offers the feature of stereo operation with two
Thermal Protection
Thermal protection on the APA2622 prevents damage to
outputs of each channel connected directly. If the MONO
pin (pin 14) is tied high, the positive and negative outputs
the device when the internal die temperature exceeds
150°C. There is a ±15°C tolerance on this trip point from
of each channel (left and right) are synchronized and in
phase. To operate in this mono mode, apply the input
device to device. Once the die temperature exceeds the
thermal set point, the device enters into the shutdown
signal to the RIGHT input and place the speaker between
the LEFT and RIGHT outputs. Connect the positive and
state and the outputs are disabled. This is not a latched
fault. The thermal fault is cleared once the temperature of
negative output together for best efficiency.
Mono mode can increase more output power compared
the die is reduced by 15°C. The device begins normal
operation at this point with no external system interaction.
to the stereo mode single channel’s output power.
Thermal protection faults are NOT reported on the /FLAG
terminal.
DC Detect
When a DC signal applies to the input of APA2622 and
the time excesses 500ms, the APA2622’s DC Detect
fault will be reported on the /FLAG pin as a low state.
The DC Detect fault will also cause the amplifier to
shutdown by changing the state of the outputs to Hi-Z.
To clear the DC Detect it is necessary to cycle the
PVDD supply. Cycling SD will NOT clear a DC Detect
fault.
A DC Detect fault is issued when the output differential
duty-cycle of either channel exceeds 16% for more than
500 msec at the same polarity. This feature protects
the speaker from large DC currents or AC currents less
than 2Hz. To avoid nuisance faults due to the DC detect
circuit, hold the SD pin low at power-up until the signals
at the inputs are stable. Also, take care to match the
impedance seen at the positive and negative inputs to
avoid nuisance DC Detect faults.
Over-Circuit Protection
APA2622 has protection from over-current conditions
caused by a short circuit on the output stage. The short
circuit protection fault is reported on the /FLAG pin as a
low state. The amplifier outputs are switched to a Hi-Z
state when the short circuit protection latch is engaged.
The latch can be cleared by cycling the /SD pin through
the low state.
Connect /FLAG to /SD pin, the over current protection will
be auto recovery.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
19
www.anpec.com.tw
APA2622
Application Information
Input Resistance,Ri
Power-Supply Decoupling Capacitor, CS
Changing the gain setting can vary the input resistance
of the amplifier from its smallest value, 9 kΩ ±20%, to the
The APA2622 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
largest value, 60kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff
ensure the output total harmonic distortion (THD) is as
low as possible. Power supply decoupling also prevents
frequency may change when changing gain steps.
the oscillations being caused by long lead length between the amplifier and the speaker. The optimum
Input Capacitor, Ci
decoupling is achieved by using two different types of
capacitors that target on different types of noise on the
In the typical application, an input capacitor Ci is required
to allow the amplifier to bias the input signal to the proper
power supply leads. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-
dc level for optimum operation. In this case, Ci and the
input impedance of the amplifier (RI) form a high-pass
series-resistance (ESR) ceramic capacitor, typically 0.
1µF placed as close as possible to the device AVDD pin
filter with the corner frequency determined in Equation 1.
f C ( hipass ) =
1
2π Ri C i
and 1µF placed to the LPVDD and RPVDD leads for works
best. For filtering lower frequency noise signals, a large
(1)
aluminum electrolytic capacitor of 220µF or greater placed
The value of Ci is important, as it directly affects the bass
(low-frequency) performance of the circuit. Consider the
near the audio power amplifier is recommended.
example where RI is 60kΩ and the specification calls for
a flat bass response down to 20Hz. Equation 1 is
Output Low-Pass Filter
If the traces from APA2622 to speaker are short, it doesn’t
reconfigured as Equation 2.
Ci =
1
2π Ri C i
require output filter for FCC & CE standard.
(2)
A ferrite bead may be needed if it’s failing the test for
FCC or CE tested without the LC filter. The figure 2 is
In this example, Ci is 0.13µF; so, one would likely choose
a value of 0.15µF as this value is commonly used. If the
the sample for adding ferrite bead; it shows choosing
high impedance in high frequency.
gain is known and is constant, use R i from Table 1 to
calculate Ci. A further consideration for this capacitor is
the leakage path from the input source through the input
network Ci and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to
the amplifier that reduces useful headroom, especially
OUTP
Ferrite
Bead
1nF
in high gain applications. For this reason, a low-leakage
tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the
capacitor should face the amplifier input in most applica-
OUTN
Ferrite
Bead
4Ω
1nF
tions as the dc level there is held at VCLAMP/2, which is
likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application.
Additionally, lead-free solder can create dc offset volt-
Figure 2. Ferrite Bead Output Filter
ages and it is important to ensure that boards are cleaned
properly.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
20
www.anpec.com.tw
APA2622
Application Information (Cont.)
During each high-side switching cycle, the bootstrap
capacitors hold the VGS high enough to keep the high-
Output Low-Pass Filter (cont.)
Figure 3 and Figure 4 are examples for adding the LC
side MOSFETs turned on.
filter (Butterworth), it’s recommended for the situation that
the trace form amplifier to speaker is too long, and needs
Layout Recommendation
to eliminate the radiated emission or EMI.
OUTP
The APA2622 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed
33µH
circuit board. The following suggestions will help to meet
EMC requirements.
1µF
OUTN
33µH
1. The high frequency decoupling capacitors should be
placed as close to the PVDD and AVDD terminals as
8Ω
possible. Large (100µF or greater) bulk power supply
decoupling capacitors should be placed near the
1µF
APA2622 on the LPVDD and RPVDD supplies. Local,
high-frequency bypass capacitors should be placed as
Figure 3. Typical LC Output Filter, Cutoff Frequency of
close to the PVDD pins as possible. These caps can
be connected to the thermal pad directly for an excellent
27 kHz, Speaker Impedance = 8Ω
ground connection. Consider adding a small, good
quality low ESR ceramic capacitor between 1000pF and
OUTP
15µH
10nF and a larger mid-frequency cap of value between
0.1µF and 1µF also of good quality to the PVDD con-
2.2µF
OUTN 15µH
nections at each end of the chip.
2. Keep the current loop from each of the outputs through
4Ω
the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this
2.2µF
current loop determines its effectiveness as an antenna.
3. Grounding— The AVDD (pin 7) decoupling capacitor
should be grounded to analog ground (AGND). The
Figure 4. Typical LC Output Filter, Cutoff Frequency of
27 kHz, Speaker Impedance = 4Ω
PVDD decoupling capacitors should connect to PGND.
Analog ground and power ground should be connected
BSN and BSP CAPACITORS
The full H-bridge output stages which use only NMOS
transistors require bootstrap capacitors for the high
at the thermal pad, which should be used as a central
ground connection or star ground for the APA2622.
4. Output filter— The ferrite EMI filter (Figure 3) should be
placed as close to the output terminals as possible for
side of each output to turn on correctly. A 0.22µF
capacitor, rated for at least 25V, must be connected
the best EMI performance. The LC filter (Figure 4 and
Figure 5) should be placed close to the outputs. The
from each output to its corresponding bootstrap input.
Specifically, one 0.22µF capacitor must be connected
capacitors used in both the ferrite and LC filters should
be grounded to power ground.
from OUTPx to BSPx, and one 0.22µF capacitor must
be connected from OUTNx to BSNx. (See the application circuit) The bootstrap capacitors connected
between the BSxx pins and corresponding output
function as a floating power supply for the high-side Nchannel power MOSFET gate drive circuitry.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
21
www.anpec.com.tw
APA2622
Application Information (Cont.)
Layout Recommendation (cont.)
5. Thermal Pad— The thermal pad must be soldered to
the PCB for proper thermal performance and optimal
reliability. The vias should connect to a solid copper
plane, either on an internal layer or on the bottom layer
of the PCB. The vias must be solid vias, not thermal
relief or webbed vias.
2.0mm
0.7mm
3.0mm
0.65mm
6.5mm
Via diameter
= 0.3mm x 8
6.4mm
TSSOP-28P Land Pattern Recommendation
1.5mm
2.7mm
0.25mm
0.4mm
Via diameter
= 0.3mm x 9
0.3mm
QFN4x4-28 Land Pattern Recommendation
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
22
www.anpec.com.tw
APA2622
Application Information (Cont.)
Layout Recommendation
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
23
www.anpec.com.tw
APA2622
Package Information
TSSOP-28P
D
SEE VIEW A
E2
EXPOS
ED PAD
E1
E
D1
c
0.25
b
S
Y
M
B
O
L
VIEW A
L
GAUGE PLANE
SEATING PLANE
0
A1
A2
A
e
TSSOP-28P
INCHES
MILLIMETERS
MIN.
MAX.
A
MIN.
MAX.
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.031
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.008
D
9.60
9.80
0.378
0.386
D1
4.50
6.00
0.177
0.236
E
6.20
6.60
0.244
0.260
0.177
0.138
E1
4.30
4.50
0.169
E2
2.50
3.50
0.098
0.75
0.018
8o
0o
e
0.65 BSC
L
0.45
0
0o
0.026 BSC
0.030
8o
Note : 1. Followed from JEDEC MO-153 AET.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
24
www.anpec.com.tw
APA2622
Package Information
QFN4x4-28B
D
b
E
A
Pin 1
A1
D2
A3
NX
aaa c
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
QFN4x4-28B
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.80
1.00
0.031
0.039
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
0.006
0.010
b
0.15
0.25
D
3.90
4.10
0.154
0.161
0.110
D2
2.50
2.80
0.098
E
3.90
4.10
0.154
0.161
E2
2.50
2.80
0.098
0.110
e
0.4 BSC
L
0.30
K
0.20
aaa
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
0.016 BSC
0.012
0.50
0.020
0.008
0.08
0.003
25
www.anpec.com.tw
APA2622
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TSSOP-28P
Application
QFN4x4-28B
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
16.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
16.0±0.30
1.75±0.10
7.50±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
4.00±0.10
12.00±0.10
2.00±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±0.20
1.30±0.20
4.0±0.10
8.0±0.10
6.9±0.20 10.20.±0.20
1.50±0.20
(mm)
Devices Per Unit
Package Type
TSSOP-28P
QFN4x4-28B
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
Unit
Tape & Reel
Tape & Reel
Quantity
2000
3000
26
www.anpec.com.tw
APA2622
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
27
www.anpec.com.tw
APA2622
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (t p) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
28
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
www.anpec.com.tw
APA2622
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Dec., 2015
29
www.anpec.com.tw