95624

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Added note to paragraph 1.2.2 and table I regarding the 4 transistor
design. Paragraph 1.3; changed the power dissipation for device types
05-09 from 2.9 W max to 3.3 W max. Table I; changed the ICC max limit
for device types 05-09 from 520 mA to 600 mA. Table I; changed the
ICCDR1 max limit from 12 mA to 28 mA. Figure 1; changed dimension A
minimum from 0.175 inches to 0.115 inches. Redrew entire document . sld
00-09-27
Michael Jones
B
Drawing updated to reflect current requirements. -sld
04-03-29
Raymond Monnin
C
Table I; Changed the maximum limit for COE and CAD tests from 32
pF to 30 pF. -sld
06-02-06
Raymond Monnin
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REV STATUS
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PMIC N/A
PREPARED BY
Gary Zahn
STANDARD MICROCIRCUIT
DRAWING
CHECKED BY
Michael C. Jones
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF
DEFENSE
AMSC N/A
APPROVED BY
Kendall A. Cottongim
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
MICROCIRCUIT, HYBRID, MEMORY,
DIGITAL, 512K x 32-BIT, STATIC RANDOM
ACCESS MEMORY, CMOS
DRAWING APPROVAL DATE
96-08-09
REVISION LEVEL
C
SIZE
A
SHEET
DSCC FORM 2233
APR 97
CAGE CODE
67268
1 OF
5962-95624
20
5962-E251-06
1. SCOPE
1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A
choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When
available, a choice of radiation hardness assurance levels are reflected in the PIN.
1.2 PIN. The PIN shall be as shown in the following example:
5962
⏐
⏐
⏐
Federal
stock class
designator
\
95624
⏐
⏐
⏐
RHA
designator
(see 1.2.1)
01
⏐
⏐
⏐
Device
type
(see 1.2.2)
/
H
⏐
⏐
⏐
Device
class
designator
(see 1.2.3)
N
⏐
⏐
⏐
Case
outline
(see 1.2.4)
X
⏐
⏐
⏐
Lead
finish
(see 1.2.5)
\/
Drawing number
1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA
levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type 1/
01
02
03
04
05
06
07
08
09
10
11
12
Generic number
WS512K32F-120G4Q
WS512K32F-100G4Q
WS512K32F-85G4Q
WS512K32F-70G4Q
WS512K32F-55G4Q
WS512K32F-45G4Q
WS512K32F-35G4Q
WS512K32F-25G4Q
WS512K32F-20G4Q
WS512K32M-45G4Q
WS512K32M-35G4Q
WS512K32M-25G4Q
Circuit function
Access time
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
SRAM, 512K x 32-bit
120 ns
100 ns
85 ns
70 ns
55 ns
45 ns
35 ns
25 ns
20 ns
45 ns
35 ns
25 ns
1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All
levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and
E) or QML Listing (Class G and D). The product assurance levels are as follows:
Device class
Device performance documentation
K
Highest reliability class available. This level is intended for use in space
applications.
H
Standard military quality class level. This level is intended for use in applications
where non-space high reliability devices are required.
1/ Due to the nature of the 4 transistor design of the die in these device types, topologically pure testing is important,
particularly for high reliability applications. The device manufacturer should be consulted concerning their testing
methods and algorithms.
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REVISION LEVEL
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G
Reduced testing version of the standard military quality class. This level uses the
Class H screening and In-Process Inspections with a possible limited temperature
range, manufacturer specified incoming flow, and the manufacturer guarantees (but
may not test) periodic and conformance inspections (Group A, B, C and D).
E
Designates devices which are based upon one of the other classes (K, H, or G)
with exception(s) taken to the requirements of that class. These exception(s) must
be specified in the device acquisition document; therefore the acquisition document
should be reviewed to ensure that the exception(s) taken will not adversely affect
system performance.
D
Manufacturer specified quality class. Quality level is defined by the manufacturers
internal, QML certified flow. This product may have a limited temperature range.
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
N
Descriptive designator
See figure 1
Terminals
Package style
68
Co-fired, single cavity, quad flat pack,
low capacitance
1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534.
1.3 Absolute maximum ratings. 1/
Supply voltage range (VCC) .......................................................
Signal voltage range (VG) ..........................................................
Power dissipation (PD) :
Device types 01 through 09 ....................................................
Device types 10 through 12 ....................................................
Storage temperature range........................................................
Lead temperature (soldering, 10 seconds).................................
-0.5 V dc to +7.0 V dc
-0.5 V dc to +7.0 V dc
3.3 W Maximum at 5 MHz
4.4 W Maximum at 5 MHz
-65°C to +150°C
+300°C
1.4 Recommended operating conditions.
Supply voltage range (VCC) .......................................................
Input low voltage range (VIL)......................................................
Input high voltage range (VIH) ....................................................
Case operating temperature range (TC).....................................
+4.5 V dc to +5.5 V dc
-0.5 V dc to +0.8 V dc
+2.2 V dc to VCC + 0.3 V dc
-55°C to +125°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38534 - Hybrid Microcircuits, General Specification for.
1/
Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
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REVISION LEVEL
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DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in
accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as
designated in the device manufacturer's Quality Management (QM) plan or as designated for the applicable device class. The
manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as
defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not
affect the form, fit, or function of the device for the applicable device class.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38534 and herein.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.
3.2.4 Logic diagram(s). The logic diagram(s) shall be as specified on figures 4 and 5.
3.2.5 Block diagram. The block diagram shall be as specified on figure 6.
3.2.6 Output load circuit. The output load circuit shall be as specified on figure 7.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full specified operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with
the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked.
3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described
herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample,
for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those
which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be
made available to the preparing activity (DSCC-VA) upon request.
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TABLE I. Electrical performance characteristics.
Test
Group A
subgroups
Conditions 1/ 2/ 3/
Symbol
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Limits
Device
types
Min
Unit
Max
DC parameters
Input leakage current
ILI
VCC = 5.5 V dc, VIN = GND
or VCC
1,2,3
All
10
µA
Output leakage current
ILO
CS = VIH, OE = VIH, VOUT =
GND or VCC
1,2,3
All
10
µA
Operating supply current
ICC
CS = VIL, OE = VIH,
f = 5 MHz, VCC = 5.5 V dc
1,2,3
01-04
05-09
10-12
200
600
800
mA
Standby current
ISB
CS = VIH, OE = VIH,
f = 5 MHz, VCC = 5.5 V dc
1,2,3
01-04
05-09
10-12
4.0
60
120
mA
Input low level
VIL
1,2,3
All
Input high level
VIH
1,2,3
All
Output low voltage
VOL
VCC = 4.5 V, IOL = 2.1 mA
1,2,3
01-06
0.4
VCC = 4.5 V, IOL = 8.0 mA
1,2,3
07-12
0.4
VCC = 4.5 V, IOL = -1.0 mA
1,2,3
01-06
2.4
VCC = 4.5 V, IOL = -4.0 mA
1,2,3
07-12
2.4
Output high voltage
VOH
0.8
2.2
V
V
V
V
Dynamic characteristics
OE capacitance 4/
COE
VIN = 0 V, f = 1.0 MHz,
TA = +25°C
4
All
30
pF
WE capacitance 4/
CWE
VIN = 0 V, f = 1.0 MHz,
TA = +25°C
4
All
32
pF
CS 1-4 capacitance 4/
CCS
VIN = 0 V, f = 1.0 MHz,
TA = +25°C
4
All
15
pF
Data I/O capacitance 4/
CI/O
VIN = 0 V, f = 1.0 MHz,
TA = +25°C
4
All
15
pF
See footnotes at end of table.
STANDARD
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REVISION LEVEL
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TABLE I. Electrical performance characteristics - Continued.
Test
Group A
subgroups
Conditions 1/ 2/ 3/
Symbol
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Limits
Device
types
Min
Unit
Max
Dynamic characteristics - Continued
Address input capacitance
4/
CAD
VIN = 0 V, f = 1.0 MHz,
TA = +25°C
4
All
See 4.3.1c
7,8A,8B
All
30
pF
Functional testing
Functional tests
Data retention characteristics
Data retention supply voltage
VDR
CS ≥ VDR - 0.2 V
9,10,11
All
Data retention current
ICCDR1
VCC = 3 V
9,10,11
01-04
05-09
10-12
2.0
5.5
1.6
28
40
V
mA
Read cycle AC timing characteristics
Read cycle time
tRC
See figure 4
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
Address access time
tAA
See figure 4
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
120
100
85
70
55
45
35
25
20
ns
120
100
85
70
55
45
35
25
20
ns
See footnotes at end of table.
STANDARD
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REVISION LEVEL
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TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/ 3/
-55°C ≤ TC ≤+125°C
unless otherwise specified
Group A
subgroups
Device
types
Limits
Min
Unit
Max
Read cycle AC timing characterisitics - Continued
Chip select access time
tACS
See figure 4
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
120
100
85
70
55
45
35
25
20
ns
Output enable to output valid
tOE
See figure 4
9,10,11
01
02
03
04,10
05-07,11
08,12
09
60
50
40
35
25
12
10
ns
Output hold from address
change
tOH
See figure 4
9,10,11
01-04
10-12
05-09
5
5
0
ns
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
120
100
85
70
55
45
35
25
20
ns
Write AC timing characteristics WE controlled
Write cycle time
tWC
See figure 5
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
Group A
subgroups
Conditions 1/ 2/ 3/
Symbol
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Limits
Device
types
Min
Unit
Max
Write AC timing characteristics WE controlled - Continued
Chip select to end of write
tCW
See figure 5
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
100
80
75
60
50
35
25
17
15
ns
Address valid to end of write
tAW
See figure 5
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
100
80
75
60
50
35
25
17
15
ns
Data valid to end of write
tDW
See figure 5
9,10,11
01,02
03,04,10
05,06
07,11
08
09
12
40
30
25
20
13
12
10
ns
Write pulse width
tWP
See figure 5
9,10,11
01,02
03,04
05
06,10
07,11
08,12
09
60
50
40
35
25
17
15
ns
Address setup time
tAS
See figure 5
9,10,11
01-04
05-09
10-12
0
2
0
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
Group A
subgroups
Conditions 1/ 2/ 3/
Symbol
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Limits
Device
types
Min
Unit
Max
Write AC timing characteristics WE controlled - Continued
Address hold time
tAH
See figure 5
9,10,11
01-06
07-12
5
0
ns
Data hold time
tDH
See figure 5
9,10,11
All
0
ns
Write AC timing characteristics CS controlled
Write cycle time
tWC
See figure 5
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
120
100
85
70
55
45
35
25
20
ns
Chip select to end of write
tCW
See figure 5
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
100
80
75
60
50
35
25
17
15
ns
Address valid to end of write
tAW
See figure 5
9,10,11
01
02
03
04
05
06,10
07,11
08,12
09
100
80
75
60
50
35
25
17
15
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
Group A
subgroups
Conditions 1/ 2/ 3/
Symbol
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Limits
Device
types
Min
Unit
Max
Write AC timing characteristics CS controlled - Continued
Data valid to end of write
tDW
See figure 5
9,10,11
01,02
03,04,10
05,06
07,11
08
09
12
40
30
25
20
13
12
10
ns
Write pulse width
tWP
See figure 5
9,10,11
01,02
03,04
05
06,10
07,11
08,12
09
60
50
40
35
25
17
15
ns
Address setup time
tAS
See figure 5
9,10,11
01-04
05-09
10-12
0
2
0
ns
Address hold time
tAH
See figure 5
9,10,11
01-06
07-12
5
0
ns
Data hold time
tDH
See figure 5
9,10,11
All
0
ns
1/ Unless otherwise specified, 4.5 V dc ≤ VCC ≤ 5.5 V dc and VSS = 0.
2/ Unless otherwise specified, the DC test conditions are as follows:
Input pulse levels: VIH = VCC - 0.3 V and VIL = 0.3 V.
Unless otherwise specified, the AC test conditions are as follows:
Input pulse levels: VIL = 0 V and VIH = 3.0 V.
Input rise and fall times: 5 nanoseconds.
Input and output timing reference levels: 1.5 V.
3/ Due to the nature of the 4 transistor design of the die used in these device types, topologically pure testing is important,
particularly for high reliability applications. The device manufacturer should be consulted concerning their testing
methods and alogorithms.
4/ Guaranteed by design, but not tested.
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Case outline N.
FIGURE 1. Case outline(s).
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Case outline N - Continued.
Symbol
Millimeters
Inches
Min
Max
Min
Max
A
2.92
5.10
.115
.200
A1
1.40
1.65
.055
.065
A2
1.14
1.40
.045
.055
b
0.30
0.46
.012
.018
C
0.23
0.31
.009
.012
D/E
63.63
66.42
2.505
2.615
D1/E1
39.24
40.01
1.545
1.575
D2/E2
71.25
84.20
2.805
3.315
e
1.14
1.40
.045
.055
e1
20.19
20.45
.795
.805
j
4.83
5.33
.190
.210
k
37.72
38.48
1.485
1.515
L
12.19
13.21
.480
.520
S1
9.45
9.86
.372
.388
NOTES:
1. The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of
measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound
units shall rule.
2. Pin numbers are for reference only.
FIGURE 1. Case outline(s) - Continued.
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Device
types
All
Device
types
All
Device
types
All
Device
types
All
Case
outlines
N
Case
outlines
N
Case
outlines
N
Case
outlines
N
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
GND
18
GND
35
OE
52
GND
2
CS1
19
I/O8
36
CS4
53
I/O23
3
A5
20
I/O9
37
A17
54
I/O22
4
A4
21
I/O10
38
A18
55
I/O21
5
A3
22
I/O11
39
NC
56
I/O20
6
A2
23
I/O12
40
NC
57
I/O19
7
A1
24
I/O13
41
NC
58
I/O18
8
A0
25
I/O14
42
NC
59
I/O17
9
NC
26
I/O15
43
NC
60
I/O16
10
I/O0
27
VCC
44
I/O31
61
VCC
11
I/O1
28
A11
45
I/O30
62
A10
12
I/O2
29
A12
46
I/O29
63
A9
13
I/O3
30
A13
47
I/O28
64
A8
14
I/O4
31
A14
48
I/O27
65
A7
15
I/O5
32
A15
49
I/O26
66
A6
16
I/O6
33
A16
50
I/O25
67
WE
17
I/O7
34
CS2
51
I/O24
68
CS3
FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95624
A
REVISION LEVEL
C
SHEET
13
Power
Mode
High Z
Standby
Standby
VIH
High Z
Active
Read
VIH
VIH
High Z
Active
Output disable
X
VIL
Data In
Active
Write
CS
OE
WE
VIH
X
X
VIL
VIL
VIL
VIL
I/O
NOTES:
1. VIH = High Logic Level
2. VIL = Low Logic Level
3. X = Do not care (either high or low)
4. High Z = High Impedance State
FIGURE 3. Truth table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95624
A
REVISION LEVEL
C
SHEET
14
FIGURE 4. Read cycle timing diagrams.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95624
A
REVISION LEVEL
C
SHEET
15
FIGURE 5. Write cycle timing diagrams.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95624
A
REVISION LEVEL
C
SHEET
16
FIGURE 6. Block diagram.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95624
A
REVISION LEVEL
C
SHEET
17
Parameter
Input Pulse Level
Typ.
Unit
0 - 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Load Capacitance
50
pF
NOTES:
1. VZ is programmable from +2 V to +7 V.
2. IOL and IOH are programmable from 0 to 16 mA.
3. Tester impedance is Z0 = 75 ohms.
4. VZ is typically the midpoint of VOL and VOH.
5. IOL and IOH are adjusted to simulate a typical
resistive load circuit.
6. ATE tester includes jig capacitance.
FIGURE 7. Output load circuit.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95624
A
REVISION LEVEL
C
SHEET
18
TABLE II. Electrical test requirements.
MIL-PRF-38534 test requirements
Subgroups
(in accordance with
MIL-PRF-38534, group A test
table)
Interim electrical parameters
1,4,7,9
Final electrical parameters
1*,2,3,4,7,8A,8B,9,10,11
Group A test requirements
1,2,3,4,7,8A,8B,9,10,11
Group C end-point electrical
parameters
1,2,3,4,7,8A,8B,9,10,11
End-point electrical parameters
for Radiation Hardness Assurance
(RHA) devices
Not applicable
* PDA applies to subgroup 1.
3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this
drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturer's product meets
the performance requirements of MIL-PRF-38534 and herein.
3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of
microcircuits delivered to this drawing.
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as
modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form,
fit, or function as described herein.
4.2 Screening. Screening shall be in accordance with MIL-PRF-38534. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1)
Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2)
TA as specified in accordance with table I of method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests
prior to burn-in are optional at the discretion of the manufacturer.
4.3 Conformance and periodic inspections. Conformance inspection (CI) and periodic inspection (PI) shall be in accordance
with MIL-PRF-38534 and as specified herein.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95624
A
REVISION LEVEL
C
SHEET
19
4.3.1 Group A inspection (CI). Group A inspection shall be in accordance with MIL-PRF-38534 and as follows:
a. Tests shall be as specified in table II herein.
b. Subgroups 5 and 6 shall be omitted.
c. Subgroups 7 and 8 shall include verification of the truth table on figure 3.
4.3.2 Group B inspection (PI). Group B inspection shall be in accordance with MIL-PRF-38534.
4.3.3 Group C inspection (PI). Group C inspection shall be in accordance with MIL-PRF-38534 and as follows:
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test, method 1005 of MIL-STD-883.
(1)
Test condition B. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005 of MIL-STD-883.
(2)
TA as specified in accordance with table I of method 1005 of MIL-STD-883.
(3)
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.3.4 Group D inspection (PI). Group D inspection shall be in accordance with MIL-PRF-38534.
4.3.5 Radiation Hardness Assurance (RHA) inspection. RHA inspection is not currently applicable to this drawing.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38534.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated as specified in MIL-PRF38534.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used
for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962)
should contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone (614)
692-1081.
6.6 Sources of supply. Sources of supply are listed in MIL-HDBK-103 and QML-38534. The vendors listed in MIL-HDBK-103
and QML-38534 have submitted a certificate of compliance (see 3.7 herein) to DSCC-VA and have agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95624
A
REVISION LEVEL
C
SHEET
20
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 06-02-06
Approved sources of supply for SMD 5962-95624 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38534 during the next revisions. MIL-HDBK-103 and QML-38534 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revisions of MIL-HDBK-103 and QML-38534. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
5962-9562401HNC
5962-9562402HNC
5962-9562403HNC
5962-9562404HNC
5962-9562405HNC
5962-9562406HNC
5962-9562407HNC
5962-9562408HNC
5962-9562409HNC
5962-9562410HNC
5962-9562411HNC
5962-9562412HNC
Vendor
CAGE
number
54230
54230
54230
54230
54230
54230
54230
54230
54230
54230
54230
54230
Vendor similar PIN 2/
WS512K32F-120G4Q, WS512K32F-120G4TQ
WS512K32F-100G4Q, WS512K32F-100G4TQ
WS512K32F-85G4Q, WS512K32F-85G4TQ
WS512K32F-70G4Q, WS512K32F-70G4TQ
WS512K32F-55G4Q, WS512K32F-55G4TQ
WS512K32F-45G4Q, WS512K32F-45G4TQ
WS512K32F-35G4Q, WS512K32F-35G4TQ
WS512K32F-25G4Q, WS512K32F-25G4TQ
WS512K32F-20G4Q, WS512K32F-20G4TQ
WS512K32M-45G4Q, WS512K32M-45G4TQ
WS512K32M-35G4Q, WS512K32M-35G4TQ
WS512K32M-25G4Q, WS512K32M-25G4TQ
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that part. If the
desired lead finish is not listed contact the Vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired to this
number may not satisfy the performance requirements of this drawing.
Vendor CAGE
number
54230
Vendor name
and address
White Electronic Designs Corporation
3601 East University Drive
Phoenix, AZ 85034
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.