1200V, 40A, VCE(sat) 1.8V, VGE(th) min 4.9V, tr 47ns - tf 10ns, Eon 2.7mJ, Eoff 1.1mJ - Die Size - 6.7 x 6.5 mm2 - FGH40T120SM IGBT DIE

FGH40T120SM
Field Stop Trench IGBT Chip
1200V, 40A, VCE(sat) = 1.8V
Part
VCES
ICn
VCE (sat) Typ
Die Size
FGH40T120SM
1200V
40A
1.8
6.66 x 6.49 mm
2
See page 2 for ordering part numbers & supply formats
Features
Applications
•
AC & DC Motor Controls
•
High Speed Switching & High Input Impedance
•
General Purpose Inverters
•
Positive Temperature Coefficient
•
Low Saturation Voltage
Maximum Ratings
Symbol
Parameter
Ratings
Units
VCES
Collector to Emitter Voltage
1200
V
Gate to Emitter Voltage
±25
Transient Gate to Emitter Voltage
±30
VGES
IC
V
Collector Current
1
Continuous (TC = 25°C)
80
A
Collector Current
1
Continuous (TC = 100°C)
40
A
ICM
Pulsed Collector Current
160
A
ILM
Clamped Inductive Load Current @ TC = 25°C
160
A
TJ, TSTG
Operation Junction & Storage Temperature
-55 to 175
°C
Static Characteristics, TJ = 25° unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
BVCES
Collector to Emitter Breakdown Voltage
VGE = 0V, IC = 250 µA
1200
-
-
V
ICES
Collector Cut-Off Current
VCE = VCES , VGE = 0V
-
-
250
µA
IGES
G-E Leakage Current
VGE = VGES, VCE = 0V
-
-
±400
nA
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
VGE(th)
G-E Threshold Voltage
IC = 40mA, VCE = VGE
4.9
6.2
7.5
V
IC = 40A, VGE = 15V
-
1.8
2.4
V
VCE(sat)
Collector to Emitter Saturation Voltage
IC = 40A, VGE = 15V
TC = 175°C
-
2.0
-
V
1.
2.
3.
Notes:
Performance will vary based on assembly technique and substrate choice
Defined by chip design, not subject to 100% production test at wafer level
Specified in discrete package for indicative purposes only, bare die performance will vary depending on module
design.
Further Information - Contact your Micross sales office or email your enquiry to [email protected]
©2015 Fairchild Semiconductor Corporation & Micross Components
Page1
On Characteristics, TJ = 25°C unless otherwise noted
Dynamic Characteristics2, TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Cies
Input Capacitance
Coes
Output Capacitance
Cres
Reverse Transfer Capacitance
Qg
Total Gate Charge
Qge
Gate to Emitter Charge
Qgc
Gate to Collector Charge
VCE = 30V, VGE = 0V
f = 1MHz
VCE = 600V, IC = 40A
VGE = 15V
Min
Typ
Max
Units
-
4300
-
pF
-
180
-
pF
-
100
-
pF
-
370
-
nC
-
23
-
nC
-
210
Min
Typ
Max
-
40
-
ns
-
47
-
ns
-
475
-
ns
-
10
nC
Switching Characteristics3, TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
td(on)
Turn-On Delay Time
tr
Rise Time
td (off)
Turn-Off Delay Time
tf
Fall Time
Eon
Turn-On Switching Loss
-
2.7
-
mJ
Eoff
Turn-Off Switching Loss
-
1.1
-
mJ
Ets
Total Switching Loss
-
3.8
-
mJ
td (on)
Turn-On Delay Time
-
40
-
ns
tr
Rise Time
-
55
-
ns
td (off)
Turn-Off Delay Time
-
520
-
ns
tf
Fall Time
-
50
-
ns
Eon
Turn-On Switching Loss
-
3.4
-
mJ
Eoff
Turn-Off Switching Loss
-
2.5
-
mJ
Ets
Total Switching Loss
-
5.9
-
mJ
VCC = 600V, IC = 40A
RG = 10Ω, VGE = 15V
Inductive Load, TC = 25°C
VCC = 600V, IC = 40A
RG = 10Ω, VGE = 15V
Inductive Load, TC = 175°C
Units
ns
Notes:
1. Performance will vary based on assembly technique and substrate choice
2. Defined by chip design, not subject to 100% production test at wafer level
3. Specified in discrete package for indicative purposes only, bare die performance will vary depending on
module design.
Ordering Guide
Part Number
Format
Detail / Drawing
FGH40T120SMW
Un-sawn wafer, electrical rejects inked
Page 3
FGH40T120SMF
Sawn wafer on film-frame
Page 4
FGH40T120SMD
Singulated die / chips in waffle pack
Page 4
Page2
Note: Singulated Die / Chips can also be supplied in Pocket Tape or SurfTape® on request
Further Information - Contact your Micross sales office or email your enquiry to [email protected]
©2015 Fairchild Semiconductor Corporation & Micross Components
Die Drawing – Dimensions (µm)
EMITTER
GATE
EMITTER
CHIP BACKSIDE IS COLLECTOR
Mechanical Data
Parameter
Units
Chip Dimensions Un-sawn
6660 x 6490
µm
Chip Thickness (Nominal)
125
µm
Gate Pad Size
350 x 513
µm
Wafer Diameter
150 (subject to change)
mm
80 (subject to change)
µm
Saw Street
Wafer orientation on frame
Wafer notch parallel with frame flat
Topside Metallisation & Thickness
Al
Backside Metallisation & Thickness
Al/V/Ni/Ag
4
µm
0.35
µm
Nitride
Recommended Die Attach Material
Soft Solder or Conductive Epoxy
Recommended Wire Bond - Gate
Al 125µm X1
Recommended Wire Bond – Source
Al 380µm X2
Page3
Topside Passivation
Further Information - Contact your Micross sales office or email your enquiry to [email protected]
©2015 Fairchild Semiconductor Corporation & Micross Components
Sawn Wafer on Film-Frame – Dimensions (inches)
Die in Waffle Pack – Dimensions (mm)
A
X
X = 6.86mm ±0.13mm pocket size
Y = 6.86mm ±0.13mm pocket size
Z = 0.89mm ±0.08mm pocket depth
A = 5° ±1/2° pocket draft angle
No Cross Slots
Array = 4 X 4 (16)
Y
Z
X
OVERALL TRAY SIZE
Size = 50.67mm ±0.25mm
Height = 3.94mm ±0.13mm
Flatness = 0.30mm
DISCLAIMER THE INFORMATION HEREIN IS GIVEN TO DESCRIBE CERTAIN COMPONENTS AND SHALL NOT BE CONSIDERED AS WARRANTED CHARACTERISTICS. NO
RESPONSIBILITY IS ASSUMED FOR ITS USE; NOR FOR ANY INFRINGEMENT OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS
GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF EITHER MICROSS COMPONENTS OR FAIRCHILD SEMICONDUCTOR CORPORATION.
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR
DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY
ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND
CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
(a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use
provided in the labelling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Further Information - Contact your Micross sales office or email your enquiry to [email protected]
©2015 Fairchild Semiconductor Corporation & Micross Components
Page4
1. Life support devices or systems are devices or systems which,
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