w WM8903-6201-FL40-M-REV1 Example Configurations DOC TYPE: Example Configurations BOARD REFERENCE: WM8903-6201-FL40-M-REV1 BOARD TYPE: Customer Mini Board WOLFSON DEVICE(S): WM8903 DATE: May 2009 DOC REVISION: Rev 1.1 INTRODUCTION The WM8903-6201-FL40-M-REV1 Customer Mini Board is compatible with the 6201-EV1-REV2 customer evaluation board and together they provide a complete hardware platform for evaluation of the WM8903. The WM8903 Customer Mini Board can also be used independently and connected directly to a processor board using flying wires or appropriate headers. This document will cover both, but performance data will be based on the Wolfson system with 6201-EV1-REV2 motherboard. Configurations covered are listed below: • DAC to headphone playback to HPOUTL/R • DAC to headphone playback to HPOUTL/R with ultra-low bias • DAC to line out playback LINEOUTL/R • DAC to differential line out playback LOP-LON/ROP-RON • IN1LR bypass to HPOUTL/R • IN1LR record to ADC This document should be used as a starting point for evaluation of WM8903 but it will not cover every possible configuration. Assumptions: 1. The user is familiar with the 6201-EV1-REV2 main board and that the board is configured correctly for the path of interest (see related documents below) 2. The user has control of the WM8903 register settings, for example by installing Wolfson WISCE software Related documents: 1. WM8903 datasheet 2. WM8903-6201-FL40-M-REV1 Schematic and Layout.pdf 3. 6201-EV1-REV2 Schematic and Layout.pdf 4. WISCE Quick Start Guide.pdf WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ May 2009, Rev 1.1 Copyright ©2009 Wolfson Microelectronics plc WM8903-6201-FL40-M-REV1 Customer Information TABLE OF CONTENTS INTRODUCTION .............................................................................................................1 TABLE OF CONTENTS ..................................................................................................2 BOARD CONFIGURATIONS STAND-ALONE................................................................3 BOARD CONFIGURATIONS WITH 6201-EV1-REV2 MAIN BOARD.............................5 DAC TO HEADPHONE PLAYBACK TO HPOUTL/R ...............................................................5 DAC TO HEADPHONE PLAYBACK TO HPOUTL/R WITH ULTRA-LOW BIAS......................8 DAC TO LINE OUT PLAYBACK TO LINEOUTL/R ..................................................................9 DAC TO DIFFERENTIAL LINE OUT PLAYBACK TO LOP-LON/ROP-RON .........................11 IN1LR TO HP AND LINEOUT (BYPASS) ..............................................................................13 IN1LR RECORD TO ADC .....................................................................................................15 APPLICATION SUPPORT ............................................................................................19 IMPORTANT NOTICE ...................................................................................................20 w Customer Information May 2009, Rev 1.1 2 WM8903-6201-FL40-M-REV1 Customer Information BOARD CONFIGURATIONS STAND-ALONE The WM8903 Customer Mini Board can be used a stand-alone module for direct connection to a processor board via flying leads or dedicated headers. This section will detail important considerations and provide all information required to do this without risking damage to the device. CONNECTION DIAGRAM Figure 1 below shows the connections required to power-up and control the WM8903 Customer Mini Board. Please refer to the Table 1 for further detail on external I/O connections. CONTROL IF ANALOGUE IN IN2R IN1R IN3L IN2L IN1L SDIN SCLK GPIO3 DCVDD DBVDD AMIC / DMIC IF MICBIAS IN1L DMIC_DAT DMIC_LR DMIC IF IN3R MICBIAS ROP RON AUDIO IF MCLK DMIC_DAT DMIC_LR INTERRUPT BCLK DACDAT LRC ADCDAT AVDD LON LOP LINEOUTL CPVDD LINEGND LINEOUTR HPOUTL HPGND HPOUTR ANALOGUE OUT Figure 1 Stand-Alone Board Configuration w Customer Information May 2009, Rev 1.1 3 WM8903-6201-FL40-M-REV1 Customer Information I/O TABLE SIGNAL BOARD REFERENCE IMPORTANT NOTES Voltage Supplies AVDD H5, H3: pin 8 AVDD = 1.71V to 2.0V CPVDD H6, H1: pin 20 CPVDD = 1.71V to 2.0V DCVDD H8, H4: pin 18 DCVDD = 1.14V to 1.89V DBVDD H7, H4: pin 20 DBVDD = 1.42V to 3.6V Ground DGND AGND CPGND Common ground TP1, TP12, TP26, H1: pin 2, H2 pin 4, H3: pin 12 Analogue and digital grounds must always be within 0.3V of each other. Control Interface SDIN SCLK Master Clock MCLK TP36, H4: pin 14 TP38, H4: pin 16 TP2, H1 pin 4 Both control interface signals should swing between DGND and DBVDD. Signal should swing between DGND and DVDD. Digital I/O GPIO2/ TP3, H1: pin 6 DMIC_DAT GPIO1/ TP4, H1: pin 8 DMIC_LR INTERRUPT TP5, H1: pin 10 GPIO3/ADDR TP38, H4: pin 16 Audio Interface BCLK TP6, H1: pin 12 DACDAT TP7, H1 pin 14 LRC TP8, H1 pin 16 ADCDAT TP9, H1 pin 18 Analogue Inputs IN3R IN2R IN1R IN3L IN2L IN1L MICBIAS TP30, H3: pin 20 TP31, H4: pin 2 TP32, H4: pin 4 TP33, H4: pin 6 TP34, H4: pin 8 TP35, H4: pin 10 TP29, H3 pin 18 Digital microphone interface, signals should swing between DGND and DBVDD. Signals should swing between DGND and DBVDD. All audio interface signals should swing between DGND and DBVDD. Full scale signal swing should not exceed AVDD/3 Vrms. Microphone bias voltage output (0.9 x AVDD) Analogue Outputs HPOUTR HPOUTL HPGND TP16, H2 pin 12 TP18, H2 pin 16 TP17, H2 pin 14 Ground referenced headphone output LINEOUTR LINEOUTL LINEGND TP19, H2 pin 18 TP21, H3 pin 2 TP20, H2 pin 20 Ground referenced line output LOP LON ROP RON TP22, H3 pin 4 TP23, H3 pin 6 TP28, H3 pin 16 TP27, H3 pin 14 HP reference pin, recommended to be connected to the common ground at headphone connector. LINE reference pin, recommended to be connected to the common ground at line output connector. Fully differential line output, Left channel Fully differential line output, Right channel Table 1 I/O Configuration w Customer Information May 2009, Rev 1.1 4 WM8903-6201-FL40-M-REV1 Customer Information BOARD CONFIGURATIONS WITH 6201-EV1-REV2 MAIN BOARD This section focuses on evaluation of the WM8903-6201-FL40-M-REV1 Customer Mini Board in combination with the 6201-EV1-REV2 main board. This system is the reference platform for measurement data contained in this document. Please note that only a limited number of usage modes will be covered. DAC TO HEADPHONE PLAYBACK TO HPOUTL/R The following section details the configuration for DAC to headphone playback to HPOUTL/R. For board configuration, please refer to Figure 3. PATH DIAGRAM Figure 2 Path Diagram (DAC to headphone playback to HPOUTL/R) w Customer Information May 2009, Rev 1.1 5 WM8903-6201-FL40-M-REV1 Customer Information BOARD CONFIGURATION Figure 3 Board Configuration (DAC to Headphone/Line out/Differential Line Out) REGISTER SETTINGS Both sets of register writes are the typical sequence to configure the desired path. Note that the charge pump is required for this configuration. 01 WSQ startup RevC1.txt w Customer Information REG INDEX DATA VALUE 0x00 0x0000 SW Reset 0x15 0x0C08 Clock Rates 1 0x19 0x0002 Audio Interface 1 0x6C 0x0100 Write Sequencer 0 0x16 0x0004 Clock Rates 2 0x6F 0x0100 Write Sequencer 3 COMMENT May 2009, Rev 1.1 6 WM8903-6201-FL40-M-REV1 Customer Information 02 HP playback 0dB.txt REG INDEX DATA VALUE COMMENT 0x43 0x001C Enable DCS on HP outputs ONLY 0x5E 0x0000 Disable Line output amplifiers 0x0F 0x0000 Disable Line output PGAs 0x39 0x0039 Set HPOUTL to 0dB 0x3A 0x00B9 Set HPOUTR to 0dB and perform volume update 0x68 0x0001 Class W dynamic control enable PERFORMANCE PLOT Test conditions: • WM8903-6201-FL40-M-REV1 and 6201-EV1-REV2 PCBs • WM8903 with manufacturing mark code TFP (Rev C1) • Input = SPDIF • Input signal = 997Hz, 24 bit, 256fs (fs = 48kHz) • Output path: jumpers were added to J35 and J36 to link pins 1-2. This applies a 32R load to each headphone output. • Supplies: From USB via voltage regulators on 6201-EV1-REV2 (as per Board configuration diagram) • BW Filter: 20Hz-22kHz • Cyan = Left channel, red = right channel. Audio Precision 05/19/09 15:28:04 +0 -10 -20 -30 -40 d B V -50 -60 -70 -80 -90 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Sweep Trace Color Line Style Thick Data Axis Comment 1 1 1 2 Cyan Red Solid Solid 1 1 Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left 32R output load 32R output load WM8903_SPDIF_DAC_to_HP_OUT_3.5mm_30R.at27 Figure 4 Performance Plot (DAC to headphone playback to HPOUTL/R) w Customer Information May 2009, Rev 1.1 7 WM8903-6201-FL40-M-REV1 Customer Information DAC TO HEADPHONE PLAYBACK TO HPOUTL/R WITH ULTRA-LOW BIAS The following section details the configuration for DAC to headphone playback to HPOUTL/R with Ultra-Low Bias. The path diagram for this configuration is identical to the ‘DAC to headphone playback to HPOUTL/R’ configuration. The key difference is that the bias supplies have been reduced, which improves power consumption with a slight reduction in performance. Board configuration is identical to “DAC to Headphone Playback”, please refer to Figure 3. REGISTER SETTINGS Both sets of register writes are the typical sequence to configure the desired path. Note that the charge pump is required for this configuration. 01 WSQ startup RevC1.txt REG INDEX DATA VALUE 0x00 0x0000 SW Reset 0x15 0x0C08 Clock Rates 1 COMMENT 0x19 0x0002 Audio Interface 1 0x6C 0x0100 Write Sequencer 0 0x16 0x0004 Clock Rates 2 0x6F 0x0100 Write Sequencer 3 02-B Low power HP playback 0dB - Ultra low bias.txt REG INDEX DATA VALUE 0x43 0x001C Enable DCS on HP outputs ONLY 0x5E 0x0000 Disable Line output amplifiers 0x0F 0x0000 Disable Line output PGAs COMMENT 0x39 0x0039 Set HPOUTL to 0dB 0x3A 0x00B9 Set HPOUTR to 0dB and perform volume update 0x68 0x0001 Class W dynamic control enable 0x08 0x000F Bias reduction: Set DACBIAS_SEL to 01 (x0.5) and set DACVMID_BIAS_SEL to 11 (x0.75) 0xAC 0x0030 Set PGABIAS to 011 (x0.5) PERFORMANCE PLOT Test conditions: • WM8903-6201-FL40-M-REV1 and 6201-EV1-REV2 PCBs • WM8903 with manufacturing mark code TFP (Rev C1) • Input = SPDIF • Input signal = 997Hz, 24 bit, 256fs (fs = 48kHz) • Output path: jumpers were added to J35 and J36 to link pins 1-2. This applies a 32R load to each headphone output. • Supplies: From USB via voltage regulators on 6201-EV1-REV2 (as per Board configuration diagram) • BW Filter: 20Hz-22kHz Cyan = Left channel, red = right channel. w Customer Information May 2009, Rev 1.1 8 WM8903-6201-FL40-M-REV1 Customer Information Audio Precision 05/19/09 15:28:49 +0 -10 -20 -30 -40 d B V -50 -60 -70 -80 -90 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Sweep Trace Color Line Style Thick Data Axis Comment 1 1 1 2 Cyan Red Solid Solid 1 1 Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left 32R output Load 32R output Load WM8903_SPDIF_DAC_to_HP_OUT_3.5mm_30R_ultra_low_bias.at27 Figure 5 Performance Plot (DAC to headphone playback to HPOUTL/R with ultra-low bias) DAC TO LINE OUT PLAYBACK TO LINEOUTL/R The following section details the configuration for DAC to line out playback to LINEOUTL/R. Board configuration is identical to “DAC to Headphone Playback”, please refer to Figure 3. PATH DIAGRAM Figure 6 Path Diagram (DAC to line out playback LINEOUTL/R) w Customer Information May 2009, Rev 1.1 9 WM8903-6201-FL40-M-REV1 Customer Information REGISTER SETTINGS Both sets of register writes are the typical sequence to configure the desired path. Note that the charge pump is required for this configuration. 01 WSQ startup RevC1.txt REG INDEX DATA VALUE COMMENT 0x00 0x0000 SW Reset 0x15 0x0C08 Clock Rates 1 0x19 0x0002 Audio Interface 1 0x6C 0x0100 Write Sequencer 0 0x16 0x0004 Clock Rates 2 0x6F 0x0100 Write Sequencer 3 03 LINEOUT playback.txt REG INDEX DATA VALUE 0x0E 0x0000 0x43 0x0013 Enable DC Servo for Line output ONLY 0x5A 0x0000 Disable HP amplifier 0x68 0x0001 Class W dynamic control enable COMMENT Disable HP PGAs (Left and right) PERFORMANCE PLOT Test conditions: • WM8903-6201-FL40-M-REV1 and 6201-EV1-REV2 PCBs • WM8903 with manufacturing mark code TFP (Rev C1) • Input = SPDIF • Input signal = 997Hz, 24 bit, 256fs (fs = 48kHz) • Output path: input impedance of test equipment = 100k. • Supplies: From USB via voltage regulators on 6201-EV1-REV2 (as per Board configuration diagram) • BW Filter: 20Hz-22kHz Cyan = Left channel, red = right channel. w Customer Information May 2009, Rev 1.1 10 WM8903-6201-FL40-M-REV1 Customer Information Audio Precision 05/19/09 14:35:10 -70 -72.5 -75 -77.5 -80 -82.5 -85 d B V -87.5 -90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Sweep Trace Color Line Style Thick Data Axis 1 1 1 2 Cyan Red Solid Solid 1 1 Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left Comment WM8903_SPDIF_DAC_to_LineOut.at27 Figure 7 Performance Plot (DAC to line out playback LINEOUTL/R) DAC TO DIFFERENTIAL LINE OUT PLAYBACK TO LOP-LON/ROP-RON The following section details the configuration for DAC to line out playback to LOP-LON/ROP-RON. For board configuration, please refer to Figure 3.. PATH DIAGRAM Figure 8 Path Diagram (DAC to differential line out playback LOP-LON/ROP-RON) w Customer Information May 2009, Rev 1.1 11 WM8903-6201-FL40-M-REV1 Customer Information REGISTER SETTINGS Both sets of register writes are the typical sequence to configure the desired path. The charge pump is not required for this configuration. 01 WSQ startup RevC1.txt REG INDEX DATA VALUE 0x00 0x0000 SW Reset 0x15 0x0C08 Clock Rates 1 0x19 0x0002 Audio Interface 1 0x6C 0x0100 Write Sequencer 0 0x16 0x0004 Clock Rates 2 0x6F 0x0100 Write Sequencer 3 COMMENT 04 Diff Line outputs (No CP).txt REG INDEX DATA VALUE COMMENT 0x0000 MIXOUTL_ENA=0, MIXOUTR_ENA=0 0x0E 0x0000 HPL_PGA_ENA=0, HPR_PGA_ENA=0 0x0F 0x0000 LINEOUTL_PGA_ENA=0, LINEOUTR_PGA_ENA=0 0x10 0x0003 MIXSPKL_ENA=1, MIXSPKR_ENA=1 0x11 0x0003 SPKL_ENA=1, SPKR_ENA=1 0x34 0x0008 DACL_TO_MIXSPKL=1, DACR_TO_MIXSPKL=0, BYPASSL_TO_MIXSPKL=0, BYPASSR_TO_MIXSPKL=0 0x36 0x0004 DACL_TO_MIXSPKR=0, DACR_TO_MIXSPKR=1, BYPASSL_TO_MIXSPKR=0, BYPASSR_TO_MIXSPKR=0 0x43 0x0000 DCS_MASTER_ENA=0, DCS_ENA=0000 0x0000 HPL_RMV_SHORT=0, HPL_ENA_OUTP=0, HPL_ENA_DLY=0, HPL_ENA=0, HPR_RMV_SHORT=0, HPR_ENA_OUTP=0, HPR_ENA_DLY=0, HPR_ENA=0 0x5E 0x0000 LINEOUTL_RMV_SHORT=0, LINEOUTL_ENA_OUTP=0, LINEOUTL_ENA_DLY=0, LINEOUTL_ENA=0, LINEOUTR_RMV_SHORT=0, LINEOUTR_ENA_OUTP=0, LINEOUTR_ENA_DLY=0, LINEOUTR_ENA=0 0x62 0x0000 Charge Pump Disable: CP_ENA=0 0x3E 0x00B9 SPKL_MUTE=0, SPKVU=1, SPKLZC=0, SPKL_VOL=11_1001 0x3F 0x00B9 SPKR_MUTE=0, SPKVU=1, SPKRZC=0, SPKR_VOL=11_1001 0x0D 0x5A PERFORMANCE PLOT Test conditions: • WM8903-6201-FL40-M-REV1 and 6201-EV1-REV2 PCBs • WM8903 with manufacturing mark code TFP (Rev C1) • Input = SPDIF • Input signal = 997Hz, 24 bit, 256fs (fs = 48kHz) • Output path: input impedance of test equipment = 100k. • Supplies: From USB via voltage regulators on 6201-EV1-REV2 (as per Board configuration diagram) • BW Filter: 20Hz-22kHz Cyan = Left channel, red = right channel. w Customer Information May 2009, Rev 1.1 12 WM8903-6201-FL40-M-REV1 Customer Information Audio Precision 05/19/09 15:29:40 -60 -62 -64 -66 -68 -70 -72 -74 -76 -78 d B V -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 dBFS Sweep Trace Color Line Style Thick Data Axis Comment 1 1 1 2 Cyan Red Solid Solid 1 1 Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left Ref L Ref R WM8903_SPDIF_DAC_to_DIFF_LINE_OUT.at27 Figure 9 Performance Plot (DAC to differential line out playback LOP-LON/ROP-RON) IN1LR TO HP AND LINEOUT (BYPASS) The following section details the configuration for IN1LR bypass path to HP & Line Out. For board configuration, please refer to Figure 11. PATH DIAGRAM Figure 10 Path Diagram w Customer Information May 2009, Rev 1.1 13 WM8903-6201-FL40-M-REV1 Customer Information BOARD CONFIGURATION Left Audio In USB Left Audio In Right Audio In S/PDIF Input Line Out (clocks charge pump) Headphone Out (Either output) Optional headphone load links Figure 11 Board Configuration (IN1LR bypass to headphone/line out) REGISTER SETTINGS Both sets of register writes are the typical sequence to configure the desired path. Note that the charge pump is required for this configuration. 01 WSQ startup RevC1.txt w Customer Information REG INDEX DATA VALUE 0x00 0x0000 SW Reset 0x15 0x0C08 Clock Rates 1 COMMENT 0x19 0x0002 Audio Interface 1 0x6C 0x0100 Write Sequencer 0 0x16 0x0004 Clock Rates 2 0x6F 0x0100 Write Sequencer 3 May 2009, Rev 1.1 14 WM8903-6201-FL40-M-REV1 Customer Information 05B_ IN1LR _HP&LINEOUT(bypass).txt REG INDEX DATA VALUE 0x0C 0x0003 INL_ENA=1, INR_ENA=1 0x2C 0x0005 LINMUTE=0, LIN_VOL=0_0101 0x2D 0x0005 RINMUTE=0, RIN_VOL=0_0101 0x2E 0x0044 INL_CM_ENA=1, L_IP_SEL_N=00, L_IP_SEL_P=01, L_MODE=00 0x2F 0x0044 INR_CM_ENA=1, R_IP_SEL_N=00, R_IP_SEL_P=01, R_MODE=00 0x32 0x0002 DACL_TO_MIXOUTL=0, DACR_TO_MIXOUTL=0, BYPASSL_TO_MIXOUTL=1, BYPASSR_TO_MIXOUTL=0 0x33 0x0001 DACL_TO_MIXOUTR=0, DACR_TO_MIXOUTR=0, BYPASSL_TO_MIXOUTR=0, BYPASSR_TO_MIXOUTR=1 COMMENT IN1LR RECORD TO ADC The following section details board configuration for line input to ADC. For board configuration, please refer to Figure 13. PATH DIAGRAM Figure 12 Path Diagram (IN1LR record to ADC) w Customer Information May 2009, Rev 1.1 15 WM8903-6201-FL40-M-REV1 Customer Information BOARD CONFIGURATION Figure 13 Board Configuration (IN1LR to ADC) w Customer Information May 2009, Rev 1.1 16 WM8903-6201-FL40-M-REV1 Customer Information REGISTER SETTINGS 07 IN1LR _ADC_mode0_256fs_48k.txt Register settings provided below are the typical sequence to configure the desired path. REG INDEX DATA VALUE 0x00 0x0000 SW Reset 0x15 0x0C08 Set clocking: 256fs, fs=48kHz 0x19 0x0002 Set Slave mode 0x16 0x0006 Enable SYSCLK 0x04 0x001B Enable start-up bias 0x05 0x0077 Set VMID 0x0C 0x0003 Enable Analogue Inputs 0x12 0x0003 Enable left and right ADC 0x26 0x0010 Enable ADC high pass filter 0x04 0x001B Enable Master Bias 0x04 0x000B POBCTRL = 0 0x04 0x0009 Disable start-up bias, leave master bias on COMMENT 0x0004 BCLK_DIV=0_0100 0x1B 0x0040 LRCLK_RATE=000_0100_0000 0x2C 0x0005 Un-mute left analogue input 0x2D 0x0005 Un-mute right analogue input 0x2E 0x0044 INL_CM_ENA=1, L_IP_SEL_N=00, L_IP_SEL_P=01, L_MODE=00 0x2F 0x0044 INR_CM_ENA=1, R_IP_SEL_N=00, R_IP_SEL_P=01, R_MODE=00 0x1A PERFORMANCE PLOT Test conditions: • WM8903-6201-FL40-M-REV1 and 6201-EV1-REV2 PCBs • WM8903 with manufacturing mark code TFP (Rev C1) • Input = analog signal to IN1LR. • Clocking, MCLK supplied at 256fs (fs = 48kHz) • Supplies: From USB via voltage regulators on 6201-EV1-REV2 (as per Board configuration diagram) • BW Filter: 20Hz-22kHz Cyan = Left channel, red = right channel. w Customer Information May 2009, Rev 1.1 17 WM8903-6201-FL40-M-REV1 Customer Information Audio Precision 05/19/09 15:30:48 +0 -5 -10 -15 -20 -25 -30 -35 -40 d B F S -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 dBV Sweep Trace Color Line Style Thick Data Axis 1 1 1 2 Cyan Red Solid Solid 1 1 DSP Anlr.THD+N Ampl A DSP Anlr.THD+N Ampl B Left Left Comment WM8903_LINEIN1_to_ADC_(SPDIF).at27 Figure 14 Performance Plot (IN1LR record to ADC) w Customer Information May 2009, Rev 1.1 18 WM8903-6201-FL40-M-REV1 Customer Information APPLICATION SUPPORT If you require more information or require technical support, please contact the Wolfson Microelectronics Applications group through the following channels: Email: Telephone Apps: Fax: Mail: [email protected] +44 (0) 131 272 7070 +44 (0) 131 272 7001 Applications Engineering at the address on the last page or contact your local Wolfson representative. Additional information may be made available on our web site at: http://www.wolfsonmicro.com w Customer Information May 2009, Rev 1.1 19 WM8903-6201-FL40-M-REV1 Customer Information IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 E-mail :: [email protected] w Customer Information May 2009, Rev 1.1 20