90899

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Updated boilerplate. Added device types 09 - 13. Moved endurance
and data retention testing requirements from Section 4 of drawing to
Section 3 of drawing. Editorial changes throughout.
94-03-25
M. A. Frye
B
Updated boilerplate. Added vendor CAGE 01295 as a source of
supply. Editorial changes throughout. - glg
98-04-16
Raymond Monnin
C
Changed standoff width on "U" package. Added vendor CAGE
0EU86 as a source of supply. - glg
99-11-16
Raymond Monnin
D
Boilerplate update and part of five year review. tcr
06-12-21
Raymond Monnin
E
Update drawing to meet current MIL-PRF-38535 requirements. – glg
15-07-27
Charles Saffle
REV
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REV STATUS
REV
E
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OF SHEETS
SHEET
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PMIC N/A
PREPARED BY
Gary L. Gross
DLA LAND AND MARITIME
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
Ray Monnin
APPROVED BY
Michael A. Frye
MICROCIRCUIT, MEMORY, DIGITAL, CMOS
128K X 8-BIT FLASH EEPROM, MONOLITHIC
SILICON
DRAWING APPROVAL DATE
92-08-31
REVISION LEVEL
E
SIZE
A
SHEET
DSCC FORM 2233
APR 97
CAGE CODE
67268
1 OF
5962-90899
24
5962-E404-15
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
90899
01
Q
X
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
02
03
04
05
06
07
08
09
10
11
12
13
28F010
28F010
28F010
28F010
28F010
28F010
28F010
28F010
28F010
28F010A
28F010A
28F010A
28F010A
Circuit function
Access time
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
(128 K x 8) CMOS flash EEPROM
250 ns
200 ns
150 ns
120 ns
250 ns
200 ns
150 ns
120 ns
90 ns
250 ns
200 ns
150 ns
120 ns
Endurance
10,000 cycles
10,000 cycles
10,000 cycles
10,000 cycles
1,000 cycles
1,000 cycles
1,000 cycles
1,000 cycles
10,000 cycles
100,000 cycles
100,000 cycles
100,000 cycles
100,000 cycles
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
T
U
X
Y
Z
Descriptive designator
See figure 1
See figure 1
GDIP1-T32 or CDIP2-T32
CQCC1-N32
See figure 1
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
Terminals
32
32
32
32
32
Package style
"J" lead chip carrier
Flat pack
Dual-in-line
Rectangular leadless chip carrier
Gullwing lead chip carrier
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
2
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings. 1/
Endurance:
Device types 01-04, 09 ............................................................................ 10,000 cycles/byte, minimum
Device types 05-08 .................................................................................. 1,000 cycles/byte, minimum
Device types 10-13 .................................................................................. 100,000 cycles/byte, minimum
Supply voltage range (VCC) 2/ .................................................................... -2.0 V dc to +7.0 V dc
Storage temperature range (Tstg) ................................................................ -65°C to +150°C
Maximum power dissipation (PD) ................................................................ 1.0 W
Lead temperature (soldering, 10 seconds) ................................................. +300°C
Junction temperature (TJ) 3/ ...................................................................... +150°C
Thermal resistance, junction-to-case (ΘJC) (case outline X, Y) ................... See MIL-STD-1835
Thermal resistance, junction-to-case (ΘJC) (case outlines T, Z).................. 13°C/W
Thermal resistance, junction-to-case (ΘJC) (case outline U) ....................... 27°C/W
Voltage on any pin with respect to ground 2/ ............................................. -2.0 V dc to +7.0 V dc
Voltage on pin A9 with respect to ground 4/ ............................................... -2.0 V dc to +13.5 V dc
VPP supply voltage with respect to ground 4/ ............................................. -2.0 V dc to +14.0 V dc
VCC supply voltage with respect to ground 2/ ............................................. -2.0 V dc to +7.0 V dc
Output short circuit current 5/ ..................................................................... 200 mA
Data retention ............................................................................................. 10 years minimum
1.4 Recommended operating conditions.
Supply voltage range (VCC) ......................................................................... +4.5 V dc to +5.5 V dc
Operating temperature range (Tcase) ........................................................... -55°C to +125°C
Low level input voltage range (VIL) .............................................................. -0.5 V dc to +0.8 V dc
High level input voltage range (VIH) ............................................................ +2.0 V dc to VCC +0.5 V dc
High level input voltage range, CMOS (VIH) ................................................ VCC -0.5 V dc to VCC +0.5 V dc
Chip clear (VP) ............................................................................................ 11.4 V dc to 12.6 V dc
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, method 5012) .................................................. 100 percent
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Minimum dc voltage on input or VO pins is -0.5 V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods
of up to 20 ns. Maximum dc voltage on output and VO pins is VCC +0.5 V. During voltage transitions outputs may overshoot
to VCC +2.0 V for periods up to 20 ns.
3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
4/ Minimum dc input voltage on A9 or VPP may overshoot to +14.0 V for periods less than 20 ns.
5/ No more than one output shorted at a time. Duration of short circuit should not be greater than 1 second.
6/ All voltages are referenced to VSS (ground).
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JESD 78
-
IC Latch-Up Test.
(Copies of this document are available on line at http://www.jedec.org or from JEDEC - Solid State Technology Association,
3103 North 10th Street, Suite 247, Arlington, VA 22201)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
4
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table. The truth table shall be as specified on figure 3.
3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing
shall be as specified on figure 3 herein. When required, in screening (see 4.2 herein), or quality conformance inspection groups
A, B, C, or D (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test in a checkerboard or similar
pattern (a minimum of 50 percent of the total number of bits programmed).
3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this document.
3.2.3.3 Command definitions. The command definitions table shall be as specified on figure 3.
3.2.4 Switching test circuits and waveforms. The switching test circuits and waveforms shall be as specified on figure 4.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. Marking for device classes Q and V shall be in accordance with MILPRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of
supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MILPRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of
product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C 1/
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Min
Units
Max
DC CHARACTERISTICS
Input leakage
current
ILI
VCC = VCC max,
VIN = VCC max or VSS
1, 2, 3
All
±1.0
μA
Output leakage
current
ILO
VCC = VCC max,
VOUT = VCC max or VSS
1, 2, 3
All
±10
μA
VCC standby
current (TTL)
ICCS1
VCC = VCC max, CE = VIH
1, 2, 3
All
1.0
mA
VCC standby
current (CMOS)
ICCS2
CE = VCC ±0.2 V,
VCC = VCC max
1, 2, 3
All
100
μA
VCC active read
current
ICC1
VCC = VCC max, CE = VIL
IOUT = 0 mA, f = 6.0 MHz,
1, 2, 3
All
30
mA
OE = VIH
VCC programming
current
ICC2
CE = VIL, programming in
progress
1, 2, 3
All
30 2/
mA
VCC erase
current
ICC3
CE = VIL, erasure in progress
1, 2, 3
All
30 2/
mA
VPP standby
current
IPPS
VPP = VPPL
1, 2, 3
All
±10
μA
VPP read current
IPP1
VPP = VPPH
1, 2, 3
All
200
μA
VPP = VPPL
VPP programming
current
IPP2
±10
VPP = VPPH, programming in
progress
1, 2, 3
All
30 2/
mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
6
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C 1/
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Min
Units
Max
DC CHARACTERISTICS - Continued
VPP erase current
IPP3
Low level input
voltage
VPP = VPPH erasure in progress
1, 2, 3
All
30 2/
mA
VIL
1, 2, 3
All
-0.5 2/
0.8
V
High level input
voltage (TTL)
VIH1
1, 2, 3
All
2.0
VCC+ 0.5
2/
V
High level input
voltage (CMOS)
VIH2
1, 2, 3
All
0.7 VCC
VCC+ 0.5
2/
V
Low level output
voltage
VOL
IOL = 2.1 mA, VCC = VCC min
1, 2, 3
All
0.45
V
High level output
voltage (TTL)
VOH1
IOH = -2.5 mA, VCC = VCC min
1, 2, 3
All
High level output
voltage (CMOS)
VOH2
IOH = -2.5 mA, VCC = VCC min
1, 2, 3
All
VOH3
IOH = -100 μA, VCC = VCC min
A9 auto select
voltage
VID
A9 = VID
1, 2, 3
All
A9 auto select
current
IID
A9 = VID max, VCC = VCC max
1, 2, 3
All
VPP during read
only operations
VPPL
NOTE: erase/program are
inhibited when VPP = VPPL
1, 2, 3
All
VPP during read/write
operations
VPPH
1, 2, 3
All
7, 8A, 8B
All
Functional tests
See 4.4.1d
2.4
V
0.85 VCC
V
VCC- 0.4
2/
V
11.5
13.0
V
500 2/
μA
0
VCC+ 2.0
2/
V
11.4
12.6
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
7
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C 1/
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Min
Units
Max
CAPACITANCE 2/
Input capacitance
CIN1
VIN = 0 V, TA = 25°C,
f = 1.0 Mhz, see 4.4.1c
4
All
10
pF
Output capacitance
COUT
VOUT = 0 V, TA = 25°C,
f = 1.0 Mhz, see 4.4.1c
4
All
12
pF
VPP input capacitance
CIN2
VIN = 0 V, TA = 25°C,
f = 1.0 Mhz, see 4.4.1c
4
All
12
pF
AC CHARACTERISTICS - READ ONLY OPERATIONS (See figure 5 as applicable.)
Read cycle time
Chip enable access
time
Address access
time
tAVAV
2/
tELQV
tAVQV
9, 10, 11
9, 10, 11
9, 10, 11
01,05,10
250
02,06,11
200
03,07,12
150
04,08,13
120
09
90
ns
01,05,10
250
02,06,11
200
03,07,12
150
04,08,13
120
09
90
01,05,10
250
02,06,11
200
03,07,12
150
04,08,13
120
09
90
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
8
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C 1/
4.5 V ≤ VCC ≤ 5.5 V
unless otherwise specified
Group A
Subgroups
Device
type
Limits
Min
Units
Max
AC CHARACTERISTICS - READ ONLY OPERATIONS - Continued. (See figure 5 as applicable.)
Output enable
access time
tGLQV
Chip enable to
output in low Z
tELQX
Chip disable to
output in high Z
tEHQZ
Output enable to
output in low Z
tGLQX
Output disable to
output in high Z
tGHQZ
Output hold from
address, CE , or
OE change
tAXQX
Write recovery
time before read
tWHGL
9, 10, 11
2/
2/
3/
01,05
65
02,06
60
03,07,10,
11,12
55
04,08,13
50
09
40
9, 10, 11
All
9, 10, 11
All
9, 10, 11
All
9, 10, 11
01,05
60
02,06
45
03,07,10,
11,12
35
04,08,09,
13
30
ns
ns
0 2/
55
ns
0 2/
ns
ns
9, 10, 11
All
0 2/
ns
9, 10, 11
All
6.0
μs
ERASE AND PROGRAMMING PERFORMANCE
Chip erase
Excludes 00H programming
9, 10, 11
All
60
s
Chip program
Excludes system overhead 4/
9, 10, 11
All
24
s
1/ Case temperatures are instant on.
2/ Parameters shall be tested as part of device initial characterization and after design and process change. Parameter
shall be guaranteed to the limits specified in table I for all lots not specifically tested.
3/ Whichever occurs first.
4/ Minimum byte programming time excluding system overhead is 16 μs (10 μs programming +6.0 μs write recovery), while
maximum is 400 μs/byte (16 μs x 25 loops allowed by algorithm). Maximum chip programming time is specified lower than
the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
9
3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime's agent,
and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore
documentation shall be made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 41 (see MIL-PRF-38535, appendix A).
3.11 Processing of EEPROMs. All testing requirements and quality assurance provisions herein shall be satisfied by the
manufacturer prior to delivery.
3.11.1 Conditions of the supplied devices. Devices will be supplied in an unprogrammed or clear state. No provision will be
made for supplying programmed devices.
3.11.2 Erasure of EEPROMs. When specified, devices shall be erased in accordance with procedures and characteristics
specified in 4.5.1.
3.11.3 Programming of EEPROMs. When specified, devices shall be programmed in accordance with procedures and
characteristics specified in 4.5.2.
3.11.4 Verification of state of EEPROMs. When specified, devices shall be verified as either written to the specified pattern
or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper
state. Any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be removed from
the lot or sample.
3.12 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitors, this
reprogrammability test shall be done only for initial characterization and after any design or process changes which may affect
the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of
program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendor's procedure
shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with
test data.
3.13 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall
be done for initial characterization and after any design or process change which may affect data retention. The methods and
procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military
temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of
the acquiring or preparing activity, along with test data.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
10
Case T
NOTE: Metric equivalents are given in parenthesis.
Symbol
Inches
Millimeters
Min
Max
Min
Max
Notes
A
.057
.080
1.45
2.03
A1
.122
.159
3.10
4.04
Solid lid
A2
.010
.014
0.25
0.36
Solid lid
A3
.055
.065
1.38
1.65
φB
.014
.018
0.36
0.46
CP
.000
.004
0.00
0.10
D
.540
.565
13.72
14.35
D1
.400
D2
E
10.16
.500
Reference
12.70
.440
.464
11.17
11.79
E1
.300
7.62
E2
.400
10.16
Reference
e
.043
.057
1.09
1.45
R
0.027
0.033
0.68
0.84
N
Typical
32
FIGURE 1. Case outlines.
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Case U
Inches
.001
.002
.005
.006
.008
.017
.020
.034
mm
0.03
0.05
0.13
0.15
0.20
0.43
0.51
0.86
Inches mm
.040
1.02
.045
1.15
.050
1.27
.132
3.35
.295
7.49
.280
7.11
.410 10.41
.820 20.83
NOTES:
1. Terminal one shall be identified by a mechanical index on the lead or body, or a mark on the top surface within the
region shown.
2. Terminal identification numbers need not appear on the package.
3. Weight: 1.5 g maximum.
4. Dimensions are in inches.
5. Metric equivalents are given for general information only.
FIGURE 1. Case outlines - Continued.
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Case Z
Family: Ceramic leadless chip carrier
Inches
Millimeters
Symbol
Min
Max
Min
Max
A
.057
.080
1.45
2.03
A1
.122
.159
3.10
4.04
Solid lid
A2
.010
.014
0.25
0.36
Solid lid
A3
.055
.065
1.40
1.65
B
.014
.018
0.36
0.46
CP
.000
.004
0.00
0.10
D
.670
D1
D2
17.01
.400
10.16
.540
.560
E
Reference
13.71
14.22
.570
E1
Notes
14.49
.300
7.62
E2
.440
.460
e
.043
.057
N
Reference
11.18
11.68
1.09
1.45
Typical
32
FIGURE 1. Case outlines - Continued.
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Device types
All
Case outlines
All
Terminal number
Terminal symbol
1
VPP
2
A16
3
A15
4
A12
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
DQ0
14
DQ1
15
DQ2
16
VSS
17
DQ3
18
DQ4
19
DQ5
20
DQ6
21
DQ7
22
CE
23
A10
24
OE
25
A11
26
A9
27
A8
28
A13
29
A14
30
NC
31
WE
32
VCC
FIGURE 2. Terminal connections.
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Bus operations
Pins
Read only
Read/write
1/
2/
3/
4/
5/
VPP 1/
A0
A9
CE
OE
WE
DQ0 - DQ7
Operation
Read
VPPL
A0
A9
VIL
VIL
VIH
Data out
Output disable
VPPL
X 2/
X 2/
VIL
VIH
VIH
3-state
Standby
VPPL
X 2/
X 2/
VIH
X 2/
X 2/
3-state
Auto-select manufacturer
code 3/
VPPL
VIL
VID 4/
VIL
VIL
VIH
5/
Auto-select device code 3/
VPPL
VIH
VID 4/
VIL
VIL
VIH
6/
Read
VPPH
A0
A9
VIL
VIL
VIH
Data out 7/
Output disable
VPPH
X 2/
X 2/
VIL
VIH
VIH
3-state
Standby 8/
VPPH
X 2/
X 2/
VIH
X 2/
X 2/
3-state
Write
VPPH
A0
A9
VIL
VIH
VIL
Data in 9/
Refer to dc characteristics. When VPP = VPPL memory contents can be read but not written or erased.
X can be VIL or VIH.
Manufacture and device code may also be accessed via a command register write sequence.
VID is the auto select high voltage. Refer to dc characteristics.
The output for DQ0 - DQ7 shall be as follows:
DQ0 - DQ7
DATA = 89H
DATA = 01H
6/
The output for DQ0 - DQ7 shall be as follows:
DQ0 - DQ7
DATA = B4H (device types 01-09, 11-13)
DATA = A7H (device types 01-09)
DATA = A2H (device types 10-13)
7/
8/
9/
Read operations with VPP = VPPH may access array data or the auto select codes.
With VPP at high voltage, the standby current equals ICC + IPP (standby).
Refer to command definitions for valid Data-In during a write operation.
FIGURE 3. Truth tables.
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Command definitions, device types 01-09
Command
BUS
cycles
required
First BUS cycle
Second BUS cycle
Operation
1/
Address
2/
Data
3/
Operation
1/
Address
2/
Data
3/
Read memory
1
Write
X
00H/FFH
Read
RA
RD
Read auto select codes 4/
2
Write
X
90H/80H
Read
IA
ID
Setup erase/erase
2
Write
X
20H
Write
X
20H
Erase verify
2
Write
EA
A0H
Read
X
EVD
Setup program/program
2
Write
X
40H
Write
PA
PD
Program verify
2
Write
X
C0H
Read
X
PVD
Reset 5/
2
Write
X
FFH
Write
X
FFH
1/ Refer to BUS operations for definitions.
2/ RA = Address of the memory location to be read.
IA = Identifier address: 00H/01H for manufacturer code, 01H/A7H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Address is latched on the falling edge of the write-enable pulse.
3/ RD = Data read from location RA during read operation.
ID = Data read from location IA during device identification.
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write-enable.
PVD = Data read from location PA during program verify. PA is latched on the program command.
4/ Following the read Auto Select code ID command, two read operations access manufacturer and device codes.
5/ The second bus cycle must be followed by the desired command register write.
Command definitions, device types 10-13
Command
BUS
cycles
required
First BUS cycle
Second BUS cycle
Operation
1/
Address
2/
Data
3/
Operation
1/
Address
2/
Data
3/
Read memory
1
Write
X
00H/FFH
Read
RA
RD
Read auto select codes 4/
3
Write
X
80H/90H
Read
00H/01H
01H/A2H
Embedded erase setup/erase
2
Write
X
30H
Write
X
30H
Embedded program
setup/program
2
Write
X
10H/50H
Write
PA
PD
Reset 5/
2
Write
X
FFH
Write
X
FFH
1/ Refer to BUS operations for definitions.
2/ RA = Address of the memory location to be read.
PA = Address of memory location to be programmed.
Address are latched on the falling edge of the WE pulse.
3/ RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE .
4/ Following the read Auto Select code ID command, two read operations access manufacturer and device codes.
5/ The second bus cycle must be followed by the desired command register write.
FIGURE 3. Truth tables - Continued.
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AC testing: Inputs are driven at 2.4 V for a
logic "1" and 0.45 V for a logic "0". Input pulse
rise and fall times are ≤ 10 ns.
FIGURE 4. Switching test circuits and waveforms.
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AC waveforms for read operations
FIGURE 4. Switching test circuits and waveforms - Continued.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)
electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b.
Prior to burn-in, the devices shall be programmed (see 4.5.2 herein) with a checkerboard pattern or equivalent
(manufacturers at their option may employ an equivalent pattern provided it is a topologically true alternating bit
pattern). The pattern shall be read before and after burn-in. Devices having bits not in the proper state after burn-in
shall constitute a device failure and shall be included in the Percent Defective Allowable (PDA) calculation and shall be
removed from the lot.
c.
The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1)
Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1c herein).
d.
Interim and final electrical parameters shall be as specified in table IIA herein.
e.
After the completion of all screening, the device shall be erased and verified prior to delivery.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B and as detailed in table IIB herein.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of
MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in
accordance with MIL-PRF-38535, appendix A and as specified herein (see 3.1). Inspections to be performed for device class M
shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through
4.4.4).
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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Line
no.
Test
requirements
Subgroups
(per method
5005, table I)
Subgroups
(per MIL-PRF-38535,
table III)
Device
class
M
1/
2/
3/
4/
5/
6/
7/
Device
class
Q
Device
class
V
1,7,9
or
2,8A,10
1,7,9
or
2,8A,10
Not
required
Not
required
1
Interim electrical
parameters
(see 4.2)
2
Static burn-in I
method 1015
3
Same as line 1
4
Dynamic burn-in
(method 1015)
5
Same as line 1
6
Final electrical
parameters
1*,2,3,7*,
8A,8B,9,10,
11
1*,2,3,7*,
8A,8B,9,10,
11
1*,2,3,7*,
8A,8B,9,10,
11
7
Group A test
requirements
1,2,3,4**,7,8A,
8B,9,10,
11
1,2,3,4**,7,
8A,8B,9,10,
11
1,2,3,4**,7,
8A,8B,9,10,
11
8
Group C end-point
electrical
parameters
2,8A,10
1,2,3,7
8A,8B
1,2,3,7,
8A,8B,9,10,
11 Δ
9
Group D end-point
electrical
parameters
2,8A,10
2,3,7
8A,8B
2,3,7
8A,8B
10
Group E end-point
electrical
parameters
1,7,9
1,7,9
1,7,9
Not
required
1*,7* Δ
Required
Required
Required
1*,7* Δ
Blank spaces indicate test are not applicable.
Any or all subgroups may be combined when using high-speed testers.
Subgroups 7 and 8 functional tests shall verify the truth table.
* Indicates PDA applies to subgroups 1 and 7.
** See 4.4.1c.
Δ Indicates delta limit (see table IIB) shall be required where specified, and the delta values
shall be computed with reference to the previous interim electrical parameters (see line 1).
See 4.4.1e.
4.4.1 Group A inspection.
a.
b.
Tests shall be as specified in table IIA herein.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
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c.
Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the designated
terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output
terminals tested.
d.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device, these tests shall have been fault graded in
accordance with MIL-STD-883, method 5012 (see 1.5 herein).
e.
O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JESD 78 may be used for reference.
f.
All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all
testing, the devices shall be erased and verified, (except devices submitted for groups B, C, and D testing).
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M.
a.
Steady-state life test conditions, method 1005 of MIL-STD-883:
(1)
The device selected for testing shall be programmed with a checkerboard pattern. After completion of all testing, the
devices shall be erased and verified (except devices submitted for group D testing).
(2)
Test condition D or E. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005.
(3)
TA = +125°C, minimum.
(4)
Test duration: 1,000 hours, except as specified in method 1005 of MIL-STD-883.
b.
All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit
pattern.
c.
After the completion of all testing, the devices shall be cleared and verified prior to delivery.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
The devices selected for testing shall be programmed with a checkerboard pattern. After completion of all testing, the devices
shall be erased and verified.
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TABLE IIB. Delta limits at 25°C.
Test 1/
Device types
All
ICCS2
standby
±10 percent of specified value
in table I.
ILI
±10 percent of specified value
in table I.
ILO
±10 percent of specified value
in table I.
1/ The above parameter shall be recorded before and after
the required burn-in and life tests to determine delta.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table IIA herein.
4.5 Methods of inspection. Methods of inspection shall be as specified in the appropriate figures and tables as follows.
4.5.1 Erasing procedures. The erasing procedures shall be as specified by the device manufacturer and shall be available
upon request.
4.5.2 Programming procedure. The programming procedures shall be as specified by the device manufacturer and shall be
made available upon request.
4.6 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and
9.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
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6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF38535, MIL-STD-1331, and as follows:
CIN, COUT ..................................
GND .........................................
ICC ............................................
IIL ..............................................
IIH .............................................
TC .............................................
TA .............................................
VCC ...........................................
VH .............................................
O/V ...........................................
Input and bidirectional output, terminal-to-GND capacitance.
Ground zero voltage potential.
Supply current.
Input current low.
Input current high.
Case temperature.
Ambient temperature.
Positive supply voltage.
Output enable and Write enable voltage during chip erase.
Latchup over-voltage.
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the
system must supply at least that much time (even though most devices do not require it). On the other hand, responses from
the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never
provides data later than that time.
6.5.2 Timing parameter abbreviations. All timing abbreviations use lower case characters with upper case subscripts. The
initial character is always "t" and is followed by four descriptors. These characters specify two signal points arranged in a "fromto" sequence that define a timing interval. The two descriptors for each signal specify the signal name and the signal transition.
Thus the format is:
t
Signal name from which interval is defined
Transition direction for first signal
X



X





X







Signal name to which interval is defined
Transition direction for second signal
a.
Signal definitions:
A = Address
D = Data in
Q = Data out
W = Write enable
E = Chip enable
G = Output enable
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b.
X









Transition definitions:
H = Transition to high
L = Transition to low
V = Transition to valid
X = Transition to invalid or don't care
Z = Transition to off (high impedance)
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6.5.3 Waveforms.
WAVEFORM
SYMBOL
INPUT
OUTPUT
MUST BE VALID
WILL BE VALID
CHANGE FROM
H TO L
WILL CHANGE FROM
H TO L
CHANGE FROM
L TO H
WILL CHANGE FROM
L TO H
DON'T CARE ANY
CHANGE
PERMITTED
CHANGING STATE
UNKNOWN
HIGH IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535
and MIL-HDBK-103. The vendors listed in QML-38535 and MIL-HDBK-103 have submitted a certificate of compliance (see 3.6
herein) to DLA Land and Maritime-VA and have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DLA Land and Maritime-VA.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-90899
A
REVISION LEVEL
E
SHEET
24
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 15-07-27
Approved sources of supply for SMD 5962-90899 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
5962-9089901QXA
5962-9089901MXA
5962-9089901QYA
5962-9089901MYA
5962-9089901MTA
5962-9089901MZA
5962-9089901QUA
5962-9089901MUA
5962-9089902QXA
5962-9089902MXA
5962-9089902QYA
5962-9089902MYA
5962-9089902MTA
5962-9089902MZA
5962-9089902QUA
5962-9089902MUA
5962-9089903QXA
5962-9089903MXA
5962-9089903QYA
5962-9089903MYA
5962-9089903MTA
5962-9089903MZA
5962-9089903QUA
5962-9089903MUA
5962-9089904QXA
5962-9089904MXA
5962-9089904QYA
5962-9089904MYA
5962-9089904MTA
5962-9089904MZA
5962-9089904QUA
5962-9089904MUA
Vendor
CAGE
number
Vendor
similar
PIN 2/
57300
3/
3/
57300
3/
3/
3/
3/
57300
3/
SMJ28F010B-25JDDM
AM28F010-250/BXA
MD28F010-25/B
SMJ28F010B-25FEM
AM28F010-250/BUA
MR28F010-25/B
MT28F010-25/B
MZ28F010-25/B
SMJ28F010B-25HKM
MF28F010-25/B
57300
3/
3/
57300
3/
3/
3/
3/
57300
3/
SMJ28F010B-20JDDM
AM28F010-200/BXA
MD28F010-20/B
SMJ28F010B-20FEM
AM28F010-200/BUA
MR28F010-20/B
MT28F010-20/B
MZ28F010-20/B
SMJ28F010B-20HKM
MF28F010-20/B
57300
3/
3/
57300
3/
3/
3/
3/
57300
3/
SMJ28F010B-15JDDM
AM28F010-150/BXA
MD28F010-15/B
SMJ28F010B-15FEM
AM28F010-150/BUA
MR28F010-15/B
MT28F010-15/B
MZ28F010-15/B
SMJ28F010B-15HKM
MF28F010-15/B
57300
3/
3/
57300
3/
3/
3/
3/
57300
3/
SMJ28F010B-12JDDM
AM28F010-120/BXA
MD28F010-12/B
SMJ28F010B-12FEM
AM28F010-120/BUA
MR28F010-12/B
MT28F010-12/B
MZ28F010-12/B
SMJ28F010B-12HKM
MF28F010-12/B
See footnotes at end of table.
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STANDARD MICROCIRCUIT DRAWING BULLETIN – continued.
DATE: 15-07-27
Standard
microcircuit drawing
PIN 1/
5962-9089905QXA
5962-9089905MXA
5962-9089908MTA
5962-9089908MZA
5962-9089908QUA
5962-9089908MUA
Vendor
CAGE
number
57300
3/
3/
57300
3/
3/
3/
3/
57300
3/
57300
3/
3/
57300
3/
3/
3/
3/
57300
3/
57300
3/
3/
57300
3/
3/
3/
3/
57300
3/
57300
3/
3/
57300
3/
3/
3/
3/
57300
3/
Vendor
similar
PIN 2/
SMJ28F010B-25JDDM
AM28F010-250C3/BXA
MD28F010-25/B
SMJ28F010B-25FEM
AM28F010-250C3/BUA
MR28F010-25/B
MT28F010-25/B
MZ28F010-25/B
SMJ28F010B-25HKM
MF28F010-25/B
SMJ28F010B-20JDDM
AM28F010-200C3/BXA
MD28F010-20/B
SMJ28F010B-20FEM
AM28F010-200C3/BUA
MR28F010-20/B
MT28F010-20/B
MZ28F010-20/B
SMJ28F010B-20HKM
MF28F010-20/B
SMJ28F010B-15JDDM
AM28F010-150C3/BXA
MD28F010-15/B
SMJ28F010B-15FEM
AM28F010-150C3/BUA
MR28F010-15/B
MT28F010-15/B
MZ28F010-15/B
SMJ28F010B-15HKM
MF28F010-15/B
SMJ28F010B-12JDDM
AM28F010-120C3/BXA
MD28F010-12/B
SMJ28F010B-12FEM
AM28F010-120C3/BUA
MR28F010-12/B
MT28F010-12/B
MZ28F010-12/B
SMJ28F010B-12HKM
MF28F010-12/B
5962-9089909MXA
5962-9089909MYA
5962-9089909MTA
5962-9089909MZA
5962-9089909MUA
5962-9089910QXA
5962-9089910MXA
5962-9089910QYA
5962-9089910MYA
5962-9089910QUA
3/
3/
3/
3/
3/
57300
3/
57300
3/
57300
MD28F010-90/B
MR28F010-90/B
MT28F010-90/B
MZ28F010-90/B
MF28F010-90/B
SMJ28F010B-25JDDM
AM28F010A-250/BXA
SMJ28F010B-25FEM
AM28F010A-250/BUA
SMJ28F010B-25HKM
5962-9089905QYA
5962-9089905MYA
5962-9089905MTA
5962-9089905MZA
5962-9089905QUA
5962-9089905MUA
5962-9089906QXA
5962-9089906MXA
5962-9089906QYA
5962-9089906MYA
5962-9089906MTA
5962-9089906MZA
5962-9089906QUA
5962-9089906MUA
5962-9089907QXA
5962-9089907MXA
5962-9089907QYA
5962-9089907MYA
5962-9089907MTA
5962-9089907MZA
5962-9089907QUA
5962-9089907MUA
5962-9089908QXA
5962-9089908MXA
5962-9089908QYA
5962-9089908MYA
See footnotes at end of table.
2 of 3
STANDARD MICROCIRCUIT DRAWING BULLETIN – continued.
DATE: 15-07-27
Standard
microcircuit drawing
PIN 1/
5962-9089911QXA
5962-9089911QYA
5962-9089911MXA
5962-9089911MYA
5962-9089911QUA
5962-9089912QXA
5962-9089912QYA
5962-9089912MXA
5962-9089912MYA
5962-9089912QUA
5962-9089913QXA
5962-9089913QYA
5962-9089913MXA
5962-9089913MYA
5962-9089913QUA
Vendor
CAGE
number
57300
57300
3/
3/
57300
57300
57300
3/
3/
57300
57300
57300
3/
3/
57300
Vendor
similar
PIN 2/
SMJ28F010B-20JDDM
SMJ28F010B-20FEM
AM28F010A-200/BXA
AM28F010A-200/BUA
SMJ28F010B-20HKM
SMJ28F010B-15JDDM
SMJ28F010B-15FEM
AM28F010A-150/BXA
AM28F010A-150/BUA
SMJ28F010B-15HKM
SMJ28F010B-12JDDM
SMJ28F010B-12FEM
AM28F010A-120/BXA
AM28F010A-120/BUA
SMJ28F010B-12HKM
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that part.
If the desired lead finish is not listed contact the vendor to determine
its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired to
this number may not satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
57300
Vendor name
and address
Manufacturer
code
Micross Components
7725 North Orange Blossom Trail
Orlando, FL 32810-2696
97
Device
code
B4H
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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