REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated boilerplate. Added device type 03 to drawing. Changed tAPW minimum limits from 75ns and 100 ns to the quantity tRP + tCK. Removed all references to nBSD from drawing. - glg 98-01-20 Raymond Monnin B Changes in accordance with NOR 5962-R071-98. - glg 98-03-19 Raymond Monnin C Changes to paragraph 1.3 and 1.4. Table IA changes to IL, IO, ICC2N, ICC3P, ICC3PS, ICC3N, ICC4, and ICC5. Removed number of cycles table from Table IA, sheet 12. - glg 99-03-16 Raymond Monnin D Change CAGE code to correct CAGE of 67268. Update to current boilerplate. Editorial changes throughout. - gap 02-04-02 Raymond Monnin E Boilerplate update and part of five-year review. tcr 07-12-13 Robert M. Heber F Update drawing to meet current MIL-PRF-38535 requirements. - glg 16-05-09 Charles Saffle REV F F F F F F F F F F F F F F F F SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 REV F F F F F F F F F F F F F F F F F F F F SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil Gary L. Gross STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Jeff Bowling APPROVED BY Raymond Monnin DRAWING APPROVAL DATE 97-06-17 REVISION LEVEL F MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512K x 16-BIT x 2-BANK, SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM), MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-97545 SHEET 1 OF DSCC FORM 2233 APR 97 50 5962-E338-16 1. SCOPE 1.1 Scope. This drawing documents three product assurance class levels consisting of space application (device class V), high reliability (device class Q), and nontraditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment. 1.2 PIN. The PIN is as shown in the following example: 5962 | | | Federal stock class designator \ | | | RHA designator (see 1.2.1) 97545 01 | | | Device type (see 1.2.2) / Q | | | Device class designator (see 1.2.3) X | | | Case outline (see 1.2.4) A | | | Lead finish (see 1.2.5) \/ Drawing number 1.2.1 RHA designator. Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 02 03 626162-15 626162-20 626162-12 512K word x 16 bit x 2 bank, synchronous DRAM 512K word x 16 bit x 2 bank, synchronous DRAM 512K word x 16 bit x 2 bank, synchronous DRAM 15 ns 20 ns 12 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation N Certification and qualification to MIL-PRF-38535 with a nontraditional performance environment (encapsulated in plastic) Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Y Descriptive designator See figure 1 See figure 1 Terminals 50 50 Package style Ceramic dual flat pack Plastic TSOP(II) package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes N, Q, and V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 2 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range, (VCC) .................................................................................. Supply voltage range for output drivers, (VCCQ) .................................................... Voltage range on any input pin ............................................................................. Voltage range on any output pin ........................................................................... Short-circuit output current .................................................................................... Power dissipation .................................................................................................. Operating free-air temperature range, (TA) ........................................................... Storage temperature range, (Tstg) ......................................................................... Junction temperature, (TJ) .................................................................................... Thermal resistance, junction-to-case, (JC): Case X .............................................................................................................. Case Y .............................................................................................................. -0.5 V dc to +4.6 V dc -0.5 V dc to +4.6 V dc -0.5 V dc to +4.6 V dc -0.5 V dc to VCC +0.5 V dc 50 mA 1W -55C to +125C -65C to +150C +175C +5C/W +1C/W 1.4 Recommended operating conditions. 2/ Supply voltage range, (VCC) .................................................................................. Supply voltage for output drivers, (VCCQ) .............................................................. Supply voltage, (VSS) ............................................................................................ Supply voltage for output drivers, (VSSQ) ............................................................... High-level input voltage, (VIH) ............................................................................... Low-level input voltage, (VIL) ................................................................................. Operating free-air temperature, (TA) ..................................................................... +3.135 V dc to +3.465 V dc +3.135 V dc to +3.465 V dc 3/ 0 V dc 0 V dc +2.0 V dc to VCC +0.3 V dc -0.3 V dc to +0.8 V dc -55C to +125C 1.5 Digital logic testing for device classes N, Q, and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, method 5012) ................................................................ 100 percent 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's). MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) ________ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltage values in this drawing are with respect to VSS. 3/ VCCQ VCC +0.3 V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 3 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC Solid State Technology Association (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107; http://www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with MILPRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes N, Q, and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.4 Output load circuit. The output load circuit shall be as specified on figure 4. 3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5. 3.2.6 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device class Q and V, alternate test patterns shall be under the control of the device manufacturer’s Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 4 3.5.1 Certification/compliance mark. The certification mark for device classes N, Q, and V shall be a "QML" or "Q" as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes N, Q, and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes N, Q, and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes N, Q, and V in MIL-PRF-38535. 4. VERIFICATION 4.1 Sampling and inspection. For device classes N, Q, and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. For device classes N, Q, and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device classes N, Q, and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MILPRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF38535, appendix B. 4.3 Qualification inspection for device classes N, Q, and V. Qualification inspection for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes N, Q, and V shall be in accordance with MILPRF-38535 including groups A, B, C, D, and E inspections and as specified. 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted. c. For device classes N, Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been fault graded in accordance with MIL-STD-883, method 5012 (see 1.5 herein). d. O/V (Latch up) tests shall be measured only for the initial qualification and after any process or design changes which may affect the performance of the device. For device classes N, Q and V, the procedures and circuit shall be under the control of the device manufacturer’s TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JESD 78 may be used for reference. e. Subgroup 4 (capacitance measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 Mhz. Sample size is 5 devices with no failures, and all input and output terminals tested. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 5 TABLE I. Electrical performance characteristics. Test Test conditions 1/ -55C TA +125C +3.135 V VCC +3.465 V unless otherwise specified Symbol Group A subgroups Device type Limits Min Unit Max High-level output voltage VOH IOH = -2 mA 1,2,3 All Low-level output voltage VOL IOL = +2 mA 1,2,3 All 0.4 V Input current (leakage) II 0 V Vl VCC All other pins = 0 V to VCC 1,2,3 All 10 A Output current (leakage) IO 0 V VO VCCQ Output disabled 1,2,3 All 10 A Average read or write ICC1 Burst length = 1, 1,2,3 01 75 mA 02 70 03 85 01 95 02 85 tRC tRCMIN, current Read latency = 2 IOH/IOL = 0 mA, One bank activated 2/ Precharge standby current in power-down mode Precharge standby current Read latency = 3 03 100 All 2 mA CKE & CLK VILMAX, tCK = 4/ 1,2,3 All 2 mA CKE VIHMIN, tCK = MIN 1,2,3 01 35 mA 02 30 03 40 1,2,3 All 2 mA CKE VILMAX, tCK = MIN ICC2PS ICC2N 3/ 3/ in non power-down mode CKE VIHMIN, CLK VILMAX, tCK = Active standby current in power-down mode Active standby current in V 1,2,3 ICC2P ICC2NS 2.4 4/ ICC3P CKE VILMAX, tCK = MIN, One bank activated 3/ 1,2,3 All 10 mA ICC3PS CKE & CLK VILMAX, tCK = One bank activated 4/ 1,2,3 All 10 mA ICC3N CKE VIHMIN, tCK = MIN 1,2,3 01 45 mA 02 40 03 55 All 15 non power-down mode One bank activated ICC3NS 3/ CKE VIHMIN, CLK VILMAX, 1,2,3 mA tCK = , One bank activated 4/ See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 6 TABLE I. Electrical performance characteristics - continued. Test Burst current Test conditions 1/ -55C TA +125C +3.135 V VCC +3.465 V unless otherwise specified Symbol ICC4 Continuous burst, IOH/IOL = 0 mA, 5/ Group A Device subgroups type Min 1,2,3 Read latency = 2 All banks activated, Read latency = 3 nCCD = One cycle Auto refresh ICC5 tRC tRCMIN 1,2,3 Read latency = 2 Read latency = 3 02 110 03 165 01 175 02 150 03 210 01 100 80 120 01 100 02 80 120 8.0 6.0 pF X 8.0 pF Y 6.0 X 8.0 Y 6.0 X 10.0 Y 9.0 4 Output capacitance, address and control inputs: A0-A11, Ci(AC) TA = +25°C, See 4.4.1e 6/ 4 All CS , DQMx, RAS , CAS , W Co Functional test Cycle time, CLK (system See 4.4.1c tCK clock) All 4 All 7, 8A, 8B See figures 4 and 5. 7/ Read latency = 2 9, 10, 11 Read latency = 3 Pulse duration, CLK (system clock) high tCKH Pulse duration, CLK (system clock) low tCKL See figures 4 and 5. 7/ mA 03 f = 1MHz, bias on pin under test = 0 V, all other pins are open, Output capacitance mA 02 Ci(S) 4 Max 130 Input capacitance, CLK input Ci(E) Unit 01 03 Pkg All X Y Input capacitance, CKE input Limits All L 01 20 02 30 03 15 01 15 02 20 pF pF H ns 03 12 9, 10, 11 All 4 ns 9, 10, 11 All 4 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 7 TABLE I. Electrical performance characteristics - continued. Test Access time, CLK to data Test conditions 1/ -55C TA +125C +3.135 V VCC +3.465 V unless otherwise specified Symbol tAC out See figures 4 and 5. 7/ 8/ Group A Device subgroups type Limits Min 9, 10, 11 Read latency = 2 Read latency = 3 Delay time, CLK to DQ in tLZ tHZ the high-impedance state Max 01 15 02 20 03 9 01 9 02 10 03 Delay time, CLK to DQ in the low-impedance state 9, 10, 11 All See figures 4 9, 10, 11 01 14 02 15 03 8 01 11 02 12 Read latency = 2 Read latency = 3 0 03 ns ns 8 Setup time, data input tDS See figures 4 and 5. 7/ 9, 10, 11 01, 02 4 03 3 Setup time, address tAS See figures 4 and 5. 7/ 9, 10, 11 01, 02 4 03 3 Setup time, control input tCS 9, 10, 11 01, 02 4 03 3 01, 02 4 03 3 ( CS , DQMx, RAS , CAS , ns 8 See figures 4 and 5. 7/ 9/ and 5. 7/ 10/ Unit ns ns ns W) Setup time, CKE (suspend entry/exit, power-down entry) tCES 9, 10, 11 Setup time, CKE (powerdown/self-refresh exit) tCESP See figures 4 and 5. 7/ 11/ 9, 10, 11 All 10 ns Hold time, CLK to data out tOH See figures 4 and 5. 7/ 9, 10, 11 01, 02 2 ns 03 1.5 Hold time, data input tDH 9, 10, 11 01, 02,03 2 ns Hold time, address tAH 9, 10, 11 01, 02, 03 2 ns Hold time, control input ( CS , tCH 9, 10, 11 01, 02, 03 2 ns tCEH 9, 10, 11 01, 02, 03 2 ns DQMx, RAS , CAS , W ) Hold time, CKE ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 8 TABLE I. Electrical performance characteristics - continued. Test Symbol Test conditions 1/ -55°C TA +125°C +3.135 V VCC +3.465 V Group A Device subgroups type unless otherwise specified REFR command to ACTV, MRS, or REFR command; ACTV command to ACTV, MRS, or REFR command tRC ACTV command to DEAC or DCAB command tRAS ACTV command to READ or WRT command tRCD DEAC or DCAB command to ACTV, MRS, or REFR tRP See figures 4 and 5. 7/ Min 9, 10, 11 9, 10, 11 See figures 4 and 5. 7/ 12/ 9, 10, 11 See figures 4 and 5. 7/ Limits 9, 10, 11 command 01 120 Unit Max ns 02 160 03 96 01 75 100K 02 100 100K 03 60 100K 01 30 02 40 03 24 01 45 02 60 03 36 ns ns ns Final data out of READ-P operation to ACTV, MRS, or REFR command tAPR 9, 10, 11 All device types tRP + (nEP x tCK) ns Final data in to WRT-P operation to ACTV, MRS, or REFR command tAPW 9, 10, 11 All device types tRP + tCK ns Final data in to DEAC or DCAB command tRWL 9, 10, 11 ACTV command for one bank to ACTV command for the tRRD 9, 10, 11 other bank 01 30 02 40 03 24 01 30 02 40 03 24 1 Transition time, all inputs tT See figures 4 and 5. 7/ 13/ 9, 10, 11 All Refresh interval tREF See figures 4 and 5. 7/ 9, 10, 11 All 9,10,11 All -1 All -2 All 2 All 3 Final data out to DEAC or nEP 7/ 14/ DCAB command DEAC or DCAB interrupt of data-out burst to DQ in the Read latency = 2 Read latency = 3 nHZP 7/ 14/ high-impedance state Read latency = 2 9,10,11 Read latency = 3 ns ns 5 ns 32 ms cycles cycles See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 9 TABLE I. Electrical performance characteristics - continued. Test Symbol Test conditions 1/ -55C TA +125C +3.135 V VCC +3.465 V Group A Device subgroups type unless otherwise specified READ or WRT command to interrupting STOP, READ, WRT, DEAC, or DCAB command nCCD Final data in to READ or WRT command in either bank WRT command to first data in Min Unit Max 9,10,11 All 1 cycles nCWL 9,10,11 All 1 cycles nWCD 9,10,11 All 0 0 cycles ENBL or MASK command to data in nDID 9,10,11 All 0 0 cycles ENBL or MASK command to data out nDOD 9,10,11 All 2 2 cycles HOLD command to suspended CLK edge; HOLD operation exit to entry of any command nCLE 9,10,11 All 1 1 cycles MRS command to ACTV, REFR, or MRS command nRSA 9,10,11 All 2 DESL command to control input inhibit nCDD 9,10,11 All 0 1/ 2/ 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ 14/ 7/ 14/ Limits cycles 0 cycles All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. Control and address inputs change state only twice during tRC. Control and address inputs change state only once every 2 x tCK. Control and address inputs do not change (stable). Control and address inputs change state only once every cycle. This test is performed at initial characterization and after any design or process changes. All references are made to the rising transition of CLK unless otherwise specified. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CLK that is one cycle before read latency for the READ command. An access time is measured at output reference level 1.4 V. tLZ is measured from the rising transition of CLK that is one cycle before read latency for the READ command. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. See figure 5, READ BURST waveform. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. Transition time (rise and fall) should be a minimum of 1 ns and a maximum of 5 ns measured between VIHMIN and VILMAX. This is ensured by design but not tested. A CLK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE (those CLK cycles occurring during the time when CKE is asserted low). STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 10 Case X Dimension A b C D D1 E Millimeters Min Max 2.80 3.55 .30 .50 .10 .23 20.60 21.40 18.95 19.45 16.10 16.90 Dimension E2 E3 e L Q S1 Millimeters Min Max 14.10 14.90 .76 min. .80 BSC 6.35 9.40 .66 min. .38 min. FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 11 Case Y Dimension A A1 A3 b C Millimeters Min Max --1.20 .00 .00 .25 .30 .45 .15 nom. 0 to 5 Dimension D1 E E1 e L1 Millimeters Min Max 20.85 21.05 11.56 11.96 10.06 10.26 .80 BSC .40 .60 FIGURE 1. Case outline - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 12 Device types Case outlines Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 All X, Y Terminal symbol VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ DQML W Device types Case outlines Terminal number 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 16 CAS 41 VSSQ 17 RAS 42 DQ10 18 CS A11 A10 A0 A1 A2 A3 VCC 43 DQ11 44 45 46 47 48 49 50 VCCQ DQ12 DQ13 VSSQ DQ14 DQ15 VSS 19 20 21 22 23 24 25 All X, Y Terminal symbol VSS A4 A5 A6 A7 A8 A9 NC CKE CLK DQMU NC VCCQ DQ8 DQ9 FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 13 Basic command truth table 1/ COMMAND Mode register set Bank deactivate (precharge) Deactivate all banks STATE OF BANKS CS RAS CAS W A11 A10 A9-A0 MNEMONIC T = deac B = deac L L L L X X A9 = V A8 - A7 = 0 A6 - A0 = V MRS X L L H L BS L X DEAC X L L H L X H X DCAB Bank activate/row-address entry SB = deac L L H H BS V V ACTV Column-address entry/write operation SB = actv L H L L BS L V WRT Column-address entry/write operation with auto-deactivate SB = actv L H L L BS H V WRT-P Column-address entry/read operation SB = actv L H L H BS L V READ Column-address entry/read operation with auto-deactivate SB = actv L H L H BS H V READ-P X L H H H X X X NOOP X H X X X X X X DESL T = deac B = deac L L L H X X X REFR No operation Control-input inhibit/no operation Auto refresh 2/ 1/ For execution of these commands on cycle n. - CKE (n-1) must be high, or - tCESP must be satisfied for power-down exit, or - tCES and nCLE must be satisfied for clock-suspend exit. DQMx(n) is irrelevant 2/ Auto-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry. Legend: n = CLK cycle number L = Logic low H = Logic high X = Irrelevant, either logic low or logic high V = Valid T = Bank T B = Bank B actv = Activated deac = Deactivated BS = Logic high to select bank T; logic low to select bank B SB = Bank selected by A11 at cycle n FIGURE 3a. Truth table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 14 Clock-Enable (CKE) Command Truth Table 1/ COMMAND Power-down entry on cycle (n+1) 2/ Power-down exit 4/ CLK suspend on cycle (n+1) CLK suspend exit on cycle (n+1) STATE OF BANK(S) T = no access operation 3/ B = no access operation 3/ T = power down B = power down T = access operation 3/ B = access operation 3/ T = access operation 3/ B = access operation 3/ CKE (n-1) CKE (n) CS RAS CAS MNEMONIC (n) W (n) (n) (n) H L X X X X PDE L H X X X X --- H L X X X X HOLD L H X X X X --- 1/ For execution of these commands, A0-A11 (n) and DQMx (n) are don’t care. 2/ On cycle n, the device executes the respective command (listed in Figure 3a). On cycle (n+1), the device enters powerdown mode. 3/ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation. 4/ If setup time from CKE high to the next CLK high satisfies tCESP , the device executes the respective command (listed in figure 3a). Otherwise, either a DESL or a NOOP command must be applied before any other command. Legend: n L H X T B deac = = = = = = = CLK cycle number Logic low Logic high Don’t care Bank T Bank B Deactivated FIGURE 3b. Truth table - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 15 Data Mask (DQM) Command Truth Table. 1/ COMMAND --- --- Data-in enable Data-in mask Data-out enable Data-out mask STATE OF BANK(S) T = deac and B = deac T = actv and B = actv (no access operation) 3/ T = write or B = write T = write or B = write T = read or B = read T = read or B = read DQML DQMU 2/ (n) DATA IN (n) DATA OUT (n) MNEMONIC X N/A Hi-Z --- X N/A Hi-Z --- L V N/A ENBL H M N/A MASK L N/A V ENBL H N/A Hi-Z MASK 1/ For execution of these commands on cycle n - CKE (n) must be high, or - tCESP must be satisfied for power-down exit, or - tCES and nCLE must be satisfied for clock suspend exit. CS n, RAS n, CAS n, W n, and A0-A11 are irrelevant. 2/ DQML controls D0-D7 and Q0-Q7. DQMU controls D8-D15 and Q8-Q15. 3/ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation. Legend: n L H X V M N/A T B actv deac write Read = = = = = = = = = = = = = CLK cycle number Logic low Logic high Don’t care Valid Masked input data Not applicable Bank T Bank B Activated Deactivated Activated and accepting data in on cycle n. Activated and delivering data out on cycle (n+2). FIGURE 3b. Truth table - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 16 FIGURE 4. Output load circuit. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 17 NOTES: 1. For the purposes of these examples, assume read latency = 3, and burst length = 4. 2. DQMx must be high to mask output of the read burst on cycles (nCCD - 1), nCCD, and (nCCD + 1). FIGURE 5. Timing waveforms. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 18 NOTE: For the purposes of these examples, assume read latency = 3, and burst length = 4. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 19 a) Interrupted on odd cycles. b) Interrupted on even cycles. NOTE: For these examples, assume read latency = 3, burst length = 4. NOTE: For this example, assume burst length = 4. INTERRUPTIN GCOMMAND READ, READ-P WRT, WRT-P DEAC, DCAB STOP WRITE BURST INTERRUPTION EFFECT OR NOTE ON USE DURING WRITE BURST Data that was input on the previous cycle is written; no further data inputs are accepted (see figure 5, WRITE BURST INTERRUPTED BY READ COMMAND). The new WRT (WRT-P) command and data inputs immediately supercede the write burst in progress (see figure 5, WRITE BURST INTERRUPTED BY WRITE COMMAND). The DEAC/DCAB command immediately supercedes the write burst in progress. DQMx must be used to mask the DQ bus such that the write recovery specification (tRWL) is not violated by the interrupt (see figure 5, WRITE BURST INTERRUPTED BY DEAC/DCAB COMMAND). The data on the input pins at the time of the burst-STOP command is not written; no further data is accepted. The bank remains active; however, a new read or write command cannot be entered for at least nBSD cycles after the STOP command (see figure 5, WRITE BURST INTERRUPTED BY STOP COMMAND). FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 20 NOTE: For these examples, assume burst length = 4. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 21 FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 22 FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 23 NOTE: For this example, assume read latency = 3, and burst length = 4. NOTE: For this example, assume read latency = 3, and burst length = 1. NOTE: For this example, assume burst length = 1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 24 NOTE: For this example, assume read latency = 3, and burst length = 4. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 25 FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 26 NOTE: This example illustrates minimum tRCD and nEP for device type 01 at 66 MHz. BURST TYPE (D/Q) Q BANK ROW (B/T) T ADDR R0 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 27 NOTE: This example illustrates minimum tRCD and tRWL for device type 01 at 66MHz. BURST TYPE (D/Q) D BANK ROW (B/T) T ADDR R0 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6 h C0 + 7 NOTE: Column-address sequence depends on programmed burst type and starting column address C0. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 28 NOTE: This example illustrates minimum tRCD and nEP for device type 01 at 66MHz. BURST TYPE (D/Q) D Q BANK ROW (B/T) B B ADDR R0 R0 BURST CYCLE (see note) a C0 b C0 + 1 c d C1 C1 + 1 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 29 NOTE: This example illustrates minimum tRCD for device type 01 at 66MHz. BURST BANK ROW TYPE (D/Q) (B/T) ADDR Q T R0 D T R0 BURST CYCLE (see note) a b c d e f g h C0 C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7 i j k l m n o p C1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 30 NOTE: This example illustrates minimum tRCD for device type 01 at 66MHz. BURST TYPE (D/Q) Q D BANK ROW (B/T) T T ADDR R0 R0 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6 h C0 + 7 i C1 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 31 NOTE: This example illustrates minimum tRCD for device type 01 at 66MHz. BURST TYPE (D/Q) Q BANK ROW (B/T) B ADDR R0 BURST CYCLE (see note) a b c d e f g h i C0 C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7 j k l m n o p q r s . 255 NOTE: Column-address sequence depends on programmed burst type and starting column address C0. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 32 . NOTE: This example illustrates minimum tRCD for device type 01 at 66MHz. BURST TYPE (D/Q) Q Q Q BANK ROW (B/T) B T B ADDR R0 R1 R2 BURST TYPE (D/Q) Q Q Q BANK ROW (B/T) B T B ADDR R0 R1 R2 BURST CYCLE (see note) a C0 b c d e f g h C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7 i j C1 k C1+1 C1+2 BURST CYCLE (continued) l m n o p C1+3 C1+4 C1+5 C1+6 C1+7 q C2 r s C2+1 C2 +2 . . . . NOTE: Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 33 BURST BANK ROW BURST CYCLE (see note) TYPE (D/Q) (B/T) ADDR a b c d e f ... ... Q B R0 C0 C0 + 1 Q T R1 C1 C1 + 1 Q B R0 C2 C2 + 1 . ... ... ... ... NOTE: Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 34 NOTE: This example illustrates minimum tRCD, nEP, and tRWL for device type 01 at 66MHz. BURST TYPE (D/Q) Q D BANK ROW (B/T) B T ADDR R0 R1 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 e f C1 C1 + 1 g h C1 + 2 C1 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 35 NOTE: This example illustrates minimum nCWL for device type 01 at 66MHz. BURST TYPE (D/Q) D Q BANK ROW (B/T) T B ADDR R0 R1 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 e f C1 C1 + 1 g h C1 + 2 C1 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 36 NOTE: This example illustrates minimum tRCD for device type 01 at 66MHz. BURST TYPE (D/Q) Q D BANK ROW (B/T) T T ADDR R0 R1 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 e f C1 C1 + 1 g h C1 + 2 C1 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 37 BURST TYPE (D/Q) Q Q Q Q BANK ROW (B/T) T B T B ADDR R0 R1 R0 R1 BURST CYCLE (see note) a C0 b C0 + 1 c d C1 C1 + 1 e f C2 C2 + 1 C3 C3 + 1 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 38 NOTE: This example illustrates minimum tRCD and nEP read burst, and a minimum tRWL write burst for device type 01 at 66MHz. BURST TYPE (D/Q) Q D BANK ROW (B/T) T B ADDR R0 R1 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 e f C1 C1 + 1 g h C1 + 2 C1 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 39 NOTE: This example illustrates minimum tRCD and tRWL for device type 01 at 66MHz. BURST TYPE (D/Q) Q D BANK ROW (B/T) T B ADDR R0 R1 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 e f C1 C1 + 1 g h C1 + 2 C1 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 40 NOTE: This example illustrates minimum tRC, tRCD, and nEP for device type 01 at 66 MHz. BURST TYPE (D/Q) Q BANK ROW (B/T) T ADDR R0 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 41 NOTE: This example illustrates minimum tRP, nRSA, and tRCD for device type 01 at 66 MHz. BURST TYPE (D/Q) D BANK ROW (B/T) B ADDR R0 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 42 BURST TYPE (D/Q) Q D BANK ROW (B/T) T T ADDR R0 R1 BURST CYCLE (see note) a C0 b C0 + 1 c C0 + 2 d C0 + 3 e f C1 C1 + 1 g h C1 + 2 C1 + 3 NOTE: Column-address sequence depends on programmed burst type and starting column address C0 and C1. FIGURE 5. Timing waveforms - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 43 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 Additional criteria for device classes N, Q, and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MIL-PRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes N, Q, and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C ±5C, after exposure, to the subgroups specified in table II herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 44 TABLE II. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/ Line Number Test requirements Subgroups (in accordance with MIL-PRF-38535, table III) Device class Q Device class N Device class V --- --- 1,7,9 Not required Not required Required --- --- 1*, 7* Required Required Required --- --- 1*, 7* 1 Interim electrical parameters (see 4.2) 2 Static burn-in I and II (method 1015) 3 Same as line 1 4 Dynamic burn-in (method 1015) 5 Same as line 1 6 Final electrical parameters 1*,2,3,7*,8A, 8B,9,10,11 2, 3, 8A, 8B, 10, 11 1*, 2,3,7*,8A, 8B,9,10,11 7 Group A test requirements 1,2, 3,4**, 7, 8A,8B,9,10,11 2, 3, 8A, 8B, 10, 11 1,2,3,4**,7,8A, 8B,9,10,11 8 Group C end-point electrical parameters 1,2, 3,7,8A, 8B 1, 7 1, 2, 3,7,8A, 8B,9, 10,11 9 Group D end-point electrical parameters 2, 3,8A, 8B --- 2, 3,8A, 8B 10 Group E end-point electrical parameters 1,7,9 --- 1,7,9 1/ 2/ 3/ 4/ 5/ 6/ Blank spaces indicates tests are not applicable. Any or all subgroups may be combined when using high-speed testers. Subgroups 7, 8A and 8B functional tests shall verify functionality of the device. * indicates PDA applies to subgroup 1 and 7. ** see 4.4.1e. indicates delta limited shall be required where specified, and the delta values shall be computed with reference to previous interim electrical parameters (see Line 1). For device class V, performance of delta limits shall be specified in the manufacturer’s QM plan. 7/ See 4.4.1d. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 45 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes N, Q, and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614)692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes N, Q, and V. Sources of supply for device classes N, Q, and V are listed in QML-38535 and MIL-HDBK-103. The vendors listed in QML-38535 and MIL-HDBK-103 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 46 Appendix A FUNCTIONAL ALGORITHMS Appendix A forms a part of SMD 5962- 97545 A.1 SCOPE A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be applied to the device in a topologically pure fashion. This Appendix is a mandatory part of the specification. The information contained herein is intended for compliance. A.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix. A.3 ALGORITHMS A.3.1 Algorithm A (pattern 1). A.3.1.1 Mode Register Set (MRS). This pattern ensures that the device executes the proper sequence for each of the applicable device modes. The test verifies the proper operation of the mode register and mode control logic. It is performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Step 7: Step 8: Step 9: Step 10: Step 11: Perform 8 REFR command cycles. Deactivate both banks (DCAB) Set mode register (MRS) Activate bank, perform a write burst of data starting at location 0, and deactivate bank. Increment column address by burst length and repeat step 4 for entire row. Repeat steps 4 and 5 for each row address. Activate bank and perform read burst with proper read latency for data starting at location 0. Perform write burst of complement data starting at location 0 and deactivate bank. Increment column address by burst length and repeat steps 7 and 8 for entire row. Repeat 7, 8, and 9 for each row address. Read entire array for complement data. This test is repeated for each applicable combination of burst length, burst type, and read latency that can be programmed by the mode register set (MRS) command. Test is performed at worst case limit VCC levels and temperatures. A.3.2 Algorithm B (pattern 2). A.3.2.1 March Data, Bank Interleave. This algorithm tests for address uniqueness and multiple selection. It is also a primary check of many timing parameters. This test is designed to test the row and column address decode circuitry, address control, and the operations for writing and reading both one state and zero state from all memory cells in the memory array. Additionally, it is used to test for proper two-bank interleaved access operation. It is performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Step 7: Step 8: Step 9: Perform 8 REFR command cycles. Deactivate both banks (DCAB). Set mode register (MRS). Activate bottom and top memory banks. Perform a write burst of data starting at minimum address in bottom bank followed immediately by a write burst of data starting at minimum address in top bank. Deactivate both banks (DCAB). Increment row address and repeat steps 4, 5, and 6 for each row. Increment column address by burst length and repeat steps 4 - 7 through entire array. Activate bottom and top memory banks. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 47 Appendix A - Continued. FUNCTIONAL ALGORITHMS Appendix A forms a part of SMD 5962- 97545 Step 10: Perform a read burst with proper read latency for data followed by a write burst of complement data starting at minimum address in bottom bank. Step 11: Immediately perform a read burst with proper read latency for data followed by a write burst of complement data starting at minimum address in top bank. Step 12: Deactivate both banks (DCAB). Step 13: Increment row address and repeat steps 9 - 12 for each row. Step 14: Increment column address by burst length and repeat steps 9 - 13 through entire array. Step 15: Activate bottom and top memory banks. Step 16: Perform a read burst with proper read latency for complement data followed by a write burst of data starting at maximum address in top bank. Step 17: Immediately perform a read burst with proper read latency for complement data followed by a write burst of data starting at maximum address in bottom bank. Step 18: Deactivate both banks (DCAB). Step 19: Decrement row address and repeat steps 15 - 18 for each row. Step 20: Decrement column address by burst length and repeat steps 15 - 19 through entire array. Step 21: Read entire array for data. This test is repeated for each read latency mode with worst case timings and worst case topological data pattern for burst sequences. Test is performed at worst case limit VCC levels and temperatures. A.3.3 Algorithm C (pattern 3). A.3.3.1 Refresh Interval (tREF). This pattern is intended to check the retention time (tREF) of the memory cells in the memory array. It is performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Step 7: Perform 8 REFR command cycles. Deactivate both banks (DCAB). Set mode register (MRS). Load memory with data. Pause tREF. (stop all clocks). Read data from all memory locations. Repeat steps 4, 5, and 6 using complement data. Standard read sequence and write sequence timings are used. Test is performed at worst case limit VCC levels and temperatures. A.3.4 Algorithm D (pattern 4). A.3.4.1 Auto-refresh (REFR). This pattern verifies the functionality of the auto-refresh mode. It is a test of the refresh control circuitry, specifically the internal auto-row address counter. It is performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Step 7: Step 8: Step 9: Step 10: Step 11: Step 12: Step 13: Perform 8 REFR command cycles. Deactivate both banks (DCAB). Set mode register (MRS). Perform a write burst of data starting at minimum memory address. Increment column address by burst length and repeat steps 4 across row. Increment row address and repeat step 4 and 5 for new row. Repeat steps 4 - 6 until the refresh interval (tREF) has elapsed. Perform 4096 auto-refresh cycles with the REFR command in order to refresh the entire memory array. Repeat steps 4 - 8 until entire array is written with data. Perform read burst for data starting at minimum memory address. Increment column address by burst length and repeat steps 10 across row. Increment row address and repeat step 10 and 11 for new row. Repeat steps 10 - 12 until the refresh interval (tREF) has elapsed. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 48 Appendix A - Continued. FUNCTIONAL ALGORITHMS Appendix A forms a part of SMD 5962- 97545 Step 14: Perform 4096 auto-refresh cycles with the REFR command in order to refresh the entire memory array. Step 15: Repeat steps 10 - 14 until entire array is read for data. Step 16: Repeat steps 4 - 15 for complement data. Relaxed read and write cycle timings are used to provide test execution over multiple refresh intervals. Test is performed at worst case limit VCC levels and temperatures. A.3.5 Algorithm E (pattern 5). A.3.5.1 Vcc Slew. This pattern indicates sense amplifier margin by slewing the voltage supply between memory writing and reading. It is a basic functional test of the sense amplifier circuitry. It is performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Step 7: Step 8: Step 9: Step 10: Perform 8 REFR command cycles. Deactivate both banks (DCAB). Set mode register (MRS). Load memory with background data using VCC at VCC minimum. Change VCC to VCC maximum. Read data from memory. Write memory with data complement. Change VCC to VCC minimum. Read data complement from memory. Repeat steps 4 - 9 with complement data. Test is performed at worst case limit VCC levels and temperatures. A.3.6 Algorithm F (pattern 6). A.3.6.1 Write Burst Interrupt. Provided that all applicable timing requirements are met, write burst sequences can be interrupted by read (READ/READ-P), write (WRT/WRT-P), deactivate (DEAC/DCAB), and STOP commands. A series of tests are used to verify proper execution for each of the possible interrupting command sequences. The algorithms for these tests follow a standard format and are listed here together due to their similarity. These tests are designed to ensure functionality of the interrupt control logic. They are performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Step 7: Perform 8 REFR command cycles. Deactivate both banks (DCAB). Set mode register (MRS). Load memory with data. Activate bank and begin write burst of complement data. Interrupt write burst to inhibit writing of complement data to the remaining memory addresses of burst sequence. Read memory to verify correct combination of complement data and true data in the array. Tests are performed at worst case limit VCC levels and temperatures using worst case timings for interrupt sequences. A.3.7 Algorithm G (pattern 7). A.3.7.1 Read Burst Interrupt. Provided that all applicable timing requirements are met, read burst sequences can be interrupted by read (READ/READ-P), write (WRT/WRT-P), deactivate (DEAC/DCAB), and STOP commands. A series of tests are used to verify proper execution for each of the possible interrupting command sequences. The algorithms for these tests follow a standard format and are listed here together due to their similarity. These tests are designed to ensure functionality of the interrupt control logic. In addition, for read bursts interrupted by the DEAC/DCAB commands, the tests verify that the output buffers switch to high impedance (tri-state) as specified by tHZ and nHZP. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 49 Appendix A - Continued. FUNCTIONAL ALGORITHMS Appendix A forms a part of SMD 5962- 97545 They are performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Perform 8 REFR command cycles. Deactivate both banks (DCAB). Set mode register (MRS). Load memory with data. Activate bank and begin read burst of data. Interrupt read burst and verify that interrupting command properly supersedes the initial read burst. Tests are performed at worst case limit VCC levels and temperatures using worst case timings for interrupt sequences. A.3.8 Algorithm H (pattern 8). A.3.8.1 Write Mask. This pattern verifies proper functionality of the input mask control circuitry. It assures that data input is inhibited during write cycles when the DQMU/DQML inputs are driven high. It is performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Perform 8 REFR command cycles. Deactivate both banks (DCAB). Set mode register (MRS). Load memory with background data. Perform write burst cycles of complement data with the DQMU/DQML inputs high. Read data from memory. Standard read and write cycle timings are used with worst case timing for DQMU/DQML mask operations. Test is performed at worst case limit VCC levels and temperatures. A.3.9 Algorithm I (pattern 9). A.3.9.1 Read Mask. This pattern verifies proper functionality of the output mask control circuitry. It assures that the data output buffers switch to high impedance during write cycles when the DQMU/DQML inputs are driven high. It is performed in the following manner: Step 1: Step 2: Step 3: Step 4: Step 5: Perform 8 REFR command cycles. Deactivate both banks (DCAB). Set mode register (MRS). Load memory with background data. Perform read burst cycles for data, and switch the DQMU/DQML inputs high during output burst cycles to verify that the outputs are properly disabled. Read data from memory. Repeat steps 4 - 6 for complement data Step 6: Step 7: Standard read and write cycle timings are used with worst case timing for DQMU/DQML mask operations. Test is performed at worst case limit VCC levels and temperatures. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE A 5962-97545 REVISION LEVEL F SHEET 50 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 16-05-09 Approved sources of supply for SMD 5962-97545 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-9754501QXA 57300 SMJ626162-15HKDM 5962-9754501NYB 3/ SMJ626162-15DGE 5962-9754502QXA 57300 SMJ626162-20HKDM 5962-9754502NYB 3/ SMJ626162-20DGE 5962-9754503QXA 57300 SMJ626162-12HKDM 5962-9754503NYB 3/ SMJ626162-12DGE 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ No longer available from an approved source. Vendor CAGE number 57300 Vendor name and address Micross Components 7725 N. Orange Blossom Trail Orlando, FL 32810-2696 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.