English

Shanghai Belling Corp., Ltd

Features

2

TM
Two-Wire Serial Interface, I C
–
Compatible
Bi-directional data transfer protocol

Page Size: 128 bytes

Page write mode
–
Wide-voltage Operation
–
VCC = 1.7V to 5.5V
Up to 128 bytes per page write

Self timed write cycle with auto clear: 5ms (max.)

Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)

Filtered inputs for noise suppression

Standby current (max.): 1 A, 1.7V

High-reliability

Operating current (max.): 2 mA, 1.7V

Hardware Data Protection
–

BL24C512G
Write Protect Pin
–
–
Endurance: 1 million cycles
Data retention: 100 years

Industrial temperature grades

Sequential & Random Read Features

Packages: SOIC/SOP, TSSOP, DFN and CSP

Memory organization: 65,536 x 8 bits

Lead-free, RoHS, Halogen free, Green
Description
The BL24C512G are EEPROM devices that use the
that Slave device, and a series of data, if appropriate. The
industrial standard 2-wire interface for communications. The
BL24C512G also has a Write Protect pin (WP) to allow
BL24C512G contains a memory array of 512K-bits
blocking any write operations over specified memory area.
(65,536x8), which is organized in 128-byte per page.
Under no circumstance, the device will be hung up. In order
The EEPROM can operate in a wide voltage range from
to refrain the state machine entering into a wrong state
1.7V to 5.5V which fits most application. This product can
during power-up sequence or a power toggle off-on
provide a low-power 2-wire EEPROM solution. The device
condition, a power on reset circuit is embedded. During
is offered in Lead-free, RoHS, halogen free or Green. The
power-up, the device does not respond to any instructions
available package types are 8-pin SOIC/SOP, TSSOP, DFN
until the supply voltage (VCC) has reached an acceptable
and CSP.
stable level above the reset threshold voltage. Once VCC
The BL24C512G is compatible with the industrial standard
passes the power on reset threshold, the device is reset
2-wire bus protocol. If in case the bus is not responded, a
and enters into the Standby mode. This would also avoid
new sent Op-code command will reset the bus and the
any inadvertent Write operations during power-up stage.
device will respond correctly. The simple bus consists of the
During power-down process, the device will enter into
Serial Clock wire (SCL) and the Serial Data wire (SDA).
standby mode, once VCC drops below the power on reset
Utilizing such bus protocol, a Master device, such as a
threshold voltage. In addition, the device will be in standby
microcontroller, can usually control one or more Slave
mode after receiving the Stop command, provided that no
devices, alike this BL24C512G. The bit stream over the
internal write operation is in progress. Nevertheless, it is
SDA line includes a series of bytes, which identifies a
illegal to send a command unless the VCC is within its
particular Slave device, an instruction, an address within
operating level.
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Shanghai Belling Corp., Ltd
Functional Block Diagram
VCC
8
SDA
5
SCL
6
WP
7
HIGH VOLTAGE
GENERATOR
TIMING &
CONTROL
X DECODER

BL24C512G
CONTROL LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
1
A1
2
A2
3
WORD ADDRESS
COUNTER
ACK
Y DECODER
CLOCK
DI/O
GND 4
EEPROM ARRAY
DATA REGISTER
nMOS
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Shanghai Belling Corp., Ltd

BL24C512G
Pin Configuration
8-Pin SOIC/SOP and TSSOP
8-Lead DFN
Top View
Top View
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
Pin Definition
Pin No.
Pin Name
I/O
Definition
1
A0
I
Device Address Input
2
A1
I
Device Address Input
3
A2
I
Device Address Input
4
GND
-
Ground
5
SDA
I/O
6
SCL
I
Serial Clock Input
7
WP
I
Write Protect Input
8
VCC
-
Power Supply
Serial Address and Data input and Data out put
Pin Descriptions
SCL
the inputs are defaulted to zero.
This input clock pin is used to synchronize the data transfer
WP
to and from the device.
WP is the Write Protect pin. While the WP pin is connected
SDA
to the power supply of BL24C512G, the entire array
The SDA is a bi-directional pin used to transfer addresses
becomes Write Protected (i.e. the device becomes Read
and data into and out of the device. The SDA pin is an open
only). When WP is tied to Ground or left floating, the normal
drain output and can be wired with other open drain or open
write operations are allowed.
collector outputs. However, the SDA pin requires a pull-up
VCC
resistor connected to the power supply.
Supply voltage
A0, A1, A2
GND
The A0, A1 and A2 are the device address inputs.
Ground of supply voltage
Typically, the A0, A1, and A2 pins are for hardware
addressing and a total of 8 devices can be connected on a
single bus system. When A0, A1, and A2 are left floating,
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Shanghai Belling Corp., Ltd
BL24C512G
 Device Operation
The BL24C512G serial interface supports communications
2
device to monitor the SDA line while cycling the SCL up to
using industrial standard 2-wire bus protocol, such as I C.
nine times. (For each clock signal transition to High, the
2-WIRE Bus
Master checks for a High level on SDA.)
The two-wire bus is defined as Serial Data (SDA), and
Standby Mode
Serial Clock (SCL). The protocol defines any device that
While in standby mode, the power consumption is minimal.
sends data onto the SDA bus as a transmitter, and the
The BL24C512G enters into standby mode during one of
receiving devices as receivers. The bus is controlled by
the following conditions: a) After Power-up, while no
Master device that generates the SCL, controls the bus
Op-code is sent; b) After the completion of an operation and
access, and generates the Start and Stop conditions. The
followed by the Stop signal, provided that the previous
BL24C512G is the Slave device.
operation is not Write related; or c) After the completion of
The Bus Protocol
any internal write operations.
Data transfer may be initiated only when the bus is not busy.
Device Addressing
During a data transfer, the SDA line must remain stable
The Master begins a transmission on by sending a Start
whenever the SCL line is high. Any changes in the SDA line
condition, then sends the address of the particular Slave
while the SCL line is high will be interpreted as a Start or
devices to be communicated. The Slave device address is 8
Stop condition.
bits format as shown in Figure. 1-5.
The state of the SDA line represents valid data after a Start
The four most significant bits of the Slave address are fixed
condition. The SDA line must be stable for the duration of
(1010) for BL24C512G.
the High period of the clock signal. The data on the SDA line
The next three bits, A0, A1 and A2, of the Slave address are
may be changed during the Low period of the clock signal.
specifically related to EEPROM. Up to eight BL24C512G
There is one clock pulse per bit of data. Each data transfer
units can be connected to the 2-wire bus.
is initiated with a Start condition and terminated by a Stop
The last bit of the Slave address specifies whether a Read
condition.
or Write operation is to be performed. When this bit is set to
Start Condition
1, Read operation is selected. While it is set to 0, Write
The Start condition precedes all commands to the device
operation is selected.
and is defined as a High to Low transition of SDA when SCL
After the Master transmits the Start condition and Slave
is High. The EEPROM monitors the SDA and SCL lines and
address byte appropriately, the associated 2-wire Slave
will not respond until the Start condition is met.
device, BL24C512G, will respond with ACK on the SDA line.
Stop Condition
Then BL24C512G will pull down the SDA on the ninth clock
The Stop condition is defined as a Low to High transition of
cycle, signaling that it received the eight bits of data.
SDA when SCL is High. All operations must end with a Stop
The BL24C512G then prepares for a Read or Write
condition.
operation by monitoring the bus.
Acknowledge
Write Operation
After a successful data transfer, each receiving device is
Byte Write
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The BL24C512G contains a reset function in case the
2-wire bus transmission on is accidentally interrupted (e.g. a
power loss), or needs to be terminated mid-stream. The
reset is initiated when the Master device creates a Start
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the BL24C512G. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
condition. To do this, it may be necessary for the Master
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Shanghai Belling Corp., Ltd
BL24C512G
memory location. The BL24C512G acknowledges once
Current Address Read
more and the Master generates the Stop condition, at which
The BL24C512G contains an internal address counter
time the device begins its internal programming cycle. While
which maintains the address of the last byte accessed,
this internal cycle is in progress, the device will not respond
incremented by one. For example, if the previous operation
to any request from the Master device.
is either a Read or Write operation addressed to the
Page Write
address location n, the internal address counter would
The BL24C512G is capable of 128-byte Page-Write
operation. A Page-Write is initiated in the same manner as a
Byte Write, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 127 more bytes. After the receipt
of each data word, the EEPROM responds immediately with
an ACK on SDA line, and the seven lower order data word
address bits are internally incremented by one, while the
higher order bits of the data word address remain constant.
increment to address location n+1. When the EEPROM
receives the Slave Addressing Byte with a Read operation
(R/W bit set to “1”), it will respond an ACK and transmit the
8-bit data byte stored at address location n+1. The Master
should not acknowledge the transfer but should generate a
Stop
condition
so
the
BL24C512G
discontinues
transmission. If 'n' is the last byte of the memory, the data
from location '0' will be transmitted. (Refer to Figure 1-8.
Current Address Read Diagram.)
If a byte address is incremented from the last byte of a page,
Random Address Read
it returns to the first byte of that page. If the Master device
Selective Read operations allow the Master device to select
should transmit more than 128 bytes prior to issuing the
at random any memory location for a Read operation. The
Stop condition, the address counter will “roll over,” and the
Master device first performs a 'dummy' Write operation by
previously written data will be overwritten. Once all 128
sending the Start condition, Slave address and byte
bytes are received and the Stop condition has been sent by
address of the location it wishes to read. After the
the Master, the internal programming cycle begins. At this
BL24C512G acknowledges the byte address, the Master
point, all received data is written to the BL24C512G in a
device resends the Start condition and the Slave address,
single Write cycle. All inputs are disabled until completion of
this time with the R/W bit set to one. The EEPROM then
the internal Write cycle.
responds with its ACK and sends the data requested. The
Acknowledge (ACK) Polling
Master device does not send an ACK but will generate a
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
Stop condition. (Refer to Figure 1-9. Random Address Read
Diagram.)
issued to indicate the end of the host's Write operation, the
Sequential Read
BL24C512G initiates the internal Write cycle. ACK polling
Sequential Reads can be initiated as either a Current
can be initiated immediately. This involves issuing the Start
Address Read or Random Address Read. After the
condition followed by the Slave address for a Write
BL24C512G sends the initial byte sequence, the Master
operation. If the EEPROM is still busy with the Write
device now responds with an ACK indicating it requires
operation, no ACK will be returned. If the BL24C512G has
additional data from the BL24C512G. The EEPROM
completed the Write operation, an ACK will be returned and
continues to output data for each ACK received. The Master
the host can then proceed with the next Read or Write
device terminates the sequential Read operation by pulling
operation.
SDA High (no ACK) indicating the last data word to be read,
Read Operation
followed by a Stop condition. The data output is sequential,
Read operations are initiated in the same manner as Write
with the data from address n followed by the data from
operations, except that the (R/W) bit of the Slave address is
address n+1,n+2 ... etc. The address counter increments by
set to “1”. There are three Read operation options: current
one automatically, allowing the entire memory contents to
address read, random address read and sequential read.
be serially read during sequential Read operation. When
the memory address boundary of the array is reached, the
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Shanghai Belling Corp., Ltd
BL24C512G
address counter “rolls over” to address 0, and the device
Read Diagram).
continues to output data. (Refer to Figure 1-10. Sequential
Diagrams
Figure 1-1. Typical System Bus Configuration
VCC
SDA
SCL
Master
Transmitter/Receiver
GT24CXX
BL24CXXX
X
Figure 1-2. output Acknowledge
SCL from Master
1
8
9
Data Output from
Transmitter
TAA
Data Output from
Receiver
TAA
ACK
SDA
STOP
CONDITION
SCL
START
CONDITION
Figure 1-3. Start and Stop Conditions
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BL24C512G
Figure 1-4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 1-5. Slave Address
Bit
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
Figure 1-6. Byte Write
S
T
A
R
T
Device
Address
SDA
Bus
Activity
W
R
I
T
E
Word Address
A
C
K
M
S
B
Word Address
A
C
K
S
T
O
P
Data
A
C
K
A
C
K
L
M
S
S
B
B
R/W
Figure 1-7. Page Write
S
T
A
R
T
Device
Address
SDA
Bus
Activity
M
S
B
W
R
I
T
E Word Address(n) Word Address(n)
A
A
A
C
C
C
K
K
K
Data(n)
Data(n+1)
A
C
K
S
T
O
P
Data(n+127)
A
C
K
A
C
K
L
M
S
S
B
B
R/W
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Shanghai Belling Corp., Ltd
BL24C512G
Figure 1-8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
S
T
O
P
Data
A
C
K
SDA
Bus
Activity
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 1-9. Random Address Read
S
T
A
R
T
W
R
I
T
E
Device
Address
SDA
Bus
Activity
Word
Address(n)
A
C
K
M
S
B
S
T
A
R
T
Word
Address(n)
A
C
K
Device
Address
R
E
A
D
A
C
K
S
T
O
P
Data n
A
C
K
N
O
L
S
B
R/W
A
C
K
DUMMY WRITE
Figure 1-10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
S
T
O
Data Byte n+x P
Data Byte n+2
A
C
K
A
C
K
N
O
R/W
A
C
K
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Shanghai Belling Corp., Ltd
BL24C512G
Timing Diagrams
Figure 1-11. Bus Timing
TR
TF
THIGH
TLOW
TSU:STO
SCL
TSU:STA
THD:STA
TSU:DAT
THD:DAT
TBUF
SDAIN
TAA
TDH
SDAOUT
TSU:WP THD:WP
WP
Figure 1-12. Write Cycle Timing
SCL
SDA
ACK
Word n
TWR
STOP
Condition
START
Condition
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Shanghai Belling Corp., Ltd

BL24C512G
Electrical Characteristics
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VS
Supply Voltage
-0.5 to + 6.5
V
VP
Voltage on Any Pin
–0.5 to VCC + 0.5
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Output Current
5
mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Range
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.7V to 5.5V
Note: Industrial grade for Commercial applications (0C to +70C).
Capacitance
Symbol
Parameter[1, 2]
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
CI/O
Input / Output Capacitance
VI/O = 0V
8
pF
Notes:
[1]
Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
[2]
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Shanghai Belling Corp., Ltd
BL24C512G
DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Symbol
Parameter[1]
VCC
Test Conditions
Min.
Max.
Unit
1.7
5.5
V
VCC
Supply Voltage
VIH
Input High Voltage
0.7*VCC
VCC+1
V
VIL
Input Low Voltage
-1
0.3* VCC
V
ILI
Input Leakage Current
5V
--
2
μA
ILO
Output Leakage Current
5V
--
2
μA
VIN = VCC max
VOL1
Output Low Voltage
1.7V
IOL = 0.15 mA
—
0.2
V
VOL2
Output Low Voltage
3V
IOL = 2.1 mA
—
0.4
V
ISB1
Standby Current
1.7V
VIN = VCC or GND
—
1
μA
ISB2
Standby Current
2.5V
VIN = VCC or GND
—
2
μA
ISB3
Standby Current
5V
VIN = VCC or GND
—
3
μA
1.7V
Read at 400 KHz
—
0.5
mA
2.5V
Read at 1 MHz
1
mA
5.5V
Read at 1 MHz
1
mA
1.7V
Write at 400 KHz
2
mA
2.5V
Write at 1 MHz
3
mA
5.5V
Write at 1 MHz
3
mA
ICC1
ICC2
Read Current
Write Current
—
Note: The parameters are characterized but not 100% tested.
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Shanghai Belling Corp., Ltd
BL24C512G
AC Electrical Characteristic
Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V
Symbol
Parameter
[1] [2]
1.7VVCC<2.5V
2.5VVCC<4.5V
4.5VVCC5.5V
Min.
Min.
Min.
Max.
400
Max.
FSCL
SCK Clock Frequency
1000
TLOW
Clock Low Period
1200
—
400
—
THIGH
Clock High Period
600
—
400
Max.
Unit
1000
KHz
400
—
ns
—
400
—
ns
TR
Rise Time (SCL and SDA)
—
300
—
300
—
300
ns
TF
Fall Time (SCL and SDA)
—
300
—
100
—
100
ns
TSU:STA
Start Condition Setup Time
600
—
200
—
200
—
ns
TSU:STO
Stop Condition Setup Time
600
—
200
—
200
—
ns
THD:STA
Start Condition Hold Time
600
—
200
—
200
—
ns
TSU:DAT
Data In Setup Time
100
—
40
—
40
—
ns
THD:DAT
Data In Hold Time
0
—
0
—
0
—
ns
100
900
50
400
50
400
ns
100
—
50
—
50
—
ns
—
5
—
5
—
5
ms
1000
—
400
—
400
—
ns
TAA
Clock to Output Access time (SCL
Low to SDA Data Out Valid)
TDH
Data Out Hold Time (SCL Low to
SDA Data Out Change)
TWR
Write Cycle Time
TBUF
Bus Free Time Before New
Transmission
TSU:WP
WP pin Setup Time
600
—
400
—
400
THD:WP
WP pin Hold Time
1200
—
1200
—
1200
—
ns
—
100
—
50
—
50
ns
T
Notes:
Noise Suppression Time
[1]
[2]
ns
The parameters are characterized but not 100% tested.
AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.7V)
CL = 100 pF
Input pulse voltages: 0.3*VCC to 0.7*VCC
Input rise and fall times: ≤ 50 ns
Timing reference voltages: half VCC level
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Shanghai Belling Corp., Ltd

BL24C512G
Package Information
SOIC/SOP
8L 150mil SOP Package Outline
Detail A
D
E
E1
b
ZD
Detail A
GAUGE
PLANE
A
SEATING
PLANE
e
SYMBOLS
L
Θ
L1
A1
DIMENSIONS IN MILLIMETERS
DIMENSIONS IN INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
1.35
--
1.75
0.053
--
0.069
A1
0.10
--
0.25
0.004
--
0.010
b
0.33
--
0.51
0.013
--
0.020
D
4.80
--
5.00
0.189
--
0.197
Note:
E
5.80
--
6.20
0.228
--
0.244
1. Controlling Dimension:MM
E1
3.80
--
4.00
0.150
--
0.157
2. Dimension D and E1 do not include
Mold protrusion
3. Dimension b does not include
dambar protrusion/intrusion.
4. Refer to Jedec standard MS-012
5. Drawing is not to scale
e
L
1.27 BSC.
0.38
L1
1.27
0.015
0.25 BSC.
ZD
Θ
--
0.050 BSC.
0.545 REF.
0
--
0.050
0.010 BSC.
0.021 REF.
8°
0
--
8°
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Shanghai Belling Corp., Ltd
BL24C512G
TSSOP
8L 3x4.4mm TSSOP Package Outline
D
C
e
8
L
E
E1
1
Θ
12°(4X)
A2
0.10mm
b
A1
Note:
1. Controlling Dimension:MM
2. Dimension D and E1 do not include Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MO-153 AA
5. Drawing is not to scale
6. Package may have exposed tie bar.
A
SYMBOLS
A
A1
A2
b
c
D
E
E1
e
L
Θ
DIMENSIONS IN MILLIMETERS
MIN
-0.05
0.80
0.19
0.09
2.90
4.30
0.45
0
NOM
--1.00
--3.00
4.40
6.4 BSC
0.65 BSC
0.60
--
DIMENSIONS IN INCHES
MAX
1.20
0.15
1.05
0.30
0.20
3.10
4.50
MIN
-0.002
0.031
0.007
0.004
0.114
0.169
0.75
8°
0.018
0
NOM
--0.039
--0.118
0.173
0.252 BSC
0.026 BSC
0.024
--
MAX
0.047
0.006
0.041
0.012
0.008
0.122
0.177
0.030
8°
14
Shanghai Belling Corp., Ltd
BL24C512G
DFN
8L 3x3mm DFN Package Outline
D2
D
e
K
E
E2
L
b
PIN#1 DOT BY
MARKING
TOP VIEW
BOTTOM VIEW
PIN#1
IDENTIFICATION
CHAMFER
A
A1
SIDE VIEW
SYMBOLS
Note:
1. Controlling Dimension:MM
2. Drawing is not to scale
DIMENSIONS IN MILLIMETERS
DIMENSIONS IN INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
--
0.05
0.000
--
0.002
b
0.17
0.22
0.27
0.007
0.009
0.011
D
D2
3.00 BSC
2.375
E
E2
2.385
0.118 BSC
2.395
0.094
3.00 BSC
1.635
e
1.645
0.094
0.094
0.118 BSC
1.655
0.064
0.50BSC.
0.065
0.065
0.020BSC
K
0.23
0.28
0.33
0.009
0.011
0.013
L
0.35
0.40
0.45
0.014
0.016
0.018
15