w WM8998 High Performance Audio Hub CODEC DESCRIPTION [1] The WM8998 is a highly-integrated low-power audio hub CODEC for smartphones, tablets and other portable audio devices. It is optimised for the needs of multimedia devices using SLIMbus application processors. The WM8998 digital core combines fixed-function signal processing blocks with a fully-flexible, all-digital audio mixing and routing engine, for extensive use-case flexibility. Signal processing blocks include filters, EQ, dynamics processors and sample rate converters. A SLIMbus interface supports multi-channel audio paths and host control register access. Multiple sample rates are supported concurrently via the SLIMbus interface. Three further digital audio interfaces are provided, each supporting a wide range of standard audio sample rates and serial interface formats. Automatic sample rate detection enables seamless wideband/narrowband voice call handover. The stereo headphone driver provides ground-referenced outputs, with noise levels as low as 1μVRMS for hi-fi quality line or headphone output. The CODEC also features a stereo line output, stereo 2W Class-D speaker outputs, a dedicated BTL earpiece output, PDM for external speaker amplifiers, and an IEC-60958-3 compatible S/PDIF transmitter. A signal generator for controlling haptics devices is included; vibe actuators can connect directly to the ClassD speaker output, or via an external driver on the PDM output interface. All inputs, outputs and system interfaces can function concurrently. The WM8998 supports up to six analogue mic/line inputs, and up to three PDM digital inputs. The input multiplexers support up to three signal paths. Microphone activity detection with interrupt is available. A smart accessory interface supports most standard 3.5mm accessories. Impedance sensing and measurement is provided for external accessory and push-button detection. The WM8998 power, clocking and output driver architectures are all designed to maximise battery life in voice, music and standby modes. Low-power ‘Sleep’ is supported, with configurable wake-up events. The WM8998 is powered from a 1.8V external supply. A separate supply is required for the Class D speaker drivers (typically direct connection to 4.2V battery). Two integrated FLLs provide support for a wide range of system clock frequencies. The WM8998 is configured using the I2C or SLIMbus interfaces. The fully-differential internal analogue architecture, minimal analogue signal paths and on-chip RF noise filters ensure a very high degree of noise immunity. FEATURES Hi-Fi audio hub CODEC for mobile applications Digital audio processing core - Fully flexible digital signal routing and mixing Wind noise, sidetone and other programmable filters - Dynamic Range Control (compressor, limiter) Fully parametric EQs - Low-pass / High-pass filters Multi-channel asynchronous sample rate conversion Integrated multi-channel 24-bit hi-fi audio hub CODEC - 3 ADCs, 96dB SNR microphone input (48kHz) - 7 DACs, 122dB SNR headphone playback (48kHz) Audio inputs - Up to 6 analogue or 3 digital microphone inputs - Single-ended or differential mic/line inputs Stereo headphone output driver - 28mW into 32Ω load at 0.1% THD+N - 6.9mW typical headphone playback power consumption Pop suppression functions - 1µVRMS noise floor (A-weighted) Ground-referenced line output driver - Stereo single-ended or Mono differential configuration Mono BTL earpiece output driver - 100mW into 32Ω BTL load at 5% THD+N Stereo (2 x 2W) Class D speaker output drivers - Direct drive of external haptics vibe actuators Two-channel digital speaker (PDM) output interface IEC-60958-3 compatible S/PDIF transmitter SLIMbus audio and control interface 3 full digital audio interfaces - Standard sample rates from 8kHz up to 192kHz - TDM support on all AIFs - 6 channel input and output on AIF1 and AIF2 Flexible clocking, derived from MCLKn, BCLKn or SLIMbus 2 low-power FLLs support reference clocks down to 32kHz Advanced accessory detection functions - Low-power standby mode and configurable wake-up Configurable functions on 5 GPIO pins Integrated LDO regulators and charge pumps Support for single 1.8V supply operation Small W-CSP package, 0.4mm pitch APPLICATIONS Smartphones and Multimedia handsets Tablets and Mobile Internet Devices (MID) WOLFSON MICROELECTRONICS plc Product Brief, June 2014, Rev 3.0 [1] This product is protected by Patents US 7,622,984, US 7,626,445, US 7,765,019 and GB 2,432,765 Copyright 2014 Wolfson Microelectronics plc WM8998 Pre-Production BLOCK DIAGRAM MICBIAS1 MICBIAS Generators MICBIAS2 LDO 2 Charge Pump 2 Charge Pump 1 LDO 1 SPKVDDL MICBIAS3 SPKGNDL SPKVDDR AVDD Reference Generator AGND SPKGNDR VREFC HPOUTL DAC HPOUTFB1/MICDET2 IN1BLN IN1BLP - IN1ALN/DMICCLK1 ADC + IN1ALP DAC HPOUTR DAC LINEOUTL LINEOUTFB Digital Core IN1BRN DAC LINEOUTR DAC EPOUTP EPOUTN DAC SPKOUTLP SPKOUTLN DAC SPKOUTRP SPKOUTRN IN1BRP - IN1ARN/DMICDAT1 5-Band Equaliser (EQ) Dynamic Range Control (DRC) Low Pass / High Pass Filter (LHPF) ADC + IN1ARP Digital Mic Interface Asynchronous Sample Rate Conversion Automatic Sample Rate Detection Tone Generator PWM Signal Generator Haptic Control Signal Generator S/PDIF Output Generator IN2BN IN2BP IN2AN/DMICCLK2 - IN2AP/DMICDAT2 + ADC SPKCLK PDM Driver SPKDAT Digital Mic Interface AEC (Echo Cancellation) Loopback MCLK1 MCLK2 AIFnBCLK AIFnLRCLK Clocking Control 2 x FLL External Accessory Detect JACKDET MICDET1/HPOUTFB2 HPDETL HPDETR SYSCLK ASYNCCLK Digital Audio Interface AIF1 Digital Audio Interface AIF2 Digital Audio Interface AIF3 SLIM Bus Interface GPIO Control Interface SLIMCLK w Product Brief , June 2014, Rev 3.0 2 WM8998 Pre-Production TABLE OF CONTENTS DESCRIPTION ................................................................................................................ 1 FEATURES ..................................................................................................................... 1 APPLICATIONS ............................................................................................................. 1 BLOCK DIAGRAM ......................................................................................................... 2 TABLE OF CONTENTS.................................................................................................. 3 PIN CONFIGURATION ................................................................................................... 4 ORDERING INFORMATION ........................................................................................... 5 PIN DESCRIPTION ......................................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ................................................................................. 8 RECOMMENDED OPERATING CONDITIONS .............................................................. 9 ELECTRICAL CHARACTERISTICS ............................................................................ 10 TERMINOLOGY ......................................................................................................................... 20 DEVICE DESCRIPTION ............................................................................................... 21 INTRODUCTION ........................................................................................................................ 21 HI-FI AUDIO CODEC ................................................................................................................. 21 DIGITAL AUDIO CORE ............................................................................................................. 22 DIGITAL INTERFACES ............................................................................................................. 22 OTHER FEATURES .................................................................................................................. 23 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 24 PACKAGE DIMENSIONS ............................................................................................. 25 IMPORTANT NOTICE .................................................................................................. 26 ADDRESS: ................................................................................................................................. 26 REVISION HISTORY .................................................................................................... 27 w Product Brief, June 2014, Rev 3.0 3 WM8998 Pre-Production PIN CONFIGURATION w Product Brief , June 2014, Rev 3.0 4 WM8998 Pre-Production ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8998ECS/R -40C to +85C PACKAGE MOISTURE SENSITIVITY LEVEL W-CSP (Pb-free, Tape and reel) PEAK SOLDERING TEMPERATURE MSL1 260C Note: Reel quantity = 7000 PIN DESCRIPTION A description of each pin on the WM8998 is provided below. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. All Digital Output pins are CMOS outputs, unless otherwise stated. PIN NO NAME TYPE DESCRIPTION F7 ADDR Digital Input Control interface (I2C) address select A2, B7, D10, E12, H4 AGND Supply Analogue ground (Return path for AVDD) Audio interface 1 bit clock J12 AIF1BCLK Digital Input / Output F10 AIF1LRCLK Digital Input / Output Audio interface 1 left / right clock H11 AIF1RXDAT Digital Input Audio interface 1 RX digital audio data G10 AIF1TXDAT Digital Output Audio interface 1 TX digital audio data J9 AIF2BCLK Digital Input / Output Audio interface 2 bit clock H9 AIF2LRCLK Digital Input / Output Audio interface 2 left / right clock G7 AIF2RXDAT Digital Input Audio interface 2 RX digital audio data H8 AIF2TXDAT Digital Output Audio interface 2 TX digital audio data J6 AIF3BCLK Digital Input / Output Audio interface 3 bit clock H5 AIF3LRCLK Digital Input / Output Audio interface 3 left / right clock G5 AIF3RXDAT Digital Input Audio interface 3 RXdigital audio data F5 AIF3TXDAT Digital Output Audio interface 3 TX digital audio data Analogue supply Charge pump 1 fly-back capacitor pin A3, A7, J4 AVDD Supply B9 CP1CA Analogue Output B10 CP1CB Analogue Output Charge pump 1 fly-back capacitor pin A10 CP1VOUTN Analogue Output Charge pump 1 negative output decoupling pin A9 CP1VOUTP Analogue Output Charge pump 1 positive output decoupling pin B11 CP2CA Analogue Output Charge pump 2 fly-back capacitor pin A11 CP2CB Analogue Output Charge pump 2 fly-back capacitor pin C11 CP2VOUT Analogue Output Charge pump 2 output decoupling pin / Supply for LDO2 C10 CPGND Supply Charge pump 1 & 2 ground (Return path for CPVDD) C9 CPVDD Supply Supply for Charge Pump 1 & 2 G12, J10 DBVDD1 Supply Digital buffer (I/O) supply (core functions and Audio Interface 1) J7 DBVDD2 Supply Digital buffer (I/O) supply (for Audio Interface 2, GPIO2, GPIO4) J5 DBVDD3 Supply Digital buffer (I/O) supply (for Audio Interface 3, GPIO3) H13, J8 DCVDD Supply Digital core supply D5, D6, D7, D8, E4, E5, E6, E7, E8, E9, E10, F4, F6, G6, G13, H6 DGND Supply Digital ground (Return path for DCVDD, DBVDD1, DBVDD2 and DBVDD3) A5 EPOUTN Analogue Output Earpiece negative output A4 EPOUTP Analogue Output Earpiece positive output F9 GPIO1 Digital Input / Output General Purpose pin GPIO1. The output configuration is selectable CMOS or Open Drain. w Product Brief, June 2014, Rev 3.0 5 WM8998 PIN NO Pre-Production NAME TYPE DESCRIPTION H7 GPIO2 Digital Input / Output G4 GPIO3 Digital Input / Output General Purpose pin GPIO3. The output configuration is selectable CMOS or Open Drain. G8 GPIO4 Digital Input / Output General Purpose pin GPIO4. The output configuration is selectable CMOS or Open Drain. E11 GPIO5 Digital Input / Output General Purpose pin GPIO5. The output configuration is selectable CMOS or Open Drain. D11 GPSWN Analogue Output General Purpose analogue switch contact (negative) D12 GPSWP Analogue Input General Purpose analogue switch contact (positive) B12 HPDETL Analogue Input Headphone left (HPOUTL) sense input A12 HPDETR Analogue Input Headphone right (HPOUTR) sense input HPOUTFB1/ MICDET2 Analogue Input HPOUTL and HPOUTR ground feedback pin 1/ Microphone & accessory sense input 2 A13 General Purpose pin GPIO2. The output configuration is selectable CMOS or Open Drain. B8 HPOUTL Analogue Output Left headphone output A8 HPOUTR Analogue Output Right headphone output C1 IN1ALN/ DMICCLK1 Analogue Input / Digital Output Left channel negative differential Mic/Line input / Digital MIC clock output 1 C2 IN1ALP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input C3 IN1ARN/ DMICDAT1 Analogue input / Digital Input Right channel negative differential Mic/Line input / Digital MIC data input 1 C4 IN1ARP Analogue Input Right channel single-ended Mic/Line input / Right channel positive differential Mic/Line input B1 IN2AN/ DMICCLK2 Analogue Input / Digital Output Negative differential Mic/Line input / Digital MIC clock output 2 B2 IN2AP/ DMICDAT2 Analogue Input / Digital Input Single-ended Mic/Line input / Positive differential Mic/Line input/ Digital MIC data input 2 D1 IN1BLN Analogue Input Left channel negative differential Mic/Line input D2 IN1BLP Analogue Input Left channel single-ended Mic/Line input / Left channel positive differential Mic/Line input D3 IN1BRN Analogue input Right channel negative differential Mic/Line input D4 IN1BRP Analogue Input Right channel single-ended Mic/Line input / Right channel positive differential Mic/Line input B3 IN2BN Analogue Input Negative differential Mic/Line input B4 IN2BP Analogue Input Single-ended Mic/Line input / Positive differential Mic/Line input F11 IRQ ¯¯¯ Digital Output Interrupt Request (IRQ) output (default is active low). The pin configuration is selectable CMOS or Open Drain. C8 JACKDET Analogue Input Jack detect input F13 LDOENA Digital Input Enable pin for LDO1 Supply Supply for LDO1 Analogue Output LDO1 output E13 LDOVDD D13 LDOVOUT A6 LINEOUTFB Analogue Input LINEOUTL and LINEOUTR ground loop noise rejection feedback B6 LINEOUTL Analogue Output Left line output B5 LINEOUTR Analogue Output Right line output Digital Input Master clock 1 H12 MCLK1 F12 MCLK2 Digital Input Master clock 2 C7 MICBIAS1 Analogue Output Microphone bias 1 C6 MICBIAS2 Analogue Output Microphone bias 2 C5 MICBIAS3 Analogue Output Microphone bias 3 B13 MICDET1/ HPOUTFB2 Analogue Input Microphone & accessory sense input 1/ HPOUTL and HPOUTR ground feedback pin 2 w Product Brief , June 2014, Rev 3.0 6 WM8998 Pre-Production PIN NO NAME A1, C13 MICVDD TYPE Analogue Output DESCRIPTION LDO2 output decoupling pin (generated internally by WM8998). (Can also be used as reference/supply for external microphones.) D9 RESET ¯¯¯¯¯¯ Digital Input Digital Reset input (active low) J11 SCLK Digital Input Control interface (I2C) clock input F8 SDA Digital Input / Output Control interface (I2C) data input and output The output function is implemented as an Open Drain circuit. J13 SLIMCLK Digital Input SLIMBus Clock input G11 SLIMDAT Digital Input / Output SLIMBus Data input / output H10 SPKCLK Digital Output Digital speaker (PDM) clock output G9 SPKDAT Digital Output Digital speaker (PDM) data output G1, G2 SPKGNDL Supply Left speaker driver ground (Return path for SPKVDDL) H1, H2 SPKGNDR Supply Right speaker driver ground (Return path for SPKVDDR) F2 SPKOUTLN Analogue Output Left speaker negative output F1 SPKOUTLP Analogue Output Left speaker positive output J2 SPKOUTRN Analogue Output Right speaker negative output J1 SPKOUTRP Analogue Output Right speaker positive output E1, E2, E3, F3, G3 SPKVDDL Supply Left speaker driver supply H3, J3 SPKVDDR Supply Right speaker driver supply C12 VREFC Analogue Output Bandgap reference decoupling capacitor connection w Product Brief, June 2014, Rev 3.0 7 WM8998 Pre-Production ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. MIN MAX Supply voltages (LDOVDD, AVDD, DCVDD, CPVDD) CONDITION -0.3V +2.0V Supply voltages (DBVDD1, DBVDD2, DBVDD3) -0.3V +4.0V Supply voltages (SPKVDDL, SPKVDDR) -0.3V +6.0V Voltage range digital inputs (DBVDD1 domain) AGND - 0.3V DBVDD1 + 0.3V Voltage range digital inputs (DBVDD2 domain) AGND - 0.3V DBVDD2 + 0.3V Voltage range digital inputs (DBVDD3 domain) AGND - 0.3V DBVDD3 + 0.3V Voltage range digital inputs (DMICDATn) AGND - 0.3V MICVDD + 0.3V Voltage range analogue inputs (IN1A*, IN1B*, IN2A*, MICDETn, HPOUTFBn, LINEOUTFB) AGND - 0.3V MICVDD + 0.3V AGND - 3.3V MICVDD + 0.3V Voltage range analogue inputs (IN2B*) Voltage range analogue inputs (JACKDET, HPDETL, HPDETR) CP1VOUTN - 0.3V AVDD + 0.3V Voltage range analogue inputs (GPSWP, GPSWN) AGND - 0.3V MICVDD + 0.3V Ground (DGND, CPGND, SPKGNDL, SPKGNDR) AGND - 0.3V AGND + 0.3V Operating temperature range, TA -40ºC +85ºC Operating junction temperature, TJ -40ºC +125ºC Storage temperature after soldering -65ºC +150ºC Note: CP1VOUTN is an internal supply, generated by the WM8998 Charge Pump (CP1). The CP1VOUTN voltage may vary between AGND and -CPVDD. w Product Brief , June 2014, Rev 3.0 8 WM8998 Pre-Production RECOMMENDED OPERATING CONDITIONS PARAMETER TYP MAX DCVDD (≤24.576MHz clocking) 1.14 1.2 1.9 DCVDD (>24.576MHz clocking) 1.71 1.8 1.9 Digital supply range (I/O) DBVDD1 1.7 1.9 Digital supply range (I/O) DBVDD2, DBVDD3 1.7 3.47 V LDOVDD 1.7 1.8 1.9 V 1.8 1.9 V Digital supply range (Core) See notes 2, 3, 4, 5 LDO supply range Charge Pump supply range SYMBOL MIN CPVDD 1.7 Speaker supply range SPKVDDL, SPKVDDR 2.4 Analogue supply range See note 2 AVDD 1.7 Ground See note 1 Power supply rise time See notes 7, 8, 9, 10 Operating temperature range DGND, AGND, CPGND, SPKGNDL, SPKGNDR 1.8 DCVDD 10 1 TA -40 V V 5.5 V 1.9 V 0 All other supplies UNIT V 2000 µs 85 °C Notes: 1. 2. 3. The grounds must always be within 0.3V of AGND. AVDD must be supplied before DCVDD. DCVDD must not be powered if AVDD is not present. There are no other power sequencing requirements. An internal LDO (powered by LDOVDD) can be used to provide the DCVDD supply. 4. 5. ‘Sleep’ mode is supported when DCVDD is below the limits noted, provided AVDD and DBVDD1 are present. Under default conditions, digital core clocking rates above 24.576MHz are inhibited. The register-controlled clocking limit should only be raised when the applicable DCVDD voltage is present. 6. An internal Charge Pump and LDO (powered by CPVDD) provide the microphone bias supply; the MICVDD pin should not be connected to an external supply. 7. DCVDD minimum rise time does not apply when this is powered using the internal LDO. 8. If DCVDD is supplied externally, and the rise time exceeds 2ms, then RESET ¯¯¯¯¯¯ must be asserted (low) during the rise, and held asserted until after DCVDD is within the recommended operating limits. 9. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin. However, Wolfson strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed. 10. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling capacitor and pin. w Product Brief, June 2014, Rev 3.0 9 WM8998 Pre-Production ELECTRICAL CHARACTERISTICS Test Conditions AVDD = 1.8V, With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Signal Level (IN1AL, IN1AR, IN1BL, IN1BR, IN2A, IN2B) Full-scale input signal level (0dBFS output) VINFS Single-ended PGA input, 6dB PGA gain 0.5 -6 VRMS dBV Differential PGA input, 0dB PGA gain 1 0 VRMS dBV Notes: 1. The full-scale input signal level is also the maximum analogue input level, before clipping occurs. 2. The full-scale input signal level changes in proportion with AVDD. For differential input, it is calculated as AVDD / 1.8. 3. A 1.0VRMS differential signal equates to 0.5VRMS/-6dBV per input. 4. A sinusoidal input signal is assumed. Test Conditions TA = +25ºC With the exception of the condition(s) noted above, the following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Pin Characteristics (IN1AL, IN1AR, IN1BL, IN1BR, IN2A, IN2B) Input resistance Input capacitance RIN Differential input, All PGA gain settings 24 Single-ended input, 0dB PGA gain 16 CIN k 5 pF Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Input Programmable Gain Amplifiers (PGAs) Minimum programmable gain 0 dB Maximum programmable gain 31 dB 1 dB Programmable gain step size Guaranteed monotonic Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Microphone Input Signal Level (DMICDAT1, DMICDAT2) Full-scale input signal level (0dBFS output) 0dB gain -6 dBFS Notes: 5. The digital microphone input signal level is measured in dBFS, where 0dBFS is a signal level equal to the full-scale range (FSR) of the PDM input. The FSR is defined as the amplitude of a 1kHz sine wave whose positive and negative peaks are represented by the maximum and minimum digital codes respectively - this is the largest 1kHz sine wave that will fit in the digital output range without clipping. Note that, because the definition of FSR is based on a sine wave, the PDM data format can support signals larger than 0dBFS. w Product Brief , June 2014, Rev 3.0 10 WM8998 Pre-Production Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Headphone Output Driver (HPOUTL, HPOUTR) Load resistance Load capacitance DC offset at Load Charge Pump Normal mode (default) 15 Charge Pump Low Impedance mode 6 Device survival with load applied indefinitely 0.1 Ω Direct connection, Single-ended mode 500 Direct connection, Differential (BTL) mode 250 Connection via 16Ω series resistor 2 Single-ended mode 0.1 Differential (BTL) mode 0.2 pF nF mV Note - to support HPOUT loads less than 15Ω, the Charge Pump (CP1) must be configured for low impedance operation. Line Output Driver (LINEOUTL, LINEOUTR) Load resistance Load capacitance DC offset at Load Normal operation 600 Mono Mode (BTL) 600 Device survival with load applied indefinitely 0.1 Ω Direct connection, Single-ended mode 500 Direct connection, Differential (BTL) mode 250 Connection via 16Ω series resistor 2 Single-ended mode 0.1 Differential (BTL) mode 0.2 pF nF mV Earpiece Output Driver (EPOUTP+EPOUTN) Load resistance Load capacitance Charge Pump Normal mode (default) 30 Charge Pump Low Impedance mode 15 Device survival with load applied indefinitely 0.1 Ω Direct connection (BTL) 250 pF Connection via 16Ω series resistor 2 nF DC offset at Load 0.1 mV Note - to support HPOUT loads less than 15Ω, the Charge Pump (CP1) must be configured for low impedance operation. Speaker Output Driver (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN) Load resistance Normal operation 4 Device survival with load applied indefinitely 0 Ω Load capacitance 200 pF DC offset at Load 5 mV SPKVDD leakage current 1 µA w Product Brief, June 2014, Rev 3.0 11 WM8998 Pre-Production Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Input Paths (IN1AL, IN1AR, IN1BL, IN1BR, IN2A, IN2B) to ADC (Differential Input Mode, INn_SRC = x0) Signal to Noise Ratio (A-weighted) Total Harmonic Distortion Total Harmonic Distortion Plus Noise SNR High performance mode (INn_OSR = 1) 86 Normal mode (INn_OSR = 0) 93 THD -1dBV input -88 THD+N -1dBV input -86 Channel separation (Left/Right) Input noise floor Common mode rejection ratio 96 CMRR PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR dB dB -76 dB 100 dB A-weighted, PGA gain = +18dB 3.2 µVRMS PGA gain = +30dB 65 dB PGA gain = 0dB 70 100mV (peak-peak) 217Hz 70 100mV(peak-peak) 10kHz 65 100mV (peak-peak) 217Hz 95 100mV(peak-peak) 10kHz 95 dB dB Analogue Input Paths (IN1AL, IN1AR, IN1BL, IN1BR, IN2A, IN2B) to ADC (Single-Ended Input Mode, INn_SRC = x1) PGA Gain = +6dB unless otherwise stated. Signal to Noise Ratio (A-weighted) Total Harmonic Distortion Total Harmonic Distortion Plus Noise SNR High performance mode (INn_OSR = 1) 94 Normal mode (INn_OSR = 0) 92 THD -7dBV input -81 THD+N -7dBV input -80 Channel separation (Left/Right) Input noise floor PSRR PSRR (SPKVDDL, SPKVDDR) PSRR dB dB -71 dB 100 dB 4.6 µVRMS 100mV (peak-peak) 217Hz 70 dB 100mV(peak-peak) 10kHz 50 A-weighted, PGA gain = +18dB PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) w 83 100mV (peak-peak) 217Hz 85 100mV(peak-peak) 10kHz 70 dB Product Brief , June 2014, Rev 3.0 12 WM8998 Pre-Production Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Headphone Output (HPOUTL, HPOUTR; RL = 32) Maximum output power PO 0.1% THD+N 28 mW SNR A-weighted, Output signal = 1Vrms 122 dB THD PO = 20mW -86 dB THD+N PO = 20mW -84 dB THD PO = 5mW -89 dB THD+N PO = 5mW -85 dB Channel separation (Left/Right) PO = 20mW 110 dB Output noise floor A-weighted 1 µVRMS 100mV (peak-peak) 217Hz 115 dB 100mV (peak-peak) 10kHz 80 100mV (peak-peak) 217Hz 115 100mV(peak-peak) 10kHz 80 Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR dB DAC to Headphone Output (HPOUTL, HPOUTR; RL = 16) Maximum output power Signal to Noise Ratio Total Harmonic Distortion PO 0.1% THD+N SNR A-weighted, Output signal = 1Vrms 114 34 mW 122 dB THD PO = 20mW -78 dB THD+N PO = 20mW -76 dB THD PO = 5mW -78 THD+N PO = 5mW -77 Channel separation (Left/Right) PO = 20mW 110 Output noise floor A-weighted 1 100mV (peak-peak) 217Hz 115 100mV (peak-peak) 10kHz 80 Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz 115 100mV(peak-peak) 10kHz 115 dB -67 dB 2 µVRMS dB dB dB DAC to Line Output (HPOUTL, HPOUTR; Load = 10k, 50pF) Full-scale output signal level VOUT 0dBFS input 1 0 Signal to Noise Ratio SNR A-weighted, Output signal = 1Vrms 114 THD 0dBFS input -89 THD+N 0dBFS input -88 Total Harmonic Distortion Total Harmonic Distortion Plus Noise Channel separation (Left/Right) 122 dB dB -73 dB 2 µVRMS 110 Output noise floor PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR w Vrms dBV A-weighted 1 100mV (peak-peak) 217Hz 115 100mV (peak-peak) 10kHz 80 100mV (peak-peak) 217Hz 115 100mV(peak-peak) 10kHz 80 dB dB dB Product Brief, June 2014, Rev 3.0 13 WM8998 Pre-Production Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Line Output (LINEOUTL, LINEOUTR; Load = 10k, 50pF) Full-scale output signal level VOUT 0dBFS input 1 0 Signal to Noise Ratio SNR A-weighted, Output signal = 1Vrms 114 THD 0dBFS input -89 THD+N 0dBFS input -88 Total Harmonic Distortion Total Harmonic Distortion Plus Noise Channel separation (Left/Right) Vrms dBV 122 dB dB -73 dB 2 µVRMS 110 Output noise floor PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR A-weighted 1 100mV (peak-peak) 217Hz 127 100mV (peak-peak) 10kHz 90 100mV (peak-peak) 217Hz 130 100mV(peak-peak) 10kHz 85 dB dB dB DAC to Earpiece Output (EPOUTP+EPOUTN, RL = 32 BTL) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion PO SNR 0.1% THD+N 83 5% THD+N 100 A-weighted, Output signal = 2Vrms 118 mW 127 dB THD PO = 50mW -92 dB THD+N PO = 50mW -90 dB THD PO = 5mW -85 THD+N PO = 5mW -83 -73 dB A-weighted 1 2.5 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 113 100mV (peak-peak) 10kHz 115 PSRR (SPKVDDL, SPKVDDR) PSRR Total Harmonic Distortion Plus Noise Output noise floor 100mV (peak-peak) 217Hz 130 100mV(peak-peak) 10kHz 100 dB dB dB DAC to Earpiece Output (EPOUTP+EPOUTN, RL = 16 BTL) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion PO 0.1% THD+N 83 10% THD+N 110 A-weighted, Output signal = 2Vrms 127 dB THD PO = 50mW -92 dB THD+N PO = 50mW -90 dB SNR mW THD PO = 5mW -90 dB THD+N PO = 5mW -88 dB A-weighted 1 µVRMS PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR 100mV (peak-peak) 217Hz 113 dB 100mV (peak-peak) 10kHz 115 PSRR (SPKVDDL, SPKVDDR) PSRR Total Harmonic Distortion Plus Noise Output noise floor w 100mV (peak-peak) 217Hz 130 100mV(peak-peak) 10kHz 100 dB Product Brief , June 2014, Rev 3.0 14 WM8998 Pre-Production Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Speaker Output (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN, Load = 8, 22µH, BTL) High Performance mode (OUT4_OSR=1) Maximum output power Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise PO SNR SPKVDD = 5.0V, 1% THD+N 1.37 SPKVDD = 4.2V, 1% THD+N 0.97 SPKVDD = 3.6V, 1% THD+N 0.71 A-weighted, Output signal = 3Vrms 90 W 100 dB THD PO = 0.7W -74 dB THD+N PO = 0.7W -73 dB THD PO = 0.5W -74 THD+N PO = 0.5W -73 Channel separation (Left/Right) PO = 0.5W 95 Output noise floor A-weighted 30 PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR 100mV (peak-peak) 217Hz 80 100mV (peak-peak) 10kHz 70 100mV (peak-peak) 217Hz 70 100mV (peak-peak) 10kHz 70 dB -57 dB 95 µVRMS dB dB dB DAC to Speaker Output (SPKOUTLP+SPKOUTLN, SPKOUTRP+SPKOUTRN, Load = 4, 15µH, BTL) High Performance mode (OUT4_OSR=1) Maximum output power PO SPKVDD = 5.0V, 1% THD+N 2.4 SPKVDD = 4.2V, 1% THD+N 1.69 SPKVDD = 3.6V, 1% THD+N 1.24 A-weighted, Output signal = 3Vrms 100 dB THD PO = 1.0W -61 dB THD+N PO = 1.0W -60 dB THD PO = 0.5W -64 dB THD+N PO = 0.5W -63 dB Channel separation (Left/Right) PO = 0.5W 85 dB Output noise floor A-weighted 30 µVRMS 100mV (peak-peak) 217Hz 80 dB 100mV (peak-peak) 10kHz 70 Signal to Noise Ratio Total Harmonic Distortion Total Harmonic Distortion Plus Noise Total Harmonic Distortion Total Harmonic Distortion Plus Noise SNR PSRR (DBVDDn, LDOVDD, CPVDD, AVDD) PSRR PSRR (SPKVDDL, SPKVDDR) PSRR w 100mV (peak-peak) 217Hz 70 100mV (peak-peak) 10kHz 70 W dB Product Brief, June 2014, Rev 3.0 15 WM8998 Pre-Production Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Input / Output (except DMICDATn and DMICCLKn) Digital I/O is referenced to DBVDD1, DBVDD2 or DBVDD3. See “Recommended Operating Conditions” for the valid operating voltage range of each DBVDDn domain. Input HIGH Level Input LOW Level VIH VIL VDBVDDn =1.8V ±10% 0.65 VDBVDDn VDBVDDn =3.3V ±10% 0.7 VDBVDDn V VDBVDDn =1.8V ±10% 0.35 VDBVDDn VDBVDDn =3.3V ±10% 0.3 VDBVDDn V Note that digital input pins should not be left unconnected or floating. Output HIGH Level VOH IOH = 1mA Output LOW Level VOL IOL = -1mA 0.9 VDBVDDn V Input capacitance 0.1 VDBVDDn V 1 µA 10 pF Input leakage -1 Pull-up resistance (where applicable) 42 49 56 kΩ Pull-up resistance (where applicable) 28 36 45 kΩ Digital Microphone Input / Output (DMICDATn and DMICCLKn) DMICDATn and DMICCLKn are each referenced to a selectable supply, VSUP, according to the INn_DMIC_SUP registers 0.65 VSUP DMICDATn input HIGH Level VIH DMICDATn input LOW Level VIL DMICCLKn output HIGH Level VOH IOH = 1mA DMICCLKn output LOW Level VOL IOL = -1mA V 0.35 VSUP V 0.2 VSUP V 1 µA 0.8 VSUP V Input capacitance 10 Input leakage -1 pF SLIMbus Digital Input / Output (SLIMCLK and SLIMDAT) 1.8V I/O Signalling (ie. 1.65V ≤ DBVDD1 ≤1.95V) 0.65 VDBVDD1 Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH IOH = 1mA Output LOW Level VOL IOL = -1mA V 0.35 VDBVDD1 0.9 VDBVDD1 V V Pin capacitance 0.1 VDBVDD1 V 5 pF 26.5 MHz General Purpose Input / Output (GPIOn) Clock output frequency GPIO pin configured as OPCLK or FLL output General Purpose Switch See “Absolute Maximum Ratings” for voltage limits applicable to the GPSWP and GPSWN pins. Switch resistance RDS(ON) Switch closed, I=1mA 40 Ω Switch resistance RDS(OFF) Switch open 100 MΩ w Product Brief , June 2014, Rev 3.0 16 WM8998 Pre-Production Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Microphone Bias (MICBIAS1, MICBIAS2, MICBIAS3) Note - No capacitor on MICBIASn Note - In regulator mode, it is required that VMICVDD - VMICBIASn > 200mV Minimum Bias Voltage VMICBIAS Maximum Bias Voltage Bias Voltage output step size Regulator mode (MICBn_BYPASS=0) Load current ≤ 1.0mA Bias Voltage accuracy Output Noise Density Integrated noise voltage Load capacitance w V 0.1 PSRR V +5% V Regulator mode (MICBn_BYPASS=0), VMICVDD - VMICBIAS >200mV 2.4 mA Bypass mode (MICBn_BYPASS=1) 5.0 Regulator mode (MICBn_BYPASS=0), MICBn_LVL = 4h, Load current = 1mA, Measured at 1kHz 50 nV/Hz Regulator mode (MICBn_BYPASS=0), MICBn_LVL = 4h, Load current = 1mA, 100Hz to 7kHz, A-weighted 4 µVrms 100mV (peak-peak) 217Hz 95 dB 100mV (peak-peak) 10kHz 65 Regulator mode (MICBn_BYPASS=0), MICBn_EXT_CAP=0 Regulator mode (MICBn_BYPASS=0), MICBn_EXT_CAP=1 Output discharge resistance V 2.8 -5% Bias Current Power Supply Rejection Ratio (DBVDDn, LDOVDD, CPVDD, AVDD) 1.5 MICBn_ENA=0, MICBn_DISCH=1 50 1.8 pF 4.7 µF 5 kΩ Product Brief, June 2014, Rev 3.0 17 WM8998 Pre-Production Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT HP_IMPEDANCE_ RANGE=00 4 30 HP_IMPEDANCE_ RANGE=01 8 100 HP_IMPEDANCE_ RANGE=10 100 1000 HP_IMPEDANCE_ RANGE=11 1000 10000 Load impedance detection range Detection via the MICDET1 or MICDET2 pin (ACCDET_MODE=100) 400 6000 Ω Load impedance detection accuracy (ACCDET_MODE=001, 010 or 100) -30 +30 % Ω External Accessory Detect Load impedance detection range Detection via HPDETL pin (ACCDET_MODE=001) or HPDETR pin (ACCDET_MODE=010) Load impedance detection range Detection via the MICDET1 or MICDET2 pin (ACCDET_MODE=000). 2.2kΩ (2%) MICBIAS resistor. Note these characteristics assume no other component is connected to MICDETn. Jack Detection input threshold voltage (JACKDET) Jack Detect pull-up resistance w VJACKDET for MICD_LVL[0] = 1 0 3 for MICD_LVL[1] = 1 17 21 for MICD_LVL[2] = 1 36 44 for MICD_LVL[3] = 1 62 88 for MICD_LVL[4] = 1 115 160 for MICD_LVL[5] = 1 207 381 for MICD_LVL[8] = 1 475 30000 Jack insertion 0.5 x AVDD Jack removal 0.85 x AVDD 0.65 Ω 1 V 1.3 MΩ Product Brief , June 2014, Rev 3.0 18 WM8998 Pre-Production Test Conditions DBVDD1 = DBVDD2 = DBVDD3 = LDOVDD = CPVDD = AVDD = 1.8V, DCVDD = 1.2V (powered from LDO1), MICVDD = 3.0V (powered from LDO2), SPKVDDL = SPKVDDR = 4.2V, TA = +25ºC, 1kHz sinusoid signal, fs = 48kHz, Input PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX 1.7 2.7 3.3 UNIT MICVDD Charge Pump and Regulator (CP2 and LDO2) Output voltage VMICVDD Programmable output voltage step size Maximum output current Start-up time 4.7µF on MICVDD, IMICBIASn = 1mA V 50 mV 8 mA 4.5 ms Frequency Locked Loop (FLL1, FLL2) Output frequency Normal operation, input reference supplied Lock Time 13 50 Free-running mode, no reference supplied 30 FREF = 32kHz, FOUT = 24.576MHz 10 FREF = 12MHz, FOUT = 24.576MHz 1 MHz ms RESET pin Input RESET input pulse width (To trigger a Hardware Reset, the RESET input must be asserted for longer than this duration) 1 µs Test Conditions The following electrical characteristics are valid across the full range of recommended operating conditions. Device Reset Thresholds AVDD Reset Threshold VAVDD VAVDD rising VAVDD falling DCVDD Reset Threshold VDCVDD VDCVDD rising VDCVDD falling DBVDD1 Reset Threshold VDBVDD1 V 1.03 V 0.96 V 0.48 VDBVDD1 rising VDBVDD1 falling 0.96 0.54 0.54 Note that the reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured outside the voltage ranges defined in the “Recommended Operating Conditions” section. Refer to this section for the WM8998 power-up sequencing requirements. w Product Brief, June 2014, Rev 3.0 19 WM8998 Pre-Production TERMINOLOGY 1. 2. 3. 4. 5. 6. 7. 8. 9. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum full scale output signal and the output with no input signal applied. (Note that this is measured without any mute function enabled.) Total Harmonic Distortion (dB) – THD is the ratio of the RMS sum of the harmonic distortion products in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output. Total Harmonic Distortion plus Noise (dB) – THD+N is the ratio of the RMS sum of the harmonic distortion products plus noise in the specified bandwidth (see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output. Power Supply Rejection Ratio (dB) - PSRR is the ratio of a specified power supply variation relative to the output signal that results from it. PSRR is measured under quiescent signal path conditions. Common Mode Rejection Ratio (dB) – CMRR is the ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that results from it. Channel Separation (L/R) (dB) – left-to-right and right-to-left channel separation is the difference in level between the active channel (driven to maximum full scale output) and the measured signal level in the idle channel at the test signal frequency. The active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the associated idle channel. Multi-Path Crosstalk (dB) – is the difference in level between the output of the active path and the measured signal level in the idle path at the test signal frequency. The active path is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied. All performance measurements are specified with a 20kHz low pass ‘brick-wall’ filter and, where noted, an A-weighted filter. Failure to use these filters will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise. w Product Brief , June 2014, Rev 3.0 20 WM8998 Pre-Production DEVICE DESCRIPTION INTRODUCTION The WM8998 is a highly integrated low-power audio hub CODEC for mobile telephony and portable devices. It provides flexible, high-performance audio interfacing for handheld devices in a small and cost-effective package. It is optimised for the needs of tablet devices and multimedia phones using SLIMbus application processors. The WM8998 digital core provides configurable capability for signal processing algorithms, including parametric equalisation (EQ) and dynamic range control (DRC). Highly flexible digital mixing, including stereo full-duplex asynchronous sample rate conversion, provides use-case flexibility across a broad range of system architectures. A signal generator for controlling haptics vibe actuators is included. The WM8998 provides multiple digital audio interfaces, including SLIMbus, in order to provide independent and fully asynchronous connections to different processors (eg. application processor, baseband processor and wireless transceiver). A flexible clocking arrangement supports a wide variety of external clock references, including clocking derived from the digital audio interface. Two integrated Frequency Locked Loop (FLL) circuits provide additional flexibility. Unused circuitry can be disabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications. Configurable ‘Wake-Up’ actions can be associated with the low-power standby (Sleep) mode. Versatile GPIO functionality is provided, and support for external accessory / push-button detection inputs. Comprehensive Interrupt (IRQ) logic and status readback are also provided. HI-FI AUDIO CODEC The WM8998 is a high-performance low-power audio CODEC which uses a simple analogue architecture. Input path multiplexers select from up to 6 analogue mic/line and 3 digital microphone inputs; combinations of up to 3 inputs can be supported. 7 DACs are incorporated, providing a dedicated DAC for each output channel. The analogue outputs comprise a 28mW (122dB SNR) stereo headphone amplifier with groundreferenced output, a flexible (single-ended or differential) line output, a 100mW differential (BTL) earpiece driver, and a Class D stereo speaker driver capable of delivering 2W per channel into a 4Ω load. Six analogue inputs are provided, each supporting single-ended or differential input modes. In differential mode, the input path SNR is 96dB. Up to 3 analogue or digital input paths can be supported at one time. The audio CODEC is controlled directly via register access. The simple analogue architecture, combined with the integrated tone generator, enables simple device configuration and testing, minimising debug time and reducing software effort. The WM8998 output drivers are designed to support as many different system architectures as possible. Each output has a dedicated DAC which allows mixing, equalisation, filtering, gain and other audio processing to be configured independently for each channel. This allows each signal path to be individually tailored for the load characteristics. All outputs have integrated pop and click suppression features. The headphone, line and earpiece output drivers are ground-referenced, powered from an integrated charge pump, enabling high quality, power efficient headphone playback without any requirement for DC blocking capacitors. Ground loop feedback is incorporated, providing rejection of noise on the ground connections. The Class D speaker drivers deliver excellent power efficiency. High PSRR, low leakage and optimised supply voltage ranges enable powering from switching regulators or directly from the battery. Battery current consumption is minimised across a wide variety of voice communication and multimedia playback use cases. The WM8998 is cost-optimised for a wide range of mobile phone applications, and features two channels of Class D power amplification. For applications requiring more than two channels of power amplification (or when using the integrated Class D path to drive a haptics actuator), the PDM output channels can be used to drive two external PDM-input speaker drivers. In applications where stereo loudspeakers are physically widely separated, the PDM outputs can ease layout and EMC by avoiding the need to run the Class-D speaker outputs over long distances and interconnects. w Product Brief, June 2014, Rev 3.0 21 WM8998 Pre-Production DIGITAL AUDIO CORE The WM8998 uses a core architecture based on all-digital signal routing, making digital audio effects available on all signal paths, regardless of whether the source data input is analogue or digital. The digital mixing desk allows different audio effects to be applied simultaneously on many independent paths, whilst also supporting a variety of sample rates concurrently. This helps support many new audio use-cases. Soft mute and un-mute control allows smooth transitions between use-cases without interrupting existing audio streams elsewhere. Highly flexible digital mixing, including mixing between audio interfaces, is possible. The WM8998 performs stereo full-duplex asynchronous sample rate conversion, providing use-case flexibility across a broad range of system architectures. Automatic sample rate detection is provided, enabling seamless wideband/narrowband voice call handover. Dynamic Range Controller (DRC) functions are available for optimising audio signal levels. In playback modes, the DRC can be used to maximise loudness, while limiting the signal level to avoid distortion, clipping or battery droop, in particular for high-power output drivers such as speaker amplifiers. In record modes, the DRC assists in applications where the signal level is unpredictable. The 5-band parametric equaliser (EQ) functions can be used to compensate for the frequency characteristics of the output transducers. EQ functions can be cascaded to provide additional frequency control. Programmable high-pass and low-pass filters are also available for general filtering applications such as removal of wind and other low-frequency noise. DIGITAL INTERFACES Three serial digital audio interfaces (AIFs) each support PCM, TDM and I2S data formats for compatibility with most industry-standard chipsets. AIF1 and AIF2 support six input/output channels each; AIF3 supports two input/output channels. Bidirectional operation at sample rates up to 192kHz is supported. Three digital PDM input channels are available (one stereo, and one mono interface); these are typically used for digital microphones, powered from the integrated MICBIAS power supply regulators. Two PDM output channels are also available (one stereo interface); these are typically used for external power amplifiers. Embedded mute codes provide a control mechanism for external PDMinput devices. The WM8998 features a MIPI-compliant SLIMbus interface, providing 4 input, and 6 output channels of audio support. Mixed audio sample rates are supported on the SLIMbus interface. The SLIMbus interface also supports read/write access to the WM8998 control registers. An IEC-60958-3 compatible S/PDIF transmitter is incorporated, enabling stereo S/PDIF output on a GPIO pin. Standard S/PDIF sample rates of 32kHz up to 192kHz are all supported. The WM8998 is equipped with an I2C slave port (at up to 1MHz). Full access to the register map is also provided via the SLIMbus port. w Product Brief , June 2014, Rev 3.0 22 Pre-Production WM8998 OTHER FEATURES The WM8998 incorporates two 1kHz tone generators which can be used for ‘beep’ functions through any of the audio signal paths. The phase relationship between the two generators is configurable, providing flexibility in creating differential signals, or for test scenarios. Two Pulse Width Modulation (PWM) signal generators are incorporated. The duty cycle of each PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting. The PWM signal generators can be output directly on a GPIO pin. The WM8998 provides 5 GPIO pins, supporting selectable input/output functions for interfacing, detection of external hardware, and to provide logic outputs to other devices. Comprehensive Interrupt (IRQ) functionality is also provided for monitoring internal and external event conditions. A signal generator for controlling haptics devices is included, compatible with both Eccentric Rotating Mass (ERM) and Linear Resonant Actuator (LRA) haptic devices. The haptics signal generator is highly configurable, and can execute programmable drive event profiles, including reverse drive control. An external vibe actuator can be driven directly by the Class D speaker output. The WM8998 can be powered from a 1.8V external supply. A separate supply (4.2V) is typically required for the Class D speaker driver. Integrated Charge Pump and LDO Regulators circuits are used to generate supply rails for internal functions and to support powering or biasing of external microphones. A smart accessory interface is included, supporting most standard 3.5mm accessories. Jack detection, accessory sensing and impedance measurement is provided, for external accessory and push-button detection. Accessory detection can be used as a ‘Wake-Up’ trigger from low-power standby. Microphone activity detection with interrupt is also available. System clocking can be derived from the MCLK1 or MCLK2 input pins. Alternatively, the SLIMbus interface, or the audio interfaces (configured in Slave mode), can be used to provide a clock reference. Two integrated Frequency Locked Loop (FLL) circuits provide support for a wide range of clocking configurations, including the use of a 32kHz input clock reference. w Product Brief, June 2014, Rev 3.0 23 WM8998 Pre-Production RECOMMENDED EXTERNAL COMPONENTS DGND AGND CPGND SPKVDDL SPKGNDL 1.8V SPKGNDR 4.2V 1.0 F VREFC SDA SPKVDDR SCLK CPVDD ADDR Control Interface LDOVDD 4.7 F 4.7 F AVDD DBVDD1 MCLK1 DBVDD2 MCLK2 Master Clocks DBVDD3 GPIO1 4.7 F GPIO2 5 x 0.1 F GPIO GPIO3 DCVDD GPIO4 4.7 F GPIO5 LDOVOUT GPSWP LDO Control LDOENA Reset Control GPSWN RESET Interrupt Output IRQ CP1CA 2.2 F CP1CB SLIMbus Interface SLIMCLK CP1VOUTP SLIMDAT CP1VOUTN CP2CA AIF1BCLK 4.7 F 470nF CP2CB AIF1LRCLK Audio Interface 1 4.7 F 4.7 F CP2VOUT AIF1RXDAT AIF1TXDAT WM8998 JACKDET Jack Detect input AIF2BCLK Audio Interface 2 AIF2LRCLK HPOUTL AIF2RXDAT HPOUTR AIF2TXDAT HPOUTFB1/MICDET2 Headphone (Note: HPOUTFB ground connection close to headset jack) HPDETL AIF3BCLK Audio Interface 3 AIF3RXDAT AIF3TXDAT LINEOUTL Line Output LINEOUTR LINEOUTFB MICBIAS1 VDD CHAN GND Stereo Digital Microphone connection HPDETR AIF3LRCLK VDD CHAN GND (Note: LINEOUTFB ground connection close to output jack) CLK DAT DMIC IN1ALP IN1ALN/DMICCLK1 CLK DAT DMIC EPOUTN Earpiece Speaker EPOUTP IN1ARP IN1ARN/DMICDAT1 SPKOUTLN Loudspeaker SPKOUTLP 1 F Single-ended Line connection Outputs HPOUT and LINEOUT can be configured as Stereo pairs or Differential Mono. IN1BLP IN1BLN 1 F IN1BRP SPKOUTRN Loudspeaker SPKOUTRP IN1BRN SPKCLK MICBIAS2 MICDET1/HPOUTFB2 2.2k Differential Microphone connection 1 F 1 F Digital Speaker (PDM) interface SPKDAT IN2BP IN2BN MICBIAS1 Bias / Supplies for Microphones and External Accessory Detection MICBIAS2 2.2k Analogue and Digital Inputs w IN2AP/DMICDAT2 MICBIAS3 IN2AN/DMICCLK2 MICVDD 4.7 F Product Brief , June 2014, Rev 3.0 24 Pre-Production WM8998 PACKAGE DIMENSIONS w Product Brief, June 2014, Rev 3.0 25 WM8998 Pre-Production IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. 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ADDRESS: Wolfson Microelectronics plc 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w Product Brief , June 2014, Rev 3.0 26 WM8998 Pre-Production REVISION HISTORY DATE REV DESCRIPTION OF CHANGES 08/05/14 2.0 First Release. 25/06/14 2.1 Electrical Characteristics updated w PAGE CHANGED BY PH 11-19 PH Product Brief, June 2014, Rev 3.0 27