SS2015 CMOS High Sensitivity Micropower Hall Latch Packages Features and Benefits 1. 2. 3. 4. 5. 6. 7. 8. 9. Operation down to 4.5V Wide operating voltage range High sensitivity for direct reed switch replacement applications Output switches with absolute value of North or South pole from magnet Temperature compensation Open-Collector pre-driver 60V maximum withstand voltage Reverse polarity protection Package: TO-92S(SIP) 3 pin SIP (suffix UA) Functional Block Diagram Application Examples 1. 2. 3. 4. Brush-less DC Motor Brush-less DC Fan Revolution counting Speed measurement General Description: The SS2015 Hall effect latch sensor IC is fabricated from mixed signal CMOS technology. It incorporates advanced chopper-stabilization techniques to provide accurate and stable magnetic switch points. The circuit design provides an internally controlled clocking mechanism to cycle power to the Hall element and analog signal processing circuits. This serves to place the high current-consuming portions of the circuit into a “Sleep” mode. Periodically the device is “Awakened” by this internal logic and the magnetic flux from the Hall element is evaluated against the predefined thresholds. If the flux density is above or below the BOP/BRP thresholds then the output transistor is driven to change states accordingly. While in the “Sleep” cycle the output transistor is latched in its previous state. The design has been optimized for service in applications requiring extended operating lifetime in battery powered systems. An internal bandgap regulator is used to provide temperature compensated supply voltage for internal circuits and allows a wide operating supply range. The output transistor of the SS2015 will be latched on (BOP) in the presence of a sufficiently strong South or North magnetic field facing the marked side of the package. The output will be latched off (BRP) in the absence of a magnetic field. 1 V3.10 Nov 1, 2013 SS2015 CMOS High Sensitivity Micropower Hall Latch Typical Application Circuit SEC's pole-independent sensing technique allows for operation with either a north pole or south pole magnet orientation, enhancing the manufacturability of the device. The state-of-the-art technology provides the same output polarity for either pole face. It is strongly recommended that an external bypass be connected (in close proximity to the Hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chopper-stabilization technique. This is especially true due to the relatively high impedance of battery supplies. Functional Block Diagrams VDD Voltage Output Amp Hall Plate GND 2 V3.10 Nov 1, 2013 SS2015 CMOS High Sensitivity Micropower Hall Latch Pin Definitions and Descriptions SIP Pin № Name Type Function 1 3 2 VDD OUT GND Supply Output Ground Supply Voltage pin Open Drain Output pin Ground pin Absolute Maximum Ratings Parameter Symbol Supply Voltage (operating) Reverse Voltage, Output Voltage Output Current Operating Temperature Range Storage Temperature Range ESD Sensitivity VDD -VDD VOUT IOUT TA TS - Value Units 24 -24 30 50 -20 to 85 -55 to 150 4000 V V V mA °C °C V Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DC Electrical Characteristics DC Operating Parameters: TA = 25°C, VDD= 12V. Parameter Symbol Operating Voltage Supply Current Saturation Voltage VDD IDD VSAT IOFF Output Leakage Output Rise Time Output Fall Time Test Conditions Min Typ Max Units Operating Average IOUT = 20mA, B>BOP 4.5 B<BRP, VOUT = 20V 5 5 0.4 0.01 24 10 0.5 5 V mA V µA tr RL = 1.1K O, CL = 20pf 0.3 1.5 µS tf RL = 1.1K O, CL = 20pf 0.3 1.5 µS 3 V3.10 Nov 1, 2013 SS2015 CMOS High Sensitivity Micropower Hall Latch Magnetic Characteristics Operating Parameters: TA = 25°C, VDD =12V Parameter Symbol Min Operating Point Release Point Hysteresis BOP BRP BHYST 5 -70 Type Max Units 70 -5 Gs Gs Gs 80 ESD Protection Human Body Model (HBM) tests according to: Mil. Std. 883F method 3015.7 Parameter Symbol ESD Voltage VESD Limit Values Min Max ±4 Unit Notes kV Performance Characteristics Unique Features CMOS Hall IC Technology The chopper stabilized amplifier uses switched capacitor techniques to eliminate the amplifier offset voltage, which, in bipolar devices, is a major source of temperature sensitive drift. CMOS makes this advanced technique possible. The CMOS chip is also much smaller than a bipolar chip, allowing very sophisticated circuitry to be placed in less space. The small chip size also contributes to lower physical stress and less power consumption. Installation Comments Consider temperature coefficients of Hall IC and magnetic, as well as air gap and life time variations. Observe temperature limits during wave soldering. Typical IR solder-reflow profile: – No Rapid Heating and Cooling. – Recommended Preheating for max. 2minutes at 150°C – Recommended Reflowing for max. 5seconds at 240°C 4 V3.10 Nov 1, 2013 SS2015 CMOS High Sensitivity Micropower Hall Latch ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 5 V3.10 Nov 1, 2013 SS2015 CMOS High Sensitivity Micropower Hall Latch Package Information 2.13 1.87 0.75 ± 0.05 1.52 ± 0.1 Package UA, 3-Pin IP: 3° ± 1° 1.00 1.20 45° ± 1° 4.0 ± 0.01 1 2 3 3.0 ± 0.01 Sensor Location Active Area Depth: 0.84(Nom) 3° ± 1° 6° ± 1° 3° ± 1° 6° ± 1° 1 2 3 0.05 ± 0.05 1.6.± 0.1 0.44± 0.01 0.38 ± 0.01 14 .5 ± 1 0.39± 0.01 Notes: 1). Controlling dimension : mm ; 2). Leads must be free of flash and plating voids ; 3). Do not bend leads within 1 mm of lead to package interface ; 4). PINOUT: Pin 1 VDD Pin 2 GND Pin 3 Output 1.27 2.54 Ordering Information Part No. Pb-free Temperature Code Package Code Packing SS2015EUA YES -40°C to 85°C TO-92 Bulk, 1000 pieces/bag SS2015KUA YES -40°C to 125°C TO-92 Bulk, 1000 pieces/bag SS2015LUA YES -40°C to 150°C TO-92 Bulk, 1000 pieces/bag 6 V3.10 Nov 1, 2013