D1U4CS-W Communications www.murata-ps.com D1U4CS-W Communications Protocol Application Note Communication Protocol Support The D1U4CS-W family of power supplies currently supports 3.3V-bus and 5V-bus standard-mode (100kHz) I2C Serial Communication as outlined in Philips Semiconductors “The I2C Bus Specification Version 2.1” (January 2000). The available address lines currently allows for communication with up to 8 D1U4CS-W power supplies on a single serial communication bus. Each D1U4CS-W power supply contains a : The D1U4CS-W family of power supplies can also support 3.3V-bus and 5V-bus SMBUS Serial Communication as outlined in the SBS Implementers forum “System Management Bus (SMBUS) Specification Version 2.0” (August 2000) 1. 2K serial EEPROM device used for FRU data storage (FRU data specs customer specific) D1U4CS-W power supplies are configured to operate as slave-only devices. 2. System-On-Chip (SOC) -type controller used for D1U4CS-W status, fault, and parametric data reporting and remote on/off control However, they can be re-configured to support single master operation and multimaster and slave operation. I2C Device Addressing The D1U4CS-W family of power supplies supports 8-bit I2C addressing (7-bit slave address plus 1-bit read/write control). The specified I2C addresses are as follows: Table A1 - I2C Device Addresses Device Name Device Type Standalone EEPROM Flash-Emulated EEPROM I2C Port 24AA024 microcontroller flash-emulated EEPROM microcontroller PS Slot # 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 I2C Address 1010 000 1010 001 1010 010 1010 011 1010 100 1010 101 1010 110 1010 111 1110 000 1110 001 1110 010 1110 011 1110 100 1110 101 1110 110 1110 111 1011 000 1011 001 1011 010 1011 011 1011 100 1011 101 1011 110 1011 111 0xA0 0xA2 0xA4 0xA6 0xA8 0xAA 0xAC 0xAE 0xE0 0xE2 0xE4 0xE6 0xE8 0xEA 0xEC 0xEE 0xB0 0xB2 0xB4 0xB6 0xB8 0xBA 0xBC 0xBE For full details go to www.murata-ps.com/rohs www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 1 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note RAM Bytes Accessible Through I2C Serial Communications Upon power up, the D1U4CS-W power supplies maintain 27 RAM bytes that are accessible through I2C serial communication. These bytes provide power supply status information, fault information, and sensor data. The 27 data bytes are ordered as follows: Byte 0: Status0 - Power supply operation status 0 Byte 1: Status1 - Power supply operation status 1 Byte 2: Fault0 - Power supply fault 0 Byte 3: Fault1 - Power supply fault 1 Byte 4: Vout2 - Upper (MSB) Byte of 16-bit representation of Main Output Voltage Byte 5: Vout1 - Lower (LSB) Byte of 16-bit representation of Main Output Voltage Byte 6: Iout2 - Upper (MSB) Byte of 16-bit representation of Main Output Current Byte 7: Iout1 - Lower (LSB) Byte of 16-bit representation of Main Output Current Byte 8: Stanby_Vout2 - Upper (MSB) Byte of 16-bit representation of Standby Output Voltage Byte 9: Stanby_Vout1 - Lower (LSB) Byte of 16-bit representation of Standby Output Voltage Byte 10: Stanby_Iout2 - Upper (MSB) Byte of 16-bit representation of Standby Output Current Byte 11: Stanby_Iout1 - Lower (LSB) Byte of 16-bit representation of Standby Output Current Byte 12: Fan1_Speed2 - Upper (MSB) Byte of 16-bit representation of Fan1 speed Byte 13: Fan1_Speed1 - Lower (LSB) Byte of 16-bit representation of Fan1 speed Byte 14: Fan2_Speed2 - Upper (MSB) Byte of 16-bit representation of Fan2 speed Byte 15: Fan2_Speed1 - Lower (LSB) Byte of 16-bit representation of Fan2 speed Byte 16: Amb_Temp_2 - Upper (MSB) Byte of 16-bit representation of Ambient Temperature Byte 17: Amb_Temp_1 - Lower (LSB) Byte of 16-bit representation of Ambient Temperature Byte 18: HS2_Temp_2 - Upper (MSB) Byte of 16-bit representation of heatsink 2 Temperature Byte 19: HS2_Temp_1 - Lower (LSB) Byte of 16-bit representation of heatsink 2 Temperature Byte 20; AC_RmsV2 - Upper (MSB) Byte of 16-bit representation of AC RMS voltage Byte 21: AC_RmsV1 - Lower (LSB) Byte of 16-bit representation of AC RMS voltage Byte 22: AC_RmsI2 - Upper (MSB) Byte of 16-bit representation of AC RMS current Byte 23: AC_RmsI1 - Lower (LSB) Byte of 16-bit representation of AC RMS current Byte 24: HS1_Temp_2 - Upper (MSB) Byte of 16-bit representation of heatsink1 temperature Byte 25: HS1_Temp_1 - Lower (LSB) Byte of 16-bit representation of heatsink1 temperature Byte 26: Confirmation_Byte - Trimming and Calibration Confirmation Byte Status/Fault Bits Definition Byte 0 - The D1U4CS-W Status 0 register function and definitions are as follows: 7 PS_ON MSB 6 PWOK BYTE 0 – Status0 Register 4 3 Fail Fan Failure 2 OT Warning 1 OT Critical 0 AC HI Range LSB Bit Status Description Bit # 7 6 5 4 3 2 1 0 5 ACOK Set Main Output is Enabled PWOK is OK AC is Ok PS is Failed Fan2 or Fan1 is Failed PS Temperature Warning PS Shutdown due to OT AC Hi is Detected Clear Main Output is Disabled PWOK is not OK AC is Faulted PS is not Failed No Fan Fail No PS Temperature Warning No Over Temperature Shutdown No AC Hi is Detected www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 2 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Byte 1 - The D1U4CS-W Status1 register function and definitions are as follows: 7 Flash Constants MSB Bit # 7 6 5 4 3 2 1 0 6 - BYTE 1 – Status1 Register 4 3 Heatsink2 Sensor Heatsink1 Sensor 5 - Bit Status Description Set Flash Constants Corrupted Heatsink2 Sensor Failed Heatsink1 Sensor Failed AC I Sensor Failed AC V Sensor Failed Primary-Secondary Communication Failed 2 AC I Sensor 1 AC V Sensor 0 Pri-Sec Comm. LSB 1 AC Low 0 24V Fault LSB Clear Flash Constants OK Heatsink2 Sensor OK Heatsink1 Sensor OK AC I Sensor OK AC V Sensor OK Primary-Secondary Communication OK Byte 2 - The D1U4CS-W Fault 0 register function and definitions are as follows: 7 Main OV MSB Bit # 7 6 5 4 3 2 1 0 6 Main UV BYTE 2 – Fault0 Register 4 3 Standby Fault Fan1 Warning 5 Main OC 2 Fan2 Warning Bit Status Description Set Main Output Over-voltage Fault Main Output Under-voltage Fault Main Output Over-current Fault Standby Fault Fan1 Warning Fan2 Warning AC Low is Detected 24V is below 18V Clear No OV Fault No UV Fault No OC Fault No Standby Fault No fan1 Warning No fan2 Warning No AC Low is Detected 24V is above 19V Byte 3 - The D1U4CS-W Fault1 register is reserved for future use. Byte 26 - The D1U4CS-W confirmation register function and definitions are as follows: 7 Trimming MSB Bit # 7 6 5 4 3 2 1 0 6 AC I lo line cal. 5 AC I hi line cal. BYTE 26 – Confirmation Register 4 3 AC V lo line cal. AC V hi line cal. Bit Status Description Set Main V, I, and Standby V Trimming Done AC I Lo Line Calibration Done AC I Hi Line Calibration Done AC V Lo Line Calibration Done AC V Hi Line Calibration Done Standby Voltage Calibration Done Main Voltage Calibration Done Main Current Calibration Done 2 Stby V cal. 1 Main V cal. 0 Main I cal. LSB Clear Trimming Not Done AC I Lo Line Calibration Not Done AC I Hi Line Calibration Not Done AC V Lo Line Calibration Not Done AC V Hi Line Calibration Not Done Standby Voltage Calibration Not Done Main Voltage Calibration Not Done Main Current Calibration Not Done www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 3 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Sensor Data Interpretation Byte 4 (MSB) and Byte 5 (LSB) - 16-bit 2’s complement representation of the Main Output Voltage Model D1U4CS-W Data Range -128 to +127.996 V (DC) Transfer Equation (1/256 V)/LSB Accuracy +/- 2% of rated output voltage (00-500C) Byte 6 (MSB) and Byte 7 (LSB) - 16-bit unsigned integer representation of the Main Output Current Model D1U4CS-W Data Range 0-1023.984375 A (DC) Transfer Equation (1/64 A)/LSB Accuracy +/- 5% of rated output current (00-500C) Byte 8 (MSB) and Byte 9 (LSB) - 16-bit 2’s complement representation of the Standby Output Voltage Model D1U4CS-W Data Range -128 to +127.996 V (DC) Transfer Equation (1/256 V)/LSB Accuracy +/- 2% of rated output voltage (00-500C) Byte 10 (MSB) and Byte 11 (LSB) - 16-bit unsigned integer representation of the Standby Output Current Model D1U4CS-W Data Range 0-1023.984375 A (DC) Transfer Equation (1/64 A)/LSB Accuracy +/- 5% of rated output current (00-500C) Byte 12 (MSB) and Byte 13 (LSB) - 16-bit unsigned integer representation of the Fan1 Speed in RPM Model D1U4CS-W Data Range 0-65,535 RPM Transfer Equation 1 RPM/LSB Accuracy +/- 200 RPM within limits (00-500C) Byte 14 (MSB) and Byte 15 (LSB) - 16-bit unsigned integer representation of the Fan2 Speed in RPM Model D1U4CS-W Data Range 0-65,535 RPM Transfer Equation 1 RPM/LSB Accuracy +/- 200 RPM within limits (00-500C) Byte 16 (MSB) and Byte 17 (LSB) - 16-bit 2’s complement representation of the Ambient Temperature in deg C Model D1U4CS-W Data Range -5120C to +511.9843750C Transfer Equation (1/64 0C)/LSB Accuracy +/- 30C within limits (00 to +500C) Byte 18 (MSB) and Byte 19 (LSB) - 16-bit 2’s complement representation of the Heatsink 2 Temperature in deg C Model D1U4CS-W Data Range -5120C to +511.9843750C Transfer Equation (1/64 0C)/LSB Accuracy +/- 30C within limits (00 to +500C) Byte 20 (MSB) and Byte 21 (LSB) - 16-bit 2’s complement representation of the Input RMS Voltage Model D1U4CS-W Data Range -1024 to +1023.98675 V (RMS) Transfer Equation (1/32 V)/LSB Accuracy +/- 5% of rated input voltage (00-500C) Byte 22 (MSB) and Byte 23 (LSB) - 16-bit unsigned integer representation of the Input RMS Current Model D1U4CS-W Data Range 0-1023.984375 A (RMS) Transfer Equation (1/64 A)/LSB Accuracy +/- 5% of rated input current (00-500C) Byte 24 (MSB) and Byte 25 (LSB) - 16-bit 2’s complement representation of the Heatsink 1 Temperature in deg C Model D1U4CS-W Data Range -5120C to +511.9843750C Transfer Equation (1/64 0C)/LSB Accuracy +/- 30C within limits (00 to +500C) Power Supply Enable/Disable Control Enable Action: 1. If I2C commands to enable the PS (single byte command 0xD4), the PS will be enabled; 2. If PS_ON_L switch is ON (PSON_L=LOW), the PS will be enabled; Disable Action: 1. If I2C commands to disable the PS (single byte command 0xD3), the PS will be disabled; 2. If PS_ON_L switch is OFF (PSON_L=High), the PS will be disabled; This means the latest command overrides the previous command. At any moment, PSON_L switch can enable and disable the ps. Similarly, at any moment, I2C can enable and disable the ps. The latest control signal dominates. www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 4 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Fan Speed Control The D1U4CS-W power supply autonomously adjusts the fan pwm using the efficiency-improving cooling algorithm. The firmware calculates the fan pwm based on the following input data: load current, temperature, output voltages, and ps operating state. For safety reason, if micro-controller enters reset state, fan goes full speed. I2C Read/Write Method for Microcontroller PSMI Port Using the slot specific I2C address 0xB?, the D1U4CS-W family supports the standard access method of PSMI (Power Supply Management Interface). The PSMI Read method is as follows: The host transmits the register number to the slave; After receiving ACK from slave, the host could start a read request; After receiving ACK from slave, the host could receive the low byte from the slave; After ACK from host, the host could receive the high byte from the slave; After completion of transmitting high byte, the slave will transition to idle state; The data transmission sequence should be as follows: PSMI Read Method START Slave Address W ACK START Slave Address R Note: Shaded data is from slave to master Register Number ACK Low Byte ACK ACK High Byte ACK STOP The PSMI Write method is as follows: The host transmits the register number to the slave; After receiving ACK from slave, the host transmits the low byte to the slave; After receiving ACK from slave, the host transmits the high byte to the slave; After receiving ACK from slave, the host transmits STOP to the slave; After receiving STOP from host, the slave start internal writing operation; During internal writing operation, further read/write is prohibited; The data transmission sequence should be as follows: PSMI Write Method START Slave Address W Note: Shaded data is from slave to master ACK Register Number ACK Low Byte ACK High Byte ACK STOP Mapping of the Microcontroller RAM Bytes to PSMI Registers The implemented PSMI registers are detailed in the Table A3. Here is a mapping of the microcontroller RAM bytes to the PSMI registers. Table A2 - Mapping of Micontroller RAM Bytes to PSMI Registers Data Name Byte Number PSMI Register Status1 Status0 Byte1 Byte0 0xD0 Fault1 Fault0 Byte3 Byte2 0xD1 Vout1 Vout2 Byte5 Byte4 0x28 Iout1 Iout2 Byte7 Byte6 0x33 Standby_Vout1 Standby_Vout2 Byte9 Byte8 0x29 Standby_Iout1 Standby_Iout2 Byte11 Byte10 0x34 Fan1_Speed1 Fan1_Speed2 Byte13 Byte12 0x20 Fan2_Speed1 Fan2_Speed2 Byte15 Byte14 0x21 Amb_Temp1 Amb_Temp2 Byte17 Byte16 0x02 HS2_Temp1 HS2_Temp2 Byte19 Byte18 0x01 AC_RmsV1 AC_RmsV2 Byte21 Byte20 0x32 AC_RmsI1 AC_RmsI2 Byte23 Byte22 0x3D HS1_Temp1 HS1_Temp2 Byte25 Byte24 0x00 Note: This table shows the data transmission sequence of PSMI: low byte first. For example, to transmit PSMI register 0xD0, the Byte1 is transmitted first, Byte0 is trasmitted later www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 5 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Summary of the Implemented PSMI Registers Table A3 - The PSMI Registers Implemented for D1U4CS-W Family Power Supply Register dec hex 0 00 1 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0A 11 0B 12 0C 13 0D 14 0E 15 0F 16 10 17 11 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 19 26 1A 27 1B 28 1C 29 1D 30 1E 31 1F 32 20 33 21 34 22 35 23 36 24 37 25 38 26 39 27 40 28 41 29 42 2A 43 2B 44 2C 45 2D 46 2E 47 2F 48 30 49 31 50 32 PSMI Description Register Access Contents T1 temperature sensor data T2 temperature sensor data T3 temperature sensor data T4 temperature sensor data Reserved Reserved Thermal sensor configuration Temperature sensor types T1 temperature sensor offset T2 temperature sensor offset T3 temperature sensor offset T4 temperature sensor offset Fan speed resolutions (F1, F2) Fan speed resolutions (F3, F4) F1 fan speed control configuration F2 fan speed control configuration F3 fan speed control configuration F4 fan speed control configuration Voltage/current sensor configuration Fan control associations F1/F2 fan temperature associations F3/F4 fan temperature associations Shutdown events supported Status events supported Control functions supported Warning events supported Reserved configuration registers Reserved configuration registers Reserved configuration registers Reserved configuration registers Reserved configuration registers Reserved configuration registers F1 fan speed sensor F2 fan speed sensor F3 fan speed sensor F4 fan speed sensor F1 fan speed control F2 fan speed control F3 fan speed control F4 fan speed control Vout1 voltage sensor Vout2 voltage sensor Vout3 voltage sensor Vout4 voltage sensor Vout5 voltage sensor Vout6 voltage sensor Vout7 voltage sensor Vout8 voltage sensor Vout9 voltage sensor Vout10 voltage sensor Vin voltage sensor Read Only Read Only Read Only No Access No Access No Access Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only No Access No Access No Access No Access No Access No Access Read Only Read Only Read Only Read Only Read / Write Read / Write Read / Write Read / Write Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only see A8 see A8 see A8 0000 0000 0000 1300 0000 0000 0000 0000 0000 0000 0000 983A 983A 0000 0000 520A 0000 0000 0000 3F00 3000 0005 2100 0000 0000 0000 0000 0000 0000 see A8 see A8 0000 0000 see PSMI 2.12 0000 0000 0000 see A8 see A8 0000 0000 0000 0000 0000 0000 0000 0000 see A8 www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 6 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Register dec hex 51 33 52 34 53 35 54 36 55 37 56 38 57 39 58 3A 59 3B 60 3C 61 3D 62 3E 63 3F 64 40 65 41 66 42 67 43 68 44 69 45 70 46 71 47 72 48 73 49 74 4A 75 4B 76 4C 77 4D 78 4E 79 4F 80 50 81 51 82 52 83 53 84 54 85 55 86 56 87 57 88 58 89 59 90 5A 91 5B 92 5C 93 5D 94 5E 95 5F 96 60 97 61 98 62 99 63 100 64 101 65 102 66 103 67 104 68 PSMI Description Register Access Contents Vout1 current sensor Vout2 current sensor Vout3 current sensor Vout4 current sensor Vout5 current sensor Vout6 current sensor Vout7 current sensor Vout8 current sensor Vout9 current sensor Vout10 current sensor Vin current sensor Discovery Key 1 / Discovery Key 2 Discovery Key 3 / Discovery Key 4 PSMI Major / Minor Version Power supply code major / minor version Supplier ID1 Supplier ID2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Vout1 peak current sensor Vout2 peak current sensor Vout3 peak current sensor Vout4 peak current sensor Vout5 peak current sensor Vout6 peak current sensor Vout7 peak current sensor Vout8 peak current sensor Vout9 peak current sensor Vout10 peak current sensor Vin peak current sensor Shutdown events register Thermal warning events register Output current warning event register Input warning events Status Register Reset Control Register T1 maximum temperature T2 maximum temperature T3 maximum temperature T4 maximum temperature F1 operating minimum Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read / Write Reset Read / Write Reset Read / Write Reset Read / Write Reset Read / Write Reset Read / Write Reset Read Only Read Only Read Only Read Only Read Only see A8 see A8 0000 0000 0000 0000 0000 0000 0000 0000 see A8 5053 4D49 020C 0101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 see PSMI 2.12 see PSMI 2.12 see PSMI 2.12 see PSMI 2.12 see PSMI 2.12 see PSMI 2.12 4010 4010 4010 0000 8813 www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 7 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Register dec hex 105 69 106 6A 107 6B 108 6C 109 6D 110 6E 111 6F 112 70 113 71 114 72 115 73 116 74 117 75 118 76 119 77 120 78 121 79 122 7A 123 7B 124 7C 125 7D 126 7E 127 7F 128 80 129 81 130 82 131 83 132 84 133 85 134 86 135 87 136 88 137 89 138 8A 139 8B 140 8C 141 8D 142 8E 143 8F 144 90 145 91 146 92 147 93 148 94 149 95 150 96 151 97 152 98 153 99 154 9A 155 9B 156 9C 157 9D 158 9E PSMI Description Register Access Contents F2 operating minimum F3 operating minimum F4 operating minimum Maximum fan speed sound power Vout1 maximum voltage Vout1 minimum voltage Vout2 maximum voltage Vout2 minimum voltage Vout3 maximum voltage Vout3 minimum voltage Vout4 maximum voltage Vout4 minimum voltage Vout5 maximum voltage Vout5 minimum voltage Vout6 maximum voltage Vout6 minimum voltage Vout7 maximum voltage Vout7 minimum voltage Vout8 maximum voltage Vout8 minimum voltage Vout9 maximum voltage Vout9 minimum voltage Vout10 maximum voltage Vout10 minimum voltage Vout1 current spec1 Vout1 current spec2 Vout1 current spec3 Vout1 current spec4 Vout1 current spec5 Vout1 current spec6 Vout1 current spec7 Vout1 current spec8 Vout1 current spec9 Vout1 current spec10 Vout2 current spec1 Vout2 current spec2 Vout2 current spec3 Vout2 current spec4 Vout2 current spec5 Vout2 current spec6 Vout2 current spec7 Vout2 current spec8 Vout2 current spec9 Vout2 current spec10 Vout3 current spec1 Vout3 current spec2 Vout3 current spec3 Vout3 current spec4 Vout3 current spec5 Vout3 current spec6 Vout3 current spec7 Vout3 current spec8 Vout3 current spec9 Vout3 current spec10 Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only 8813 0000 0000 0000 330C CD0B DA05 DA04 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4009 A40A 070C 0000 0000 0000 0000 0000 0000 0700 C000 DD00 FA00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 8 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Register dec hex 159 9F 160 A0 161 A1 162 A2 163 A3 164 A4 165 A5 166 A6 167 A7 168 A8 169 A9 170 AA 171 AB 172 AC 173 AD 174 AE 175 AF 176 B0 PSMI Description Register Access Contents Input current limit spec1 Input current limit spec2 Input current limit spec3 Input voltage limit spec1 Input voltage limit spec2 Input voltage limit spec3 Vout1 output power limit Vout2 output power limit Vout3 output power limit Combined output select1 (power limit) Combined output power limit1 Combined output select2 (power limit) Combined output power limit2 Output current sensor bandwidth Input current sensor bandwidth High line / light load output power High line / medium load output power High line / high load output power Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only 6301 B200 0000 A00A 4015 0000 9001 0F00 0000 9F01 1200 9F01 1200 8813 6400 8C00 C800 9001 177 B1 High line / light load & High line / medium load efficiency limit Read Only 5055 178 179 180 181 B2 B3 B4 B5 High line / high load efficiency limit Low line / light load output power Low line / medium load output power Low line / high load output power Read Only Read Only Read Only Read Only 5500 8C00 C800 9001 182 B6 Low line / light load & Low line / medium load efficiency limit Read Only 5055 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF Read Only Read Only Read Only Read Only Read Only Read Only No Access No Access No Access TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 5500 4300 0000 0000 0000 0201 0000 0000 0000 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 208 D0 Read Only see A8 Low line / high load efficiency limit Vout1 load share error limit Vout2 load share error limit Vout3 load share error limit Vout4 load share error limit Redundancy configuration Reserved Reserved Reserved Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Vendor specific registers Custom feature area Lo Byte: vPS_Status1 Hi Byte: vPS_Status0 www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 9 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Register dec hex 209 D1 210 D2 211 D3 212 D4 213 D5 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF PSMI Description Custom feature area Lo Byte: vPS_Fault1 Hi Byte: vPS-Fault0 Custom feature area Lo Byte: Confirmation Byte Hi Byte: 0x00 Custom feature area One Byte Command to Disable ps Custom feature area One Byte Command to Enable ps Custom feature area One Byte Command to De-assert SMBALERT/L Custom feature area Custom feature area Custom feature area Custom feature area Custom feature area Custom feature area Custom feature area Custom feature area Custom feature area Custom feature area Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Access Contents Read Only see A8 Read Only see A3 Write Only see A5 Write Only see A5 Write Only see A12 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access No Access TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 10 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Flash-Emulated EEPROM Read/Write Method The D1U4CS-W family supports a 2 Kbit flash-emulated EEPROM. This enables the host to read and write the microcontroller’s internal flash memory that was reserved as the emulated EEPROM. The read protocol includes Current Address Read, Sequential Read, and Random Read. The write protocol includes Byte Write and Multi-Byte Write. The Current Address Read method is as follows: The internal read address pointer is initialized to point to the address 0; The address pointer is incremented by one after each byte read operation; After the last address (255) has been read, the pointer wraps to the address 0; The data transmission sequence should be as follows: Emulated EEPROM Current Address Read START Slave Address Note: Shaded data is from slave to master R ACK Data NACK STOP The Sequential Read method is as follows: The internal read address pointer is pointing to the address 0; The address pointer is incremented by one after each byte read operation; After the last address (255) has been read, the pointer wraps to the address 0; The data transmission sequence should be as follows: Emulated EEPROM Sequential Read START Slave Address R Note: Shaded data is from slave to master ACK Data(0) ACK … Data(i) NACK STOP The Random Read method is as follows: The internal read address pointer is set at any time by a write command: Write Command to Set Read Address Pointer START Slave Address W Note: Shaded data is from slave to master ACK Read Address ACK Subsequent data transmission sequence should be as follows: Emulated EEPROM Random Read START Slave Address R Note: Shaded data is from slave to master ACK Data NACK STOP The address pointer is incremented by one after each byte read operation; After the last address (255) has been read, the pointer wraps to the address 0; The Byte Write method is as follows: The host transmits the write address to the slave; After receiving ACK from slave, the host transmits the data to the slave; After receiving ACK from slave, the host transmits STOP to the slave; After receiving STOP from host, the slave start internal writing operation; During internal writing operation, further read/write is prohibited; The data transmission sequence should be as follows: Emulated EEPROM Byte Write START Slave Address W Note: Shaded data is from slave to master ACK Write Address ACK Data ACK STOP The Multi-Byte Write method is as follows: The host transmits the write address to the slave; After receiving ACK from slave, the host transmits the data 0 to the slave; After receiving ACK from slave, the host transmits data 1 to the slave; After transmitting data n and receiving ACK from slave, the host transmits STOP to the slave; After receiving STOP from host, the slave start internal writing operation; During internal writing operation, further read/write is prohibited; The data transmission sequence should be as follows: www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 11 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Emulated EEPROM Page Write START Slave Address W Note: Shaded data is from slave to master ACK Write Address ACK Data(0) ACK …… Data(n) ACK STOP Diagnostic Data structure in the Emulated EEPROM Total size of the emulated EEPROM is 256 Bytes. The first 64 bytes are used to store product information. The remaining space is used to store firmware diagnostic data. The product information is as follows: 1. Manufacturer: 2. Manufacturer’s Part Number: 3. Product serial Number: 4. Customer Specification Number: 5. Customer Revision Number: 6. Firmware Revision Number: “MURATA-PS,” addresses 0-8 “D1U4CS-W-2200-12-HxxC,” addresses 9-14 “123456789,” addresses 15-23 “804-120109-001-A,” addresses 24-39 “A1,” addresses 40-41 “V01R01A1,” addresses 42-49 When the main output voltage is shutdown due to OT, OC, or OV faults, the firmware captures a snapshot of the internal data (RAM Byte0 to Byte26), and put the snapshot in the EEPROM. Only one snapshot is available for retrieval. The latest snapshot overrides the previous snapshot. The data is structured like this: Byte0: Byte1: Byte2: Byte3: Byte4: Byte5: Byte6: Byte7: Byte8: Byte9: Byte10: Byte11: Byte12: Byte13: Byte14: Byte15: Byte16: Byte17: Byte18: Byte19: Byte20: Byte21: Byte22: Byte23: Byte24: Byte25: Byte26: address 64 address 65 address 66 address 67 address 68 address 69 address 70 address 71 address 72 address 73 address 74 address 75 address 76 address 77 address 78 address 79 address 80 address 81 address 82 address 83 address 84 address 85 address 86 address 87 address 88 address 89 address 90 The latest snapshot is retained until a host erases it or a new snapshot overrides it. SMBAlert/L Signal If any of the OV, OC, or OT faults is detected, the SMBALERT/L signal is asserted. When SMBALERT/L is detected or periodically, a host can use the SMBUS Alert Response Address (ARA: 0x0C) to talk to the unit. Here is the method a host de-asserts the SMBALET/L signal: The host broadcasts to all the slaves on the network using ARA address 0x0C; Only the slave that asserted the SMBALERT/L acknowledges and transmits its I2C Device Address to the broadcasting I2C host; SMBUS Alert Method START Slave Address R Note: Shaded data is from slave to master ACK Device Address ACK P The host then talks to the received I2C Device Address using the PSMI register 0xD5; The PSMI register 0xD5 is a one byte command for the host to command the slave to de-assert SMBALERT/L signal; The host could repeat the above steps until the SMBALERT/L is de-asserted; however, a slave may have repeated OT fault since OT is an auto-recoverable fault, in this case, it is the host’s decision to repeat the above de-asserting steps or just let the slave take care of the SMBALERT/L signal. www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 12 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note Here are the timing diagrams for SMBALERT/L Assertion and De-assertion. Main OV to SMBALERT/L Assertion Delay OV Pulse Width 12V_OV SMBALERT/L Assertion Delay SMBALERT/L Main OC to SMBALERT/L Assertion Delay OC Pulse Width 12V_OC SMBALERT/L Assertion Delay SMBALERT/L Main OT to SMBALERT/L Assertion Delay OT Pulse Width 12V_OT SMBALERT/L Assertion Delay SMBALERT/L I2C Command to SMBALERT/L De-assertion Delay www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 13 of 14 D1U4CS-W Communications D1U4CS-W Communications Protocol Application Note I2C Command Received S P I2C Clock and Data Lines SMBALERT/L De-assertion Delay SMBALERT/L Table A4. Summary of SMBALERT/L Timing Parameters SMBALERT Timing Main OV Pulse Width Main OC Pulse Width Main OT Pulse Width SMBALERT/L Assertion Delay SMBALERT/L De-assertion delay Min 200 us 200 us 200 us 0 0 Max 10 ms 10 ms Note Rise and fall times must be within spec Rise and fall times must be within spec Rise and fall times must be within spec SMBALERT/L Signal during Power Up/Down and Turn On/Off ACOK PSON/L +12V SMBALERT/L initially follows VDD. It only alerts Main OV, OC, and OT faults. SMBALERT/L Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. ISO 9001 and 14001 REGISTERED This product is subject to the following operating requirements and the Life and Safety Critical Application Sales Policy: Refer to: http://www.murata-ps.com/requirements/ Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. © 2013 Murata Power Solutions, Inc. www.murata-ps.com/support 15 Feb 2013 ACAN33.A05 Page 14 of 14