OPA121 44 QQ ： 71 Low Cost Precision Difet ® OPERATIONAL AMPLIFIER 51 81 9 ® APPLICATIONS ● LOW NOISE: 6nV/√Hz typ at 10kHz ● LOW BIAS CURRENT: 5pA max ● LOW OFFSET: 2mV max ● OPTOELECTRONICS ● DATA ACQUISITION ● TEST EQUIPMENT ● MEDICAL EQUIPMENT 43 41 5 ， DESCRIPTION ● RADIATION HARD EQUIPMENT 18 66 ● LOW DRIFT: 3µV/°C typ ● HIGH OPEN-LOOP GAIN: 110dB min ● HIGH COMMON-MODE REJECTION: 86dB min 85 ， FEATURES Case (TO-99) and Substrate 8 7 +VCC 限 公 司 The OPA121 is a precision monolithic dielectricallyisolated FET (Difet ®) operational amplifier. Outstanding performance characteristics are now available for low-cost applications. 讯 科 技 有 Noise, bias current, voltage offset, drift, open-loop gain, common-mode rejection, and power supply rejection are superior to BIFET® amplifiers. Very low bias current is obtained by dielectric isolation with on-chip guarding. 深 圳 市 金 合 Laser-trimming of thin-film resistors gives very low offset and drift. Extremely low noise is achieved with new circuit design techniques (patented). A new cascode design allows high precision input specifications and reduced susceptibility to flicker noise. Standard 741 pin configuration allows upgrading of existing designs to higher performance levels. –In 2 3 +In Noise-Free Cascode* 6 Output Trim 10kΩ 1 5 Trim 10kΩ 2kΩ 2kΩ 2kΩ 2kΩ 4 –VCC *Patented OPA121 Simplified Circuit Difet ®, Burr-Brown Corp. BIFET®, National Semiconductor Corp. International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1984 Burr-Brown Corporation PDS-539F Printed in U.S.A. September, 1993 SPECIFICATIONS ELECTRICAL At VCC = ±15VDC and TA = +25°C unless otherwise noted. Pin 8 connected to ground. OPA121KM TYP (1) MAX MIN TYP 40 15 8 6 0.7 1.6 15 0.8 (1) (1) (1) (1) (1) (1) (1) MAX 50 18 10 7 0.8 2 21 1.1 nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fA, p-p fA/√Hz ±0.5 ±3 104 ±6 ±50 ±0.5 ±3 104 ±6 VCM = 0VDC Device Operating ±1 ±5 VCM = 0VDC Device Operating ±0.7 ±4 OFFSET CURRENT(2) Input Offset Current RL ≥ 2kΩ 110 120 106 114 dB 2 32 2 6 10 2 32 2 6 10 MHz kHz V/µs µs µs 5 5 µs ±12 ±10 100 1000 40 V mA Ω pF mA ±15 VDC 18 66 ， 司 限 讯 科 技 有 Gain = –1 合 市 金 71 V dB RL = 2kΩ VO = ±10VDC DC, Open Loop Gain = +1 圳 pA ±11 100 RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current ±11 ±5.5 10 ±12 ±10 100 1000 40 ±11 ±5.5 10 ±15 ±5 IO = 0mADC Ambient Temperature Ambient Temperature Ambient Temperature 深 ±8 ±10 82 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ Gain = –1, RL = 2kΩ 10V Step TEMPERATURE RANGE Specification Operating Storage θ Junction-Ambient ±0.7 ±11 104 FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate Settling Time, 0.1% 0.01% Overload Recovery, 50% Overdrive(3) POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent pA ±10 86 公 OPEN-LOOP GAIN, DC Open-Loop Voltage Gain ±10 VIN = ±10VDC 1013 || 1 1014 || 3 VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection ±1 43 41 5 IMPEDANCE Differential Common-Mode ±50 ： BIAS CURRENT(2) Input Bias Current 86 ±3 ±10 mV µV/°C dB µV/V QQ 86 ±2 ±10 85 ， VCM = 0VDC TA = TMIN to TMAX 44 VOLTAGE(2) OFFSET Input Offset Voltage Average Drift Supply Rejection UNITS 9 MIN 81 CONDITIONS INPUT NOISE Voltage, fO = 10Hz fO = 100Hz fO = 1kHz fO = 10kHz fB = 10Hz to 10kHz fB = 0.1Hz to 10 Hz Current, fB = 0.1Hz to 10Hz fO = 0.1Hz thru 20kHz 51 PARAMETER OPA121KP, KU 2.5 0 –40 –65 200 ±18 4 ±5 +70 +85 +150 0 –25 –55 1013 || 1 1014 || 3 Ω || pF Ω || pF 2.5 150(4) ±18 4.5 VDC mA +70 +85 +125 °C °C °C °C/W NOTES: (1) Sample tested. (2) Offset voltage, offset current, and bias current are specified with the units fully warmed up. (3) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (4) 100°C/W for KU grade. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA121 2 ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted. Ambient Temperature 0 INPUT OFFSET VOLTAGE(1) Input Offset Voltage Average Drift Supply Rejection TYP +70 0 TYP ±80 ±1 ±3 94 ±20 VCM = 0VDC Device Operating ±23 ±115 ±23 VCM = 0VDC Device Operating ±16 ±100 ±16 RATED OUTPUT Voltage Output Current Output Short Circuit Current POWER SUPPLY Current, Quiescent UNITS +70 °C ±5 ±10 mV µV/°C dB µV/V ±80 ±250 RL ≥ 2kΩ 106 116 RL = 2kΩ VO = ±10VDC VO = 0VDC ±10.5 ±5.25 10 ±11 ±10 40 44 ±10 80 IO = 0mADC 100 pA pA ±11 96 V dB 110 dB ±11 ±10 40 V mA mA ±10.5 ±5.25 10 2.5 ±200 71 ±11 98 ： ±10 82 QQ VIN = ±10VDC OPEN-LOOP GAIN, DC Open-Loop Voltage Gain 82 43 41 5 VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection ±3 ±10 MAX 51 82 OFFSET CURRENT(1) Input Offset Current MIN ±1 ±3 94 ±20 VCM = 0VDC BIAS CURRENT(1) Input Bias Current OPA121KP, KU MAX 81 MIN 85 ， TEMPERATURE RANGE Specification Range CONDITIONS 9 OPA121KM PARAMETER 4.5 2.5 5 mA 18 66 NOTE: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up. ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS Top View M-Package TO-99 (Hermetic) Substrate and Case ， Supply ........................................................................................... ±18VDC Internal Power Dissipation(1) ......................................................... 500mW Differential Input Voltage ............................................................... ±36VDC Input Voltage Range ..................................................................... ±18VDC Storage Temperature Range M package .................................................................... –65°C to +150°C P, U packages ............................................................... –55°C to +125°C Operating Temperature Range M package ...................................................................... –40°C to +85°C P, U packages ................................................................. –25°C to +85°C Lead Temperature M, P packages (soldering, 10s) ................................................... +300°C U package (soldering, 3s) ........................................................... +260°C Output Short-Circuit Duration(2) ............................................... Continuous Junction Temperature .................................................................... +175°C 公 司 Offset Trim 1 有 限 –In 2 +In 技 讯 科 Top View PACKAGE TO-99 8-Pin Plastic DIP 8-Pin SOIC 001 006 182 3 6 5 Output Offset Trim P-Package Plastic Mini-DIP U-Package Plastic SOIC 合 市 金 圳 深 OPA121KM OPA121KP OPA121KU OPA121 –V CC PACKAGE INFORMATION MODEL 7 +VCC 4 NOTES: (1) Packages must be derated based on θJA = 150°C/W (P package); θJA = 200°C/W (M package); θJA = 100°C/W (U package). (2) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ. PACKAGE DRAWING NUMBER(1) 8 Offset Trim 1 8 Substrate –In 2 7 +VCC OPA121 +In 3 6 Output –V CC 4 5 Offset Trim NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL OPA121KM OPA121KP OPA121KU PACKAGE TEMPERATURE RANGE TO-99 8-Pin Plastic DIP 8-Pin SOIC 0°C to +70°C 0°C to +70°C 0°C to +70°C ® 3 OPA121 TYPICAL PERFORMANCE CURVES TA = +25°C, VCC = ±15VDC unless otherwise noted. BIAS AND OFFSET CURRENT vs TEMPERATURE INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k 1k 100 1 9 10 1 0.01 100 1k 10k Frequency (Hz) 100k 1M –50 –25 0 +25 +50 +75 0.01 +100 +125 1M 10M Ambient Temperature (°C) ： 10 0.1 85 ， QQ 1 71 1 44 0.1 Offset Current (pA) KM 10 10 81 100 100 KM 51 KP, KU Bias Current (pA) Voltage Noise (nV/√Hz) 1k POWER SUPPLY REJECTION vs FREQUENCY BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 140 KM 0.1 0.1 司 –10 –5 0 +5 100 80 +10 60 40 20 0 0.01 1 +15 10 100 1k 10k 100k Frequency (Hz) 技 有 限 Common-Mode Voltage (V) 公 0.01 –15 120 18 66 Offset Current 43 41 5 1 Power Supply Rejection (dB) Bias Current 1 Offset Current (pA) 10 ， Bias Current (pA) 10 讯 科 COMMON-MODE REJECTION vs FREQUENCY OPEN-LOOP FREQUENCY RESPONSE 140 KM Voltage Gain (dB) 合 市 金 100 80 圳 60 –45 120 40 深 Common-Mode Rejection (dB) KM 120 Gain 100 Ø 80 60 Phase Margin ∼ ≈ 65° 40 –90 –135 20 20 0 –180 0 1 10 100 1k 10k 100k 1M 1 10M 100 1k 10k Frequency (Hz) Frequency (Hz) ® OPA121 10 4 100k 1M 10M Phase Shift (Degrees) 140 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. SMALL SIGNAL TRANSIENT RESPONSE LARGE SIGNAL TRANSIENT RESPONSE +80 9 0 81 0 +40 51 Output Voltage (mV) Output Voltage (V) +15 +40 44 -15 25 0 50 71 +80 0 1 2 3 4 5 Time(µs) 85 ， QQ ： Time(µs) INPUT CURRENTS vs INPUT VOLTAGE WITH ±VCC PINS GROUNDED 43 41 5 Maximum Safe Current IIN +1 18 66 V 0 –1 ， Maximum Safe Current –2 –10 –5 0 +5 +10 +15 有 限 Input Voltage (V) 公 –15 司 Input Current (mA) +2 APPLICATIONS INFORMATION 技 +VCC 讯 科 OFFSET VOLTAGE ADJUSTMENT 7 2 The OPA121 offset voltage is laser-trimmed and will require no further trim for most applications. As with most amplifiers, externally trimming the remaining offset can change drift performance by about 0.3µV/°C for each 100µV of adjusted offset. Note that the trim (Figure 1) is similar to operational amplifiers such as 741 and AD547. The OPA121 can replace most BIFET amplifiers by leaving the external null circuit unconnected. 6 合 OPA121 1 3 市 金 5 ±10mV Typical Trim Range 4 圳 * 深 –VCC *10k Ω to 1M Ω Trim Potentiometer (100k Ω Recommended) INPUT PROTECTION FIGURE 1. Offset Voltage Trim. Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-to-substrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –VCC. than 6V more negative than –VCC. A 10kΩ series resistor will limit input current to a safe level with up to ±15V input levels even if both supply voltages are lost. Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), Unlike BIFET amplifiers, the Difet OPA121 requires input current limiting resistors only if its input voltage is greater ® 5 OPA121 this may cause a noticeable degradation of offset voltage and drift. Non-Inverting Static protection is recommended when handling any precision IC operational amplifier. 8 2 GUARDING AND SHIELDING In As in any situation where high impedances are involved, careful shielding is required to reduce “hum” pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. 3 OPA121 6 Out TO-99 Bottom View 9 81 4 5 6 In 6 Out OPA121 2 44 8 7 1 8 Mini-DIP Bottom View 8 5 85 ， BOARD LAYOUT FOR INPUT GUARDING Guard top and bottom of board. Alternate: use Teflon standoff for sensitive input pins. 43 41 5 QQ ： 71 3 51 3 2 If guarding is not required, pin 8 (case) should be connected to ground. 1 7 2 6 3 4 18 66 FIGURE 2. Connection of Input Guard. 80 司 公 限 有 Input Bias Current (pA) 70 ， The input bias currents of most popular BIFET operational amplifiers are affected by common-mode voltage (Figure 3). Higher input FET gate-to-drain voltage causes leakage and ionization (bias) currents to increase. Due to its cascode input stage, the extremely-low bias current of the OPA121 is not compromised by common-mode voltage. 技 LF156/157 TA = +25°C; curves taken from mfg. published typical data 60 50 AD547 40 30 LF155 LF156/157 20 10 0 –10 LF155 AD547 OPA121 OPA121 OP-15/16/17 "Perfect Bias Current Cancellation" 讯 科 –20 –10 –5 0 +5 +10 合 Common-Mode Voltage (VDC) 深 圳 市 金 FIGURE 3. Input Bias Current vs Common-Mode Voltage. ® OPA121 OPA121 Inverting The amplifier case should be connected to any input shield or guard via pin 8. This insures that the amplifier itself is fully surrounded by guard potential, minimizing both leakage and noise pickup (see Figure #2). Teflon™ E.I. du Pont de Nemours & Co. 8 2 6 Out In Leakage currents across printed circuit boards can easily exceed the bias current of the OPA121. To avoid leakage problems, it is recommended that the signal input lead of the OPA121 be wired to a Teflon™ standoff. If the OPA121 is to be soldered directly into a printed circuit board, utmost care must be used in planning the board layout. A “guard” pattern should completely surround the high-impedance input leads and should be connected to a low-impedance point which is at the signal input potential. BIAS CURRENT CHANGE VERSUS COMMON-MODE VOLTAGE 3 Buffer 6