APL5333

APL5333
3A Bus Termination Regulator
Features
General Description
•
Sourcing and Sinking Current up to 3A
The APL5333 linear regulator is designed to provide a
•
Wide Input Voltage Range: 1.2V to 3.6V
•
VTT and VTTREF Voltage Tracks at Half the
regulated voltage with bi-directional output current for
DDR-SDRAM termination. The APL5333 integrates two
power transistors to source or sink current up to 3A. It
also incorporate current-limit, thermal shutdown into a
VREF Voltage
•
VTT and VTTREF Voltage with ±20mV Accuracy
•
Excellent Load Transient Response
single chip.
The output voltage of APL5333 tracks the voltage at VREF
- Droop Compensation
pin. An internal resistor divider is used to provide a half
voltage of VREF for VTTREF and VTT Voltage. The VTT
- Fast Loop Response
•
Stable with 20µF Ceramic Output Capacitors
•
Current Limit Protection
•
Thermal Shutdown Protection
•
Power-On-Reset Function on VCNTL
•
S3, S5 Input Signals for ACPI States
•
Available in a Thermal Enhanced MSOP-10P
output voltage is only requiring 20µF of ceramic output
capacitance for stability and fast transient response. The
S3 and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF. The MSOP-10P package with a copper
pad is available which provides excellent thermal
impedance.
Package
•
Lead Free Available (RoHS Compliant)
Simplified Application Circuit
Applications
VIN
VCNTL
APL5333
•
DDR 1/2/3 Memory Termination
•
SSTL-2, STL-18 and HSTL Termination
VTT
1 VREF
2 VIN
3
4
VTT
PGND
VCNTL
S5
10
5V
9
GND 8
7
S3
5 VTTSNS VTTREF 6
Ordering and Marking Information
Package Code
XA : MSOP-10P
Temperature Range
I : - 40 to 85 oC
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device
APL5333
Lead Free Code
Handling Code
Temperature Range
Package Code
APL5333 XA :
L5333
XXX
XX
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte in plate termination finish; which are fully compliant
with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of
IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
1
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APL5333
Pin Configuration
APL5333
VREF 1
VIN 2
VTT 3
10 VCNTL
9 S5
8 GND
PGND 4
VTTSNS 5
7 S3
6 VTTREF
MSOP-10P
Absolute Maximum Ratings
Symbol
(Note 1)
Rating
Unit
VCNTL Supply Voltage (VCNTL to GND)
-0.3~6
V
VIN
VIN Supply Voltage (VIN to GND)
-0.3~6
V
VTT
VTT Output Voltage (VTT to GND)
-0.3~6
V
VTTREF Output Voltage (VTTREF to GND)
-0.3~6
V
VTTSNS, VREF, S3 and S5 Voltage
-0.3~6
V
-0.3~0.3
V
VCNTL
VTTREF
Parameter
PGND to GND Voltage
TJ
Maximum Junction Temperature
TSTG
Storage Temperature Range
TSDR
Maximum Lead Soldering Temperature
150
o
-65 to 150
o
260, 10 sec
o
C
C
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute mximum rating
conditions for extended periods may affect device reliability.
Thermal Characteristic
(Note 2)
Symbol
θJA
Parameter
Junction to Ambient Resistance in Free Air
Rating
Unit
60
°C/W
Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Symbol
VCNTL
Range
Unit
VCNTL to GND
Parameter
4.5~5.5
V
VIN
VIN to GND
1.2~3.6
V
VTT
VTT to GND
0.6~1.8
V
VREF
VREF to GND
1.2~3.6
V
IVTT
VTT Output Current (Note 4)
-3~+3
A
CIN
VIN Input Capacitor
4.7~100
µF
Capacitance of VTT Output Multi-layer Ceramic Capacitor
(MLCC)
4.7~47
µF
COUT
TA
Ambient Temperature
-40~+80
o
TJ
Junction Temperature
-40~+125
o
C
C
Note 3 : Refer to the typical application circuit
Note 4 : If the VTT output current is “+3A”, then VTT source would be 3A current, and vice versa.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
2
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APL5333
Electrical Characteristics
VCNTL=5V, VIN=VREF=1.8V, TA = -40 to 85°C, unless otherwise specified. Typical values refer to TA =25°C.
Symbol
Parameter
Test Conditions
APL5333
Min
Typ
Max
0.3
0.7
2
20
40
80
-
0.04
1.0
Unit
SUPPLY CURRENT
IVCNTL
VCNTL Supply Current
VCNTL Standby Current
o
VIN Supply Current
TA =25 C, VS3=0V, VS5=5V, no load
TA =25oC, VS3=VS5=0V, no load
VIN=VREF=0V
TA =25oC, VS3=VS5=5V, no load
0.7
2
4
VIN Standby Current
TA =25oC, VS3=0V, VS5=5V, no load
-
6
10
VIN Shutdown Current
TA =25oC, VS3=VS5=0V, no load
-
0.3
1.0
VCNTL Shutdown Current
IVIN
TA =25oC, VS3=VS5=5V, no load
mA
µA
mA
µA
INPUT CURRENT
IVREF
IVTTSNS
VREF Input Current
VS3=VS5=5V
1
3
5
VTTSNS Input Current
VS3=VS5=5V
-1.00
-
1.00
VCNTL Rising
3.6
3.8
4.0
V
0.1
0.2
0.3
V
VIN=VREF=2.5V
-
1.25
-
VIN=VREF=1.8V
-
0.9
-
VIN=VREF=1.5V
-
0.75
-
VIN=VREF=2.5V, IVTT=0A
-20
-
20
VIN=VREF=2.5V, IVTT=±1.5A
-30
-
30
VIN=VREF=2.5V, IVTT=±3A
-40
-
40
VIN=VREF=1.8V, IVTT=0A
-20
-
20
VIN=VREF=1.8V, IVTT=±1A
-30
-
30
VIN=VREF=1.8V, IVTT=±2A
-40
-
40
VIN=VREF=1.5V, IVTT=0A
-20
-
20
VIN=VREF=1.5V, IVTT=±1A
-30
-
30
VIN=VREF=1.5V, IVTT=±2A
-40
-
40
3.3
3.8
4.5
µA
POWER-ON-RESET
VCNTL POR Threshold
VCNTL POR Hysteresis
VTT OUTPUT
VTT
VTT Output Voltage
VTT Output Voltage Tolerance
VTT Current Limit
VTT < 0.5 X VREF X 1.05 and
VTT > 0.5 X VREF X 0.95
VTT Short Circuit Current Limit
RDS(ON)
Internal Power MOSFETs RDS(ON)
VTT Leakage Current
VTTSNS Leakage Current
VTT Discharge Current
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
VTT > 0.5 X VREF X 1.1 or
V
mV
A
1
1.7
2.3
Upper MOSFET
-
230
330
Lower MOSFET
-
230
330
-
2.5
4.0
µA
-1.00
-
1.00
µA
20
35
50
mA
VTT < 0.5 X VREF X 0.9
VTT=1.25V, VS3=0V, VS5=5V,
TA =25oC
VTT=1.25V, TA =25oC
VTT=0.5V, VS3=VS5=0V, TA =25oC
VREF=0V
3
mΩ
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APL5333
Electrical Characteristics (Cont.)
VCNTL=5V, VIN=VREF=1.8V, TA = -40 to 85°C, unless otherwise specified. Typical values refer to TA =25°C.
Symbol
Parameter
Test Conditions
APL5333
Min
Typ
Max
VIN=VREF =2.5V
-
1.25
-
VIN=VREF =1.8V
-
0.9
-
VIN=VREF =1.5V
-
0.75
-
Unit
VTTREF OUTPUT
VTTREF
VTTREF Output Voltage
V
VTTREF Output Voltage
Tolerance
VIN=VREF, IVTTREF<10mA
-20
-
+20
mV
IVTTREF
VTTREF Source Current Limit
VTTREF=0V
10
20
30
mA
IVREFDIS
VTTREF Discharge Current
1
2
3
mA
1.6
-
-
V
-
-
0.3
V
-1
-
1
µA
-
150
-
o
-
o
VTTREF=2.5V, VS3=VS5=0V,
TA =25oC
LOGIC THRESHOLD
VIH
High Threshold Voltage
VS3, VS5 Rising
VIL
Low Threshold Voltage
VS3, VS5 Falling
Leakage Current
o
S3, S5, TA =25 C
THERMAL SHUTDOWN
TSD
Thermal Shutdown Temperature
TJ Rising
Thermal Shutdown Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
-
4
30
C
C
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APL5333
Typical Operating Characteristics
(Refer to the section “Typical Application Circuits”, VCNTL=5V, VIN=VREF=1.8V, VTT=0.9V, TA=25oC)
Frequency Response
Frequency Response
200
20
150
Phase (degree)
40
Gain (dB)
0
VTT=1.25V, IVTT=+2.5A
-20
VTT=0.75V, IVTT=+2.5A
-40
100
50
VTT=1.25V, IVTT=+2.5A
0
VTT=0.75V, IVTT=+2.5A
-50
-60
-80
1000
10000
100000
-100
1000
1000000
10000
Frequency (Hz)
VCNTL Supply Current, IVCNTL (μA)
800
VTT=1.25V, IVTT=+1.5A
-10
VTT=0.75V, IVTT=+1.5A
PSRR (dB)
1000000
VCNTL Supply Current vs. VCNTL Voltage
VCNTL PSRR
0
-20
VTT=0.9V, IVTT=+1.5A
-30
-40
-50
-60
1000
10000
Frequency (Hz)
S3=S5=high
700
600
500
400
VVCNTL=5V
300
200
100
0
100000
0
Dropout Voltage vs. VTT Output Current
1
2
3
4
5
VCNTL Voltage, VCNTL (V)
6
Dropout Voltage vs. VTT Output Current
1000
1000
VTT=0.75V
900
800
Dropout Voltage, VDROP (mV)
Dropout Voltage, VDROP (mV)
100000
Frequency (Hz)
TJ=125oC
700
TJ=75oC
600
TJ=25oC
500
400
300
200
TJ=-50oC
TJ=-25oC
100
1
2
VTT Output Current, IVTT(A)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
800
TJ=125oC
700
TJ
600
500
400
300
200
0
3
5
=75oC
TJ=25oC
TJ=-50oC
TJ=-25oC
100
0
0
VTT=0.9V
900
0
1
2
VTT Output Current, IVTT(A)
3
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APL5333
Typical Operating Characteristics (Cont.)
(Refer to the section “Typical Application Circuits”, VCNTL=5V, VIN=VREF=1.8V, VTT=0.9V, TA=25oC)
VTTREF and VTT Offset Voltage vs.
Junction Temperature
Dropout Voltage vs. VTT Output Current
VTTREF and VTT Offset Voltage (mV)
1200
Dropout Voltage, VDROP (mV)
VTT=1.25V
1000
TJ=125oC
TJ=75oC
800
TJ=25oC
600
400
200
TJ=-50oC
TJ=-25oC
0
1
2
VTT Output Current, IVTT(A)
0
8
IVTT=-10mA
6
4
2
0
-2
IVTT=10mA
-4
-6
-8
-10
-50
3
-25
0
25
50
75 100
Junction Temperature (oC)
125
VTT Source Current Limit vs.
Junction Temperature
VTT Load Regulation vs.
Output Current
30
5
20
VTT Sourcing Current Limit (A)
VTT Load Regulation (mV)
10
VTT=0.9V
10
0
-10
-20
-30
-3
-2
-1
0
1
2
Output Current, IVTT (A)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
VIN=1.8V
4
3
2
1
0
3
-50 -25
6
0
25 50 75 100 125 150
Junction Temperature (oC)
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APL5333
Operating Waveforms
(Refer to the section “Typical Application Circuits”, VCNTL=5V, VIN=VREF=1.8V, VTT=0.9V, TA=25oC)
Power off
Power on
RLOAD=1Ω
RLOAD=1Ω
VCNTL
VCNTL
1
1
2
3
4
VIN
3
VTT
VTT
IVTT
IVTT
4
CH1 : VCNTL , 5V/div
CH2 : VIN , 1V/div
CH3 : VTT , 500mV/div
CH4 : IVTT , 1A/div
Time : 2ms/div
CH1 : VCNTL , 5V/div
CH2 : VIN , 1V/div
CH3 : VTT , 500mV/div
CH4 : IVTT , 1A/div
Time : 5ms/div
S5 Low to High
1
VIN
2
S5 High to Low
VS5
VS5
1
VS3
2
VS3
2
VTTREF
VTTREF
3
3
VTT
VTT
4
4
CH1 : VS5 , 5V/div
CH2 : VS3 , 5V/div
CH3 :VTTREF , 1V/div
CH4 : VTT , 1V/div
Time : 10µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
CH1 : VS5 , 5V/div
CH2 : VS3 , 5V/div
CH3 :VTTREF , 1V/div
CH4 : VTT , 1V/div
Time : 20µs/div
7
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APL5333
Operating Waveforms (Cont.)
(Refer to the section “Typical Application Circuits”, VCNTL=5V, VIN=VREF=1.8V, VTT=0.9V, TA=25oC)
S3 Low to High
S3 and S5 High to Low
VS5
VS5
1
1
VS3
VS3
2
2
VTTREF
VTTREF
3
3
4
VTT
VTT
4
CH1 : VS5 , 5V/div
CH2 : VS3 , 5V/div
CH3 :VTTREF , 1V/div
CH4 : VTT , 1V/div
Time : 20µs/div
CH1 : VS5 , 5V/div
CH2 : VS3 , 5V/div
CH3 :VTTREF , 1V/div
CH4 : VTT , 1V/div
Time : 5ms/div
Current Limit and Short
Circuit Current Limit
VIN
1
VTTREF
2
VTT
3
IVTT
4
CH1 : VIN , 2V/div
CH2 : VTTREF , 1V/div
CH3 : VTT , 500mV/div
CH4 : IVTT , 2A/div
Time : 500µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
8
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APL5333
Pin Description
PIN NO.
1
PIN NAME
VREF
2
VIN
3
VTT
4
5
6
7
8
9
PGND
VTTSNS
VTTREF
S3
GND
S5
10
VCNTL
DESCRIPTION
Reference Voltage Input for VTT and VTTREF Regulator.
Power Input for VTT and VTTREF Pin. An input capacitor should be connected from VIN to
PGND.
VTT Output Voltage Pin. Source and sink current up to 3A. To insure the stability issue, the
output capacitor typical 20µF(10µF*2) should be connected from VTT to PGND.
Power Ground for VIN and VTT.
Voltage Sense for VTT. Connect to the positive node of VTT output capacitors.
VTT Reference Output Pin. A small capacitor 0.1µF should be connected from VTTREF to GND.
S3 Signal Input.
Signal Ground.
S5 Signal Input
Power Input for Internal Control Circuitry. A bypass capacitor 0.1µF should be connected near
the pin.
Block Diagram
VIN
VREF
VTTREF
GND
VCNTL
POR
VTT
S3
Soft-start and
Control Logic
S5
VTTSNS
Thermal
Shutdown
Current Limit
PGND
Typical Application Circuit
VIN
2.5/1.8/1.5V
VCNTL
CIN
10µF
VTT
1.25/0.9/0.75V
-3~+3A
APL5333
1
2
3
4
COUT
2x10µF
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
5
5V
10
C2
0.1µF
VCNTL
VREF
VIN
S5
VTT
GND
S3
PGND
VTTSNS
VTTREF
9
9
8
7
6
C1
0.1µF
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APL5333
Function Description
VTT Source/Sink Regulator
output voltage rise. If the load current is above the current
The APL5333 is a low dropout source/sink linear regulator
limit 1.7A at start-up, the VTT cannot start sucessfully.
STATE
S0
S3
S4/5
with maximum 3A source/sink current. Two internal Nchannel MOSFETs controlled by separate high bandwidth
error amplifiers regulate the output voltage by sourcing
current from VIN or sinking current to PGND. To prevent
S3
H
L
L
S5
H
H
L
VTTREF
1
1
0 (discharge)
VTT
1
0 (high-Z)
0 (discharge)
Table1. The truth table of S3 and S5 pins
two pass elements from shoot-through, a voltage offset
is created between two positive inputs of the error
S3, S5 Control
amplifiers. The APL5333 has a droop compensation for
minimizing the amplitude of the peak-to-peak VTT volt-
The S3 and S5 signals control the VTT and VTTREF states
and these pins should be connected to SLP_S3 and
SLP_S5 signals respectively. The table1 shows the truth
age during load transient response. The droop voltage,
added to the reference voltage applied to the positive
table of the S3 and S5 pins. When both S3 and S5 are
above the logic threshold voltage, the VTT and VTTREF
inputs, is regulated by and proportional to the VTT sourcing and sinking output current. Therefore, the droop volt-
are turned on at S0 state. When S3 is low and S5 is high,
the VTT voltage is disabled and left high impedance in S3
age is positive at sinking current and negative at sourcing current. Typical droop voltage is within ±40mV in all
state. When both S3 and S5 are low, the VTT and VTTREF
are turned off and discharged to the ground through inter-
conditions.
Power-on-Reset (POR)
nal MOSFETs during S4/S5 state. (Note that if the S3 is
forced high and S5 is forced low, then VTTREF is dis-
The APL5333 monitors the VCNTL pin voltage for
power-on-reset function to prevent erroneous operation.
charged and VTT is at high-Z state. Such condition is not
recommended.)
The built-in POR circuit keeps the outputs shutoff until
internal circuit is operating properly. Typical POR thresh-
Thermal Shutdown
old is 3.8V with 0.2V hysteresis.
A thermal shutdown circuit limits the junction tempera-
VTTREF Regulator
ture of the APL5333. When the junction temperature exceeds +150°C, the device will turn off the MOSFETs,
VTTREF voltage follows 1/2VREF voltage which is the
allowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start cycle
reference of the VTT regulator. The VTTREF block consists
of a resistor divider and a low pass filter. The regulator
after the junction temperature cools by 30oC, resulting in
a pulsed output during continuous thermal overload
can source current up to 10mA. To insure the stability, a 0.
1µF ceramic capacitor should be connected from VTTREF
conditions. The thermal shutdown designed with a 30°C
hysteresis lowers the average junction temperature
to GND.
during continuous thermal overload conditions, extending lifetime of the device. For normal operation, device
Soft-start, Current Limit and Short Circuit Current Limit
The APL5333 provides a current limit protection to pre-
power dissipation should be externally limited so that
vent the device from burnout. According to the voltage
between VTT and VTTREF, current limit level is divided
junction temperatures will not exceed +125°C.
into two levels. When the VTT voltage is out of the 10%
VTTREF voltage, the current limit is 1.7A (typical) and VTT
voltage comes inside the 5% of VTTREF voltage, the
current limit switches to 3.8A (typical). The APL5333
provides a soft-start function, using the constant current
to charge the output capacitor that gives a rapid and linear
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2008
10
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APL5333
Application Information
Layout Consideration
Input Capacitor
Figure 1 illustrates the layout. Below is a checklist for
The APL5333 requires proper input capacitors to supply
your layout:
1. Please place the input capacitors close to the VIN.
surge current during stepping load transients to prevent
the input rail from dropping. Because the parasitic induc-
2. Output capacitors for VTT must be close to the pin with
short and wide track.
tor from the voltage sources or other bulk capacitors to
the VIN limits the slew rate of the surge current, it is nec-
3. VTTSNS should be connected to the output capacitors
of VTT separated from large current path to avoid ef-
essary to place the input capacitors near VIN as close as
possible. Input capacitors should be greater than 4.7µF. A
fect of ESR and ESL. The ESR and ESL of ground track
between VTT and GND should be minimized.
capacitor of 0.47µF (MLCC) or above is recommended
for VCNTL pin noise decoupling.
4. VREF should be connected to VIN by a separate track.
VREF is the reference voltage of VTTREF, so avoid any
Output Capacitor
noise to get into the VREF.
5. PGND is the ground of VIN and VTT. GND is the signal
The APL5333 needs a proper output capacitor to maintain circuit stability and improve transient response over
ground of VREF, VTTREF S3 and S5. GND and PGND
should be isolated with a single point connection be-
temperature and current. In order to insure the circuit
stability, a 4.7µF MLCC (minimum) as an output capaci-
tween them.
6. Soldering the exposed pad to ground is good for
tor must be placed near the VTT. With X5R and X7R
dielectrics, 20µF is sufficient at all operating temperatures.
heatsinking. Numerous vias 0.33 mm in diameter connected from the thermal land to the internal/solder-
Attaching two 10µF ceramic capacitors in parallel, the effects from ESR and ESL can be minimized.
side ground plane(s) should be used to enhance
dissipation.
Thermal Consideration
The APL5333 maximum power dissipation depends on
the differences of the thermal resistance and tempera-
Large ground plane is good for heatsinking. Optimum
performance can only be achieved when the device is
mounted on a PC board according to the board layout
ture between junction and ambient air. The power dissipation PD across the device is:
diagrams which are shown as Figure 2.
PD = (TJ - TA) / θJA
VIN
where (TJ-TA) is the temperature difference between the
junction and ambient air. θ JA is the thermal resistance
VCNTL
CIN
between junction and ambient air. Assuming the TA=25°C
and maximum TJ=150°C (typical thermal limit threshold),
VTT
APL5333
1
VCNTL
VREF
2 VIN
3
S5
GND
VTT
the maximum power dissipation is calculated as:
4
PD(max)=(150-25)/60
COUT
5
PGND
VTTSNS
S3
VTTREF
5V
10
C2
9
8
7
6
C1
= 2.08(W)
For normal operation, do not exceed the maximum operating junction temperature of TJ = 125°C. The calculated
power dissipation should be less than:
Figure 1
PD =(125-25)/60
= 1.66(W)
The exposed pad provides an electrical connection to
ground and channels heat away. Connect the exposed
pad to ground by using a large ground plane.
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APL5333
Application Information (Cont.)
Layout Consideration (Cont.)
For dissipating heat
PGND
GND
CIN
VCNTL
VIN
C2
COUT
VTT
C1
PGND
APL5333
GND
Figure 2 Recommended Layout
Recommended Minimum Footprint
8
7
6
5
10
9
8
7
6
0.061
0.010
0.181
0.098
0.098
1
2
0.020
3
4
5
Unit : Inch
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APL5333
Package Information
MSOP-10P
D
SEE
VIEW A
e
E
E2
EXPOSED
PAD
E1
D1
c
0.25
A
A2
b
L
0
A1
GAUGE PLANE
SEATING PLANE
VIEW A
S
Y
M
B
O
L
MSOP-10P
INCHES
MILLIMETERS
MIN.
MIN.
MAX.
A
MAX.
0.043
1.10
A1
0.00
0.15
0.000
0.006
A2
0.75
0.95
0.030
0.037
b
0.17
0.33
0.007
0.013
c
0.08
0.23
0.003
0.009
D
2.90
3.10
0.114
0.122
D1
1.50
2.50
0.059
0.098
E
4.70
5.10
0.185
0.201
E1
2.90
3.10
0.114
0.122
E2
1.50
2.50
0.059
0.098
e
0.50 BSC
0.020 BSC
L
0.40
0.80
0.016
0.031
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MO-187 BA-T.
2. Dimension “D”does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not flash or protrusions.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 6 mil per side.
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APL5333
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
330.0±2.00 50 MIN.
MSOP-10P
P0
T1
C
d
D
W
E1
12.4+2.00 13.0+0.50
1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10
-0.00
-0.20
P1
P2
4.00±0.10 8.00±0.10 2.00±0.10
D0
D1
1.5+0.10
-0.00
1.5 MIN.
T
A0
B0
F
5.5±0.10
K0
0.6+0.00
6.70±0.20 3.30±0.20 1.40±0.20
-0.40
(mm)
Devices Per Unit
Package Type
Unit
Quantity
MSOP- 10P
Tape & Reel
3000
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APL5333
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Time 25°C to Peak Temperature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
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APL5333
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Package Thickness
<2.5 mm
≥2.5 mm
3
Volume mm3
<350
240 +0/-5°C
225 +0/-5°C
Volume mm
≥350
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Package Thickness
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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