RF6555 Product Data Sheet

RFMD + TriQuint = Qorvo
RF6555
RF6555
2.0V TO 3.6V, 2.4GHz FRONT END MODULE
The RF6555 integrates a complete solution in a single Front
End Module (FEM) for WiFi and ZigBee® applications in the
2.4GHz to 2.5GHz band. This FEM integrates the PA plus
harmonic filter in the transmit path. The RF6555 also has an
integrated LNA with bypass mode internally. The RF6555
provides a single balanced TDD access for Rx and Tx paths
along with two ports on the output for connecting a diversity
solution or a test port. The device is provided in a 5mm x 5mm
x 1mm, 24-pin laminate package.
Package: Laminate, 24-Pin,
5mm x 5mm x 1mm
Features
■
Tx Output Power = 18dBm
■
Integrated RF Front End Module
with Rx Balun, PA, Filter, LNA with
Bypass Mode, and DP2T Switch
■
Single Bidirectional Differential
Transceiver Interface.
■
Voltage Range = 2.0V to 3.6V
Applications
■
ZigBee® 802.15.4 Based Systems
for Remote Monitoring and Control
■
Set-top Boxes
■
AA Battery Operation
■
2.4GHz ISM Band Applications
■
Smart Meters for Energy
Management
Functional Block Diagram
Ordering Information
RF6555SB
Standard 5-piece sample bag
RF6555SQ
Standard 25-piece sample bag
RF6555SR
Standard 100-piece reel
RF6555TR13
Standard 2500-piece reel
RF6555PCK-410
Fully assembled eval board w/ 5-piece sample bag
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RF6555
RFMD + TriQuint = Qorvo
Absolute Maximum Ratings
Parameter
Rating
Caution! ESD sensitive device.
Unit
DC Supply Voltage
5.0
V
DC Supply Current
150
mA
Operating Case Temperature
-40 to +85
ºC
Storage Temperature
-40 to +150
ºC
ESD Human Body Model RF Pins
1000
V
ESD Human Body Model All Other Pins
500
V
ESD Charge Device Model All Pins
500
V
Moisture Sensitivity Level
MSL 2
Maximum Tx Input Power
+5
dBm
Maximum Rx Input Power
+8
dBm
RFMD Green: RoHS status based on EU
Directive 2011/65/EU (at time of this
document revision), halogen free per IEC
61249-2-21, < 1000ppm each of
antimony trioxide in polymeric materials
and red phosphorus as a flame retardant,
and <2% antimony in solder.
Exceeding any one or a combination of the Absolute
Maximum Rating conditions may cause permanent
damage to the device. Extended application of Absolute
Maximum Rating conditions to the device may reduce
device reliability. Specified typical performance or
functional operation of the device under Absolute
Maximum Rating conditions is not implied.
Nominal Operating Parameters
Specification
Parameter
Unit
Min
Typ
Condition
Max
Parameter
VBATT
2.0
3.0
3.6
VDC
Operating Temperature Range
-40
+25
+85
ºC
1.0
µA
+150
°C
ZO
Storage Temperature
Ω
50
Off Mode Current
0.05
-40
All logic low, Temp = 25°C; Over Voltage.
ESD, HBM
1000
V
RF pins
ESD, HBM
500
V
All other pins
ESD, CDM
500
V
All pins
MSL
MSL3
Current Sourced through CT Pin
18
mA
Voltage Drop from CT Pin to RXP/RXN
0.1
V
2480
MHz
Tx Path
Frequency
2405
Input Return Loss
10
dB
Output Return Loss
10
dB
Gain
22
25
21
+0.8
Pins 5, 6 (RFM, RFP) 100Ω differential
dB
2.7V to 3.6V
dB
VCC=2.0V; Temp=25oC
Gain Flatness
-0.8
Rated Output Power
20
dBm
dB
Nominal conditions (VB=3.3 to 3.6, All Temp)
18
dBm
Nominal conditions (VB=3.0 to 3.3, All Temp)
16
dBm
Nominal conditions (VB=2.7, All Temp)
14
dBm
Nominal conditions (VB=2.0, All Temp)
dBm
VB=3.6, Temp = 25C
Saturated Output Power
22
dBm
VB=3.0, Temp = 25C
Supply Current
110
125
mA
PO =21dBm 802.15.4 OQPSK (VB=3.6, All Temp)
105
120
mA
PO =20dBm 802.15.4 OQPSK (VB=3.0, All Temp)
70
95
mA
PO =18dBm 802.15.4 OQPSK (VB=3.0, All Temp)
20
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RF6555
RFMD + TriQuint = Qorvo
Specification
Parameter
Unit
Min
Typ
50
Thermal Resistance
-45
VSWR Stability and Load
4:1
VSWR No Damage
8:1
Gain Settling Time
1
mA
PO =14dBm 802.15.4 OQPSK (VB=2.0, All Temp)
C/W
VCC = 3.0V, POUT = 18dBm, TREF = 85oC
o
78
Harmonics 2f0 to 5f0
Condition
Max
-42
10
dBm/MHz
At 18dBm, VCC = 3.0V to 3.6V
µS
Rx Path
Frequency
Gain
2405
8.5
11
Noise Figure
3
Current
8
IIP3
7
2480
MHz
13
dB
12
Temp = 25°C; over voltage and frequency
mA
Nominal conditions
dBm
Gain Flatness
Input Return Loss
-0.5
10
Output Return Loss
10
Amplitude Imbalance
-1
+1
Phase Imbalance
-15
+15
Maximum Input Power
dB
+0.5
15
dB
dB
dB
5
Pins 5, 6 (RFM, RFP) 100Ω differential
dB
dB
dBm
Bypass Mode
Frequency
2405
Insertion Loss/Noise Figure
5
Current
50
IIP3
2480
MHz
6.5
dB
23
dBm
Gain Flatness
Input Return Loss
-0.5
Output Return Loss
10
Amplitude Imbalance
-1
+1
dB
Phase Imbalance
-15
+15
dB
Maximum Input Power
10
10
SW1dB, Bypass 2.5dB, Balun 1.5dB
µA
0.5
12
dB
dB
dB
Pins 5, 6 (RFM, RFP) 100Ω differential
dBm
Logic
Logic Level “HIGH” Input Voltage
VBATT -0.2
VBATT
Logic Level “LOW” Input Voltage
0.0
0.2
V
10
µA
1
µA
Input Source Current at Logic “HIGH”
5
Switch Leakage Current at Logic “LOW”
V
Antenna Switch
RF to Control Isolation
50
ANT1 to ANT2 Isolation
20
T/R Switching Time
Revision DS20150615
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dB
dB
1
3 of 10
µS
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RF6555
RFMD + TriQuint = Qorvo
Control Logic Table
Mode
CE
C_RX_TX
C_LNA
ANTSEL
TX-ANT1
High
High
Low
Low
TX-ANT2
High
High
Low
High
RX-ANT1 LNA
High
Low
Low
Low
RX-ANT1 BYP
High
Low
High
Low
RX-ANT2 LNA
High
Low
Low
High
RX-ANT2 BYP
High
Low
High
High
Power Down
Low
Low
Low
Low
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RF6555
RFMD + TriQuint = Qorvo
Applications Schematic
C_LNA
VCC
C_Rx_Tx
24
CE
4
U2
6
1
1
19
2
18
3
17
U1
RF6555
5
15
50Ω µstrip
6
14
7
13
8
50Ω µstrip
20
50Ω µstrip
2
50Ω - 100Ω
21
4
3
2450MHz
22
CT
BALUN
5
23
ANT SEL
9
10
50Ω µstrip
J3
ANT2
50Ω µstrip
J2
ANT1
16
11
12
J1
RF_COM
C1
0.1µF
(0402)
VCC
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RF6555
RFMD + TriQuint = Qorvo
Pin Out
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RF6555
RFMD + TriQuint = Qorvo
Package Drawing
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RF6555
RFMD + TriQuint = Qorvo
PCB Patterns
Thermal vias for center slug “D” should be incorporated into the PCB design. The number and size of thermal vias will depend
on the application, power dissipation and electrical requirements. Example of the number and size of vias can be found on the
RFMD evaluation board layout (gerber files are available upon request).
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RF6555
RFMD + TriQuint = Qorvo
RF6555 2.4 GHz Front End Module
Revision DS20150615
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RF6555
RFMD + TriQuint = Qorvo
Pin Names and Descriptions
Pin
Name
1
GND
2
CE
3
GND
4
CT
5
RFN
Differential bi-directional RF port. Matched to 50Ω single-ended, 100Ω differential.
6
RFP
Differential bi-directional RF port. Matched to 50Ω single-ended, 100Ω differential.
7
GND
Ground.
8
VCC_DIG
9
GND
10
VCC_PA
11
N/C
Not connected.
12
GND
Ground.
13
GND
Ground.
14
GND
Ground.
15
ANT1
Antenna port 1. Match to 50Ω and DC blocked internally.
16
GND
GND Ground.
17
ANT2
Antenna port 2. Matched to 50Ω and DC blocked internally.
18
GND
Ground.
19
GND
Ground.
20
ANTSEL
21
N/C
22
VCC_LNA
23
C_LNA
24
C_RX_TX
Revision DS20150615
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Description
Ground.
Control voltage pin for chip enable. See logic table.
Ground.
Center tap for passing DC voltage to RFN/RFP pins that connect to the TXVR SoIC.
Voltage supply pin for digital logic circuitry.
Ground.
Voltage supply pin for Tx power amplifier.
Control pin for antenna selection. See logic table.
Not connected.
Voltage supply pin for Rx low noise amplifier.
Control voltage for pin for LNA/bypass modes. See logic table.
Control voltage pin for Tx/Rx modes. See logic table.
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