APL5337

APL5337
Source and Sink, 2A, Fast Transient Response Linear Regulator
Features
General Description
•
The APL5337 linear regulator is designed to provide a
Provide Bi-direction Current
regulated voltage with bi-direction output current for DDRSDRAM termination voltage. The APL5337 integrates two
- Sourcing or Sinking Current Up to 2A
•
Built-in Soft-Start
•
Power-On-Reset Monitoring on VCNTL Pins
•
Fast Transient Response
•
Stable with Ceramic Output Capacitors
•
±10mV High System Output Accuracy Over Load
power transistors to source or sink load current up to 2A.
It also features internal soft-start, current-limit, thermal
shutdown and enable control functions into a single chip.
The internal soft-start controls the rising rate of the output
voltage to prevent inrush current during start-up. The
current-limit circuit detects the output current and limits
and Temperature Ranges
•
Adjustable Output Voltage by External Resistors
•
Current-Limit Protection
•
On-Chip Thermal Shutdown
•
Shutdown for Standby or Suspend Mode
•
Simple SOP-8 and SOP-8 with Exposed Pad
the current during short-circuit or current overload
conditions. The on-chip thermal shutdown provides thermal protection against any combination of overload that
would create excessive junction temperatures.
The output voltage of APL5337 is regulated to track the
voltage on VREF pin. A proper resistor divider connected
(SOP-8P) Packages
•
to VIN, GND, and VREF pins is used to provide a half
voltage of VIN to VREF pin. In addition, connect an exter-
Lead Free and Green Devices Available
(RoHS Compliant)
nal ceramic capacitor and an open-drain transistor to VREF
pin for external soft-start and shutdown control.
Applications
Pulling and holding the voltage on VREF below the enable voltage threshold shuts down the output. The output
•
DDRII/III/IV SDRAM Termination Voltage
•
Motherboard and VGA Card Power Supplies
•
Setop Box
•
Low Power DDR3 DDRIII/IV
of APL5337 will be high impedance after being shut down
by VREF or the thermal shutdown function.
Pin Configuration
Simplified Application Circuit
VCNTL
+5V
VIN
+1.8V/+1.5V
VIN 1
8 VCNTL
GND 2
7 VCNTL
VREF 3
6 VCNTL
VOUT 4
5 VCNTL
Top View of SOP-8
1
3
VIN
VCNTL
APL5337
VREF VOUT
GND
2
6
4
VOUT
0.9V / 0.75V
Shutdown
Enable
VIN 1
8 NC
GND 2
7 NC
VREF 3
6 VCNTL
VOUT 4
5 NC
Top View of SOP-8P
Exposed Pad (connected to GND plane
for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
1
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APL5337
Ordering and Marking Information
Package Code
K : SOP-8 KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APL5337
Assembly Material
Handling Code
Temperature Range
Package Code
APL5337 K:
APL5337
XXXXX
XXXXX - Date Code
APL5337 KA:
APL5337
XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Parameter
Rating
Unit
VCNTL Supply Voltage (VCNTL to GND)
-0.3 ~ 7
V
VIN Supply Voltage (VIN to GND)
-0.3 ~ 5
V
VREF
VREF Input Voltage (VREF to GND)
-0.3 ~ 7
V
VOUT
VOUT Output Voltage (VOUT to GND)
-0.3 ~ VIN+0.3V
V
Symbol
VCNTL
VIN
PD
TJ
TSTG
TSDR
Power Dissipation
Internally Limited
Junction Temperature
Storage Temperature Range
Maximum Lead Soldering Temperature, 10 Seconds
W
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under
"recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Junction-to-Ambient Thermal Resistance in Free Air
Typical Value
Unit
SOP-8
SOP-8P
80
55
°C/W
SOP-8P
7
(Note 2)
Junction-to-Case Thermal Resistance in Free Air (Note 3)
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Note 3: The exposed pad of SOP-8P is soldered directly on the PCB. The case temperature is measured at the center of the exposed
pad on the underside of the SOP-8P package.
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APL5337
Recommended Operating Conditions
Symbol
VCNTL
Parameter
VCNTL Supply Voltage
Range
Unit
3.0 ~ 5.5
V
VIN
VIN Supply Voltage
1.1 ~ 4.5
V
VREF
VREF Input Voltage
0.6 ~ VCNTL - 2.2
V
-2 ~ +2
A
IOUT
CIN
COUT
VOUT Output Current
(Note 4)
Capacitance of Input Capacitor
10 ~ 100
µF
Equivalent Series Resistor (ESR) of Input Capacitor
0 ~ 200
mΩ
Capacitance of Output Multi-layer Ceramic Capacitor (MLCC)
8 ~ 47
µF
10 ~ 820
µF
-40 ~ 85
o
-40 ~ 125
o
Total Output Capacitance
TA
TJ
(Note 5)
Ambient Temperature
Junction Temperature
C
C
Note 4: The symbol “+” means the VOUT sources current to load; the symbol “-” means the VOUT sinks current from load to GND.
Note 5: It’s necessary to use a multi-layer ceramic capacitor 8µF at least as an output capacitor. Please place the ceramic
capacitor near VOUT pin as close as possible. Besides, the other kinds of capacitors (like Electrolytic, PoSCap, tantalum
capacitors) can be used as the output capacitors in parallel.
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over VCNTL=5V, VIN=1.2V~1.8V, VREF=0.5VIN, CIN=10µF, COUT=10µF
(MLCC) and TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APL5337
Test Conditions
Unit
Min.
Typ.
Max.
IOUT=0A
-
1
2
mA
VREF=0V (Shutdown)
-
-
35
µA
VREF=GND (Shutdown)
-
-
5
µA
2.3
2.6
2.9
V
-
0.35
-
V
SUPPLY CURRENT
ICNTL
VCNTL Supply Current
IVIN
VIN Supply Current at Shutdown
POWER-ON-RESET (POR)
Rising VCNTL POR Threshold
VCNTL Rising
VCNTL POR Hysteresis
OUTPUT VOLTAGE
VOUT
PSRR
IDIS
Output Voltage
VREF=0.9V
-
0.9
-
VREF=0.75V
-
0.75
-
VREF=0.6V
-
0.6
-
V
Output Accuracy to VREF
Over Load, Offset and Temperature
-10
-
10
mV
VCNTL Power Supply Rejection Ratio
VCNTL=5V, COUT=10µF, f=1kHz 1VPP
45
55
-
dB
-
22
-
µA
-
0.2
-
-
0.19
-
Discharge Current
o
TJ =25 C, VOUT=0.1V
DROPOUT VOLTAGE
VDROP
VIN-to-VOUT Dropout Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
VCNTL=5.0V VOUT=1.2V
, IOUT=1A
VOUT=0.6V
3
TJ=25oC
o
TJ=25 C
V
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APL5337
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over VCNTL=5V, VIN=1.2V or 1.8V, VREF=0.5VIN, CIN=10µF, COUT=10µF
(MLCC) and TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C.
Symbol
Parameter
APL5337
Test Conditions
Unit
Min.
Typ.
Max.
VREF Enable Voltage Threshold
0.15
0.3
0.4
V
VREF Bias Current
-100
-
+100
nA
Soft-Start Interval
0.1
0.2
0.4
ms
2.6
3.2
3.8
ENABLE AND SOFT-START
IVREF
tSS
PROTECTIONS
Sourcing Current
ILIM
Current-Limit
Sinking Current
TSD
Thermal Shutdown Temperature
TJ Rising
Thermal Shutdown Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
4
TJ=25oC
o
TJ=-40~125 C
2.3
3.0
3.7
TJ=25oC
-2.6
-3.2
-3.8
TJ=-40~125oC
-2.3
-3.0
-3.7
-
150
-
o
-
30
-
o
A
C
C
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APL5337
Typical Operating Characteristics
VCNTL Supply Current vs. Junction
Temperature
VCNTL Shutdown Current vs.
Junction Temperature
35
VCNTL Shutdown Current (µA)
VCNTL Supply Current (µA)
600
540
480
420
360
300
-50 -25
0
25
50
25
20
15
10
-50
75 100 125 150
-25
0
25
50
75 100 125 150
Junction Temperature ( oC)
Junction Temperature ( oC)
VIN Shutdown Current vs. VIN Supply
Voltage
VIN Supply Current vs. VIN Supply
Voltage
0.5
6
VREF=0V
0.4
VIN Supply Current (µA)
VIN Shutdown Current (µA)
30
0.3
0.2
0.1
VREF=0.9V
5
4
3
2
1
0
0
0
0.5
1.0
1.5
0
2.0
VIN Supply Voltage(V)
0.5
1.0
1.5
2.0
VIN Supply Voltage (V)
Offset Voltage vs. Junction Temperature
2
Offset Voltage (mV)
1.6
1.2
0.8
0.4
0
-50
-25
0 25 50 75 100 125 150
Junction Temperature (oC)
Copyright  ANPEC Electronics Corp.
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APL5337
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=1.5V or 1.8V or 1.35V, TA=25oC unless otherwise
specified.
[email protected] Load Transient (Source)
1
[email protected] Load Transient (Sink)
VIN
1
VOUT
VOUT
2
2
VREF
3
3
IOUT
VREF
IOUT
4
4
VCNTL=3.3V, VREF=0.9V, VIN=1.8V
CH1: VIN, 100mV/Div, AC
CH2: VOUT, 20mV/Div, AC
CH3: VREF, 20mV/Div, AC
CH4: IOUT, 1A/Div, DC
TIME: 20µs/Div
VCNTL=3.3V, VREF=0.9V, VIN=1.8V
CH1: VIN, 100mV/Div, AC
CH2: VOUT, 20mV/Div, AC
CH3: VREF, 20mV/Div, AC
CH4: IOUT, 1A/Div, DC
TIME: 20µs/Div
[email protected] Load Transient (Source)
1
VIN
[email protected] Load Transient (Sink)
VIN
1
VOUT
2
VIN
VOUT
2
VREF
VREF
3
3
IOUT
IOUT
4
4
VCNTL=3.3V, VREF=0.75V, VIN=1.5V
CH1: VIN, 100mV/Div, AC
CH2: VOUT, 20mV/Div, AC
CH3: VREF, 20mV/Div, AC
CH4: IOUT, 1A/Div, DC
TIME: 20µs/Div
VCNTL=3.3V, VREF=0.75V, VIN=1.5V
CH1: VIN, 100mV/Div, AC
CH2: VOUT, 20mV/Div, AC
CH3: VREF, 20mV/Div, AC
CH4: IOUT, 1A/Div, DC
TIME: 20µs/Div
Copyright  ANPEC Electronics Corp.
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APL5337
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=1.5V or 1.8V or 1.35V, TA=25oC unless otherwise
specified.
VREF=0.675V Load Transient (Source)
VREF=0.675V Load Transient (Sink)
1
1
2
2
3
3
4
4
VCNTL=3.3V, VREF=0.675V, VIN=1.35V
VCNTL=3.3V, VREF=0.675V, VIN=1.35V
CH1: VIN, 200mV/Div, DC, Offset=1.35V
CH1: VIN, 200mV/Div, DC, Offset=1.35V
CH2: VOUT, 50mv/Div, DC, Offset=0.675V
CH2: VOUT, 20mv/Div, DC, Offset=0.675V
CH3: VREF, 20mV/Div, DC, Offset=0.675V
CH3: VREF, 50mV/Div, DC, Offset=0.675V
CH4: IOUT, 0.5A/Div, DC
CH4: IOUT, 0.5A/Div, DC
TIME: 0.2mS/Div
TIME: 0.2mS/Div
Power on @ VCNTL=3.3V
Power on @ VCNTL=5V
VIN
VIN
1
1
VOUT
2
3
2
3
VREF
VCNTL=3.3V, VREF=0.9V, VIN=1.8V
CH1: VIN, 100mV/Div, AC
CH2: VOUT, 200mV/Div, DC
CH3: VREF, 200mV/Div, DC
TIME: 10mS/Div, Load=600Ω
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
VOUT
VREF
VCNTL=5V, VREF=0.9V, VIN=1.8V
CH1: VIN, 100mV/Div, DC
CH2: VOUT, 200mV/Div, DC
CH3: VREF, 200mV/Div, DC
TIME: 10mS/Div, Load=600Ω
7
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APL5337
Pin Description
PIN
NO.
FUNCTION
NAME
SOP-8P
SOP-8
1
1
VIN
Main Power Input Pin. Connect this pin to a voltage source and an input capacitor.
The APL5337 sources current to VOUT pin by controlling the upper pass MOSFET,
providing a current path from VIN to VOUT.
2
2
GND
Power and Signal Ground. Connect this pin to system ground plane with shortest
traces. The APL5337 sinks current from VOUT pin by controlling the lower pass
MOSFET, providing a current path from VOUT to GND. This pin is also the ground
path for internal control circuitry.
VREF
Reference Voltage Input and Active-high Enable Control Pin. Apply a voltage to this
pin as a reference voltage for the APL5337. Connect this pin to a resistor diver,
between VIN and GND, and a capacitor for filtering noise purpose. Applying and
holding the voltage below the enable voltage threshold on this pin by an open-drain
transistor shuts down the output. During shutdown, the VOUT pin has high input
impedance.
Output Pin of The Regulator. Connect this pin to load and output capacitors (>8µF
MLCC is necessary) required for stability and improving transient response. The
output voltage is regulated to track the reference voltage and capable of sourcing or
sinking current up to 1.5A.
3
3
4
4
VOUT
5, 7, 8
-
NC
6
5~8
VCNTL
Power Input Pin for Internal Control Circuitry. Connect this pin to a voltage source,
providing a bias for the internal control circuitry. A decoupling capacitor is connected
near this pin.
Exposed Pad
-
GND
Chip Substrate Connection of The Chip. Connect this pad to system ground plane
for good thermal conductivity.
No Internal Connection.
Block Diagram
VIN
VCNTL
Power-OnReset
VREF
Enable
EN
POR
VREF
Thermal
Shutdown
THSD
Error
Amplifier
and
Soft-Start
VOUT
Current-Limit
GND
Copyright  ANPEC Electronics Corp.
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APL5337
Typical Application Circuit
VCNTL
+5V
VIN
1.2V ~ 1.8V
1
C2
47µF
R1
100kΩ
3
VIN
VCNTL
APL5337
VREF
GND
Q1
Enable
R2
100kΩ
4
VOUT
0.6V ~ 0.9V
2
VREF
Shutdown
VOUT
C1
1µF
6
C5
10µF
C4
1µF
C3
100µF
(optional)
The ceramic capacitor C5 ( at least 8µF) is necessary for output stability.
Copyright  ANPEC Electronics Corp.
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APL5337
Function Description
Power-On-Reset
Internal and External Soft-Start
A Power-On-Reset (POR) circuit monitors both input volt-
The APL5337 is designed with an internal soft-start func-
ages at VCNTL pins to prevent wrong logic controls. The
POR function initiates a soft-start process after both of
tion to control the rise rate of the output voltage to prevent
inrush current during start-up.
the supply voltages exceed their rising POR voltage
thresholds during powering on.
When release the pull-low transistor connected with VREF
pin, the current via the resistor divider charges the exter-
Output Voltage Regulation
nal soft-start capacitor (C4) and the VREF starts to rise up.
The IC starts a soft-start process when the VREF reaches
The output voltage on VOUT pin is regulated to track the
the enable voltage threshold. The output voltage is regulated to follow the lower voltage, which is either the inter-
reference voltage applied on VREF pin. Two internal Nchannel power MOSFETs controlled by high bandwidth
nal soft-start voltage ramp or the VREF voltage, to rise up.
The external soft-start interval is programmable by the
error amplifiers regulate the output voltage by sourcing
current from VIN pin or sinking current to GND pin. An
resistor-divider and the soft-start capacitor (C4).
internal output voltage sense pad is bonded to the VOUT
pin with a bonding wire for perfect load regulation.
Thermal Shutdown
For preventing the two power MOSFETs from shootthrough, a small voltage offset between the positive in-
The thermal shutdown circuit limits the junction temperature of the APL5337. When the junction temperature ex-
puts of the two error amplifiers is designed. It results in
higher output voltage while the regulator sinks light or
ceeds 150oC, a thermal sensor turns off the both pass
transistors, allowing the device to cool down. The ther-
heavy load current.
The APL5337 provides a very fast load transient response
mal sensor allows the regulator to regulate again after
the junction temperature cools by 30oC, resulting in a
at small output capacitance to save total cost.
pulsed output during continuous thermal overload
conditions. The thermal limit is designed with a 30 oC
Current-Limit
hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the
The APL5337 monitors the output current, both sourcing
and sinking current, and limits the maximum output cur-
APL5337.
rent to prevent damages during current overload or shortcircuit (shorten from VOUT to GND or VIN) conditions.
Enable
The VREF pin is a multi-function input pin which is the
reference voltage input pin and the enable control input
pin. Applying and holding the voltage (VREF) on VREF below 0.3V (typical) shuts down the output of the regulator.
In the typical application, an NPN transistor or N-channel
MOSFET is used to pull down the VREF while applying a
“high” signal to turn on the transistor. When shutdown
function is active, both of the internal power MOSFETs are
turned off and the impedance of the VOUT pin is larger
than 10mΩ.
Copyright  ANPEC Electronics Corp.
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APL5337
Application Information
Table 1: Output Capacitor Guide
Power Sequencing
Vendor
The input sequence of powers applied for VIN and VCNTL
is not necessary to be concerned.
Description
10µF, 6.3V, X7R, 0805, GRM21BR70J106K
Murata
10µF, 6.3V, X5R, 0805, GRM21BR60J106K
Reference Voltage
Murata website: www.murata.com
A reference voltage is applied at the VREF pin by a resistor divider between VIN and GND pins. An external by-
Operation Region and Power Dissipation
pass capacitor is also connected to VREF. The capacitor
and the resistor divider form a low-pass filter to reduce
The APL5337 maximum power dissipation depends on
the thermal resistance and temperature difference be-
the inherent reference noise from VIN. The capacitor is a
0.1µF or greater ceramic capacitor and connected as close
tween the die junction and ambient air. The power dissipation PD across the device is:
to VREF as possible. More capacitance and large resistor divider will increase the soft-start interval. Do not place
PD ≤
any additional loading on this reference input pin.
(TJ − TA )
θJA
Where (TJ-TA) is the temperature difference between the
junction and ambient air. θJA is the thermal resistance
o
between junction and ambient air. Assuming the TA=25 C
Input Capacitor
The APL5337 requires proper input capacitors to supply
current surge during stepping load transients to prevent
o
and maximum TJ=150 C (typical thermal limit threshold),
the maximum power dissipation is calculated as:
the input rail from dropping. Because the parasitic inductors from the voltage sources or other bulk capacitors to
(150 − 25)
80
= 1.56( W )
PD(max) =
the VIN pin limit the slew rate of the input current, more
parasitic inductance needs more input capacitance. For
the APL5337, the total capacitance of input capacitors
value including MLCC and aluminum electrolytic capaci-
For normal operation, do not exceed the maximum junco
tion temperature of TJ = 125 C. The calculated power dis-
tors should be larger than 10µF.
For VCNTL pin, a capacitor of 0.47µF (MLCC) or above is
sipation should less than:
(125 − 25)
80
= 1.25( W )
PD =
recommended for noise decoupling.
Output Capacitor
PCB Layout Consideration
The APL5337 needs a proper output capacitor to maintain circuit stability and improve transient response. In
order to insure the circuit stability, a 10µF X5R or X7R
Figure 1 illustrates the layout. Below is a checklist for
your layout:
1. Please place the input capacitors close to the VIN.
MLCC output capacitor is sufficient at all operating temperatures and it must be placed near the VOUT. The maxi-
2. Please place the output capacitors close to the VOUT,
a MLCC capacitor larger than 8µF must be placed near
mum distance from output capacitor to VOUT must within
10mm. Total output capacitors value including MLCC and
the VOUT. The distance from VOUT to output MLCC
must be less than 10mm.
aluminum electrolytic capacitors should be larger than
10µF.
3. To place APL5337 and output capacitors near the load
is good for load transient response.
Table 1 provides the suitable output capacitors for
APL5337.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
4. Large current paths, the bold lines in Figure 1, must
have wide tracks.
11
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APL5337
Application Information (Cont.)
Recommended Minimum Footprint
0.024
to the APL5337 to top-layer ground plane. Numerous
vias 0.254mm in diameter should be used to connect
8
7
6
5
0.024
8
0.072
5. For SOP-8P package, please solder the thermal pad
7
both top-layer and internal ground planes. The ground
planes and PCB form a heat sink to channel major
6
5
0.072
PCB Layout Consideration (Cont.)
0.118
0.212
0.212
0.138
power dissipation of the APL5337 into ambient air.
Large ground plane is good for heatsinking. Optimum
performance can only be achieved when the device is
mounted on a PC board according to the board layout
diagrams which are shown as Figure 2.
1
2
0.050
APL5337
VIN
C2
3
4
Unit : Inch
SOP-8
1
2
0.050
3
4
Unit : Inch
SOP-8P
VCNTL
VREF
VOUT
GND
C5
C3
(optional)
Figure 1.
For dissipating
heat
VCNTL
C2
+
Ground
C3
+
C5
VIN
<10mm
VOUT
SOP-8
VCNTL
For dissipating
heat
Ground
C2
+
C5
VIN
<10mm
C3
+
VOUT
Ground
SOP-8P
Figure 2. Recommended Layout
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APL5337
Package Information
SOP-8
-T-
SEATING PLANE < 4 mils
D
E
E1
SEE VIEW A
h X 45
°
c
A
0.25
b
GAUGE PLANE
SEATING PLANE
A1
A2
e
L
VIEW A
S
Y
M
B
O
L
SOP-8
INCHES
MILLIMETERS
MIN.
MAX.
A
MIN.
MAX.
1.75
0.069
0.010
0.004
0.25
A1
0.10
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
e
0.049
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
13
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APL5337
Package Information
SOP-8P
-T- SEATING PLANE < 4 mils
D
SEE VIEW A
h X 45o
E
THERMAL
PAD
E1
E2
D1
c
A1
0.25
A2
A
b
e
GAUGE PLANE
SEATING PLANE
θ
L
VIEW A
S
Y
M
B
O
L
A
SOP-8P
INCHES
MILLIMETERS
MAX.
MIN.
MIN.
MAX.
1.60
A1
0.00
A2
1.25
b
0.31
0.063
0.15
0.000
0.51
0.012
0.020
0.010
0.006
0.049
c
0.17
0.25
0.007
D
4.80
5.00
0.189
0.197
0.138
D1
2.50
3.50
0.098
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
E2
2.00
3.00
0.079
e
1.27 BSC
0.118
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0o C
8o C
θ
0oC
8o C
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
14
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APL5337
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOP-8(P)
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
(mm)
Devices Per Unit
Package Type
SOP-8(P)
Unit
Tape & Reel
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
Quantity
2500
15
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APL5337
Taping Direction Information
SOP-8(P)
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
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16
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APL5337
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
17
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APL5337
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jun., 2013
18
www.anpec.com.tw