HD74HC354 8-to-1-line Data Selector/Multiplexer/Register (with 3-state outputs) REJ03D0613–0200 (Previous ADE-205-492) Rev.2.00 Jan 31, 2006 Description This data selectors/multiplexers contains full on-chip binary decoding to select one of eight data sources. The data select address is stored in transparent latches that are enabled by a low level address on pin 11, Select Control. Data on the 8 input lines is stored in a parallel input/output register which in the HD74HC354 is composed of 8 transparent latches enabled by a low level on pin 9, Data Control. Both true (Y) and complementary (W) 3-state outputs are available. Features • • • • • • High Speed Operation: tpd (DC to W, Y) = 23 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type HD74HC354P DILP-20 pin HD74HC354FPEL SOP-20 pin (JEITA) Package Code (Previous Code) PRDP0020AC-B (DP-20NEV) PRSP0020DD-B (FP-20DAV) Package Abbreviation P — FP EL (2,000 pcs/reel) PRSP0020DC-A RP (FP-20DBV) Note: Please consult the sales office for the above package availability. HD74HC354RPEL SOP-20 pin (JEDEC) Rev.2.00 Jan 31, 2006 page 1 of 9 Taping Abbreviation (Quantity) EL (1,000 pcs/reel) HD74HC354 Function Table S1 X X X L L L L L L L L H H H H H H H H Select S2 X X X L L L L H H H H L L L L H H H H S0 X X X L L H H L L H H L L H H L L H H Inputs Data Control DC X X X L H L H L H L H L H L H L H L H G1 H X X L L L L L L L L L L L L L L L L Outputs Output Enable G2 X H X L L L L L L L L L L L L L L L L G3 X X L H H H H H H H H H H H H H H H H Notes: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance Pin Arrangement D7 1 20 VCC D6 2 19 Y D5 3 18 W D4 4 17 G3 D3 5 16 G2 D2 6 15 G1 D1 7 14 S0 D0 8 13 S1 Data control 9 12 S2 Outputs Data inputs Select 11 Select control GND 10 (Top view) Rev.2.00 Jan 31, 2006 page 2 of 9 Output enables W Z Z Z D0 D0n D1 D1n D2 D2n D3 D3n D4 D4n D5 D5n D6 D6n D7 D7n Y Z Z Z D0 D0n D1 D1n D2 D2n D3 D3n D4 D4n D5 D5n D6 D6n D7 D7n HD74HC354 Logic Diagram S0 D C Q C S1 D C Q C S2 D C Q C SC D0 D C Q C D1 D C VCC Q C D2 D C W Q C D3 VCC D C Q C Y D4 D C Q C D5 D C Q C D6 D C Q C D7 D C Q C DC G1 G2 G3 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Symbol VCC VIN, VOUT IIK, IOK Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 Unit V V mA Output current VCC, GND current Power dissipation Storage temperature IO ICC or IGND PT Tstg ±35 ±75 500 –65 to +150 mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00 Jan 31, 2006 page 3 of 9 HD74HC354 Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Output voltage Symbol VCC (V) Ta = 25°C Typ Max — — — — — — Ta = –40 to+85°C Unit Min Max 1.5 — V 3.15 — 4.2 — VIH 2.0 4.5 6.0 Min 1.5 3.15 4.2 VIL 2.0 4.5 6.0 — — — — — — 0.5 1.35 1.8 — — — 0.5 1.35 1.8 V VOH 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 1.9 4.4 5.9 4.18 5.68 — — — — — — 2.0 4.5 6.0 — — 0.0 0.0 0.0 — — — — — — — — 0.1 0.1 0.1 0.26 0.26 ±0.5 1.9 4.4 5.9 4.13 5.63 — — — — — — — — — — — 0.1 0.1 0.1 0.33 0.33 ±5.0 V 6.0 6.0 — — — — ±0.1 4.0 — — ±1.0 40 VOL Off-state output current Input current IOZ Quiescent supply current ICC Iin Rev.2.00 Jan 31, 2006 page 4 of 9 V Test Conditions Vin = VIH or VIL IOH = –20 µA Vin = VIH or VIL IOH = –6 mA IOH = –7.8 mA IOL = 20 µA IOH = 6 mA IOH = 7.8 mA µA Vin = VIH or VIL, Vout = VCC or GND µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC354 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Propagation delay time Symbol VCC (V) tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Output enable time tZH tZL Output disable time tLZ tHZ Setup time tsu Hold time th Pulse width tw Output rise/fall time tTLH tTHL Input capacitance Cin Ta = 25°C Typ Max — 235 23 47 — 40 — 270 26 54 — 46 — 285 26 57 — 48 — 300 26 60 — 51 — 150 12 30 — 26 — 165 Ta = –40 to +85°C Unit Test Conditions Min Max — 295 ns D0 – D7 to output — 59 — 50 — 340 ns Data control to output — 68 — 58 — 355 ns S0 – S2 to output — 71 — 60 — 375 ns Select control to output — 75 — 64 — 190 ns — 38 — 33 — 205 ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 Min — — — — — — — — — — — — — — — — 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 — — 50 10 10 5 5 5 80 16 14 — — — 15 — — 2 — — 0 — — 4 — — 4 — 33 28 — — — — — — — – — 60 12 10 — — 65 13 13 5 5 5 100 20 17 — — — 41 35 — — — — — — — — — 75 15 13 — — 5 10 — 10 Rev.2.00 Jan 31, 2006 page 5 of 9 ns D0 – D7 to Data control, S0 – S7 to Select control ns D0 – D7 to Data control, S0 – S7 to Select control ns Select control or Data control ns pF HD74HC354 Test Circuit VCC Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω Output 1 kΩ SC See Function Table Input VCC W GND CL = 50 pF S0 to S2 VCC Output D0 to D7 1 kΩ Y G1, G2 OPEN S1 OPEN S1 GND CL = 50 pF G3 DC VCC TEST t PLH / t PHL S1 OPEN t ZH/ t HZ t ZL / t LZ GND VCC Note : 1. CL includes probe and jig capacitance. Waveforms • Waveform – 1 tr D0 to D7 or S0 to S2 tf 90 % 50 % VCC 90 % 50 % 10 % 10 % t PLH 0V t PHL 90 % VOH 90 % 50 % 10 % Output Y t PHL 50 % 10 % t TLH t PLH t THL 90 % 90 % 50 % 10 % Output W t THL 50 % 10 % t TLH Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns Rev.2.00 Jan 31, 2006 page 6 of 9 VOL VOH VOL HD74HC354 • Waveform – 2 tr D0 to D7 or S0 to S2 tf VCC 90 % 90 % 50 % 50 % 50 % 10 % 10 % t su th tf th tr 90 % 50 % DC or SC 0V t su VCC 90 % 50 % 50 % 50 % 10 % 10 % 0V t PLH t PHL Y VOH 90 % 90 % 50 % 10 % 50 % 10 % t TLH t THL t PLH t PHL 90 % 90 % W VOL 50 % 10 % 50 % 10 % VOH VOL t TLH t THL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns • Waveform – 3 tf G1, G2 90 % G3 10 % tr 90 % 50 % 10 % t ZL 90 % 10 % VCC 90 % 50 % 10 % t LZ 0V VOH 50 % Waveform – A 10 % t ZH Waveform – B t HZ 50 % 90 % VOL VOH VOL Notes : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns 2. Waveform– A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform– B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Jan 31, 2006 page 7 of 9 HD74HC354 Package Dimensions JEITA Package Code P-DIP20-6.3x24.5-2.54 RENESAS Code PRDP0020AC-B Previous Code DP-20NEV MASS[Typ.] 1.26g D 11 E 20 1 10 b3 0.89 Z Dimension in Millimeters Min Nom Max A Reference Symbol A1 e D 24.50 E 6.30 L θ c e1 A1 0.51 b p 0.40 b 3 JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV 0.48 0.56 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.27 L 2.54 MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 7.00 1.30 Z ( Ni/Pd/Au plating ) 25.40 5.08 A bp e 7.62 1 11 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Z e *3 bp Nom Max D 12.60 13.0 E 5.50 A2 10 1 A1 x Dimension in Millimeters Min M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 2.20 A L1 bp b1 c A c 1 θ 0° HE A1 θ y L Detail F e 8° 1.27 x 0.12 y 0.15 0.80 Z 0.50 L L Rev.2.00 Jan 31, 2006 page 8 of 9 7.50 1 0.70 1.15 0.90 HD74HC354 JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A *1 Previous Code FP-20DBV MASS[Typ.] 0.52g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET. 11 HE c *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 12.80 13.2 E 7.50 A2 10 1 Z e *3 bp x A1 M 0.10 0.20 0.30 0.34 0.40 0.46 0.20 0.25 0.30 10.40 10.65 A L1 2.65 bp b1 c A c A1 θ L y 1 θ 0° HE 10.00 8° 1.27 e x 0.12 y 0.15 0.935 Z Detail F L L Rev.2.00 Jan 31, 2006 page 9 of 9 0.40 1 0.70 1.45 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .5.0