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TSL2571
Light-to-Digital Converter
General Description
The TSL2571 family of devices provides ambient light sensing
(ALS) that approximates human eye response to light intensity
under a variety of lighting conditions and through a variety of
attenuation materials. While useful for general purpose light
sensing, the device is particularly useful for display
management with the purpose of extending battery life and
providing optimum viewing in diverse lighting conditions.
Display panel and keyboard backlighting can account for up to
30 to 40 percent of total platform power. The ALS features are
ideal for use in notebook PCs, LCD monitors, flat-panel
televisions, and cell phones.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of TSL2571, Light-to-Digital
Converter are listed below:
Figure 1:
Added Value Of Using TSL2571
Benefits
Features
• Enables Operation in IR Light Environments
• Patented Dual-Diode Architecture
• Enables Dark Room to High Lux Sunlight
Operation
• 1M:1 Dynamic Range
• Digital Interface is Less Susceptible to
Noise
• I2C Digital Interface
• Enables Low Standby Power Consumption
• 2.5μA Quiescent Current (Sleep Mode)
• Reduces Board Space Requirements while
Simplifying Designs
• Available in 2mm x 2mm Dual Flat No-Lead (FN) Packages
• Ambient Light Sensing (ALS)
• Approximates Human Eye Response
• Programmable Analog Gain
• Programmable Integration Time
• Programmable Interrupt Function with Upper and
Lower Threshold
• Resolution Up to 16 Bits
• Very High Sensitivity — Operates Well Behind
Darkened Glass
• Up to 1,000,000:1 Dynamic Range
ams Datasheet
[v1-00] 2016-May-26
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TSL2571 − General Description
• Programmable Wait Timer
• Programmable from 2.72 ms to > 8 Seconds
• Wait State — 65μA Typical Current
• I²C Interface Compatible
• Up to 400 kHz (I²C Fast Mode)
• Dedicated Interrupt Pin
• Small 2 mm x 2 mm ODFN Package
• Sleep Mode — 2.5μA Typical Current
Applications
TSL2571, Light-to-Digital Converter is ideal for:
• Display Management
• Backlight Control
• Portable Device Power Optimization
• Cell Phones, PDA, GPS
• Notebooks and Monitors
• LCD TVs
Functional Block Diagram
The functional blocks of this device are shown below:
Figure 2:
TSL2571 Block Diagram
Interrupt
GND
INT
Wait Control
V DD
CH0
Data
ALS Control
CH0
CH1
ADC
CH1
Data
Lower Limit
I 2 C Interface
Upper Limit
CH0
ADC
SCL
SDA
CH1
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Pin Assignments
Pin Assignments
Figure 3:
Package FN Dual Flat No-Lead (Top View)
VDD 1
6 SDA
SCL 2
5 INT
GND 3
4 NC
Figure 4:
Terminal Functions
Terminal
Type
Description
Name
No
VDD
1
SCL
2
GND
3
Power supply ground. All voltages are referenced to GND.
NC
4
Do not connect.
INT
5
O
Interrupt — open drain (active low).
SDA
6
I/O
I²C serial data I/O terminal — serial data I/O for I²C .
ams Datasheet
[v1-00] 2016-May-26
Supply voltage.
I
I²C serial clock input terminal — clock signal for I²C serial data.
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TSL2571 − Detailed Description
Detailed Description
The TSL2571 light-to-digital device includes on-chip
photodiodes, integrating amplifiers, ADCs, accumulators,
clocks, buffers, comparators, a state machine, and an I²C
interface. The device combines one photodiode (CH0), which is
responsive to both visible and infrared light, and one
photodiode (CH1), which is responsive primarily to infrared
light. Two integrating ADCs simultaneously convert the
amplified photodiode currents into a digital value providing up
to 16 bits of resolution. Upon completion of the conversion
cycle, the conversion result is transferred to the data registers.
This digital output can be read by a microprocessor through
which the illuminance (ambient light level) in lux is derived
using an empirical formula to approximate the human eye
response.
Communication to the device is accomplished through a fast
(up to 400 kHz), two-wire I²C serial bus for easy connection to
a microcontroller or embedded controller. The digital output of
the device is inherently more immune to noise when compared
to an analog interface.
The device provides a separate pin for level-style interrupts.
When interrupts are enabled and a pre-set value is exceeded,
the interrupt pin is asserted and remains asserted until cleared
by the controlling firmware. The interrupt feature simplifies and
improves system efficiency by eliminating the need to poll a
sensor for a light intensity value. An interrupt is generated when
the value of an ALS conversion exceeds either an upper or lower
threshold. In addition, a programmable interrupt persistence
feature allows the user to determine how many consecutive
exceeded thresholds are necessary to trigger an interrupt.
Interrupt thresholds and persistence settings are configured
independently.
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under
Recommended Operating Conditions is not implied. Exposure
to absolute-maximum-rated conditions for extended periods
may affect device reliability.
Figure 5:
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
Symbol
VDD(1)
Parameter
Min
Max
Units
3.8
V
-0.5
3.8
V
Supply voltage
VO
Digital output voltage range
IO
Digital Output current
-1
+20
mA
Storage temperature range
-40
85
°C
TSTRG
ESDHBM
ESD tolerance, human body model
±2000
V
Note(s):
1. All voltages are with respect to GND.
ams Datasheet
[v1-00] 2016-May-26
Page 5
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TSL2571 − Electrical Characteristics
Electrical Characteristics
Figure 6:
Recommended Operating Conditions
Symbol
VDD
TA
Parameter
Min
Typ
Max
Units
Supply voltage
2.6
3
3.6
V
Operating free-air temperature
-30
70
°C
Figure 7:
Operating Characteristics; VDD = 3V, TA = 25°C (unless otherwise noted)
Symbol
Parameter
IDD
VOL
ILEAK
VIH
VIL
Supply current
Test Conditions
Min
Typ
Max
Active
175
250
Wait mode
65
Sleep mode — no I²C
activity
2.5
μA
4
3 mA sink current
0
0.4
6 mA sink current
0
0.6
−5
5
INT SDA output low voltage
V
Leakage current, SDA, SCL,
INT pins
TSL25711, TSL25715
0.7 VDD
TSL25713, TSL25717
1.25
μA
V
SCL SDA input high voltage
TSL25711, TSL25715
0.3 VDD
TSL25713, TSL25717
0.54
SCL SDA input low voltage
Page 6
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Unit
V
ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Electrical Characteristics
Figure 8:
ALS Characteristics; VDD = 3V, TA = 25°C, Gain = 16, AEN = 1 (unless otherwise noted)(1) (2) (3)
Parameter
Dark ADC count value
ADC integration time
step size
Test Conditions
Channel
Ee = 0, AGAIN = 120×
ATIME = 0xDB (100 ms)
Min
Typ
Max
Unit
CH0
0
1
5
CH1
0
1
5
2.58
2.72
2.9
ms
1
256
steps
counts
ATIME = 0xFF
ADC Number of
integration steps
ADC counts per step
ATIME = 0xFF
0
1024
counts
ADC count value
ATIME = 0xC0
0
65535
counts
λp = 625 nm, Ee = 171.6
CH0
μW/cm2
ADC count value
ADC count value
ratio: CH1/CH0
ATIME = 0xF6 (27 ms) (2)
CH1
λp = 850 nm, Ee = 219.7
CH0
μW/cm2
ATIME = 0xF6 (27 ms) (3)
CH1
Gain scaling, relative
to 1× gain setting
5000
6000
790
counts
λp = 625 ATIME 0xF6 (27 ms) (2)
4000
5000
6000
2800
10.8
15.8
20.8
%
λp = 850 ATIME 0xF6 (27 ms)
(3)
41
56
CH0
29.1
CH1
4.6
λp = 850 nm, ATIME = 0xF6
CH0
22.8
(27 ms) (3)
CH1
12.7
λp = 625 nm, ATIME = 0xF6
Re Irradiance
responsivity
4000
(27 ms)
(2)
68
counts/
(μW/ cm2)
8×
−10
10
16×
−10
10
120×
−10
10
%
Note(s):
1. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 625 nm LEDs
and infrared 850 nm LEDs are used for final product testing for compatibility with high-volume production.
2. The 625 nm irradiance Ee is supplied by an AlInGaP light-emitting diode with the following typical characteristics: peak wavelength
λp = 625 nm and spectral halfwidth Δλ½ = 20 nm.
3. The 850 nm irradiance Ee is supplied by a GaAs light-emitting diode with the following typical characteristics: peak wavelength
λp = 850 nm and spectral halfwidth Δλ½ = 42 nm.
ams Datasheet
[v1-00] 2016-May-26
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TSL2571 − Electrical Characteristics
Figure 9:
Wait Characteristics; VDD = 3V, TA = 25°C, WEN = 1 (unless otherwise noted)
Parameter
Wait step size
Test Conditions
Channel
WTIME = 0xFF
Wait number of
integration steps
Min
Typ
Max
Unit
2.58
2.72
2.9
ms
256
steps
Max
Unit
400
kHz
1
Figure 10:
AC Electrical Characteristics; VDD = 3V, TA = 25°C, (unless otherwise noted)
Parameter(1)
Symbol
Test
Conditions
Min
Typ
f(SCL)
Clock frequency (I²C only)
t(BUF)
Bus free time between start and stop
condition
1.3
μs
t(HDSTA)
Hold time after (repeated) start
condition. After this period, the first
clock is generated.
0.6
μs
t(SUSTA)
Repeated start condition setup time
0.6
μs
t(SUSTO)
Stop condition setup time
0.6
μs
t(HDDAT)
Data hold time
0
μs
t(SUDAT)
Data setup time
100
ns
t(LOW)
SCL clock low period
1.3
μs
t(HIGH)
SCL clock high period
0.6
μs
tF
Clock/data fall time
300
ns
tR
Clock/data rise time
300
ns
Ci
Input pin capacitance
10
pF
0
Note(s):
1. Specified by design and characterization; not production tested.
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Electrical Characteristics
Figure 11:
Timing Diagrams - Parameter Measurement Information
t(LOW)
t(R)
t(F)
VIH
SCL
VIL
t(HDSTA)
t(BUF)
t(HIGH)
t(HDDAT)
t(SUSTA)
t(SUSTO)
t(SUDAT)
VIH
SDA
VIL
P
Stop
Condition
S
S
Start
Condition
Start
P
Stop
t(LOWSEXT)
SCLACK
SCLACK
t(LOWMEXT)
t(LOWMEXT)
t(LOWMEXT)
SCL
SDA
ams Datasheet
[v1-00] 2016-May-26
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TSL2571 − Typical Characteristics
Typical Characteristics
Figure 12:
Spectral Responsivity
1
Ch 0
Normalized Responsivity
0.8
0.6
0.4
Ch 1
0.2
0
300
400
500
600
700
800
900 1000 1100
λ − Wavelength − nm
Figure 13:
Normalized IDD vs.VDD and Temperature
VDD and TEMPERATURE
110%
108%
IDD Normalized @ 3 V, 25C
75C
106%
104%
50C
25C
102%
100%
0C
98%
96%
94%
92%
2.7
2.8
2.9
3
3.1
3.2
3.3
VDD — V
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Typical Characteristics
Figure 14:
Normalized Responsivity vs. Angular Displacement
1.0
Optical Axis
Normalized Responsivity
0.8
0.6
0.4
0.2
0
−90
ams Datasheet
[v1-00] 2016-May-26
-Q
+Q
−60
−30
0
30
60
Q − Angular Displacement − °
90
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TSL2571 − Principles of Operation
Principles of Operation
System State Machine
The device provides control of ALS and power management
functionality through an internal state machine (see Figure 15).
After a power-on-reset, the device is in the sleep mode. As soon
as the PON bit is set, the device will move to the start state. It
will then continue through the Wait and ALS states. If these
states are enabled, the device will execute each function. If the
PON bit is set to 0, the state machine will continue until all
conversions are completed and then go into a low power sleep
mode.
Figure 15:
Simplified State Diagram
Sleep
PON = 1 (r 0:b0)
PON = 0 (r 0:b0)
Start
ALS
Wait
Note(s): In this document, the nomenclature uses the bit field
name in italic followed by the register number and bit number
to allow the user to easily identify the register and bit that
controls the function. For example, the power on (PON) is in
register 0, bit 0. This is represented as PON (r0:b0).
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Principles of Operation
Photodiodes
Conventional silicon detectors respond strongly to infrared
light, which the human eye does not see. This can lead to
significant error when the infrared content of the ambient light
is high (such as with incandescent lighting) due to the
difference between the silicon detector response and the
brightness perceived by the human eye.
This problem is overcome through the use of two photodiodes.
The channel 0 photodiode, referred to as the CH0 channel, is
sensitive to both visible and infrared light, while the channel 1
photodiode, referred to as CH1, is sensitive primarily to infrared
light. Two integrating ADCs convert the photodiode currents to
digital outputs. The ADC digital outputs from the two channels
are used in a formula to obtain a value that approximates the
human eye response in units of lux.
ALS Operation
The ALS engine contains ALS gain control (AGAIN) and two
integrating analog-to-digital converters (ADC) for the Channel
0 and Channel 1 photodiodes. The ALS integration time (ATIME)
impacts both the resolution and the sensitivity of the ALS
reading. Integration of both channels occurs simultaneously
and upon completion of the conversion cycle, the results are
transferred to the data registers (C0DATA and C1DATA). This
data is also referred to as channel count. The transfers are
double-buffered to ensure data integrity.
Figure 16:
ALS Operation
ATIME(r 1)
2.72 ms to 696 ms
CH0
ALS
CH0
Data
C0DATAH(r 0x15), C0DATA(r 0x14)
ALS Control
CH0
CH1
ADC
CH1
Data
C1DATAH(r 0x17), C1DATA(r 0x16)
CH1
AGAIN(r 0x0F, b1:0)
1, 8, 16, 120 Gain
ams Datasheet
[v1-00] 2016-May-26
Page 13
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TSL2571 − Principles of Operation
The registers for programming the integration and wait times
are a 2’s compliment values. The actual time can be calculated
as follows:
ATIME = 256 - Integration Time / 2.72 ms
Inversely, the time can be calculated from the register value as
follows:
Integration Time = 2.72 ms × (256 - ATIME)
In order to reject 50/60-Hz ripple strongly present in fluorescent
lighting, the integration time needs to be programmed in
multiples of 10 / 8.3 ms or the half cycle time. Both frequencies
can be rejected with a programmed value of
50 ms (ATIME = 0xED) or multiples of 50 ms (i.e. 100, 150, 200,
400, 600).
The registers for programming the AGAIN hold a two-bit value
representing a gain of 1×, 8×, 16×, or 120×. The gain, in terms
of amount of gain, will be represented by the value AGAINx, i.e.
AGAINx = 1, 8, 16, or 120.
Lux Equation
The lux calculation is a function of CH0 channel count (C0DATA),
CH1 channel count (C1DATA), ALS gain (AGAINx), and ALS
integration time in milliseconds (ATIME_ms). If an aperture,
glass/plastic, or a light pipe attenuates the light equally across
the spectrum (300 nm to 1100 nm), then a scaling factor referred
to as glass attenuation (GA) can be used to compensate for
attenuation. For a device in open air with no aperture or
glass/plastic above the device, GA = 1. If it is not spectrally flat,
then a custom lux equation with new coefficients should be
generated. (See ams application note).
Counts per Lux (CPL) needs to be calculated only when ATIME
or AGAIN is changed, otherwise it remains a constant. The first
segment of the equation (Lux1) covers fluorescent and
incandescent light. The second segment (Lux2) covers dimmed
incandescent light. The final lux is the maximum of Lux1, Lux2,
or 0.
CPL = (ATIME_ms × AGAINx) / (GA × 53)
Lux1 = (C0DATA - 2 × C1DATA) / CPL
Lux2 = (0.6 × C0DATA - C1DATA) / CPL
Lux = MAX(Lux1, Lux2, 0)
Page 14
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Principles of Operation
Interrupts
The interrupt feature simplifies and improves system efficiency
by eliminating the need to poll the sensor for light intensity
values outside of a user-defined range. While the interrupt
function is always enabled and it’s status is available in the
status register (0x13), the output of the interrupt state can be
enabled using the ALS interrupt enable (AIEN) field in the
enable register (0x00).
Two 16-bit interrupt threshold registers allow the user to set
limits below and above a desired light level range. An interrupt
can be generated when the ALS CH0 data (C0DATA) falls outside
of the desired light level range, as determined by the values in
the ALS interrupt low threshold registers (AILTx) and ALS
interrupt high threshold registers (AIHTx). It is important to
note that the low threshold value must be less than the high
threshold value for proper operation.
To further control when an interrupt occurs, the device provides
a persistence filter. The persistence filter allows the user to
specify the number of consecutive out-of-range ALS
occurrences before an interrupt is generated. The persistence
register (0x0C) allows the user to set the ALS persistence
(APERS) value. See the persistence register for details on the
persistence filter values. Once the persistence filter generates
an interrupt, it will continue until a special function interrupt
clear command is received (see Command Register).
Figure 17:
Programmable Interrupt
AIHTH(r 07), AIHTL(r 06)
Upper Limit
CH0
ADC
APERS(r 0x0C, b3:0)
ALS Persistence
CH0
Data
Lower Limit
CH0
AILTH(r 05), AILTL(r 04)
ams Datasheet
[v1-00] 2016-May-26
Page 15
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State Diagram
Figure 18 shows a more detailed flow for the state machine. The
device starts in the sleep mode. The PON bit is written to enable
the device. A 2.72-ms delay will occur before entering the start
state.
If the WEN bit is set, the state machine will then cycle through
the wait state. If the WLONG bit is set, the wait cycles are
extended by 12× over normal operation. When the wait counter
terminates, the state machine will step to the ALS state.
The AEN should always be set. In this case, a minimum of 1
integration time step should be programmed. The ALS state
machine will continue until it reaches the terminal count at
which point the data will be latched in the ALS register and the
interrupt set, if enabled.
Figure 18:
Expanded State Diagram
1 to 256 steps
Step: 2.72 ms
Time: 2.72 ms − 696 ms
120 Hz Minimum − 8 ms
100 Hz Minimum − 10 ms
Sleep
PON = 1
PON = 0
Start
ALS
ALS
Check
AEN = 1
Wait
Check
ALS
Delay
2.72 ms
WEN = 1
Wait
WLONG = 0
1 to 256 steps
Step: 2.72 ms
Time: 2.72 ms − 696 ms
Minimum − 2.72 ms
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WLONG = 1
1 to 256 steps
Step: 32.64 ms
Time: 32.64 ms − 8.35 s
Minimum − 32.64 ms
ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Principles of Operation
I²C Protocol
Interface and control are accomplished through an I²C serial
compatible interface (standard or fast mode) to a set of registers
that provide access to device control functions and output data.
The devices support the 7-bit I²C addressing protocol.
The I²C standard provides for three types of bus transaction:
read, write, and a combined protocol (see Figure 34). During a
write operation, the first byte written is a command byte
followed by data. In a combined protocol, the first byte written
is the command byte followed by reading a series of bytes. If a
read command is issued, the register address from the previous
command will be used for data access. Likewise, if the MSB of
the command is not set, the device will write a series of bytes
at the address stored in the last valid command with a register
address. The command byte contains either control information
or a 5-bit register address. The control commands can also be
used to clear interrupts.
The I²C bus protocol was developed by Philips (now NXP). For
a complete description of the I²C protocol, please review the
NXP I²C design specification at
http://www.i2c-bus.org/references/.
Figure 19:
I²C Protocols
1
7
1
1
S
Slave Address
W
A
8
Command Code
1
8
1
A
Data Byte
A
8
1
1
...
P
I2C Write Protocol
1
S
7
Slave Address
1
R
1
8
A
1
Data
A
Data
A
1
...
P
I2C Read Protocol
1
7
1
1
8
1
1
7
1
1
S
Slave Address
W
A
Command Code
A
S
Slave Address
R
A
8
Data
A
N
P
R
S
S
W
...
ams Datasheet
[v1-00] 2016-May-26
1
8
1
A
Data
A
1
...
P
Acknowledge (0)
Not Acknowledged (1)
Stop Condition
Read (1)
Start Condition
Repeated Start Condition
Write (0)
Continuation of protocol
Master-to-Slave
Slave-to-Master
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TSL2571 − Register Description
Register Description
Register Set
The device is controlled and monitored by data registers and a
command register accessed through the serial interface. These
registers provide for a variety of control functions and can be
read to determine results of the ADC conversions. The register
set is summarized in Figure 20.
Figure 20:
Register Address
Address
Register Name
R/W
−−
COMMAND
W
0x00
ENABLE
0x01
Register Function
Reset Value
Specifies register address
0x00
R/W
Enables states and interrupts
0x00
ATIME
R/W
ALS ADC time
0xFF
0x03
WTIME
R/W
Wait time
0xFF
0x04
AILTL
R/W
ALS interrupt low threshold low byte
0x00
0x05
AILTH
R/W
ALS interrupt low threshold high byte
0x00
0x06
AIHTL
R/W
ALS interrupt high threshold low byte
0x00
0x07
AIHTH
R/W
ALS interrupt high threshold high byte
0x00
0x0C
PERS
R/W
Interrupt persistence filters
0x00
0x0D
CONFIG
R/W
Configuration
0x00
0x0F
CONTROL
R/W
Control register
0x00
0x12
ID
R
Device ID
0x13
STATUS
R
Device status
0x00
0x14
C0DATA
R
CH0 ADC low data register
0x00
0x15
C0DATAH
R
CH0 ADC high data register
0x00
0x16
C1DATA
R
CH1 ADC low data register
0x00
0x17
C1DATAH
R
CH1 ADC high data register
0x00
ID
The mechanics of accessing a specific register depends on the
specific protocol used. See the section on I²C protocols on the
previous pages. In general, the COMMAND register is written
first to specify the specific control/status register for following
read/write operations.
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Register Description
Command Register
The command registers specifies the address of the target
register for future write and read operations.
Figure 21:
Command Register
7
COMMAND
6
COMMAND
Field
Bits
COMMAND
7
5
TYPE
4
3
2
1
0
−−
ADD
Description
Select Command Register. Must write as 1 when addressing COMMAND register.
Selects type of transaction to follow in subsequent data transfers.
TYPE
FIELD VALUE
DESCRIPTION
00
Repeated byte protocol transaction
01
Auto-increment protocol transaction
10
Reserved — Do not use
11
Special function — See description below
6:5
Transaction type 00 will repeatedly read the same register with each data access.
Transaction type 01 will provide an auto-increment function to read successive
register bytes.
Address register/special function field. Depending on the transaction type, see above,
this field either specifies a special function command or selects the specific
control-status-register for following write and read transactions. The field values listed
below apply only to special function commands:
ADD
4:0
FIELD VALUE
DESCRIPTION
00000
Normal — no action
00110
ALS interrupt clear
other
Reserved — do not write
ALS interrupt clear — clears any pending ALS interrupt. This special function is self
clearing.
ams Datasheet
[v1-00] 2016-May-26
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TSL2571 − Register Description
Enable Register (0x00)
The ENABLE register is used to power the device ON/OFF, enable
functions, and interrupts.
Figure 22:
Enable Register
7
6
5
Reserved
ENABLE
4
3
2
1
0
AIEN
WEN
Reserved
AEN
PON
Address
0x00
Field
Bits
Description
Reserved
7:5
AIEN
4
ALS interrupt mask. When asserted, permits ALS interrupts to be generated.
WEN
3
Wait enable. This bit activates the wait feature. Writing a 1 activates the wait timer.
Writing a 0 disables the wait timer.
Reserved
2
Reserved. Write as 0.
AEN
1
ALS Enable. Writing a 1 activates the ALS. Writing a 0 disables the ALS.
PON (1)
0
Power ON. This bit activates the internal oscillator to permit the timers and ADC
channels to operate. Writing a 1 activates the oscillator. Writing a 0 disables the
oscillator.
Reserved. Write as 0.
Note(s):
1. A minimum interval of 2.72 ms must pass after PON is asserted before ALS can be initiated. This required time is enforced by the
hardware in cases where the firmware does not provide it.
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Register Description
ALS Timing Register (0x01)
The ALS timing register controls the internal integration time
of the ALS ADCs in 2.72-ms increments.
Figure 23:
ALS Timing Register
Field
ATIME
Bits
Description
VALUE
INTEG_CYCLES
TIME
MAX COUNT
0xFF
1
2.72 ms
1024
0xF6
10
27.2 ms
10240
0xDB
37
101 ms
37888
0xC0
64
174 ms
65535
0x00
256
696 ms
65535
7:0
Wait Time Register (0x03)
Wait time is set 2.72 ms increments unless the WLONG bit is
asserted in which case the wait times are 12× longer. WTIME is
programmed as a 2’s complement number.
Figure 24:
Wait Time Register
Field
WTIME
Bits
7:0
Description
REGISTER
VALUE
WAIT TIME
TIME (WLONG = 0)
TIME (WLONG = 1)
0xFF
1
2.72 ms
0.032 s
0xB6
74
201 ms
2.4 s
0x00
256
696 ms
8.3 s
Note(s):
1. The Wait Time Register should be configured before AEN is asserted.
ams Datasheet
[v1-00] 2016-May-26
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TSL2571 − Register Description
ALS Interrupt Threshold Registers (0x04 - 0x07)
The ALS interrupt threshold registers provides the values to be
used as the high and low trigger points for the comparison
function for interrupt generation. If C0DATA crosses below the
low threshold specified, or above the higher threshold, an
interrupt is asserted on the interrupt pin.
Figure 25:
ALS Interrupt Threshold Registers
Register
Address
Bits
AILTL
0x04
7:0
ALS low threshold lower byte
AILTH
0x05
7:0
ALS low threshold upper byte
AIHTL
0x06
7:0
ALS high threshold lower byte
AIHTH
0x07
7:0
ALS high threshold upper byte
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Description
ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Register Description
Persistence Register (0x0C)
The persistence register controls the filtering interrupt
capabilities of the device. Configurable filtering is provided to
allow interrupts to be generated after each ADC integration
cycle or if the ADC integration has produced a result that is
outside of the values specified by threshold register for some
specified amount of time. ALS interrupts are generated using
C0DATA.
Figure 26:
Persistence Register
7
6
PERS
5
4
3
Reserved
Field
Bits
Reserved
7:4
2
1
0
Address
0x0C
APERS
Description
Reserved
Interrupt persistence. Controls rate of interrupt to the host processor.
APERS
ams Datasheet
[v1-00] 2016-May-26
FIELD VALUE
MEANING
INTERRUPT PERSISTENCE FUNCTION
0000
Every
Every ALS cycle generates an interrupt
0001
1
1 value outside of threshold range
0010
2
2 consecutive values out of range
0011
3
3 consecutive values out of range
0100
5
5 consecutive values out of range
0101
10
10 consecutive values out of range
0110
15
15 consecutive values out of range
0111
20
20 consecutive values out of range
1000
25
25 consecutive values out of range
1001
30
30 consecutive values out of range
1010
35
35 consecutive values out of range
1011
40
40 consecutive values out of range
1100
45
45 consecutive values out of range
1101
50
50 consecutive values out of range
1110
55
55 consecutive values out of range
1111
60
60 consecutive values out of range
3:0
Page 23
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TSL2571 − Register Description
Configuration Register (0x0D)
The configuration register sets the wait long time.
Figure 27:
Configuration Register
7
6
5
CONFIG
4
3
2
Reserved
1
0
WLONG
Reserved
Address
0x0D
Field
Bits
Description
Reserved
7:2
WLONG
1
Wait Long. When asserted, the wait cycles are increased by a factor 12× from
that programmed in the WTIME register.
Reserved
0
Reserved. Write as 0.
Reserved. Write as 0.
Control Register (0x0F)
The Control register provides eight bits of miscellaneous
control to the analog block. These bits typically control
functions such as gain settings and/or diode selection.
Figure 28:
Control Register
7
6
5
CONTROL
4
3
2
1
Reserved
Field
Bits
Reserved
7:2
0
AGAIN
Address
0x0F
Description
Reserved. Write bits as 0
ALS Gain Control.
AGAIN
Page 24
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FIELD VALUE
ALS GAIN VALUE
00
1× gain
01
8× gain
10
16× gain
11
120× gain
1:0
ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Register Description
ID Register (0x12)
The ID Register provides the value for the part number. The ID
register is a read-only register.
Figure 29:
ID Register
7
6
5
4
3
ID
2
1
0
Address
0x12
ID
Field
Bits
ID
7:0
Description
0x04 = TSL25711 and TSL25715
Part number identification
0x0D = TSL25713 and TSL25717
Status Register (0x13)
The Status Register provides the internal status of the device.
This register is read only.
Figure 30:
Status Register
7
STATUS
6
5
Reserved
Field
Bit
Reserved
7:5
AINT
4
Reserved
3:1
AVALID
0
ams Datasheet
[v1-00] 2016-May-26
4
AINT
3
2
Reserved
1
0
AVALID
Address
0x13
Description
Reserved. Write as 0.
ALS Interrupt. Indicates that the device is asserting an ALS interrupt.
Reserved.
ALS Valid. Indicates that the ALS CH0 / CH1 channels have completed
an integration cycle.
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TSL2571 − Register Description
ADC Channel Data Registers (0x14 - 0x17)
ALS data is stored as two 16-bit values. To ensure the data is
read correctly, a two-byte read I²C transaction should be used
with auto increment protocol bits set in the command register.
With this operation, when the lower byte register is read, the
upper eight bits are stored in a shadow register, which is read
by a subsequent read to the upper byte. The upper register will
read the correct value even if additional ADC integration cycles
end between the reading of the lower and upper registers.
Figure 31:
ADC Channel Data Registers
Register
Address
Bits
C0DATA
0x14
7:0
ALS CH0 data low byte
C0DATAH
0x15
7:0
ALS CH0 data high byte
C1DATA
0x16
7:0
ALS CH1 data low byte
C1DATAH
0x17
7:0
ALS CH1 data high byte
Page 26
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Description
ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Application Information Hardware
Application Information
Hardware
Typical Hardware Application
A typical hardware application circuit is shown in Figure 32. A
1-μF low-ESR decoupling capacitor should be placed as close
as possible to the VDD pin.
Figure 32:
Typical Application Hardware Circuit
VDD
VBUS
VDD
RP
1 mF
TSL2571
RP
RPI
INT
SCL
GND
SDA
V BUS in Figure 32 refers to the I²C bus voltage, which is either
V DD or 1.8 V. Be sure to apply the specified I²C bus voltage shown
in the Available Options table for the specific device being used.
The I²C signals and the Interrupt are open-drain outputs and
require pull-up resistors. The pull-up resistor (R P) value is a
function of the I²C bus speed, the I²C bus voltage, and the
capacitive load. The ams EVM running at 400 kbps, uses 1.5-kΩ
resistors. A 10-kΩ pull-up resistor (RPI) can be used for the
interrupt line.
ams Datasheet
[v1-00] 2016-May-26
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TSL2571 − Application Information Hardware
PCB Pad Layout
Suggested PCB pad layout guidelines for the Dual Flat No-Lead
(FN) surface mount package are shown in Figure 33.
Note(s): Pads can be extended further if hand soldering is
needed.
Figure 33:
Suggested FN Package PCB Layout
2500
1000
1000
400
650
1700
650
400
Note(s):
1. All linear dimensions are in micrometers.
2. This drawing is subject to change without notice.
Page 28
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Mechanical Data
Mechanical Data
Figure 34:
Package FN — Dual Flat No-Lead Packaging Configuration
PACKAGE FN
Dual Flat No-Lead
TOP VIEW
466 10
PIN OUT
TOP VIEW
PIN 1
466
10
2000 100
2000
100
VDD 1
6 SDA
SCL 2
5 INT
GND 3
4 NC
Photodiode Array Area
END VIEW
SIDE VIEW
295
Nominal
650 50
203 8
650
300
50
BOTTOM VIEW
CL of Photodiode Array Area
(Note )
CL of Solder Contacts
20 Nominal
140 Nominal
CL of Solder Contacts
CL of Photodiode Array Area (Note )
PIN 1
750 150
RoHS
Pb
Green
Lead Free
Note(s):
1. All linear dimensions are in micrometers. Dimension tolerance is ±20μm unless otherwise noted.
2. The die is centered within the package within a tolerance of ± 3 mils.
3. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
4. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish.
5. This package contains no lead (Pb).
6. This drawing is subject to change without notice.
ams Datasheet
[v1-00] 2016-May-26
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TSL2571 − Mechanical Data
Figure 35:
Package FN Carrier Tape
TOP VIEW
2.00 0.05
1.75
4.00
8.00
1.50
4.00
B
+ 0.30
− 0.10
3.50 0.05
1.00
0.25
A
B
A
DETAIL B
DETAIL A
5 Max
5 Max
2.18 0.05
0.254
0.02
Ao
0.83 0.05
Ko
2.18 0.05
Bo
Note(s):
1. All linear dimensions are in millimeters. Dimension tolerance is ±0.10 mm unless otherwise noted.
2. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481-B 2001.
4. Each reel is 178 millimeters in diameter and contains 3500 parts.
5. ams packaging tape and reel conform to the requirements of EIA Standard 481-B.
6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
7. This drawing is subject to change without notice.
Page 30
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Manufacturing Information
The FN package has been tested and has demonstrated an
ability to be reflow soldered to a PCB substrate.
Manufacturing Information
The solder reflow profile describes the expected maximum heat
exposure of components during the solder reflow process of
product on a PCB. Temperature is measured on top of
component. The components should be limited to a maximum
of three passes through this solder reflow profile.
Figure 36:
Soldier Reflow Profile
Parameter
Reference
Device
Average temperature gradient in preheating
2.5°C/s
tsoak
2 to 3 minutes
Time above 217°C (T1)
t1
Max 60 s
Time above 230°C (T2)
t2
Max 50 s
Time above Tpeak −10°C (T3)
t3
Max 10 s
Peak temperature in reflow
Tpeak
260°C
Soak time
Temperature gradient in cooling
Max −5°C/s
Figure 37:
Solder Reflow Profile Graph
Tpeak
Not to scale — for reference o
T3
T2
Temperature (C)
T1
Time (s)
t3
t2
tsoak
t1
Note(s):
1. Not to scale - for reference only.
ams Datasheet
[v1-00] 2016-May-26
Page 31
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TSL2571 − Manufacturing Information
Manufacturing Information
Moisture Sensitivity
Optical characteristics of the device can be adversely affected
during the soldering process by the release and vaporization of
moisture that has been previously absorbed into the package.
To ensure the package contains the smallest amount of
absorbed moisture possible, each device is dry-baked prior to
being packed for shipping.
Devices are packed in a sealed aluminized envelope called a
moisture barrier bag with silica gel to protect them from
ambient moisture during shipping, handling, and storage
before use.
The FN package has been assigned a moisture sensitivity level
of MSL 3 and the devices should be stored under the following
conditions:
• Temperature Range: 5°C to 50°C
• Relative Humidity: 60% maximum
• Total Time: 12 months from the date code on the
aluminized envelope—if unopened
• Opened Time: 168 hours or fewer
Rebaking will be required if the devices have been stored
unopened for more than 12 months or if the aluminized
envelope has been open for more than 168 hours. If rebaking
is required, it should be done at 50°C for 12 hours.
Page 32
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Ordering & Contact Information
Ordering & Contact Information
Figure 38:
Ordering Information
Ordering Code
Device
Address
Package Leads
Interface Description
TSL25711FN
TSL25711
0x39
FN−6
I²C Vbus = VDD Interface
TSL25713FN
TSL25713
0x39
FN−6
I²C Vbus = 1.8 V Interface
TSL25715FN
TSL25715
0x29
FN−6
I²C Vbus = VDD Interface
TSL25717FN
TSL25717(1)
0x29
FN−6
I²C Vbus = 1.8 V Interface
Note(s):
1. Contact ams for availability.
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
[email protected]
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
ams Datasheet
[v1-00] 2016-May-26
Page 33
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TSL2571 − RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
Page 34
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ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
ams Datasheet
[v1-00] 2016-May-26
Page 35
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TSL2571 − Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Page 36
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Product Status
Definition
Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
ams Datasheet
[v1-00] 2016-May-26
TSL2571 − Revision Information
Revision Information
Changes from 117B (2012-Jan) to current revision 1-00 (2016-May-26)
Page
Content of TAOS datasheet was updated to latest ams design
Updated Key Benefits & Features
1
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
ams Datasheet
[v1-00] 2016-May-26
Page 37
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TSL2571 − Content Guide
Content Guide
Page 38
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1
1
2
2
General Description
Key Benefits & Features
Applications
Functional Block Diagram
3
4
5
6
10
Pin Assignments
Detailed Description
Absolute Maximum Ratings
Electrical Characteristics
Typical Characteristics
12
12
13
13
14
15
16
17
Principles of Operation
System State Machine
Photodiodes
ALS Operation
Lux Equation
Interrupts
State Diagram
I²C Protocol
18
18
19
20
21
21
22
23
24
24
25
25
26
Register Description
Register Set
Command Register
Enable Register (0x00)
ALS Timing Register (0x01)
Wait Time Register (0x03)
ALS Interrupt Threshold Registers (0x04 - 0x07)
Persistence Register (0x0C)
Configuration Register (0x0D)
Control Register (0x0F)
ID Register (0x12)
Status Register (0x13)
ADC Channel Data Registers (0x14 - 0x17)
27
27
28
Application Information Hardware
Typical Hardware Application
PCB Pad Layout
29
31
Mechanical Data
Manufacturing Information
32
32
Manufacturing Information
Moisture Sensitivity
33
34
35
36
37
Ordering & Contact Information
RoHS Compliant & ams Green Statement
Copyrights & Disclaimer
Document Status
Revision Information
ams Datasheet
[v1-00] 2016-May-26